xref: /illumos-gate/usr/src/uts/sun4u/opl/sys/opl_hwdesc.h (revision 68ac2337)
125cf1a30Sjl /*
225cf1a30Sjl  * CDDL HEADER START
325cf1a30Sjl  *
425cf1a30Sjl  * The contents of this file are subject to the terms of the
525cf1a30Sjl  * Common Development and Distribution License (the "License").
625cf1a30Sjl  * You may not use this file except in compliance with the License.
725cf1a30Sjl  *
825cf1a30Sjl  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
925cf1a30Sjl  * or http://www.opensolaris.org/os/licensing.
1025cf1a30Sjl  * See the License for the specific language governing permissions
1125cf1a30Sjl  * and limitations under the License.
1225cf1a30Sjl  *
1325cf1a30Sjl  * When distributing Covered Code, include this CDDL HEADER in each
1425cf1a30Sjl  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1525cf1a30Sjl  * If applicable, add the following below this CDDL HEADER, with the
1625cf1a30Sjl  * fields enclosed by brackets "[]" replaced with your own identifying
1725cf1a30Sjl  * information: Portions Copyright [yyyy] [name of copyright owner]
1825cf1a30Sjl  *
1925cf1a30Sjl  * CDDL HEADER END
2025cf1a30Sjl  */
2125cf1a30Sjl /*
22*68ac2337Sjl  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
2325cf1a30Sjl  * Use is subject to license terms.
2425cf1a30Sjl  */
2525cf1a30Sjl 
2625cf1a30Sjl #ifndef	_SYS_OPL_HWDESC_H
2725cf1a30Sjl #define	_SYS_OPL_HWDESC_H
2825cf1a30Sjl 
2925cf1a30Sjl #pragma ident	"%Z%%M%	%I%	%E% SMI"
3025cf1a30Sjl 
3125cf1a30Sjl #ifdef	__cplusplus
3225cf1a30Sjl extern "C" {
3325cf1a30Sjl #endif
3425cf1a30Sjl 
3525cf1a30Sjl /*
3625cf1a30Sjl  * Hardware Descriptor.
3725cf1a30Sjl  */
3825cf1a30Sjl 
3925cf1a30Sjl #define	HWD_SBS_PER_DOMAIN		32  /* System boards per domain */
4025cf1a30Sjl #define	HWD_CPUS_PER_CORE		4   /* Strands per physical core */
4125cf1a30Sjl #define	HWD_CORES_PER_CPU_CHIP		4   /* Cores per processor chip */
4225cf1a30Sjl #define	HWD_CPU_CHIPS_PER_CMU		4   /* Processor chips per CMU */
4325cf1a30Sjl #define	HWD_SCS_PER_CMU			4   /* System controllers per CMU */
4425cf1a30Sjl #define	HWD_DIMMS_PER_CMU		32  /* Memory DIMMs per CMU */
4525cf1a30Sjl #define	HWD_IOCS_PER_IOU		2   /* Oberon chips per I/O unit */
4625cf1a30Sjl #define	HWD_PCI_CHANNELS_PER_IOC	2   /* PCI channels per Oberon chip */
4725cf1a30Sjl #define	HWD_LEAVES_PER_PCI_CHANNEL	2   /* Leaves per PCI channel */
4825cf1a30Sjl #define	HWD_PCI_CHANNELS_PER_SB		4   /* PCI channels per system board */
4925cf1a30Sjl #define	HWD_CMU_CHANNEL			4   /* CMU channel number */
5025cf1a30Sjl #define	HWD_IO_BOATS_PER_IOU		6   /* I/O boats per I/O unit */
5125cf1a30Sjl #define	HWD_BANKS_PER_CMU		8   /* Memory banks per CMU */
5225cf1a30Sjl #define	HWD_MAX_MEM_CHUNKS		8   /* Chunks per board */
5325cf1a30Sjl 
5425cf1a30Sjl typedef uint32_t	hwd_stat_t;	/* component status */
5525cf1a30Sjl 
5625cf1a30Sjl /*
5725cf1a30Sjl  * Values for hwd_stat_t.
5825cf1a30Sjl  */
5925cf1a30Sjl #define	HWD_STAT_UNKNOWN	0x0000	/* No status yet */
6025cf1a30Sjl #define	HWD_STAT_PRESENT	0x0001	/* Present */
6125cf1a30Sjl #define	HWD_STAT_MISS		0x0002	/* Missing */
6225cf1a30Sjl #define	HWD_STAT_MISCONFIG	0x0003	/* Misconfigured */
6325cf1a30Sjl #define	HWD_STAT_PASS		0x0004	/* Ok */
6425cf1a30Sjl #define	HWD_STAT_FAIL		0x0080	/* Failed by XSCF */
6525cf1a30Sjl #define	HWD_STAT_FAIL_OBP	0x0081	/* Failed by POST/OBP */
6625cf1a30Sjl #define	HWD_STAT_FAIL_OS	0x0082	/* Failed by OS */
6725cf1a30Sjl 
6825cf1a30Sjl #define	HWD_STAT_FAILED		0x0080
6925cf1a30Sjl 
7025cf1a30Sjl #define	HWD_MASK_NOT_USED	0x8000	/* If this bit is set, the component */
7125cf1a30Sjl 					/* is not used (even if it presents) */
7225cf1a30Sjl 
7325cf1a30Sjl #define	HWD_STATUS_FAILED(stat)		((stat) & HWD_STAT_FAILED)
7425cf1a30Sjl #define	HWD_STATUS_OK(stat)		((stat) == HWD_STAT_PASS)
7525cf1a30Sjl #define	HWD_STATUS_PRESENT(stat)	\
7625cf1a30Sjl 		((stat) & (HWD_STAT_PRESENT | HWD_STAT_PASS))
7725cf1a30Sjl #define	HWD_STATUS_NONE(stat)			\
7825cf1a30Sjl 		(((stat) == HWD_STAT_UNKNOWN) || ((stat) == HWD_STAT_MISS))
7925cf1a30Sjl 
8025cf1a30Sjl #define	HWD_VERSION_MAJOR	1
8125cf1a30Sjl #define	HWD_VERSION_MINOR	1
8225cf1a30Sjl 
8325cf1a30Sjl /*
8425cf1a30Sjl  * Hardware Descriptor Header.
8525cf1a30Sjl  *
8625cf1a30Sjl  * Some fields occur repeatedly in different structures:
8725cf1a30Sjl  *
8825cf1a30Sjl  * spare*	This field is for future use.
8925cf1a30Sjl  *
9025cf1a30Sjl  * filler*	This field is used to show alignment. This could also
9125cf1a30Sjl  *		be used in the future for something.
9225cf1a30Sjl  *
9325cf1a30Sjl  * check_sum	This contains the check sum of the structure it resides in.
9425cf1a30Sjl  */
9525cf1a30Sjl typedef struct {
9625cf1a30Sjl 	uint32_t	hdr_magic;		/* magic code ('HWDE') */
9725cf1a30Sjl 	struct hwdesc_version {
9825cf1a30Sjl 		uint16_t	major;
9925cf1a30Sjl 		uint16_t	minor;
10025cf1a30Sjl 	} hdr_version;		/* structure version */
10125cf1a30Sjl 
10225cf1a30Sjl 	/*
10325cf1a30Sjl 	 * Domain Identifier. The OPL system can have
10425cf1a30Sjl 	 * upto 24 domains so domain id can be 0 - 23.
10525cf1a30Sjl 	 */
10625cf1a30Sjl 	uint8_t		hdr_domain_id;
10725cf1a30Sjl 	char		hdr_filler[3];
10825cf1a30Sjl 
10925cf1a30Sjl 	/*
11025cf1a30Sjl 	 * offsets from the beginning of the header to:
11125cf1a30Sjl 	 * - SB status information (hwd_sb_status_t)
11225cf1a30Sjl 	 * - domain information (hwd_domain_info_t)
11325cf1a30Sjl 	 * - SB information (hwd_sb_info_t).
11425cf1a30Sjl 	 */
11525cf1a30Sjl 	uint32_t	hdr_sb_status_offset;
11625cf1a30Sjl 	uint32_t	hdr_domain_info_offset;
11725cf1a30Sjl 	uint32_t	hdr_sb_info_offset;
11825cf1a30Sjl 
11925cf1a30Sjl 	uint32_t	hdr_spare[9];
12025cf1a30Sjl 	uint32_t	hdr_check_sum;
12125cf1a30Sjl } hwd_header_t;
12225cf1a30Sjl 
12325cf1a30Sjl /*
12425cf1a30Sjl  * SB Status
12525cf1a30Sjl  */
12625cf1a30Sjl typedef struct {
12725cf1a30Sjl 	hwd_stat_t	sb_status[HWD_SBS_PER_DOMAIN];	/* status of all LSBs */
128*68ac2337Sjl 	/* PSB number of respective LSB */
129*68ac2337Sjl 	uint8_t		sb_psb_number[HWD_SBS_PER_DOMAIN];
130*68ac2337Sjl 	uint32_t	sb_spare[7];
13125cf1a30Sjl 	uint32_t	sb_check_sum;
13225cf1a30Sjl } hwd_sb_status_t;
13325cf1a30Sjl 
13425cf1a30Sjl /*
13525cf1a30Sjl  * SP -> Domain Information.
13625cf1a30Sjl  */
13725cf1a30Sjl typedef struct {
13825cf1a30Sjl 	uint32_t	dinf_reset_factor;	/* domain reset reason */
13925cf1a30Sjl 	uint32_t	dinf_host_id;		/* domain unique id */
14025cf1a30Sjl 	uint64_t	dinf_system_frequency;	/* Hz */
14125cf1a30Sjl 	uint64_t	dinf_stick_frequency;	/* Hz */
14225cf1a30Sjl 	uint32_t	dinf_scf_command_timeout; /* SCF i/f timeout seconds */
14325cf1a30Sjl 	uint32_t	dinf_model_info;	/* FF1/2 DC1/2/3 */
14425cf1a30Sjl 	uint8_t		dinf_mac_address[6];	/* system MAC address */
14525cf1a30Sjl 	uint8_t		dinf_filler1[10];
14625cf1a30Sjl 	uint8_t		dinf_dr_status;		/* 0: DR capable, !0: no DR */
14725cf1a30Sjl 	uint8_t		dinf_filler2[7];
14825cf1a30Sjl 	/*
14925cf1a30Sjl 	 * Specification of degeneracy operation of POST by XSCF
15025cf1a30Sjl 	 *	0x00: off
15125cf1a30Sjl 	 *	0x20: component
15225cf1a30Sjl 	 *	0x40: board
15325cf1a30Sjl 	 *	0x80: system
15425cf1a30Sjl 	 */
15525cf1a30Sjl 	uint8_t		dinf_config_policy;
15625cf1a30Sjl 	/*
15725cf1a30Sjl 	 * Specification of diagnosis operation of POST by XSCF
15825cf1a30Sjl 	 *	0x00: off
15925cf1a30Sjl 	 *	0x20: min
16025cf1a30Sjl 	 *	0x40: max
16125cf1a30Sjl 	 */
16225cf1a30Sjl 	uint8_t		dinf_diag_level;
16325cf1a30Sjl 	/*
16425cf1a30Sjl 	 * Specification of boot operation of OBP by XSCF
16525cf1a30Sjl 	 *	0x00: It follows other settings.
16625cf1a30Sjl 	 *	0x80: Auto boot is not done.
16725cf1a30Sjl 	 */
16825cf1a30Sjl 	uint8_t		dinf_boot_mode;
16925cf1a30Sjl 	uint8_t		dinf_spare1[5];
17025cf1a30Sjl 	int64_t		dinf_cpu_start_time;	/* seconds since the Epoch */
17125cf1a30Sjl 	char		dinf_banner_name[64];	/* system banner string */
17225cf1a30Sjl 	char		dinf_platform_token[64]; /* platform name */
17325cf1a30Sjl 	uint32_t	dinf_floating_board_bitmap;	/* bit 0 = SB0 ... */
174*68ac2337Sjl 	char		dinf_chassis_sn[16];
175*68ac2337Sjl 	uint32_t	dinf_brand_control;
176*68ac2337Sjl 	uint32_t	dinf_spare2[7];
17725cf1a30Sjl 	uint32_t	dinf_check_sum;
17825cf1a30Sjl } hwd_domain_info_t;
17925cf1a30Sjl 
18025cf1a30Sjl /*
18125cf1a30Sjl  * CPU Strand
18225cf1a30Sjl  */
18325cf1a30Sjl typedef struct {
18425cf1a30Sjl 	hwd_stat_t	cpu_status;
18525cf1a30Sjl 	char		cpu_component_name[32];
18625cf1a30Sjl 	uint16_t	cpu_cpuid;		/* 0x0000, 0x0001, ... 0x01ff */
18725cf1a30Sjl 	uint16_t	cpu_filler;
18825cf1a30Sjl 	uint32_t	cpu_spare[6];
18925cf1a30Sjl } hwd_cpu_t;
19025cf1a30Sjl 
19125cf1a30Sjl /*
19225cf1a30Sjl  * CPU Core
19325cf1a30Sjl  */
19425cf1a30Sjl typedef struct {
19525cf1a30Sjl 	hwd_stat_t	core_status;
19625cf1a30Sjl 	char		core_component_name[32];
19725cf1a30Sjl 	uint32_t	core_filler1;
19825cf1a30Sjl 	uint64_t	core_frequency;			/* Hz */
19925cf1a30Sjl 	uint64_t	core_config;			/* bus config reg */
20025cf1a30Sjl 	uint64_t	core_version;			/* processor VER */
20125cf1a30Sjl 	uint16_t	core_manufacturer;		/* VER.manuf */
20225cf1a30Sjl 	uint16_t	core_implementation;		/* VER.impl */
20325cf1a30Sjl 	uint8_t		core_mask;			/* VER.mask */
20425cf1a30Sjl 	uint8_t		core_filler2[3];
20525cf1a30Sjl 	uint32_t	core_l1_icache_size;
20625cf1a30Sjl 	uint16_t	core_l1_icache_line_size;
20725cf1a30Sjl 	uint16_t	core_l1_icache_associativity;
20825cf1a30Sjl 	uint32_t	core_num_itlb_entries;
20925cf1a30Sjl 	uint32_t	core_l1_dcache_size;
21025cf1a30Sjl 	uint16_t	core_l1_dcache_line_size;
21125cf1a30Sjl 	uint16_t	core_l1_dcache_associativity;
21225cf1a30Sjl 	uint32_t	core_num_dtlb_entries;
21325cf1a30Sjl 	uint32_t	core_spare1[4];
21425cf1a30Sjl 	uint32_t	core_l2_cache_size;
21525cf1a30Sjl 	uint16_t	core_l2_cache_line_size;
21625cf1a30Sjl 	uint16_t	core_l2_cache_associativity;
21725cf1a30Sjl 	uint32_t	core_l2_cache_sharing;		/* bit N:coreN */
21825cf1a30Sjl 	uint32_t	core_spare2[5];
21925cf1a30Sjl 	hwd_cpu_t	core_cpus[HWD_CPUS_PER_CORE];
22025cf1a30Sjl 	uint32_t	core_spare3[4];
22125cf1a30Sjl } hwd_core_t;
22225cf1a30Sjl 
22325cf1a30Sjl /*
22425cf1a30Sjl  * CPU Chip
22525cf1a30Sjl  */
22625cf1a30Sjl typedef struct {
22725cf1a30Sjl 	hwd_stat_t	chip_status;
22825cf1a30Sjl 	char		chip_component_name[32]; /* example: "CPU#x" */
22925cf1a30Sjl 	char		chip_fru_name[32];	/* example: "CPU#x" */
23025cf1a30Sjl 	char		chip_compatible[32];	/* example: "FJSV,SPARC64-VI" */
23125cf1a30Sjl 	/*
23225cf1a30Sjl 	 * Jupiter Bus Device ID
23325cf1a30Sjl 	 * 0x0400, 0x0408, ... , 0x05f8
23425cf1a30Sjl 	 */
23525cf1a30Sjl 	uint16_t	chip_portid;
23625cf1a30Sjl 	uint16_t	chip_filler;
23725cf1a30Sjl 	uint32_t	chip_spare1[6];
23825cf1a30Sjl 	hwd_core_t	chip_cores[HWD_CORES_PER_CPU_CHIP];
23925cf1a30Sjl 	uint32_t	chip_spare2[4];
24025cf1a30Sjl } hwd_cpu_chip_t;
24125cf1a30Sjl 
24225cf1a30Sjl /*
24325cf1a30Sjl  * SC
24425cf1a30Sjl  */
24525cf1a30Sjl typedef struct {
24625cf1a30Sjl 	hwd_stat_t	sc_status;
24725cf1a30Sjl 	uint32_t	sc_filler;
24825cf1a30Sjl 	/*
24925cf1a30Sjl 	 * Top address of SC registers in this XSB
25025cf1a30Sjl 	 */
25125cf1a30Sjl 	uint64_t	sc_register_address;
25225cf1a30Sjl } hwd_sc_t;
25325cf1a30Sjl 
25425cf1a30Sjl /*
25525cf1a30Sjl  * Bank
25625cf1a30Sjl  */
25725cf1a30Sjl typedef struct {
25825cf1a30Sjl 	hwd_stat_t	bank_status;
25925cf1a30Sjl 	hwd_stat_t	bank_cs_status[2];	/* DIMM pair status */
26025cf1a30Sjl 	uint32_t	bank_filler1;
26125cf1a30Sjl 	uint64_t	bank_register_address;	/* address of mem patrol regs */
26225cf1a30Sjl 	uint8_t		bank_mac_ocd;		/* calibrated MAC OCD value */
26325cf1a30Sjl 	uint8_t		bank_filler2[3];
26425cf1a30Sjl 	uint8_t		bank_dimm_ocd[4][2];	/* calibrated DIMM OCD value */
26525cf1a30Sjl 	uint32_t	bank_tune;		/* for POST use */
26625cf1a30Sjl 	uint32_t	bank_spare[2];
26725cf1a30Sjl } hwd_bank_t;
26825cf1a30Sjl 
26925cf1a30Sjl /*
27025cf1a30Sjl  * Chunk
27125cf1a30Sjl  */
27225cf1a30Sjl typedef struct {
27325cf1a30Sjl 	uint64_t	chnk_start_address;
27425cf1a30Sjl 	uint64_t	chnk_size;
27525cf1a30Sjl } hwd_chunk_t;
27625cf1a30Sjl 
27725cf1a30Sjl /*
27825cf1a30Sjl  * Dimm
27925cf1a30Sjl  */
28025cf1a30Sjl typedef struct {
28125cf1a30Sjl 	hwd_stat_t	dimm_status;
28225cf1a30Sjl 	uint32_t	dimm_filler1;
28325cf1a30Sjl 	uint64_t	dimm_capacity;			/* bytes */
28425cf1a30Sjl 	uint64_t	dimm_available_capacity;	/* bytes */
28525cf1a30Sjl 	uint8_t		dimm_rank;			/* 1 or 2 */
28625cf1a30Sjl 	uint8_t		dimm_filler2[7];
28725cf1a30Sjl 	char		dimm_component_name[32];	/* "MEM#xyz" */
28825cf1a30Sjl 	char		dimm_fru_name[32];		/* "MEM#xyz" */
28925cf1a30Sjl } hwd_dimm_t;
29025cf1a30Sjl 
29125cf1a30Sjl /*
29225cf1a30Sjl  * CS
29325cf1a30Sjl  */
29425cf1a30Sjl typedef struct {
29525cf1a30Sjl 	hwd_stat_t	cs_status;
29625cf1a30Sjl 	uint8_t		cs_number_of_dimms;
29725cf1a30Sjl 	uint8_t		cs_filler[3];
29825cf1a30Sjl 	uint64_t	cs_available_capacity;
29925cf1a30Sjl 	uint64_t	cs_dimm_capacity;
30025cf1a30Sjl 	uint8_t		cs_dimm_badd[8];   /* Value to initialize MAC by POST */
30125cf1a30Sjl 	uint16_t	cs_dimm_add[8];    /* Value to initialize MAC by POST */
30225cf1a30Sjl 	uint8_t		cs_pa_mac_table[64]; /* PA <-> MAC address conversion */
30325cf1a30Sjl } hwd_cs_t;
30425cf1a30Sjl 
30525cf1a30Sjl /*
30625cf1a30Sjl  * Memory
30725cf1a30Sjl  */
30825cf1a30Sjl typedef struct {
30925cf1a30Sjl 	uint64_t	mem_start_address;	/* Memory start for this LSB */
31025cf1a30Sjl 	uint64_t	mem_size;		/* Memory size for this LSB */
31125cf1a30Sjl 	hwd_bank_t	mem_banks[HWD_BANKS_PER_CMU];
31225cf1a30Sjl 	/*
31325cf1a30Sjl 	 * Mirroring mode:
31425cf1a30Sjl 	 *	0x00 or 0x01
31525cf1a30Sjl 	 *	0x00 : not 'memory mirror mode'
31625cf1a30Sjl 	 *	0x01 : 'memory mirror mode'
31725cf1a30Sjl 	 */
31825cf1a30Sjl 	uint8_t		mem_mirror_mode;	/* mirroring mode */
31925cf1a30Sjl 	/*
32025cf1a30Sjl 	 * Memory configuration:
32125cf1a30Sjl 	 *	0x01 : 1 divided mode
32225cf1a30Sjl 	 *	0x02 : 2 divided mode
32325cf1a30Sjl 	 *	0x04 : 4 divided mode
32425cf1a30Sjl 	 *
32525cf1a30Sjl 	 * It is always set to 0x04 at the XSB mode.
32625cf1a30Sjl 	 */
32725cf1a30Sjl 	uint8_t		mem_division_mode;
32825cf1a30Sjl 	uint8_t		mem_piece_number;	/* 0-3 memory slot group used */
32925cf1a30Sjl 	uint8_t		mem_cs_interleave;	/* 1:cs interleave, 0:not */
33025cf1a30Sjl 	uint32_t	mem_filler[3];
33125cf1a30Sjl 	uint8_t		mem_available_bitmap[512];	/* for POST use */
33225cf1a30Sjl 	uint8_t		mem_degrade_bitmap[16384];	/* for POST use */
33325cf1a30Sjl 	hwd_chunk_t	mem_chunks[HWD_MAX_MEM_CHUNKS];
33425cf1a30Sjl 	hwd_dimm_t	mem_dimms[HWD_DIMMS_PER_CMU];
33525cf1a30Sjl 	hwd_cs_t	mem_cs[2];
33625cf1a30Sjl } hwd_memory_t;
33725cf1a30Sjl 
33825cf1a30Sjl typedef struct {
33925cf1a30Sjl 	hwd_stat_t	scf_status;
34025cf1a30Sjl 	char		scf_component_name[32];		/* "SCFI#z" */
34125cf1a30Sjl } hwd_scf_interface_t;
34225cf1a30Sjl 
34325cf1a30Sjl typedef struct {
34425cf1a30Sjl 	hwd_stat_t	tty_status;
34525cf1a30Sjl 	char		tty_component_name[32];		/* "TTY#z" */
34625cf1a30Sjl } hwd_tty_t;
34725cf1a30Sjl 
34825cf1a30Sjl typedef struct {
34925cf1a30Sjl 	uint8_t		fver_major;		/* firmware major version */
35025cf1a30Sjl 	uint8_t		fver_minor;		/* firmware minor version */
35125cf1a30Sjl 	uint8_t		fver_local;		/* firmware local version */
35225cf1a30Sjl 	uint8_t		fver_filler;
35325cf1a30Sjl } hwd_fmem_version_t;
35425cf1a30Sjl 
35525cf1a30Sjl typedef struct {
35625cf1a30Sjl 	hwd_stat_t		fmem_status;	/* status of flash */
35725cf1a30Sjl 	char			fmem_component_name[32];
35825cf1a30Sjl 	uint8_t			fmem_used;	/* non-zero: fmem is used */
35925cf1a30Sjl 	uint8_t			fmem_filler[3];
36025cf1a30Sjl 	hwd_fmem_version_t	fmem_version;
36125cf1a30Sjl 	uint32_t		fmem_spare;
36225cf1a30Sjl } hwd_fmem_t;
36325cf1a30Sjl 
36425cf1a30Sjl /*
36525cf1a30Sjl  * CMU CH
36625cf1a30Sjl  */
36725cf1a30Sjl typedef struct {
36825cf1a30Sjl 	hwd_stat_t		chan_status;
36925cf1a30Sjl 	/*
37025cf1a30Sjl 	 * CMU_CH port ID
37125cf1a30Sjl 	 *	LSB0 is 0x0008, LSB1 is 0x0018, ... , LSB15 is 0x00f8
37225cf1a30Sjl 	 */
37325cf1a30Sjl 	uint16_t		chan_portid;
37425cf1a30Sjl 	uint16_t		chan_filler;
37525cf1a30Sjl 	char			chan_component_name[32];	/* "U2P#z" */
37625cf1a30Sjl 	hwd_scf_interface_t	chan_scf_interface;
37725cf1a30Sjl 	hwd_tty_t		chan_serial;
37825cf1a30Sjl 	hwd_fmem_t		chan_fmem[2];
37925cf1a30Sjl } hwd_cmu_chan_t;
38025cf1a30Sjl 
38125cf1a30Sjl /*
38225cf1a30Sjl  * CMU
38325cf1a30Sjl  */
38425cf1a30Sjl typedef struct {
38525cf1a30Sjl 	char		cmu_component_name[32];	/* example: "CxS0y" */
38625cf1a30Sjl 	char		cmu_fru_name[32];	/* example: "Cabinet#x-CMU#y" */
38725cf1a30Sjl 
38825cf1a30Sjl 	hwd_cpu_chip_t	cmu_cpu_chips[HWD_CPU_CHIPS_PER_CMU];	/* CPU */
38925cf1a30Sjl 	hwd_sc_t	cmu_scs[HWD_SCS_PER_CMU];		/* SC */
39025cf1a30Sjl 	hwd_memory_t	cmu_memory;				/* Memory */
39125cf1a30Sjl 	hwd_cmu_chan_t	cmu_ch;					/* CMU CH */
39225cf1a30Sjl 	uint32_t	cmu_spare[32];
39325cf1a30Sjl } hwd_cmu_t;
39425cf1a30Sjl 
39525cf1a30Sjl typedef struct {
39625cf1a30Sjl 	hwd_stat_t	slot_status;
39725cf1a30Sjl 	char		slot_name[16];
39825cf1a30Sjl } hwd_slot_t;
39925cf1a30Sjl 
40025cf1a30Sjl /*
40125cf1a30Sjl  * IO Boat
40225cf1a30Sjl  */
40325cf1a30Sjl typedef struct {
40425cf1a30Sjl 	hwd_stat_t	iob_status;
40525cf1a30Sjl 	char		iob_component_name[32];
40625cf1a30Sjl 	char		iob_fru_name[32];
40725cf1a30Sjl 	/*
40825cf1a30Sjl 	 * IO_Boat type
40925cf1a30Sjl 	 *	0x01 : PCI-X Slot Type
41025cf1a30Sjl 	 *	0x02 : PCI Express Slot Type
41125cf1a30Sjl 	 */
41225cf1a30Sjl 	uint32_t	iob_type;		/* PCI-X or PCI Express */
41325cf1a30Sjl 	uint64_t	iob_io_box_info;	/* location of I/O */
41425cf1a30Sjl 	/*
41525cf1a30Sjl 	 * Information of switch on IO_boat
41625cf1a30Sjl 	 * use only switch_status[0] when PCI-X type IO_boat
41725cf1a30Sjl 	 */
41825cf1a30Sjl 	hwd_stat_t	iob_switch_status[3];	/* PCIE switch statuses */
41925cf1a30Sjl 	/*
42025cf1a30Sjl 	 * Information of bridge on IO_boat
42125cf1a30Sjl 	 * use only when PCI-X type IO_boat
42225cf1a30Sjl 	 */
42325cf1a30Sjl 	hwd_stat_t	iob_bridge_status[3];	/* PCIX bridge statuses */
42425cf1a30Sjl 	hwd_slot_t	iob_slot[6];		/* PCI slot names */
42525cf1a30Sjl 	uint32_t	iob_spare[8];
42625cf1a30Sjl } hwd_io_boat_t;
42725cf1a30Sjl 
42825cf1a30Sjl /* IOU PCI Express Slot */
42925cf1a30Sjl typedef struct {
43025cf1a30Sjl 	uint32_t	iou_type;    /* 0: empty, 1: card, 2: IO boat */
43125cf1a30Sjl 	hwd_slot_t	iou_slot;
43225cf1a30Sjl 	hwd_io_boat_t	iou_io_boat;
43325cf1a30Sjl } hwd_iou_slot_t;
43425cf1a30Sjl 
43525cf1a30Sjl typedef struct {
43625cf1a30Sjl 	hwd_stat_t	ff_onb_switch_status;
43725cf1a30Sjl 	uint8_t		ff_onb_filler[64];
43825cf1a30Sjl 	hwd_stat_t	ff_onb_bridge_status;
43925cf1a30Sjl 	hwd_stat_t	ff_onb_sas_status;
44025cf1a30Sjl 	hwd_stat_t	ff_onb_gbe_status;
44125cf1a30Sjl 	hwd_iou_slot_t	ff_onb_slot;
44225cf1a30Sjl 	hwd_slot_t	ff_onb_xslot;
44325cf1a30Sjl } hwd_ff_onboard_t;
44425cf1a30Sjl 
44525cf1a30Sjl typedef struct {
44625cf1a30Sjl 	hwd_stat_t	ioua_status; /* IOUA status */
44725cf1a30Sjl 	char		ioua_component_name[32];
44825cf1a30Sjl 	char		ioua_fru_name[32];
44925cf1a30Sjl 	hwd_stat_t	ioua_bridge_status;
45025cf1a30Sjl 	hwd_stat_t	ioua_sas_status;
45125cf1a30Sjl 	hwd_stat_t	ioua_gbe_status;
45225cf1a30Sjl } hwd_ioua_t;
45325cf1a30Sjl 
45425cf1a30Sjl typedef struct {
45525cf1a30Sjl 	uint8_t		iou_desc_filler[80];
45625cf1a30Sjl 	hwd_iou_slot_t	iou_desc_slot;
45725cf1a30Sjl } hwd_iou_slot_desc_t;
45825cf1a30Sjl 
45925cf1a30Sjl typedef struct {
46025cf1a30Sjl 	hwd_stat_t	leaf_status;
46125cf1a30Sjl 	uint16_t	leaf_port_id;		/* portid (logical leaf id) */
46225cf1a30Sjl 	uint8_t		leaf_filler[6];
46325cf1a30Sjl 	uint32_t	leaf_slot_type;		/* card or boat */
46425cf1a30Sjl 	union {
46525cf1a30Sjl 		hwd_ff_onboard_t	leaf_ff_onboard;
46625cf1a30Sjl 		hwd_ioua_t		leaf_ioua;
46725cf1a30Sjl 		hwd_iou_slot_desc_t	leaf_iou_slot;
46825cf1a30Sjl 		uint8_t			leaf_spare[448];
46925cf1a30Sjl 	} leaf_u;
47025cf1a30Sjl 	uint64_t	leaf_cfgio_offset;	/* config space offset */
47125cf1a30Sjl 	uint64_t	leaf_cfgio_size;	/* config space size */
47225cf1a30Sjl 	uint64_t	leaf_mem32_offset;	/* offset of mem32 area */
47325cf1a30Sjl 	uint64_t	leaf_mem32_size;	/* size of mem32 area */
47425cf1a30Sjl 	uint64_t	leaf_mem64_offset;	/* offset of mem64 area */
47525cf1a30Sjl 	uint64_t	leaf_mem64_size;	/* size of mem64 area */
47625cf1a30Sjl } hwd_leaf_t;
47725cf1a30Sjl 
47825cf1a30Sjl /*
47925cf1a30Sjl  * PCI CH
48025cf1a30Sjl  */
48125cf1a30Sjl typedef struct {
48225cf1a30Sjl 	hwd_stat_t	pci_status;		/* PCI CH status */
48325cf1a30Sjl 	char		pci_component_name[32];
48425cf1a30Sjl 	char		pci_fru_name[32];
48525cf1a30Sjl 	uint8_t		pci_filler[12];
48625cf1a30Sjl 	hwd_leaf_t	pci_leaf[HWD_LEAVES_PER_PCI_CHANNEL];
48725cf1a30Sjl } hwd_pci_ch_t;
48825cf1a30Sjl 
48925cf1a30Sjl /*
49025cf1a30Sjl  * System Board
49125cf1a30Sjl  */
49225cf1a30Sjl typedef struct {
49325cf1a30Sjl 	/*
49425cf1a30Sjl 	 * SB
49525cf1a30Sjl 	 */
49625cf1a30Sjl 	hwd_stat_t	sb_status;
49725cf1a30Sjl 	uint8_t		sb_mode;		/* 0:PSB 1:XSB */
49825cf1a30Sjl 	uint8_t		sb_psb_number;		/* PSB number for this LSB */
49925cf1a30Sjl 	uint8_t		sb_filler1[10];
50025cf1a30Sjl 
50125cf1a30Sjl 	hwd_cmu_t	sb_cmu;				/* CMU */
50225cf1a30Sjl 
50325cf1a30Sjl 	hwd_pci_ch_t	sb_pci_ch[HWD_PCI_CHANNELS_PER_SB]; /* PCI CH */
50425cf1a30Sjl 
50525cf1a30Sjl 	uint32_t	sb_spare[31];
50625cf1a30Sjl 	uint32_t	sb_check_sum;
50725cf1a30Sjl } hwd_sb_t;
50825cf1a30Sjl 
50925cf1a30Sjl #define	HWD_DATA_SIZE	(36 * 1024)   /* Size of HWD data from SCF */
51025cf1a30Sjl 
51125cf1a30Sjl #ifdef	__cplusplus
51225cf1a30Sjl }
51325cf1a30Sjl #endif
51425cf1a30Sjl 
51525cf1a30Sjl #endif	/* _SYS_OPL_HWDESC_H */
516