125cf1a30Sjl /* 225cf1a30Sjl * CDDL HEADER START 325cf1a30Sjl * 425cf1a30Sjl * The contents of this file are subject to the terms of the 525cf1a30Sjl * Common Development and Distribution License (the "License"). 625cf1a30Sjl * You may not use this file except in compliance with the License. 725cf1a30Sjl * 825cf1a30Sjl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 925cf1a30Sjl * or http://www.opensolaris.org/os/licensing. 1025cf1a30Sjl * See the License for the specific language governing permissions 1125cf1a30Sjl * and limitations under the License. 1225cf1a30Sjl * 1325cf1a30Sjl * When distributing Covered Code, include this CDDL HEADER in each 1425cf1a30Sjl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1525cf1a30Sjl * If applicable, add the following below this CDDL HEADER, with the 1625cf1a30Sjl * fields enclosed by brackets "[]" replaced with your own identifying 1725cf1a30Sjl * information: Portions Copyright [yyyy] [name of copyright owner] 1825cf1a30Sjl * 1925cf1a30Sjl * CDDL HEADER END 2025cf1a30Sjl */ 2125cf1a30Sjl /* 22*601c2e1eSdhain * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2325cf1a30Sjl * Use is subject to license terms. 2425cf1a30Sjl */ 2525cf1a30Sjl 2625cf1a30Sjl #ifndef _SYS_MC_OPL_H 2725cf1a30Sjl #define _SYS_MC_OPL_H 2825cf1a30Sjl 2925cf1a30Sjl #pragma ident "%Z%%M% %I% %E% SMI" 3025cf1a30Sjl 3125cf1a30Sjl #ifdef __cplusplus 3225cf1a30Sjl extern "C" { 3325cf1a30Sjl #endif 3425cf1a30Sjl 3525cf1a30Sjl #include <sys/note.h> 3625cf1a30Sjl 3725cf1a30Sjl #ifdef DEBUG 3825cf1a30Sjl #define MC_LOG if (oplmc_debug) printf 3925cf1a30Sjl extern int oplmc_debug; 4025cf1a30Sjl #else 4125cf1a30Sjl #define MC_LOG _NOTE(CONSTANTCONDITION) if (0) printf 4225cf1a30Sjl #endif 4325cf1a30Sjl 440cc8ae86Sav #define MC_PATROL_INTERVAL_SEC 10 450cc8ae86Sav 460cc8ae86Sav #define MC_POLL_EXIT 0x01 470cc8ae86Sav 4825cf1a30Sjl /* 4925cf1a30Sjl * load/store MAC register 5025cf1a30Sjl */ 5125cf1a30Sjl extern uint32_t mc_ldphysio(uint64_t); 5225cf1a30Sjl extern void mc_stphysio(uint64_t, uint32_t); 5325cf1a30Sjl #define LD_MAC_REG(paddr) mc_ldphysio(paddr) 5425cf1a30Sjl #define ST_MAC_REG(paddr, data) mc_stphysio((paddr), (data)) 5525cf1a30Sjl 5625cf1a30Sjl #define BANKNUM_PER_SB 8 5725cf1a30Sjl 580cc8ae86Sav typedef struct { 590cc8ae86Sav uint32_t cs_num; 600cc8ae86Sav uint32_t cs_status; 610cc8ae86Sav uint32_t cs_avail_hi; 620cc8ae86Sav uint32_t cs_avail_low; 630cc8ae86Sav uint32_t dimm_capa_hi; 640cc8ae86Sav uint32_t dimm_capa_low; 650cc8ae86Sav uint32_t ndimms; 660cc8ae86Sav } cs_status_t; 670cc8ae86Sav 6825cf1a30Sjl typedef struct scf_log { 6925cf1a30Sjl struct scf_log *sl_next; 7025cf1a30Sjl int sl_bank; 7125cf1a30Sjl uint32_t sl_err_add; 7225cf1a30Sjl uint32_t sl_err_log; 7325cf1a30Sjl } scf_log_t; 7425cf1a30Sjl 750cc8ae86Sav /* 760cc8ae86Sav * Current max serial number size is 12, but keep enough room 770cc8ae86Sav * to accomodate any future changes. 780cc8ae86Sav * 790cc8ae86Sav * Current max part number size is 18 + 18(Sun's partnumber + FJ's partnumber), 800cc8ae86Sav * but keep enough room to accomodate any future changes. 810cc8ae86Sav */ 820cc8ae86Sav #define MCOPL_MAX_DIMMNAME 3 830cc8ae86Sav #define MCOPL_MAX_SERIAL 20 840cc8ae86Sav #define MCOPL_MAX_PARTNUM 44 850cc8ae86Sav #define MCOPL_MAX_SERIALID (MCOPL_MAX_SERIAL + MCOPL_MAX_PARTNUM) 860cc8ae86Sav 870cc8ae86Sav typedef struct mc_dimm_info { 880cc8ae86Sav struct mc_dimm_info *md_next; 890cc8ae86Sav char md_dimmname[MCOPL_MAX_DIMMNAME + 1]; 900cc8ae86Sav char md_serial[MCOPL_MAX_SERIAL + 1]; 910cc8ae86Sav char md_partnum[MCOPL_MAX_PARTNUM + 1]; 920cc8ae86Sav } mc_dimm_info_t; 930cc8ae86Sav 94*601c2e1eSdhain typedef struct mc_retry_info { 95*601c2e1eSdhain struct mc_retry_info *ri_next; 96*601c2e1eSdhain #define RETRY_STATE_PENDING 0 97*601c2e1eSdhain #define RETRY_STATE_ACTIVE 1 98*601c2e1eSdhain #define RETRY_STATE_REWRITE 2 99*601c2e1eSdhain int ri_state; 100*601c2e1eSdhain uint32_t ri_addr; 101*601c2e1eSdhain } mc_retry_info_t; 102*601c2e1eSdhain 10325cf1a30Sjl typedef struct mc_opl_state { 10425cf1a30Sjl struct mc_opl_state *next; 10525cf1a30Sjl dev_info_t *mc_dip; 10625cf1a30Sjl uint32_t mc_status; 10725cf1a30Sjl #define MC_POLL_RUNNING 0x1 10825cf1a30Sjl #define MC_SOFT_SUSPENDED 0x2 /* suspended by DR */ 10925cf1a30Sjl #define MC_DRIVER_SUSPENDED 0x4 /* DDI_SUSPEND */ 1100cc8ae86Sav #define MC_MEMORYLESS 0x8 11125cf1a30Sjl uint32_t mc_board_num; /* board# */ 112aeb241b2Sav uint32_t mc_phys_board_num; /* physical board# */ 11325cf1a30Sjl uint64_t mc_start_address; /* sb-mem-ranges */ 11425cf1a30Sjl uint64_t mc_size; 11525cf1a30Sjl struct mc_bank { 11625cf1a30Sjl uint32_t mcb_status; 11725cf1a30Sjl #define BANK_INSTALLED 0x80000000 11825cf1a30Sjl #define BANK_MIRROR_MODE 0x40000000 /* 0: normal 1: mirror */ 119*601c2e1eSdhain #define BANK_REWRITE_MODE 0x10000000 120*601c2e1eSdhain 12125cf1a30Sjl #define BANK_PTRL_RUNNING 0x00000001 122*601c2e1eSdhain 123*601c2e1eSdhain #define MC_RETRY_COUNT 2 124*601c2e1eSdhain mc_retry_info_t mcb_retry_infos[MC_RETRY_COUNT]; 125*601c2e1eSdhain mc_retry_info_t *mcb_retry_freelist; 126*601c2e1eSdhain mc_retry_info_t *mcb_retry_pending; 127*601c2e1eSdhain mc_retry_info_t *mcb_active; 128*601c2e1eSdhain int mcb_rewrite_count; 129*601c2e1eSdhain 13025cf1a30Sjl uint64_t mcb_reg_base; 13125cf1a30Sjl uint32_t mcb_ptrl_cntl; 13225cf1a30Sjl } mc_bank[BANKNUM_PER_SB]; 13325cf1a30Sjl uchar_t mc_trans_table[2][64]; /* csX-mac-pa-trans-table */ 13425cf1a30Sjl kmutex_t mc_lock; 1350cc8ae86Sav scf_log_t *mc_scf_log[BANKNUM_PER_SB]; 1360cc8ae86Sav scf_log_t *mc_scf_log_tail[BANKNUM_PER_SB]; 1370cc8ae86Sav int mc_scf_total[BANKNUM_PER_SB]; 13825cf1a30Sjl struct memlist *mlist; 13925cf1a30Sjl int mc_scf_retry[BANKNUM_PER_SB]; 14025cf1a30Sjl int mc_last_error; 1410cc8ae86Sav /* number of times memory scanned */ 1420cc8ae86Sav uint64_t mc_period[BANKNUM_PER_SB]; 1430cc8ae86Sav uint32_t mc_speed; 1440cc8ae86Sav int mc_speedup_period[BANKNUM_PER_SB]; 1450cc8ae86Sav int mc_tick_left; 1460cc8ae86Sav mc_dimm_info_t *mc_dimm_list; 14725cf1a30Sjl } mc_opl_t; 14825cf1a30Sjl 14925cf1a30Sjl #define IS_MIRROR(mcp, bn) ((mcp)->mc_bank[bn].mcb_status\ 15025cf1a30Sjl & BANK_MIRROR_MODE) 15125cf1a30Sjl typedef struct mc_addr { 15225cf1a30Sjl int ma_bd; /* board number */ 153aeb241b2Sav int ma_phys_bd; /* phyiscal board number */ 15425cf1a30Sjl int ma_bank; /* bank number */ 15525cf1a30Sjl uint32_t ma_dimm_addr; /* DIMM address (same format as ERR_ADD) */ 15625cf1a30Sjl } mc_addr_t; 15725cf1a30Sjl 158738dd194Shyw typedef struct mc_rsaddr_info { /* patrol restart address/info */ 159738dd194Shyw struct mc_addr mi_restartaddr; 16025cf1a30Sjl int mi_valid; 161738dd194Shyw int mi_injectrestart; 162738dd194Shyw } mc_rsaddr_info_t; 16325cf1a30Sjl 16425cf1a30Sjl typedef struct mc_flt_stat { 16525cf1a30Sjl uint32_t mf_type; /* fault type */ 1660cc8ae86Sav #define FLT_TYPE_INTERMITTENT_CE 0x0001 1670cc8ae86Sav #define FLT_TYPE_PERMANENT_CE 0x0002 1680cc8ae86Sav #define FLT_TYPE_UE 0x0003 1690cc8ae86Sav #define FLT_TYPE_SUE 0x0004 1700cc8ae86Sav #define FLT_TYPE_MUE 0x0005 1710cc8ae86Sav #define FLT_TYPE_CMPE 0x0006 17225cf1a30Sjl uint32_t mf_cntl; /* MAC_BANKm_PTRL_CNTL Register */ 17325cf1a30Sjl uint32_t mf_err_add; /* MAC_BANKm_{PTRL|MI}_ERR_ADD Register */ 17425cf1a30Sjl uint32_t mf_err_log; /* MAC_BANKm_{PTRL|MI}_ERR_LOG Register */ 17525cf1a30Sjl uint32_t mf_synd; 17625cf1a30Sjl uchar_t mf_errlog_valid; 17725cf1a30Sjl uchar_t mf_dimm_slot; 17825cf1a30Sjl uchar_t mf_dram_place; 17925cf1a30Sjl uint64_t mf_flt_paddr; /* faulty physical address */ 18025cf1a30Sjl mc_addr_t mf_flt_maddr; /* faulty DIMM address */ 18125cf1a30Sjl } mc_flt_stat_t; 18225cf1a30Sjl 18325cf1a30Sjl typedef struct mc_aflt { 18425cf1a30Sjl uint64_t mflt_id; /* gethrtime() at time of fault */ 18525cf1a30Sjl mc_opl_t *mflt_mcp; /* mc-opl structure */ 18625cf1a30Sjl char *mflt_erpt_class; /* ereport class name */ 18725cf1a30Sjl int mflt_is_ptrl; /* detected by PTRL or MI */ 18825cf1a30Sjl int mflt_nflts; /* 1 or 2 */ 18925cf1a30Sjl int mflt_pr; /* page retire flags */ 19025cf1a30Sjl mc_flt_stat_t *mflt_stat[2]; /* fault status */ 19125cf1a30Sjl } mc_aflt_t; 19225cf1a30Sjl 19325cf1a30Sjl #define MAC_PTRL_STAT(mcp, i) (mcp->mc_bank[i].mcb_reg_base) 19425cf1a30Sjl #define MAC_PTRL_CNTL(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x10) 19525cf1a30Sjl #define MAC_PTRL_ERR_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x20) 19625cf1a30Sjl #define MAC_PTRL_ERR_LOG(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x24) 19725cf1a30Sjl #define MAC_MI_ERR_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x28) 19825cf1a30Sjl #define MAC_MI_ERR_LOG(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x2c) 19925cf1a30Sjl #define MAC_STATIC_ERR_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x30) 20025cf1a30Sjl #define MAC_STATIC_ERR_LOG(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x34) 20125cf1a30Sjl #define MAC_RESTART_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x40) 20225cf1a30Sjl #define MAC_REWRITE_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x44) 20325cf1a30Sjl #define MAC_EG_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x48) 20425cf1a30Sjl #define MAC_EG_CNTL(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x4c) 20525cf1a30Sjl #define MAC_MIRR(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x50) 20625cf1a30Sjl 20725cf1a30Sjl /* use PA[37:6] */ 20825cf1a30Sjl #define MAC_RESTART_PA(pa) ((pa >> 6) & 0xffffffff) 20925cf1a30Sjl /* 21025cf1a30Sjl * MAC_BANKm_PTRL_STAT_Register 21125cf1a30Sjl */ 21225cf1a30Sjl #define MAC_STAT_PTRL_CE 0x00000020 21325cf1a30Sjl #define MAC_STAT_PTRL_UE 0x00000010 21425cf1a30Sjl #define MAC_STAT_PTRL_CMPE 0x00000008 21525cf1a30Sjl #define MAC_STAT_MI_CE 0x00000004 21625cf1a30Sjl #define MAC_STAT_MI_UE 0x00000002 21725cf1a30Sjl #define MAC_STAT_MI_CMPE 0x00000001 21825cf1a30Sjl 21925cf1a30Sjl #define MAC_STAT_PTRL_ERRS (MAC_STAT_PTRL_CE|MAC_STAT_PTRL_UE\ 22025cf1a30Sjl |MAC_STAT_PTRL_CMPE) 22125cf1a30Sjl #define MAC_STAT_MI_ERRS (MAC_STAT_MI_CE|MAC_STAT_MI_UE\ 22225cf1a30Sjl |MAC_STAT_MI_CMPE) 22325cf1a30Sjl 22425cf1a30Sjl /* 22525cf1a30Sjl * MAC_BANKm_PTRL_CTRL_Register 22625cf1a30Sjl */ 22725cf1a30Sjl #define MAC_CNTL_PTRL_START 0x80000000 22825cf1a30Sjl #define MAC_CNTL_USE_RESTART_ADD 0x40000000 22925cf1a30Sjl #define MAC_CNTL_PTRL_STOP 0x20000000 23025cf1a30Sjl #define MAC_CNTL_PTRL_INTERVAL 0x1c000000 23125cf1a30Sjl #define MAC_CNTL_PTRL_RESET 0x02000000 23225cf1a30Sjl #define MAC_CNTL_PTRL_STATUS 0x01000000 23325cf1a30Sjl #define MAC_CNTL_REW_REQ 0x00800000 23425cf1a30Sjl #define MAC_CNTL_REW_RESET 0x00400000 23525cf1a30Sjl #define MAC_CNTL_CS0_DEG_MODE 0x00200000 23625cf1a30Sjl #define MAC_CNTL_PTRL_CE 0x00008000 23725cf1a30Sjl #define MAC_CNTL_PTRL_UE 0x00004000 23825cf1a30Sjl #define MAC_CNTL_PTRL_CMPE 0x00002000 23925cf1a30Sjl #define MAC_CNTL_MI_CE 0x00001000 24025cf1a30Sjl #define MAC_CNTL_MI_UE 0x00000800 24125cf1a30Sjl #define MAC_CNTL_MI_CMPE 0x00000400 24225cf1a30Sjl #define MAC_CNTL_REW_CE 0x00000200 24325cf1a30Sjl #define MAC_CNTL_REW_UE 0x00000100 24425cf1a30Sjl #define MAC_CNTL_REW_END 0x00000080 24525cf1a30Sjl #define MAC_CNTL_PTRL_ADD_MAX 0x00000040 24625cf1a30Sjl #define MAC_CNTL_REW_CMPE 0x00000020 24725cf1a30Sjl 2480cc8ae86Sav #define MAC_CNTL_PTRL_ERR_SHIFT 13 2490cc8ae86Sav #define MAC_CNTL_MI_ERR_SHIFT 10 2500cc8ae86Sav 25125cf1a30Sjl #define MAC_CNTL_PTRL_PRESERVE_BITS (MAC_CNTL_PTRL_INTERVAL) 25225cf1a30Sjl 25325cf1a30Sjl #define MAC_CNTL_PTRL_ERRS (MAC_CNTL_PTRL_CE|MAC_CNTL_PTRL_UE\ 25425cf1a30Sjl |MAC_CNTL_PTRL_CMPE) 25525cf1a30Sjl #define MAC_CNTL_MI_ERRS (MAC_CNTL_MI_CE|MAC_CNTL_MI_UE\ 25625cf1a30Sjl |MAC_CNTL_MI_CMPE) 25725cf1a30Sjl #define MAC_CNTL_REW_ERRS (MAC_CNTL_REW_CE|MAC_CNTL_REW_CMPE|\ 25825cf1a30Sjl MAC_CNTL_REW_UE|MAC_CNTL_REW_END) 25925cf1a30Sjl #define MAC_CNTL_ALL_ERRS (MAC_CNTL_PTRL_ERRS|\ 26025cf1a30Sjl MAC_CNTL_MI_ERRS|MAC_CNTL_REW_ERRS) 26125cf1a30Sjl 26225cf1a30Sjl #define MAC_ERRLOG_SYND_SHIFT 16 26325cf1a30Sjl #define MAC_ERRLOG_SYND_MASK 0xffff 26425cf1a30Sjl #define MAC_ERRLOG_DIMMSLOT_SHIFT 13 26525cf1a30Sjl #define MAC_ERRLOG_DIMMSLOT_MASK 0x7 26625cf1a30Sjl #define MAC_ERRLOG_DRAM_PLACE_SHIFT 8 26725cf1a30Sjl #define MAC_ERRLOG_DRAM_PLACE_MASK 0x1f 26825cf1a30Sjl 26925cf1a30Sjl #define MAC_SET_ERRLOG_INFO(flt_stat) \ 27025cf1a30Sjl (flt_stat)->mf_errlog_valid = 1; \ 27125cf1a30Sjl (flt_stat)->mf_synd = ((flt_stat)->mf_err_log >> \ 27225cf1a30Sjl MAC_ERRLOG_SYND_SHIFT) & \ 27325cf1a30Sjl MAC_ERRLOG_SYND_MASK; \ 27425cf1a30Sjl (flt_stat)->mf_dimm_slot = ((flt_stat)->mf_err_log >> \ 27525cf1a30Sjl MAC_ERRLOG_DIMMSLOT_SHIFT) & \ 27625cf1a30Sjl MAC_ERRLOG_DIMMSLOT_MASK; \ 27725cf1a30Sjl (flt_stat)->mf_dram_place = ((flt_stat)->mf_err_log >> \ 27825cf1a30Sjl MAC_ERRLOG_DRAM_PLACE_SHIFT) & \ 27925cf1a30Sjl MAC_ERRLOG_DRAM_PLACE_MASK; 28025cf1a30Sjl 28125cf1a30Sjl extern void mc_write_cntl(mc_opl_t *, int, uint32_t); 28225cf1a30Sjl #define MAC_CMD(mcp, i, cmd) mc_write_cntl(mcp, i, cmd) 28325cf1a30Sjl 2840cc8ae86Sav #define MAC_PTRL_START(mcp, i) { if (!(ldphysio(MAC_PTRL_CNTL(mcp, i)) \ 2850cc8ae86Sav & MAC_CNTL_PTRL_START)) \ 2860cc8ae86Sav MAC_CMD((mcp), (i), MAC_CNTL_PTRL_START); } 2870cc8ae86Sav 28825cf1a30Sjl #define MAC_PTRL_START_ADD(mcp, i) MAC_CMD((mcp), (i),\ 28925cf1a30Sjl MAC_CNTL_PTRL_START|MAC_CNTL_USE_RESTART_ADD) 29025cf1a30Sjl #define MAC_PTRL_STOP(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_PTRL_STOP) 29125cf1a30Sjl #define MAC_PTRL_RESET(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_PTRL_RESET) 29225cf1a30Sjl #define MAC_REW_REQ(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_REW_REQ) 29325cf1a30Sjl #define MAC_REW_RESET(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_REW_RESET) 29425cf1a30Sjl #define MAC_CLEAR_ERRS(mcp, i, errs) MAC_CMD((mcp), (i), errs) 29525cf1a30Sjl #define MAC_CLEAR_ALL_ERRS(mcp, i) MAC_CMD((mcp), (i),\ 29625cf1a30Sjl MAC_CNTL_ALL_ERRS) 29725cf1a30Sjl #define MAC_CLEAR_MAX(mcp, i) \ 29825cf1a30Sjl MAC_CMD((mcp), (i), MAC_CNTL_PTRL_ADD_MAX) 29925cf1a30Sjl 30025cf1a30Sjl 30125cf1a30Sjl /* 30225cf1a30Sjl * MAC_BANKm_PTRL/MI_ERR_ADD/LOG_Register 30325cf1a30Sjl */ 30425cf1a30Sjl #define MAC_ERR_ADD_INVALID 0x80000000 30525cf1a30Sjl #define MAC_ERR_LOG_INVALID 0x00000080 30625cf1a30Sjl 30725cf1a30Sjl /* 30825cf1a30Sjl * MAC_BANKm_STATIC_ERR_ADD_Register 30925cf1a30Sjl */ 31025cf1a30Sjl #define MAC_STATIC_ERR_VLD 0x80000000 31125cf1a30Sjl 31225cf1a30Sjl /* 31325cf1a30Sjl * MAC_BANKm_MIRR_Register 31425cf1a30Sjl */ 31525cf1a30Sjl #define MAC_MIRR_MIRROR_MODE 0x80000000 31625cf1a30Sjl #define MAC_MIRR_BANK_EXCLUSIVE 0x40000000 31725cf1a30Sjl 31825cf1a30Sjl #define OPL_BOARD_MAX 16 31925cf1a30Sjl #define OPL_BANK_MAX 8 32025cf1a30Sjl 321*601c2e1eSdhain #define MC_SET_REWRITE_MODE(mcp, bank) \ 322*601c2e1eSdhain ((mcp)->mc_bank[bank].mcb_status |= BANK_REWRITE_MODE) 323*601c2e1eSdhain 324*601c2e1eSdhain #define MC_CLEAR_REWRITE_MODE(mcp, bank) \ 325*601c2e1eSdhain ((mcp)->mc_bank[bank].mcb_status &= ~BANK_REWRITE_MODE) 326*601c2e1eSdhain 327*601c2e1eSdhain #define MC_REWRITE_MODE(mcp, bank) \ 328*601c2e1eSdhain ((mcp)->mc_bank[bank].mcb_status & BANK_REWRITE_MODE) 329*601c2e1eSdhain 330*601c2e1eSdhain #define MC_REWRITE_ACTIVE(mcp, bank) \ 331*601c2e1eSdhain ((mcp)->mc_bank[bank].mcb_active) 332*601c2e1eSdhain 33325cf1a30Sjl /* 33425cf1a30Sjl * MAC_BANKm_EG_ADD_Register 33525cf1a30Sjl */ 33625cf1a30Sjl #define MAC_EG_ADD_MASK 0x7ffffffc 33725cf1a30Sjl /* 33825cf1a30Sjl * To set the EG_CNTL register, bit[26-25] and 33925cf1a30Sjl * bit[21-20] must be cleared. Then the other 34025cf1a30Sjl * control bit should be set. Then the bit[26-25] 34125cf1a30Sjl * and bit[21-20] should be set while other bits 34225cf1a30Sjl * should be the same as before. 34325cf1a30Sjl */ 34425cf1a30Sjl #define MAC_EG_CNTL_MASK 0x06300000 34525cf1a30Sjl 34625cf1a30Sjl #define MAC_EG_ADD_FIX 0x80000000 34725cf1a30Sjl #define MAC_EG_FORCE_DERR00 0x40000000 34825cf1a30Sjl #define MAC_EG_FORCE_DERR16 0x20000000 34925cf1a30Sjl #define MAC_EG_FORCE_DERR64 0x10000000 35025cf1a30Sjl #define MAC_EG_FORCE_DERR80 0x08000000 35125cf1a30Sjl #define MAC_EG_DERR_ALWAYS 0x02000000 35225cf1a30Sjl #define MAC_EG_DERR_ONCE 0x04000000 35325cf1a30Sjl #define MAC_EG_DERR_NOP 0x06000000 35425cf1a30Sjl #define MAC_EG_FORCE_READ00 0x00800000 35525cf1a30Sjl #define MAC_EG_FORCE_READ16 0x00400000 35625cf1a30Sjl #define MAC_EG_RDERR_ALWAYS 0x00100000 35725cf1a30Sjl #define MAC_EG_RDERR_ONCE 0x00200000 35825cf1a30Sjl #define MAC_EG_RDERR_NOP 0x00300000 35925cf1a30Sjl 36025cf1a30Sjl #define MAC_EG_SETUP_MASK 0xf9cfffff 36125cf1a30Sjl 36225cf1a30Sjl /* For MAC-PA translation */ 363738dd194Shyw #define MC_ADDRESS_BITS 40 36425cf1a30Sjl #define PA_BITS_FOR_MAC 39 36525cf1a30Sjl #define INDEX_OF_BANK_SUPPLEMENT_BIT 39 36625cf1a30Sjl #define MP_NONE 128 36725cf1a30Sjl #define MP_BANK_0 129 36825cf1a30Sjl #define MP_BANK_1 130 36925cf1a30Sjl #define MP_BANK_2 131 37025cf1a30Sjl 37125cf1a30Sjl #define CS_SHIFT 29 37225cf1a30Sjl #define MC_TT_ENTRIES 64 37325cf1a30Sjl #define MC_TT_CS 2 37425cf1a30Sjl 37525cf1a30Sjl 37625cf1a30Sjl /* export interface for error injection */ 37725cf1a30Sjl extern int mc_inject_error(int error_type, uint64_t pa, uint32_t flags); 37825cf1a30Sjl 37925cf1a30Sjl #define MC_INJECT_NOP 0x0 38025cf1a30Sjl #define MC_INJECT_INTERMITTENT_CE 0x1 38125cf1a30Sjl #define MC_INJECT_PERMANENT_CE 0x2 38225cf1a30Sjl #define MC_INJECT_UE 0x3 38325cf1a30Sjl #define MC_INJECT_INTERMITTENT_MCE 0x11 38425cf1a30Sjl #define MC_INJECT_PERMANENT_MCE 0x12 38525cf1a30Sjl #define MC_INJECT_SUE 0x13 38625cf1a30Sjl #define MC_INJECT_MUE 0x14 38725cf1a30Sjl #define MC_INJECT_CMPE 0x15 38825cf1a30Sjl 38925cf1a30Sjl #define MC_INJECT_MIRROR_MODE 0x10 39025cf1a30Sjl #define MC_INJECT_MIRROR(x) (x & MC_INJECT_MIRROR_MODE) 39125cf1a30Sjl 392cfb9e062Shyw #define MC_INJECT_FLAG_PREFETCH 0x1 393cfb9e062Shyw #define MC_INJECT_FLAG_NO_TRAP MC_INJECT_FLAG_PREFETCH 39425cf1a30Sjl #define MC_INJECT_FLAG_RESTART 0x2 39525cf1a30Sjl #define MC_INJECT_FLAG_POLL 0x4 39625cf1a30Sjl #define MC_INJECT_FLAG_RESET 0x8 39725cf1a30Sjl #define MC_INJECT_FLAG_OTHER 0x10 39825cf1a30Sjl #define MC_INJECT_FLAG_LD 0x20 39925cf1a30Sjl #define MC_INJECT_FLAG_ST 0x40 40025cf1a30Sjl #define MC_INJECT_FLAG_PATH 0x80 40125cf1a30Sjl 4020cc8ae86Sav #ifdef DEBUG 4030cc8ae86Sav 4040cc8ae86Sav #define MCI_NOP 0x0 4050cc8ae86Sav #define MCI_CE 0x1 4060cc8ae86Sav #define MCI_PERM_CE 0x2 4070cc8ae86Sav #define MCI_UE 0x3 4080cc8ae86Sav #define MCI_SHOW_ALL 0x4 4090cc8ae86Sav #define MCI_SHOW_NONE 0x5 4100cc8ae86Sav #define MCI_CMP 0x6 4110cc8ae86Sav #define MCI_ALLOC 0x7 4120cc8ae86Sav #define MCI_M_CE 0x8 4130cc8ae86Sav #define MCI_M_PCE 0x9 4140cc8ae86Sav #define MCI_M_UE 0xA 4150cc8ae86Sav #define MCI_SUSPEND 0xB 4160cc8ae86Sav #define MCI_RESUME 0xC 4170cc8ae86Sav 4180cc8ae86Sav #endif 4190cc8ae86Sav 42025cf1a30Sjl #ifdef __cplusplus 42125cf1a30Sjl } 42225cf1a30Sjl #endif 42325cf1a30Sjl 42425cf1a30Sjl #endif /* _SYS_MC_OPL_H */ 425