125cf1a30Sjl /* 225cf1a30Sjl * CDDL HEADER START 325cf1a30Sjl * 425cf1a30Sjl * The contents of this file are subject to the terms of the 525cf1a30Sjl * Common Development and Distribution License (the "License"). 625cf1a30Sjl * You may not use this file except in compliance with the License. 725cf1a30Sjl * 825cf1a30Sjl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 925cf1a30Sjl * or http://www.opensolaris.org/os/licensing. 1025cf1a30Sjl * See the License for the specific language governing permissions 1125cf1a30Sjl * and limitations under the License. 1225cf1a30Sjl * 1325cf1a30Sjl * When distributing Covered Code, include this CDDL HEADER in each 1425cf1a30Sjl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1525cf1a30Sjl * If applicable, add the following below this CDDL HEADER, with the 1625cf1a30Sjl * fields enclosed by brackets "[]" replaced with your own identifying 1725cf1a30Sjl * information: Portions Copyright [yyyy] [name of copyright owner] 1825cf1a30Sjl * 1925cf1a30Sjl * CDDL HEADER END 2025cf1a30Sjl */ 2125cf1a30Sjl /* 22*68ac2337Sjl * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2325cf1a30Sjl * Use is subject to license terms. 2425cf1a30Sjl */ 2525cf1a30Sjl 2625cf1a30Sjl #ifndef _SYS_DRMACH_H_ 2725cf1a30Sjl #define _SYS_DRMACH_H_ 2825cf1a30Sjl 2925cf1a30Sjl #pragma ident "%Z%%M% %I% %E% SMI" 3025cf1a30Sjl 3125cf1a30Sjl #ifdef __cplusplus 3225cf1a30Sjl extern "C" { 3325cf1a30Sjl #endif 3425cf1a30Sjl 3525cf1a30Sjl #ifndef _ASM 3625cf1a30Sjl #include <sys/types.h> 3725cf1a30Sjl #include <sys/memlist.h> 3825cf1a30Sjl #include <sys/processor.h> 3925cf1a30Sjl #include <sys/cpuvar.h> 4025cf1a30Sjl #include <sys/sbd_ioctl.h> 4125cf1a30Sjl #include <sys/sysevent.h> 4225cf1a30Sjl #include <sys/ddi.h> 4325cf1a30Sjl #include <sys/sunddi.h> 4425cf1a30Sjl #include <sys/sunndi.h> 4525cf1a30Sjl #include <sys/ddi_impldefs.h> 4625cf1a30Sjl #include <sys/pte.h> 4725cf1a30Sjl #include <sys/opl.h> 4825cf1a30Sjl #endif 4925cf1a30Sjl 5025cf1a30Sjl 5125cf1a30Sjl #define MAX_BOARDS plat_max_boards() 5225cf1a30Sjl #define MAX_CPU_UNITS_PER_BOARD plat_max_cpu_units_per_board() 5325cf1a30Sjl #define MAX_MEM_UNITS_PER_BOARD plat_max_mem_units_per_board() 5425cf1a30Sjl #define MAX_IO_UNITS_PER_BOARD plat_max_io_units_per_board() 5525cf1a30Sjl #define MAX_CMP_UNITS_PER_BOARD plat_max_cmp_units_per_board() 5625cf1a30Sjl /* 5725cf1a30Sjl * DR uses MAX_CORES_PER_CMP as number of virtual CPU within a CMP 5825cf1a30Sjl */ 5925cf1a30Sjl #define MAX_CORES_PER_CMP OPL_MAX_CPU_PER_CMP 6025cf1a30Sjl 6125cf1a30Sjl 6225cf1a30Sjl /* returned with drmach_board_find_devices callback */ 6325cf1a30Sjl #define DRMACH_DEVTYPE_CPU "cpu" 6425cf1a30Sjl #define DRMACH_DEVTYPE_MEM "memory" 6525cf1a30Sjl #define DRMACH_DEVTYPE_PCI "pci" 6625cf1a30Sjl 6725cf1a30Sjl #define FMEM_LOOP_START 1 6825cf1a30Sjl #define FMEM_LOOP_COPY_READY 2 6925cf1a30Sjl #define FMEM_LOOP_COPY_DONE 3 7025cf1a30Sjl #define FMEM_LOOP_FMEM_READY 4 7125cf1a30Sjl #define FMEM_LOOP_RENAME_DONE 5 7225cf1a30Sjl #define FMEM_LOOP_DONE 6 7325cf1a30Sjl #define FMEM_LOOP_EXIT 7 7425cf1a30Sjl 7525cf1a30Sjl #define FMEM_NO_ERROR 0 76*68ac2337Sjl #define FMEM_XC_TIMEOUT 1 77*68ac2337Sjl #define FMEM_COPY_TIMEOUT 2 78*68ac2337Sjl #define FMEM_SCF_BUSY 3 79*68ac2337Sjl #define FMEM_RETRY_OUT 4 80*68ac2337Sjl #define FMEM_TIMEOUT 5 81*68ac2337Sjl #define FMEM_HW_ERROR 6 82*68ac2337Sjl #define FMEM_TERMINATE 7 83*68ac2337Sjl #define FMEM_COPY_ERROR 8 84*68ac2337Sjl #define FMEM_SCF_ERR 9 8525cf1a30Sjl 8625cf1a30Sjl #define SCF_CMD_BUSY 0x8000 8725cf1a30Sjl #define SCF_STATUS_READY 0x8000 8825cf1a30Sjl #define SCF_STATUS_SHUTDOWN 0x4000 8925cf1a30Sjl #define SCF_STATUS_POFF 0x2000 9025cf1a30Sjl #define SCF_STATUS_EVENT 0x1000 9125cf1a30Sjl #define SCF_STATUS_TIMER_ADJUST 0x0800 9225cf1a30Sjl #define SCF_STATUS_ALIVE 0x0400 9325cf1a30Sjl #define SCF_STATUS_MODE_CHANGED 0x0200 9425cf1a30Sjl #define SCF_STATUS_CMD_U_PARITY 0x0100 9525cf1a30Sjl #define SCF_STATUS_CMD_RTN_CODE 0x00f0 9625cf1a30Sjl #define SCF_STATUS_MODE_SWITCH 0x000c 9725cf1a30Sjl #define SCF_STATUS_CMD_COMPLETE 0x0002 9825cf1a30Sjl #define SCF_STATUS_CMD_L_PARITY 0x0001 9925cf1a30Sjl 10025cf1a30Sjl #define SCF_RETRY_CNT 15 10125cf1a30Sjl 102*68ac2337Sjl /* 103*68ac2337Sjl * dynamic memory blocks cannot be added back to phys_install 104*68ac2337Sjl * safely if the alignment is smaller than the largest 105*68ac2337Sjl * physical page size the OS supports. The VM subsystem 106*68ac2337Sjl * will try to coalesce smaller pages together and 107*68ac2337Sjl * it assumes that the page structures are contiguous. 108*68ac2337Sjl * That assumption does not hold so we have to work around it. 109*68ac2337Sjl * On OPL, the largest page size is 256MB so we can just 110*68ac2337Sjl * add such memory block back. For everything else, 111*68ac2337Sjl * we round them up to 4MB boundaries and make sure 112*68ac2337Sjl * they are disjoint from phys_install. 113*68ac2337Sjl */ 114*68ac2337Sjl 115*68ac2337Sjl #define MH_MPSS_ALIGNMENT (256 * 1024 * 1024) 116*68ac2337Sjl #define MH_MIN_ALIGNMENT (4 * 1024 * 1024) 117*68ac2337Sjl #define rounddown(x, y) ((x) & ~(y - 1)) 118*68ac2337Sjl 11925cf1a30Sjl #ifndef _ASM 12025cf1a30Sjl 12125cf1a30Sjl /* 12225cf1a30Sjl * OPL platform specific routines currently only defined 12325cf1a30Sjl * in opl.c and referenced by DR. 12425cf1a30Sjl */ 12525cf1a30Sjl 12625cf1a30Sjl typedef void *drmachid_t; 12725cf1a30Sjl 12825cf1a30Sjl /* 129*68ac2337Sjl * There are several requirements to do copy rename: 130*68ac2337Sjl * 1 There should be no subroutine calls/TLBmiss 131*68ac2337Sjl * once the copying has begun. 132*68ac2337Sjl * 2 There should be no external memory access by the CPU 133*68ac2337Sjl * during the memory rename programming. 134*68ac2337Sjl * 135*68ac2337Sjl * All data and instruction pages used in the copy rename 136*68ac2337Sjl * procedure are kept in locked pages to satisfy 1 and 2. 137*68ac2337Sjl * However that is not enough. To satisfy 2, we must keep 138*68ac2337Sjl * all the data and instructions in the 2 assembly routines 139*68ac2337Sjl * drmach_fmem_loop_script and drmach_fmem_exec_script 140*68ac2337Sjl * in the same contiguous page. They are packed into 141*68ac2337Sjl * the 2nd 8K page of the buffer as shown in the diagram 142*68ac2337Sjl * below. 143*68ac2337Sjl * 144*68ac2337Sjl * Note that it is important to keep the "critical" 145*68ac2337Sjl * data in one 8K page to avoid any cache line 146*68ac2337Sjl * contention. The assembly routines read all the 147*68ac2337Sjl * critical data into the cache so that there is no 148*68ac2337Sjl * external memory access during FMEM operation. 14925cf1a30Sjl * 150*68ac2337Sjl * layout of the FMEM buffers: 151*68ac2337Sjl * They are all locked in TLB and the critical data 152*68ac2337Sjl * used in drmach_fmem_xxx assembly code are all 153*68ac2337Sjl * packed in the second page. 15425cf1a30Sjl * 155*68ac2337Sjl * 1st 8k page 156*68ac2337Sjl * +--------------------------------+ 157*68ac2337Sjl * |drmach_copy_rename_program_t | 158*68ac2337Sjl * +--------------------------------+ 159*68ac2337Sjl * |drmach_copy_rename_data_t | 160*68ac2337Sjl * | | 161*68ac2337Sjl * +--------------------------------+ 162*68ac2337Sjl * 163*68ac2337Sjl * 2nd 8k page 164*68ac2337Sjl * +--------------------------------+ 165*68ac2337Sjl * |drmach_copy_rename_critical_t | 166*68ac2337Sjl * | | 167*68ac2337Sjl * +--------------------------------+ 168*68ac2337Sjl * |run (drmach_copy_rename_prog__relocatable) 169*68ac2337Sjl * |(roundup boundary to 1K) | 170*68ac2337Sjl * +--------------------------------+ 171*68ac2337Sjl * | fmem_script | 172*68ac2337Sjl * |(roundup boundary to 1K) | 173*68ac2337Sjl * +--------------------------------+ 174*68ac2337Sjl * |loop_script | 175*68ac2337Sjl * | | 176*68ac2337Sjl * +--------------------------------+ 177*68ac2337Sjl * |at least 1K NOP/0's | 178*68ac2337Sjl * | | 179*68ac2337Sjl * +--------------------------------+ 180*68ac2337Sjl * 181*68ac2337Sjl * 3rd 8k page 182*68ac2337Sjl * +--------------------------------+ 183*68ac2337Sjl * |memlist_buffer (free_mlist) | 184*68ac2337Sjl * | | 185*68ac2337Sjl * +--------------------------------+ 186*68ac2337Sjl * 187*68ac2337Sjl * 4th 8k page - drmach_cr_stat_t. 18825cf1a30Sjl * 18925cf1a30Sjl */ 190*68ac2337Sjl 19125cf1a30Sjl typedef struct { 19225cf1a30Sjl int16_t scf_command; 19325cf1a30Sjl int8_t scf_rsv1[2]; 19425cf1a30Sjl int16_t scf_status; 19525cf1a30Sjl int8_t scf_rsv2[2]; 19625cf1a30Sjl int8_t scf_version; 19725cf1a30Sjl int8_t scf_rsv3[3]; 19825cf1a30Sjl int8_t scf_rsv4[4]; 19925cf1a30Sjl uint8_t scf_tdata[16]; 20025cf1a30Sjl uint8_t scf_rdata[16]; 20125cf1a30Sjl } drmach_scf_regs_t; 20225cf1a30Sjl 20325cf1a30Sjl 20425cf1a30Sjl 20525cf1a30Sjl typedef struct { 20625cf1a30Sjl volatile uint_t stat; 20725cf1a30Sjl volatile uint_t error; 20825cf1a30Sjl int op; 20925cf1a30Sjl #define OPL_FMEM_SCF_START 0x1 21025cf1a30Sjl #define OPL_FMEM_MC_SUSPEND 0x2 21125cf1a30Sjl } drmach_fmem_mbox_t; 21225cf1a30Sjl 21325cf1a30Sjl typedef struct { 21425cf1a30Sjl uint64_t scf_reg_base; 21525cf1a30Sjl uint8_t scf_td[16]; 21625cf1a30Sjl uint64_t save_log[8]; 21725cf1a30Sjl uint64_t save_local[8]; 21825cf1a30Sjl uint64_t pstate; 21925cf1a30Sjl uint64_t delay; 22025cf1a30Sjl int (*run)(void *arg, int cpuid); 22125cf1a30Sjl int (*fmem)(void *arg, size_t sz); 22225cf1a30Sjl int (*loop)(void *arg1, size_t sz, void *arg2); 22325cf1a30Sjl void (*loop_rtn)(void *arg); 22425cf1a30Sjl uint64_t inst_loop_ret; 22525cf1a30Sjl int fmem_issued; 22625cf1a30Sjl volatile uchar_t stat[NCPU]; 22725cf1a30Sjl } drmach_copy_rename_critical_t; 22825cf1a30Sjl 22925cf1a30Sjl typedef struct { 23025cf1a30Sjl uint64_t s_copybasepa; 23125cf1a30Sjl uint64_t t_copybasepa; 23225cf1a30Sjl drmachid_t s_mem; 23325cf1a30Sjl drmachid_t t_mem; 23425cf1a30Sjl cpuset_t cpu_ready_set; 23525cf1a30Sjl cpuset_t cpu_slave_set; 23625cf1a30Sjl cpuset_t cpu_copy_set; 23725cf1a30Sjl processorid_t cpuid; 23825cf1a30Sjl drmach_fmem_mbox_t fmem_status; 23925cf1a30Sjl volatile uchar_t error[NCPU]; 24025cf1a30Sjl struct memlist *c_ml; 24125cf1a30Sjl struct memlist *cpu_ml[NCPU]; 24225cf1a30Sjl void (*mc_resume)(void); 24325cf1a30Sjl int (*scf_fmem_end)(void); 24425cf1a30Sjl int (*scf_fmem_cancel)(void); 245*68ac2337Sjl uint64_t (*scf_get_base_addr)(void); 24625cf1a30Sjl uint64_t copy_delay; 24725cf1a30Sjl uint64_t stick_freq; 24825cf1a30Sjl uint64_t copy_wait_time; 24925cf1a30Sjl processorid_t slowest_cpuid; 25025cf1a30Sjl } drmach_copy_rename_data_t; 25125cf1a30Sjl 25225cf1a30Sjl typedef struct { 25325cf1a30Sjl uint64_t nbytes[NCPU]; 25425cf1a30Sjl } drmach_cr_stat_t; 25525cf1a30Sjl 256*68ac2337Sjl typedef struct drmach_copy_rename_program { 257*68ac2337Sjl drmach_copy_rename_critical_t *critical; 258*68ac2337Sjl struct drmach_copy_rename_program *locked_prog; 259*68ac2337Sjl struct drmach_copy_rename_program *prog; 260*68ac2337Sjl drmach_copy_rename_data_t *data; 261*68ac2337Sjl caddr_t memlist_buffer; 262*68ac2337Sjl struct memlist *free_mlist; 263*68ac2337Sjl drmach_cr_stat_t *stat; 26425cf1a30Sjl } drmach_copy_rename_program_t; 26525cf1a30Sjl 26625cf1a30Sjl #define DRMACH_FMEM_LOCKED_PAGES 4 26725cf1a30Sjl #define DRMACH_FMEM_DATA_PAGE 0 26825cf1a30Sjl #define DRMACH_FMEM_CRITICAL_PAGE 1 26925cf1a30Sjl #define DRMACH_FMEM_MLIST_PAGE 2 27025cf1a30Sjl #define DRMACH_FMEM_STAT_PAGE 3 27125cf1a30Sjl 27225cf1a30Sjl /* 27325cf1a30Sjl * layout of the FMEM buffers: 27425cf1a30Sjl * 1st 8k page 27525cf1a30Sjl * +--------------------------------+ 27625cf1a30Sjl * |drmach_copy_rename_program_t | 27725cf1a30Sjl * +--------------------------------+ 27825cf1a30Sjl * |drmach_copy_rename_data_t | 27925cf1a30Sjl * | | 28025cf1a30Sjl * +--------------------------------+ 28125cf1a30Sjl * 28225cf1a30Sjl * 2nd 8k page 28325cf1a30Sjl * +--------------------------------+ 28425cf1a30Sjl * |drmach_copy_rename_critical_t | 28525cf1a30Sjl * | | 28625cf1a30Sjl * +--------------------------------+ 28725cf1a30Sjl * |run (drmach_copy_rename_prog__relocatable) 28825cf1a30Sjl * |(roundup boundary to 1K) | 28925cf1a30Sjl * +--------------------------------+ 29025cf1a30Sjl * | fmem_script | 29125cf1a30Sjl * |(roundup boundary to 1K) | 29225cf1a30Sjl * +--------------------------------+ 29325cf1a30Sjl * |loop_script | 29425cf1a30Sjl * | | 29525cf1a30Sjl * +--------------------------------+ 29625cf1a30Sjl * |at least 1K NOP/0's | 29725cf1a30Sjl * | | 29825cf1a30Sjl * +--------------------------------+ 29925cf1a30Sjl * 30025cf1a30Sjl * 3rd 8k page 30125cf1a30Sjl * +--------------------------------+ 30225cf1a30Sjl * |memlist_buffer (free_mlist) | 30325cf1a30Sjl * | | 30425cf1a30Sjl * +--------------------------------+ 30525cf1a30Sjl * 30625cf1a30Sjl * 4th 8k page - drmach_cr_stat_t. 30725cf1a30Sjl * 30825cf1a30Sjl */ 30925cf1a30Sjl 31025cf1a30Sjl typedef struct { 31125cf1a30Sjl boolean_t assigned; 31225cf1a30Sjl boolean_t powered; 31325cf1a30Sjl boolean_t configured; 31425cf1a30Sjl boolean_t busy; 31525cf1a30Sjl boolean_t empty; 31625cf1a30Sjl sbd_cond_t cond; 31725cf1a30Sjl char type[MAXNAMELEN]; 31825cf1a30Sjl char info[MAXPATHLEN]; /* TODO: what size? */ 31925cf1a30Sjl } drmach_status_t; 32025cf1a30Sjl 32125cf1a30Sjl typedef struct { 32225cf1a30Sjl int size; 32325cf1a30Sjl char *copts; 32425cf1a30Sjl } drmach_opts_t; 32525cf1a30Sjl 32625cf1a30Sjl typedef struct { 32725cf1a30Sjl uint64_t mi_basepa; 32825cf1a30Sjl uint64_t mi_size; 32925cf1a30Sjl uint64_t mi_slice_size; 33025cf1a30Sjl uint64_t mi_alignment_mask; 33125cf1a30Sjl } drmach_mem_info_t; 33225cf1a30Sjl 33325cf1a30Sjl extern sbd_error_t *drmach_mem_get_info(drmachid_t, drmach_mem_info_t *); 33425cf1a30Sjl extern int drmach_board_is_floating(drmachid_t); 33525cf1a30Sjl 33625cf1a30Sjl extern sbd_error_t *drmach_copy_rename_init( 33725cf1a30Sjl drmachid_t dst_id, 33825cf1a30Sjl drmachid_t src_id, struct memlist *src_copy_ml, 33925cf1a30Sjl drmachid_t *pgm_id); 34025cf1a30Sjl extern sbd_error_t *drmach_copy_rename_fini(drmachid_t id); 34125cf1a30Sjl extern void drmach_copy_rename(drmachid_t id); 34225cf1a30Sjl 34325cf1a30Sjl extern sbd_error_t *drmach_pre_op(int cmd, drmachid_t id, 34425cf1a30Sjl drmach_opts_t *opts); 34525cf1a30Sjl extern sbd_error_t *drmach_post_op(int cmd, drmachid_t id, 34625cf1a30Sjl drmach_opts_t *opts); 34725cf1a30Sjl 34825cf1a30Sjl extern sbd_error_t *drmach_board_assign(int bnum, drmachid_t *id); 34925cf1a30Sjl extern sbd_error_t *drmach_board_connect(drmachid_t id, 35025cf1a30Sjl drmach_opts_t *opts); 35125cf1a30Sjl extern sbd_error_t *drmach_board_deprobe(drmachid_t id); 35225cf1a30Sjl extern sbd_error_t *drmach_board_disconnect(drmachid_t id, 35325cf1a30Sjl drmach_opts_t *opts); 35425cf1a30Sjl extern sbd_error_t *drmach_board_find_devices(drmachid_t id, void *a, 35525cf1a30Sjl sbd_error_t *(*found)(void *a, const char *, int, drmachid_t)); 35625cf1a30Sjl extern int drmach_board_lookup(int bnum, drmachid_t *id); 35725cf1a30Sjl extern sbd_error_t *drmach_passthru(drmachid_t id, 35825cf1a30Sjl drmach_opts_t *opts); 35925cf1a30Sjl 36025cf1a30Sjl extern sbd_error_t *drmach_board_name(int bnum, char *buf, int buflen); 36125cf1a30Sjl 36225cf1a30Sjl extern sbd_error_t *drmach_board_poweroff(drmachid_t id); 36325cf1a30Sjl extern sbd_error_t *drmach_board_poweron(drmachid_t id); 36425cf1a30Sjl extern sbd_error_t *drmach_board_test(drmachid_t id, drmach_opts_t *opts, 36525cf1a30Sjl int force); 36625cf1a30Sjl 36725cf1a30Sjl extern sbd_error_t *drmach_board_unassign(drmachid_t id); 36825cf1a30Sjl 36925cf1a30Sjl extern sbd_error_t *drmach_configure(drmachid_t id, int flags); 37025cf1a30Sjl 37125cf1a30Sjl extern sbd_error_t *drmach_cpu_disconnect(drmachid_t id); 37225cf1a30Sjl extern sbd_error_t *drmach_cpu_get_id(drmachid_t id, processorid_t *cpuid); 37325cf1a30Sjl extern sbd_error_t *drmach_cpu_get_impl(drmachid_t id, int *ip); 37425cf1a30Sjl extern void drmach_cpu_flush_ecache_sync(void); 37525cf1a30Sjl 37625cf1a30Sjl extern sbd_error_t *drmach_get_dip(drmachid_t id, dev_info_t **dip); 37725cf1a30Sjl 37825cf1a30Sjl extern sbd_error_t *drmach_io_is_attached(drmachid_t id, int *yes); 37925cf1a30Sjl extern sbd_error_t *drmach_io_post_attach(drmachid_t id); 38025cf1a30Sjl extern sbd_error_t *drmach_io_post_release(drmachid_t id); 38125cf1a30Sjl extern sbd_error_t *drmach_io_pre_release(drmachid_t id); 38225cf1a30Sjl extern sbd_error_t *drmach_io_unrelease(drmachid_t id); 38325cf1a30Sjl 38425cf1a30Sjl extern sbd_error_t *drmach_mem_add_span(drmachid_t id, 38525cf1a30Sjl uint64_t basepa, uint64_t size); 38625cf1a30Sjl extern sbd_error_t *drmach_mem_del_span(drmachid_t id, 38725cf1a30Sjl uint64_t basepa, uint64_t size); 38825cf1a30Sjl extern sbd_error_t *drmach_mem_disable(drmachid_t id); 38925cf1a30Sjl extern sbd_error_t *drmach_mem_enable(drmachid_t id); 39025cf1a30Sjl extern sbd_error_t *drmach_mem_get_base_physaddr(drmachid_t id, 39125cf1a30Sjl uint64_t *pa); 39225cf1a30Sjl extern sbd_error_t *drmach_mem_get_memlist(drmachid_t id, 39325cf1a30Sjl struct memlist **ml); 39425cf1a30Sjl extern sbd_error_t *drmach_mem_get_slice_size(drmachid_t, uint64_t *); 39525cf1a30Sjl 39625cf1a30Sjl extern sbd_error_t *drmach_release(drmachid_t id); 39725cf1a30Sjl extern sbd_error_t *drmach_status(drmachid_t id, drmach_status_t *stat); 39825cf1a30Sjl extern sbd_error_t *drmach_unconfigure(drmachid_t id, int flags); 39925cf1a30Sjl extern int drmach_log_sysevent(int board, char *hint, int flag, 40025cf1a30Sjl int verbose); 40125cf1a30Sjl 40225cf1a30Sjl extern int drmach_verify_sr(dev_info_t *dip, int sflag); 40325cf1a30Sjl extern void drmach_suspend_last(); 40425cf1a30Sjl extern void drmach_resume_first(); 40525cf1a30Sjl 40625cf1a30Sjl #endif 40725cf1a30Sjl 40825cf1a30Sjl #ifdef __cplusplus 40925cf1a30Sjl } 41025cf1a30Sjl #endif 41125cf1a30Sjl 41225cf1a30Sjl #endif /* _SYS_DRMACH_H_ */ 413