xref: /illumos-gate/usr/src/uts/sun4u/opl/os/opl.c (revision 6a634c9d)
125cf1a30Sjl /*
225cf1a30Sjl  * CDDL HEADER START
325cf1a30Sjl  *
425cf1a30Sjl  * The contents of this file are subject to the terms of the
525cf1a30Sjl  * Common Development and Distribution License (the "License").
625cf1a30Sjl  * You may not use this file except in compliance with the License.
725cf1a30Sjl  *
825cf1a30Sjl  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
925cf1a30Sjl  * or http://www.opensolaris.org/os/licensing.
1025cf1a30Sjl  * See the License for the specific language governing permissions
1125cf1a30Sjl  * and limitations under the License.
1225cf1a30Sjl  *
1325cf1a30Sjl  * When distributing Covered Code, include this CDDL HEADER in each
1425cf1a30Sjl  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1525cf1a30Sjl  * If applicable, add the following below this CDDL HEADER, with the
1625cf1a30Sjl  * fields enclosed by brackets "[]" replaced with your own identifying
1725cf1a30Sjl  * information: Portions Copyright [yyyy] [name of copyright owner]
1825cf1a30Sjl  *
1925cf1a30Sjl  * CDDL HEADER END
2025cf1a30Sjl  */
2125cf1a30Sjl /*
22*4cca9c84SDave Plauger  * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
2325cf1a30Sjl  */
2525cf1a30Sjl #include <sys/cpuvar.h>
2625cf1a30Sjl #include <sys/systm.h>
2725cf1a30Sjl #include <sys/sysmacros.h>
2825cf1a30Sjl #include <sys/promif.h>
2925cf1a30Sjl #include <sys/platform_module.h>
3025cf1a30Sjl #include <sys/cmn_err.h>
3125cf1a30Sjl #include <sys/errno.h>
3225cf1a30Sjl #include <sys/machsystm.h>
3325cf1a30Sjl #include <sys/bootconf.h>
3425cf1a30Sjl #include <sys/nvpair.h>
3525cf1a30Sjl #include <sys/kobj.h>
3625cf1a30Sjl #include <sys/mem_cage.h>
3725cf1a30Sjl #include <sys/opl.h>
3825cf1a30Sjl #include <sys/scfd/scfostoescf.h>
3925cf1a30Sjl #include <sys/cpu_sgnblk_defs.h>
4025cf1a30Sjl #include <sys/utsname.h>
4125cf1a30Sjl #include <sys/ddi.h>
4225cf1a30Sjl #include <sys/sunndi.h>
4325cf1a30Sjl #include <sys/lgrp.h>
4425cf1a30Sjl #include <sys/memnode.h>
4525cf1a30Sjl #include <sys/sysmacros.h>
46e603b7d4Spm #include <sys/time.h>
47e603b7d4Spm #include <sys/cpu.h>
48ca3e8d88SDave Plauger #include <sys/dumphdr.h>
4925cf1a30Sjl #include <vm/vm_dep.h>
5125cf1a30Sjl int (*opl_get_mem_unum)(int, uint64_t, char *, int, int *);
520cc8ae86Sav int (*opl_get_mem_sid)(char *unum, char *buf, int buflen, int *lenp);
530cc8ae86Sav int (*opl_get_mem_offset)(uint64_t paddr, uint64_t *offp);
540cc8ae86Sav int (*opl_get_mem_addr)(char *unum, char *sid,
550cc8ae86Sav     uint64_t offset, uint64_t *paddr);
5725cf1a30Sjl /* Memory for fcode claims.  16k times # maximum possible IO units */
5825cf1a30Sjl #define	EFCODE_SIZE	(OPL_MAX_BOARDS * OPL_MAX_IO_UNITS_PER_BOARD * 0x4000)
5925cf1a30Sjl int efcode_size = EFCODE_SIZE;
6125cf1a30Sjl #define	OPL_MC_MEMBOARD_SHIFT 38	/* Boards on 256BG boundary */
6325cf1a30Sjl /* Set the maximum number of boards for DR */
6425cf1a30Sjl int opl_boards = OPL_MAX_BOARDS;
6625cf1a30Sjl void sgn_update_all_cpus(ushort_t, uchar_t, uchar_t);
6825cf1a30Sjl extern int tsb_lgrp_affinity;
7025cf1a30Sjl int opl_tsb_spares = (OPL_MAX_BOARDS) * (OPL_MAX_PCICH_UNITS_PER_BOARD) *
7125cf1a30Sjl 	(OPL_MAX_TSBS_PER_PCICH);
7325cf1a30Sjl pgcnt_t opl_startup_cage_size = 0;
753f1fa9a7Sjfrank /*
763f1fa9a7Sjfrank  * The length of the delay in seconds in communication with XSCF after
773f1fa9a7Sjfrank  * which the warning message will be logged.
783f1fa9a7Sjfrank  */
793f1fa9a7Sjfrank uint_t	xscf_connect_delay = 60 * 15;
811e2e7a75Shuah static opl_model_info_t opl_models[] = {
82195196c6Ssubhan 	{ "FF1", OPL_MAX_BOARDS_FF1, FF1, STD_DISPATCH_TABLE },
83195196c6Ssubhan 	{ "FF2", OPL_MAX_BOARDS_FF2, FF2, STD_DISPATCH_TABLE },
84195196c6Ssubhan 	{ "DC1", OPL_MAX_BOARDS_DC1, DC1, STD_DISPATCH_TABLE },
85195196c6Ssubhan 	{ "DC2", OPL_MAX_BOARDS_DC2, DC2, EXT_DISPATCH_TABLE },
86195196c6Ssubhan 	{ "DC3", OPL_MAX_BOARDS_DC3, DC3, EXT_DISPATCH_TABLE },
881e2e7a75Shuah };
891e2e7a75Shuah static	int	opl_num_models = sizeof (opl_models)/sizeof (opl_model_info_t);
91195196c6Ssubhan /*
9272b9fce9Ssubhan  * opl_cur_model
93195196c6Ssubhan  */
9472b9fce9Ssubhan static	opl_model_info_t *opl_cur_model = NULL;
9625cf1a30Sjl static struct memlist *opl_memlist_per_board(struct memlist *ml);
973f1fa9a7Sjfrank static void post_xscf_msg(char *, int);
983f1fa9a7Sjfrank static void pass2xscf_thread();
100e603b7d4Spm /*
101e603b7d4Spm  * Note FF/DC out-of-order instruction engine takes only a
102e603b7d4Spm  * single cycle to execute each spin loop
103e603b7d4Spm  * for comparison, Panther takes 6 cycles for same loop
104575a7426Spt  * OPL_BOFF_SPIN = base spin loop, roughly one memory reference time
105575a7426Spt  * OPL_BOFF_TM = approx nsec for OPL sleep instruction (1600 for OPL-C)
106575a7426Spt  * OPL_BOFF_SLEEP = approx number of SPIN iterations to equal one sleep
107575a7426Spt  * OPL_BOFF_MAX_SCALE - scaling factor for max backoff based on active cpus
108575a7426Spt  * Listed values tuned for 2.15GHz to 2.64GHz systems
109e603b7d4Spm  * Value may change for future systems
110e603b7d4Spm  */
111575a7426Spt #define	OPL_BOFF_SPIN 7
112575a7426Spt #define	OPL_BOFF_SLEEP 4
113575a7426Spt #define	OPL_BOFF_TM 1600
114575a7426Spt #define	OPL_BOFF_MAX_SCALE 8
1162850d85bSmv #define	OPL_CLOCK_TICK_THRESHOLD	128
1172850d85bSmv #define	OPL_CLOCK_TICK_NCPUS		64
1192850d85bSmv extern int	clock_tick_threshold;
1202850d85bSmv extern int	clock_tick_ncpus;
12225cf1a30Sjl int
set_platform_max_ncpus(void)12325cf1a30Sjl set_platform_max_ncpus(void)
12425cf1a30Sjl {
12525cf1a30Sjl 	return (OPL_MAX_CPU_PER_BOARD * OPL_MAX_BOARDS);
12625cf1a30Sjl }
12825cf1a30Sjl int
set_platform_tsb_spares(void)12925cf1a30Sjl set_platform_tsb_spares(void)
13025cf1a30Sjl {
13125cf1a30Sjl 	return (MIN(opl_tsb_spares, MAX_UPA));
13225cf1a30Sjl }
1341e2e7a75Shuah static void
set_model_info()1351e2e7a75Shuah set_model_info()
1361e2e7a75Shuah {
137195196c6Ssubhan 	extern int ts_dispatch_extended;
1381e2e7a75Shuah 	char	name[MAXSYSNAME];
1391e2e7a75Shuah 	int	i;
1411e2e7a75Shuah 	/*
1421e2e7a75Shuah 	 * Get model name from the root node.
1431e2e7a75Shuah 	 *
1441e2e7a75Shuah 	 * We are using the prom device tree since, at this point,
1451e2e7a75Shuah 	 * the Solaris device tree is not yet setup.
1461e2e7a75Shuah 	 */
1471e2e7a75Shuah 	(void) prom_getprop(prom_rootnode(), "model", (caddr_t)name);
1491e2e7a75Shuah 	for (i = 0; i < opl_num_models; i++) {
1501e2e7a75Shuah 		if (strncmp(name, opl_models[i].model_name, MAXSYSNAME) == 0) {
1511e2e7a75Shuah 			opl_cur_model = &opl_models[i];
1521e2e7a75Shuah 			break;
1531e2e7a75Shuah 		}
1541e2e7a75Shuah 	}
1569b71d8e9Swh 	/*
1579b71d8e9Swh 	 * If model not matched, it's an unknown model.
15878ed97a7Sjl 	 * Just return.  It will default to standard dispatch tables.
1599b71d8e9Swh 	 */
1601e2e7a75Shuah 	if (i == opl_num_models)
1619b71d8e9Swh 		return;
163195196c6Ssubhan 	if ((opl_cur_model->model_cmds & EXT_DISPATCH_TABLE) &&
164e98fafb9Sjl 	    (ts_dispatch_extended == -1)) {
165195196c6Ssubhan 		/*
166195196c6Ssubhan 		 * Based on a platform model, select a dispatch table.
167195196c6Ssubhan 		 * Only DC2 and DC3 systems uses the alternate/extended
168195196c6Ssubhan 		 * TS dispatch table.
16978ed97a7Sjl 		 * IKKAKU, FF1, FF2 and DC1 systems use standard dispatch
17078ed97a7Sjl 		 * tables.
171195196c6Ssubhan 		 */
172195196c6Ssubhan 		ts_dispatch_extended = 1;
173195196c6Ssubhan 	}
1751e2e7a75Shuah }
1771e2e7a75Shuah static void
set_max_mmu_ctxdoms()1781e2e7a75Shuah set_max_mmu_ctxdoms()
1791e2e7a75Shuah {
1801e2e7a75Shuah 	extern uint_t	max_mmu_ctxdoms;
1811e2e7a75Shuah 	int		max_boards;
1831e2e7a75Shuah 	/*
1841e2e7a75Shuah 	 * From the model, get the maximum number of boards
1851e2e7a75Shuah 	 * supported and set the value accordingly. If the model
1861e2e7a75Shuah 	 * could not be determined or recognized, we assume the max value.
1871e2e7a75Shuah 	 */
1881e2e7a75Shuah 	if (opl_cur_model == NULL)
1891e2e7a75Shuah 		max_boards = OPL_MAX_BOARDS;
1901e2e7a75Shuah 	else
1911e2e7a75Shuah 		max_boards = opl_cur_model->model_max_boards;
1931e2e7a75Shuah 	/*
1941e2e7a75Shuah 	 * On OPL, cores and MMUs are one-to-one.
1951e2e7a75Shuah 	 */
1961e2e7a75Shuah 	max_mmu_ctxdoms = OPL_MAX_CORE_UNITS_PER_BOARD * max_boards;
1971e2e7a75Shuah }
19925cf1a30Sjl #pragma weak mmu_init_large_pages
20125cf1a30Sjl void
set_platform_defaults(void)20225cf1a30Sjl set_platform_defaults(void)
20325cf1a30Sjl {
20425cf1a30Sjl 	extern char *tod_module_name;
20525cf1a30Sjl 	extern void cpu_sgn_update(ushort_t, uchar_t, uchar_t, int);
20625cf1a30Sjl 	extern void mmu_init_large_pages(size_t);
20825cf1a30Sjl 	/* Set the CPU signature function pointer */
20925cf1a30Sjl 	cpu_sgn_func = cpu_sgn_update;
21125cf1a30Sjl 	/* Set appropriate tod module for OPL platform */
21225cf1a30Sjl 	ASSERT(tod_module_name == NULL);
21325cf1a30Sjl 	tod_module_name = "todopl";
21525cf1a30Sjl 	if ((mmu_page_sizes == max_mmu_page_sizes) &&
216e12a8a13Ssusans 	    (mmu_ism_pagesize != DEFAULT_ISM_PAGESIZE)) {
21725cf1a30Sjl 		if (&mmu_init_large_pages)
21825cf1a30Sjl 			mmu_init_large_pages(mmu_ism_pagesize);
21925cf1a30Sjl 	}
22125cf1a30Sjl 	tsb_lgrp_affinity = 1;
2231e2e7a75Shuah 	set_max_mmu_ctxdoms();
224ca3e8d88SDave Plauger 
225ca3e8d88SDave Plauger 	/* set OPL threshold for compressed dumps */
226*4cca9c84SDave Plauger 	dump_plat_mincpu_default = DUMP_PLAT_SUN4U_OPL_MINCPU;
22725cf1a30Sjl }
22925cf1a30Sjl /*
23025cf1a30Sjl  * Convert logical a board number to a physical one.
23125cf1a30Sjl  */
23325cf1a30Sjl #define	LSBPROP		"board#"
23425cf1a30Sjl #define	PSBPROP		"physical-board#"
23625cf1a30Sjl int
opl_get_physical_board(int id)23725cf1a30Sjl opl_get_physical_board(int id)
23825cf1a30Sjl {
23925cf1a30Sjl 	dev_info_t	*root_dip, *dip = NULL;
24025cf1a30Sjl 	char		*dname = NULL;
24125cf1a30Sjl 	int		circ;
24325cf1a30Sjl 	pnode_t		pnode;
24425cf1a30Sjl 	char		pname[MAXSYSNAME] = {0};
24625cf1a30Sjl 	int		lsb_id;	/* Logical System Board ID */
24725cf1a30Sjl 	int		psb_id;	/* Physical System Board ID */
25025cf1a30Sjl 	/*
25125cf1a30Sjl 	 * This function is called on early stage of bootup when the
25225cf1a30Sjl 	 * kernel device tree is not initialized yet, and also
25325cf1a30Sjl 	 * later on when the device tree is up. We want to try
25425cf1a30Sjl 	 * the fast track first.
25525cf1a30Sjl 	 */
25625cf1a30Sjl 	root_dip = ddi_root_node();
25725cf1a30Sjl 	if (root_dip) {
25825cf1a30Sjl 		/* Get from devinfo node */
25925cf1a30Sjl 		ndi_devi_enter(root_dip, &circ);
26025cf1a30Sjl 		for (dip = ddi_get_child(root_dip); dip;
26125cf1a30Sjl 		    dip = ddi_get_next_sibling(dip)) {
26325cf1a30Sjl 			dname = ddi_node_name(dip);
26425cf1a30Sjl 			if (strncmp(dname, "pseudo-mc", 9) != 0)
26525cf1a30Sjl 				continue;
26725cf1a30Sjl 			if ((lsb_id = (int)ddi_getprop(DDI_DEV_T_ANY, dip,
26825cf1a30Sjl 			    DDI_PROP_DONTPASS, LSBPROP, -1)) == -1)
26925cf1a30Sjl 				continue;
27125cf1a30Sjl 			if (id == lsb_id) {
27225cf1a30Sjl 				if ((psb_id = (int)ddi_getprop(DDI_DEV_T_ANY,
27325cf1a30Sjl 				    dip, DDI_PROP_DONTPASS, PSBPROP, -1))
27425cf1a30Sjl 				    == -1) {
27525cf1a30Sjl 					ndi_devi_exit(root_dip, circ);
27625cf1a30Sjl 					return (-1);
27725cf1a30Sjl 				} else {
27825cf1a30Sjl 					ndi_devi_exit(root_dip, circ);
27925cf1a30Sjl 					return (psb_id);
28025cf1a30Sjl 				}
28125cf1a30Sjl 			}
28225cf1a30Sjl 		}
28325cf1a30Sjl 		ndi_devi_exit(root_dip, circ);
28425cf1a30Sjl 	}
28625cf1a30Sjl 	/*
28725cf1a30Sjl 	 * We do not have the kernel device tree, or we did not
28825cf1a30Sjl 	 * find the node for some reason (let's say the kernel
28925cf1a30Sjl 	 * device tree was modified), let's try the OBP tree.
29025cf1a30Sjl 	 */
29125cf1a30Sjl 	pnode = prom_rootnode();
29225cf1a30Sjl 	for (pnode = prom_childnode(pnode); pnode;
29325cf1a30Sjl 	    pnode = prom_nextnode(pnode)) {
29525cf1a30Sjl 		if ((prom_getprop(pnode, "name", (caddr_t)pname) == -1) ||
29625cf1a30Sjl 		    (strncmp(pname, "pseudo-mc", 9) != 0))
29725cf1a30Sjl 			continue;
29925cf1a30Sjl 		if (prom_getprop(pnode, LSBPROP, (caddr_t)&lsb_id) == -1)
30025cf1a30Sjl 			continue;
30225cf1a30Sjl 		if (id == lsb_id) {
30325cf1a30Sjl 			if (prom_getprop(pnode, PSBPROP,
30425cf1a30Sjl 			    (caddr_t)&psb_id) == -1) {
30525cf1a30Sjl 				return (-1);
30625cf1a30Sjl 			} else {
30725cf1a30Sjl 				return (psb_id);
30825cf1a30Sjl 			}
30925cf1a30Sjl 		}
31025cf1a30Sjl 	}
31225cf1a30Sjl 	return (-1);
31325cf1a30Sjl }
31525cf1a30Sjl /*
31625cf1a30Sjl  * For OPL it's possible that memory from two or more successive boards
31725cf1a30Sjl  * will be contiguous across the boards, and therefore represented as a
31825cf1a30Sjl  * single chunk.
31925cf1a30Sjl  * This function splits such chunks down the board boundaries.
32025cf1a30Sjl  */
32125cf1a30Sjl static struct memlist *
opl_memlist_per_board(struct memlist * ml)32225cf1a30Sjl opl_memlist_per_board(struct memlist *ml)
32325cf1a30Sjl {
32425cf1a30Sjl 	uint64_t ssize, low, high, boundary;
32525cf1a30Sjl 	struct memlist *head, *tail, *new;
32725cf1a30Sjl 	ssize = (1ull << OPL_MC_MEMBOARD_SHIFT);
32925cf1a30Sjl 	head = tail = NULL;
33156f33205SJonathan Adams 	for (; ml; ml = ml->ml_next) {
33256f33205SJonathan Adams 		low  = (uint64_t)ml->ml_address;
33356f33205SJonathan Adams 		high = low+(uint64_t)(ml->ml_size);
33425cf1a30Sjl 		while (low < high) {
33525cf1a30Sjl 			boundary = roundup(low+1, ssize);
33625cf1a30Sjl 			boundary = MIN(high, boundary);
33725cf1a30Sjl 			new = kmem_zalloc(sizeof (struct memlist), KM_SLEEP);
33856f33205SJonathan Adams 			new->ml_address = low;
33956f33205SJonathan Adams 			new->ml_size = boundary - low;
34025cf1a30Sjl 			if (head == NULL)
34125cf1a30Sjl 				head = new;
34225cf1a30Sjl 			if (tail) {
34356f33205SJonathan Adams 				tail->ml_next = new;
34456f33205SJonathan Adams 				new->ml_prev = tail;
34525cf1a30Sjl 			}
34625cf1a30Sjl 			tail = new;
34725cf1a30Sjl 			low = boundary;
34825cf1a30Sjl 		}
34925cf1a30Sjl 	}
35025cf1a30Sjl 	return (head);
35125cf1a30Sjl }
35325cf1a30Sjl void
set_platform_cage_params(void)35425cf1a30Sjl set_platform_cage_params(void)
35525cf1a30Sjl {
35625cf1a30Sjl 	extern pgcnt_t total_pages;
35725cf1a30Sjl 	extern struct memlist *phys_avail;
35825cf1a30Sjl 	struct memlist *ml, *tml;
36025cf1a30Sjl 	if (kernel_cage_enable) {
36125cf1a30Sjl 		pgcnt_t preferred_cage_size;
363e98fafb9Sjl 		preferred_cage_size = MAX(opl_startup_cage_size,
364e98fafb9Sjl 		    total_pages / 256);
36625cf1a30Sjl 		ml = opl_memlist_per_board(phys_avail);
36825cf1a30Sjl 		/*
36925cf1a30Sjl 		 * Note: we are assuming that post has load the
37025cf1a30Sjl 		 * whole show in to the high end of memory. Having
37125cf1a30Sjl 		 * taken this leap, we copy the whole of phys_avail
37225cf1a30Sjl 		 * the glist and arrange for the cage to grow
37325cf1a30Sjl 		 * downward (descending pfns).
37425cf1a30Sjl 		 */
37585f58038Sdp 		kcage_range_init(ml, KCAGE_DOWN, preferred_cage_size);
37725cf1a30Sjl 		/* free the memlist */
37825cf1a30Sjl 		do {
37956f33205SJonathan Adams 			tml = ml->ml_next;
38025cf1a30Sjl 			kmem_free(ml, sizeof (struct memlist));
38125cf1a30Sjl 			ml = tml;
38225cf1a30Sjl 		} while (ml != NULL);
38325cf1a30Sjl 	}
38525cf1a30Sjl 	if (kcage_on)
38625cf1a30Sjl 		cmn_err(CE_NOTE, "!DR Kernel Cage is ENABLED");
38725cf1a30Sjl 	else
38825cf1a30Sjl 		cmn_err(CE_NOTE, "!DR Kernel Cage is DISABLED");
38925cf1a30Sjl }
39125cf1a30Sjl /*ARGSUSED*/
39225cf1a30Sjl int
plat_cpu_poweron(struct cpu * cp)39325cf1a30Sjl plat_cpu_poweron(struct cpu *cp)
39425cf1a30Sjl {
39525cf1a30Sjl 	int (*opl_cpu_poweron)(struct cpu *) = NULL;
39725cf1a30Sjl 	opl_cpu_poweron =
39825cf1a30Sjl 	    (int (*)(struct cpu *))kobj_getsymvalue("drmach_cpu_poweron", 0);
40025cf1a30Sjl 	if (opl_cpu_poweron == NULL)
40125cf1a30Sjl 		return (ENOTSUP);
40225cf1a30Sjl 	else
40325cf1a30Sjl 		return ((opl_cpu_poweron)(cp));
40525cf1a30Sjl }
40725cf1a30Sjl /*ARGSUSED*/
40825cf1a30Sjl int
plat_cpu_poweroff(struct cpu * cp)40925cf1a30Sjl plat_cpu_poweroff(struct cpu *cp)
41025cf1a30Sjl {
41125cf1a30Sjl 	int (*opl_cpu_poweroff)(struct cpu *) = NULL;
41325cf1a30Sjl 	opl_cpu_poweroff =
41425cf1a30Sjl 	    (int (*)(struct cpu *))kobj_getsymvalue("drmach_cpu_poweroff", 0);
41625cf1a30Sjl 	if (opl_cpu_poweroff == NULL)
41725cf1a30Sjl 		return (ENOTSUP);
41825cf1a30Sjl 	else
41925cf1a30Sjl 		return ((opl_cpu_poweroff)(cp));
42125cf1a30Sjl }
42325cf1a30Sjl int
plat_max_boards(void)42425cf1a30Sjl plat_max_boards(void)
42525cf1a30Sjl {
4264af09fceSwh 	/*
4274af09fceSwh 	 * If the model cannot be determined, default to the max value.
4284af09fceSwh 	 * Otherwise, Ikkaku model only supports 1 system board.
4294af09fceSwh 	 */
4304af09fceSwh 	if ((opl_cur_model != NULL) && (opl_cur_model->model_type == IKKAKU))
4314af09fceSwh 		return (OPL_MAX_BOARDS_IKKAKU);
4324af09fceSwh 	else
4334af09fceSwh 		return (OPL_MAX_BOARDS);
43425cf1a30Sjl }
43625cf1a30Sjl int
plat_max_cpu_units_per_board(void)43725cf1a30Sjl plat_max_cpu_units_per_board(void)
43825cf1a30Sjl {
43925cf1a30Sjl 	return (OPL_MAX_CPU_PER_BOARD);
44025cf1a30Sjl }
44225cf1a30Sjl int
plat_max_mem_units_per_board(void)44325cf1a30Sjl plat_max_mem_units_per_board(void)
44425cf1a30Sjl {
44525cf1a30Sjl 	return (OPL_MAX_MEM_UNITS_PER_BOARD);
44625cf1a30Sjl }
44825cf1a30Sjl int
plat_max_io_units_per_board(void)44925cf1a30Sjl plat_max_io_units_per_board(void)
45025cf1a30Sjl {
45125cf1a30Sjl 	return (OPL_MAX_IO_UNITS_PER_BOARD);
45225cf1a30Sjl }
45425cf1a30Sjl int
plat_max_cmp_units_per_board(void)45525cf1a30Sjl plat_max_cmp_units_per_board(void)
45625cf1a30Sjl {
45725cf1a30Sjl 	return (OPL_MAX_CMP_UNITS_PER_BOARD);
45825cf1a30Sjl }
46025cf1a30Sjl int
plat_max_core_units_per_board(void)46125cf1a30Sjl plat_max_core_units_per_board(void)
46225cf1a30Sjl {
46325cf1a30Sjl 	return (OPL_MAX_CORE_UNITS_PER_BOARD);
46425cf1a30Sjl }
46625cf1a30Sjl int
plat_pfn_to_mem_node(pfn_t pfn)46725cf1a30Sjl plat_pfn_to_mem_node(pfn_t pfn)
46825cf1a30Sjl {
46925cf1a30Sjl 	return (pfn >> mem_node_pfn_shift);
47025cf1a30Sjl }
47225cf1a30Sjl /* ARGSUSED */
47325cf1a30Sjl void
plat_build_mem_nodes(prom_memlist_t * list,size_t nelems)474986fd29aSsetje plat_build_mem_nodes(prom_memlist_t *list, size_t nelems)
47525cf1a30Sjl {
47625cf1a30Sjl 	size_t	elem;
47725cf1a30Sjl 	pfn_t	basepfn;
47825cf1a30Sjl 	pgcnt_t	npgs;
47925cf1a30Sjl 	uint64_t	boundary, ssize;
48025cf1a30Sjl 	uint64_t	low, high;
48225cf1a30Sjl 	/*
48325cf1a30Sjl 	 * OPL mem slices are always aligned on a 256GB boundary.
48425cf1a30Sjl 	 */
48525cf1a30Sjl 	mem_node_pfn_shift = OPL_MC_MEMBOARD_SHIFT - MMU_PAGESHIFT;
48625cf1a30Sjl 	mem_node_physalign = 0;
48825cf1a30Sjl 	/*
48925cf1a30Sjl 	 * Boot install lists are arranged <addr, len>, <addr, len>, ...
49025cf1a30Sjl 	 */
49125cf1a30Sjl 	ssize = (1ull << OPL_MC_MEMBOARD_SHIFT);
492986fd29aSsetje 	for (elem = 0; elem < nelems; list++, elem++) {
493986fd29aSsetje 		low  = list->addr;
494986fd29aSsetje 		high = low + list->size;
49525cf1a30Sjl 		while (low < high) {
49625cf1a30Sjl 			boundary = roundup(low+1, ssize);
49725cf1a30Sjl 			boundary = MIN(high, boundary);
49825cf1a30Sjl 			basepfn = btop(low);
49925cf1a30Sjl 			npgs = btop(boundary - low);
50025cf1a30Sjl 			mem_node_add_slice(basepfn, basepfn + npgs - 1);
50125cf1a30Sjl 			low = boundary;
50225cf1a30Sjl 		}
50325cf1a30Sjl 	}
50425cf1a30Sjl }
50625cf1a30Sjl /*
50725cf1a30Sjl  * Find the CPU associated with a slice at boot-time.
50825cf1a30Sjl  */
50925cf1a30Sjl void
plat_fill_mc(pnode_t nodeid)51025cf1a30Sjl plat_fill_mc(pnode_t nodeid)
51125cf1a30Sjl {
51225cf1a30Sjl 	int board;
51325cf1a30Sjl 	int memnode;
51425cf1a30Sjl 	struct {
51525cf1a30Sjl 		uint64_t	addr;
51625cf1a30Sjl 		uint64_t	size;
51725cf1a30Sjl 	} mem_range;
51925cf1a30Sjl 	if (prom_getprop(nodeid, "board#", (caddr_t)&board) < 0) {
52025cf1a30Sjl 		panic("Can not find board# property in mc node %x", nodeid);
52125cf1a30Sjl 	}
52225cf1a30Sjl 	if (prom_getprop(nodeid, "sb-mem-ranges", (caddr_t)&mem_range) < 0) {
52325cf1a30Sjl 		panic("Can not find sb-mem-ranges property in mc node %x",
524e98fafb9Sjl 		    nodeid);
52525cf1a30Sjl 	}
52625cf1a30Sjl 	memnode = mem_range.addr >> OPL_MC_MEMBOARD_SHIFT;
52725cf1a30Sjl 	plat_assign_lgrphand_to_mem_node(board, memnode);
52825cf1a30Sjl }
53025cf1a30Sjl /*
53125cf1a30Sjl  * Return the platform handle for the lgroup containing the given CPU
53225cf1a30Sjl  *
53325cf1a30Sjl  * For OPL, lgroup platform handle == board #.
53425cf1a30Sjl  */
53625cf1a30Sjl extern int mpo_disabled;
53725cf1a30Sjl extern lgrp_handle_t lgrp_default_handle;
53925cf1a30Sjl lgrp_handle_t
plat_lgrp_cpu_to_hand(processorid_t id)54025cf1a30Sjl plat_lgrp_cpu_to_hand(processorid_t id)
54125cf1a30Sjl {
54225cf1a30Sjl 	lgrp_handle_t plathand;
54425cf1a30Sjl 	/*
54525cf1a30Sjl 	 * Return the real platform handle for the CPU until
54625cf1a30Sjl 	 * such time as we know that MPO should be disabled.
54725cf1a30Sjl 	 * At that point, we set the "mpo_disabled" flag to true,
54825cf1a30Sjl 	 * and from that point on, return the default handle.
54925cf1a30Sjl 	 *
55025cf1a30Sjl 	 * By the time we know that MPO should be disabled, the
55125cf1a30Sjl 	 * first CPU will have already been added to a leaf
55225cf1a30Sjl 	 * lgroup, but that's ok. The common lgroup code will
55325cf1a30Sjl 	 * double check that the boot CPU is in the correct place,
55425cf1a30Sjl 	 * and in the case where mpo should be disabled, will move
55525cf1a30Sjl 	 * it to the root if necessary.
55625cf1a30Sjl 	 */
55725cf1a30Sjl 	if (mpo_disabled) {
55825cf1a30Sjl 		/* If MPO is disabled, return the default (UMA) handle */
55925cf1a30Sjl 		plathand = lgrp_default_handle;
56025cf1a30Sjl 	} else
56125cf1a30Sjl 		plathand = (lgrp_handle_t)LSB_ID(id);
56225cf1a30Sjl 	return (plathand);
56325cf1a30Sjl }
56525cf1a30Sjl /*
56625cf1a30Sjl  * Platform specific lgroup initialization
56725cf1a30Sjl  */
56825cf1a30Sjl void
plat_lgrp_init(void)56925cf1a30Sjl plat_lgrp_init(void)
57025cf1a30Sjl {
57125cf1a30Sjl 	extern uint32_t lgrp_expand_proc_thresh;
57225cf1a30Sjl 	extern uint32_t lgrp_expand_proc_diff;
573cc85acdaSpm 	const uint_t m = LGRP_LOADAVG_THREAD_MAX;
57525cf1a30Sjl 	/*
57625cf1a30Sjl 	 * Set tuneables for the OPL architecture
57725cf1a30Sjl 	 *
578cc85acdaSpm 	 * lgrp_expand_proc_thresh is the threshold load on the set of
579cc85acdaSpm 	 * lgroups a process is currently using on before considering
580cc85acdaSpm 	 * adding another lgroup to the set.  For Oly-C and Jupiter
581cc85acdaSpm 	 * systems, there are four sockets per lgroup. Setting
582cc85acdaSpm 	 * lgrp_expand_proc_thresh to add lgroups when the load reaches
583cc85acdaSpm 	 * four threads will spread the load when it exceeds one thread
584cc85acdaSpm 	 * per socket, optimizing memory bandwidth and L2 cache space.
58525cf1a30Sjl 	 *
586cc85acdaSpm 	 * lgrp_expand_proc_diff determines how much less another lgroup
587cc85acdaSpm 	 * must be loaded before shifting the start location of a thread
588cc85acdaSpm 	 * to it.
58925cf1a30Sjl 	 *
590cc85acdaSpm 	 * lgrp_loadavg_tolerance is the threshold where two lgroups are
591cc85acdaSpm 	 * considered to have different loads.  It is set to be less than
592cc85acdaSpm 	 * 1% so that even a small residual load will be considered different
593cc85acdaSpm 	 * from no residual load.
594cc85acdaSpm 	 *
595cc85acdaSpm 	 * We note loadavg values are not precise.
596cc85acdaSpm 	 * Every 1/10 of a second loadavg values are reduced by 5%.
597cc85acdaSpm 	 * This adjustment can come in the middle of the lgroup selection
598cc85acdaSpm 	 * process, and for larger parallel apps with many threads can
599cc85acdaSpm 	 * frequently occur between the start of the second thread
600cc85acdaSpm 	 * placement and the finish of the last thread placement.
601cc85acdaSpm 	 * We also must be careful to not use too small of a threshold
602cc85acdaSpm 	 * since the cumulative decay for 1 second idle time is 40%.
603cc85acdaSpm 	 * That is, the residual load from completed threads will still
604cc85acdaSpm 	 * be 60% one second after the proc goes idle or 8% after 5 seconds.
605cc85acdaSpm 	 *
606cc85acdaSpm 	 * To allow for lag time in loadavg calculations
607cc85acdaSpm 	 * remote thresh = 3.75 * LGRP_LOADAVG_THREAD_MAX
608cc85acdaSpm 	 * local thresh  = 0.75 * LGRP_LOADAVG_THREAD_MAX
609cc85acdaSpm 	 * tolerance	 = 0.0078 * LGRP_LOADAVG_THREAD_MAX
610cc85acdaSpm 	 *
611cc85acdaSpm 	 * The load placement algorithms consider LGRP_LOADAVG_THREAD_MAX
612cc85acdaSpm 	 * as the equivalent of a load of 1. To make the code more compact,
613cc85acdaSpm 	 * we set m = LGRP_LOADAVG_THREAD_MAX.
61425cf1a30Sjl 	 */
615cc85acdaSpm 	lgrp_expand_proc_thresh = (m * 3) + (m >> 1) + (m >> 2);
616cc85acdaSpm 	lgrp_expand_proc_diff = (m >> 1) + (m >> 2);
617cc85acdaSpm 	lgrp_loadavg_tolerance = (m >> 7);
61825cf1a30Sjl }
62025cf1a30Sjl /*
62125cf1a30Sjl  * Platform notification of lgroup (re)configuration changes
62225cf1a30Sjl  */
62325cf1a30Sjl /*ARGSUSED*/
62425cf1a30Sjl void
plat_lgrp_config(lgrp_config_flag_t evt,uintptr_t arg)62525cf1a30Sjl plat_lgrp_config(lgrp_config_flag_t evt, uintptr_t arg)
62625cf1a30Sjl {
62725cf1a30Sjl 	update_membounds_t *umb;
62825cf1a30Sjl 	lgrp_config_mem_rename_t lmr;
62925cf1a30Sjl 	int sbd, tbd;
63025cf1a30Sjl 	lgrp_handle_t hand, shand, thand;
63125cf1a30Sjl 	int mnode, snode, tnode;
63225cf1a30Sjl 	pfn_t start, end;
63425cf1a30Sjl 	if (mpo_disabled)
63525cf1a30Sjl 		return;
63725cf1a30Sjl 	switch (evt) {
63925cf1a30Sjl 	case LGRP_CONFIG_MEM_ADD:
64025cf1a30Sjl 		/*
64125cf1a30Sjl 		 * Establish the lgroup handle to memnode translation.
64225cf1a30Sjl 		 */
64325cf1a30Sjl 		umb = (update_membounds_t *)arg;
64525cf1a30Sjl 		hand = umb->u_board;
64625cf1a30Sjl 		mnode = plat_pfn_to_mem_node(umb->u_base >> MMU_PAGESHIFT);
64725cf1a30Sjl 		plat_assign_lgrphand_to_mem_node(hand, mnode);
64925cf1a30Sjl 		break;
65125cf1a30Sjl 	case LGRP_CONFIG_MEM_DEL:
65225cf1a30Sjl 		/*
65325cf1a30Sjl 		 * Special handling for possible memory holes.
65425cf1a30Sjl 		 */
65525cf1a30Sjl 		umb = (update_membounds_t *)arg;
65625cf1a30Sjl 		hand = umb->u_board;
65725cf1a30Sjl 		if ((mnode = plat_lgrphand_to_mem_node(hand)) != -1) {
65825cf1a30Sjl 			if (mem_node_config[mnode].exists) {
65925cf1a30Sjl 				start = mem_node_config[mnode].physbase;
66025cf1a30Sjl 				end = mem_node_config[mnode].physmax;
6619853d9e8SJason Beloro 				mem_node_del_slice(start, end);
66225cf1a30Sjl 			}
66325cf1a30Sjl 		}
66525cf1a30Sjl 		break;
66725cf1a30Sjl 	case LGRP_CONFIG_MEM_RENAME:
66825cf1a30Sjl 		/*
66925cf1a30Sjl 		 * During a DR copy-rename operation, all of the memory
67025cf1a30Sjl 		 * on one board is moved to another board -- but the
67125cf1a30Sjl 		 * addresses/pfns and memnodes don't change. This means
67225cf1a30Sjl 		 * the memory has changed locations without changing identity.
67325cf1a30Sjl 		 *
67425cf1a30Sjl 		 * Source is where we are copying from and target is where we
67525cf1a30Sjl 		 * are copying to.  After source memnode is copied to target
67625cf1a30Sjl 		 * memnode, the physical addresses of the target memnode are
67725cf1a30Sjl 		 * renamed to match what the source memnode had.  Then target
67825cf1a30Sjl 		 * memnode can be removed and source memnode can take its
67925cf1a30Sjl 		 * place.
68025cf1a30Sjl 		 *
68125cf1a30Sjl 		 * To do this, swap the lgroup handle to memnode mappings for
68225cf1a30Sjl 		 * the boards, so target lgroup will have source memnode and
68325cf1a30Sjl 		 * source lgroup will have empty target memnode which is where
68425cf1a30Sjl 		 * its memory will go (if any is added to it later).
68525cf1a30Sjl 		 *
68625cf1a30Sjl 		 * Then source memnode needs to be removed from its lgroup
68725cf1a30Sjl 		 * and added to the target lgroup where the memory was living
68825cf1a30Sjl 		 * but under a different name/memnode.  The memory was in the
68925cf1a30Sjl 		 * target memnode and now lives in the source memnode with
69025cf1a30Sjl 		 * different physical addresses even though it is the same
69125cf1a30Sjl 		 * memory.
69225cf1a30Sjl 		 */
69325cf1a30Sjl 		sbd = arg & 0xffff;
69425cf1a30Sjl 		tbd = (arg & 0xffff0000) >> 16;
69525cf1a30Sjl 		shand = sbd;
69625cf1a30Sjl 		thand = tbd;
69725cf1a30Sjl 		snode = plat_lgrphand_to_mem_node(shand);
69825cf1a30Sjl 		tnode = plat_lgrphand_to_mem_node(thand);
70025cf1a30Sjl 		/*
70125cf1a30Sjl 		 * Special handling for possible memory holes.
70225cf1a30Sjl 		 */
70325cf1a30Sjl 		if (tnode != -1 && mem_node_config[tnode].exists) {
70468ac2337Sjl 			start = mem_node_config[tnode].physbase;
70568ac2337Sjl 			end = mem_node_config[tnode].physmax;
7069853d9e8SJason Beloro 			mem_node_del_slice(start, end);
70725cf1a30Sjl 		}
70925cf1a30Sjl 		plat_assign_lgrphand_to_mem_node(thand, snode);
71025cf1a30Sjl 		plat_assign_lgrphand_to_mem_node(shand, tnode);
71225cf1a30Sjl 		lmr.lmem_rename_from = shand;
71325cf1a30Sjl 		lmr.lmem_rename_to = thand;
71525cf1a30Sjl 		/*
71625cf1a30Sjl 		 * Remove source memnode of copy rename from its lgroup
71725cf1a30Sjl 		 * and add it to its new target lgroup
71825cf1a30Sjl 		 */
71925cf1a30Sjl 		lgrp_config(LGRP_CONFIG_MEM_RENAME, (uintptr_t)snode,
72025cf1a30Sjl 		    (uintptr_t)&lmr);
72225cf1a30Sjl 		break;
72425cf1a30Sjl 	default:
72525cf1a30Sjl 		break;
72625cf1a30Sjl 	}
72725cf1a30Sjl }
72925cf1a30Sjl /*
73025cf1a30Sjl  * Return latency between "from" and "to" lgroups
73125cf1a30Sjl  *
73225cf1a30Sjl  * This latency number can only be used for relative comparison
73325cf1a30Sjl  * between lgroups on the running system, cannot be used across platforms,
73425cf1a30Sjl  * and may not reflect the actual latency.  It is platform and implementation
73525cf1a30Sjl  * specific, so platform gets to decide its value.  It would be nice if the
73625cf1a30Sjl  * number was at least proportional to make comparisons more meaningful though.
73725cf1a30Sjl  * NOTE: The numbers below are supposed to be load latencies for uncached
73825cf1a30Sjl  * memory divided by 10.
73925cf1a30Sjl  *
74025cf1a30Sjl  */
74125cf1a30Sjl int
plat_lgrp_latency(lgrp_handle_t from,lgrp_handle_t to)74225cf1a30Sjl plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to)
74325cf1a30Sjl {
74425cf1a30Sjl 	/*
74525cf1a30Sjl 	 * Return min remote latency when there are more than two lgroups
74625cf1a30Sjl 	 * (root and child) and getting latency between two different lgroups
74725cf1a30Sjl 	 * or root is involved
74825cf1a30Sjl 	 */
74925cf1a30Sjl 	if (lgrp_optimizations() && (from != to ||
75025cf1a30Sjl 	    from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE))
75171b3c2ffShyw 		return (42);
75225cf1a30Sjl 	else
75371b3c2ffShyw 		return (35);
75425cf1a30Sjl }
75625cf1a30Sjl /*
75725cf1a30Sjl  * Return platform handle for root lgroup
75825cf1a30Sjl  */
75925cf1a30Sjl lgrp_handle_t
plat_lgrp_root_hand(void)76025cf1a30Sjl plat_lgrp_root_hand(void)
76125cf1a30Sjl {
76225cf1a30Sjl 	if (mpo_disabled)
76325cf1a30Sjl 		return (lgrp_default_handle);
76525cf1a30Sjl 	return (LGRP_DEFAULT_HANDLE);
76625cf1a30Sjl }
76825cf1a30Sjl /*ARGSUSED*/
76925cf1a30Sjl void
plat_freelist_process(int mnode)77025cf1a30Sjl plat_freelist_process(int mnode)
77125cf1a30Sjl {
77225cf1a30Sjl }
77425cf1a30Sjl void
load_platform_drivers(void)77525cf1a30Sjl load_platform_drivers(void)
77625cf1a30Sjl {
77725cf1a30Sjl 	(void) i_ddi_attach_pseudo_node("dr");
77825cf1a30Sjl }
78025cf1a30Sjl /*
78125cf1a30Sjl  * No platform drivers on this platform
78225cf1a30Sjl  */
78325cf1a30Sjl char *platform_module_list[] = {
78425cf1a30Sjl 	(char *)0
78525cf1a30Sjl };
78725cf1a30Sjl /*ARGSUSED*/
78825cf1a30Sjl void
plat_tod_fault(enum tod_fault_type tod_bad)78925cf1a30Sjl plat_tod_fault(enum tod_fault_type tod_bad)
79025cf1a30Sjl {
79125cf1a30Sjl }
79325cf1a30Sjl /*ARGSUSED*/
79425cf1a30Sjl void
cpu_sgn_update(ushort_t sgn,uchar_t state,uchar_t sub_state,int cpuid)79525cf1a30Sjl cpu_sgn_update(ushort_t sgn, uchar_t state, uchar_t sub_state, int cpuid)
79625cf1a30Sjl {
79725cf1a30Sjl 	static void (*scf_panic_callback)(int);
79825cf1a30Sjl 	static void (*scf_shutdown_callback)(int);
80025cf1a30Sjl 	/*
80125cf1a30Sjl 	 * This is for notifing system panic/shutdown to SCF.
80225cf1a30Sjl 	 * In case of shutdown and panic, SCF call back
80325cf1a30Sjl 	 * function should be called.
80425cf1a30Sjl 	 *  <SCF call back functions>
80525cf1a30Sjl 	 *   scf_panic_callb()   : panicsys()->panic_quiesce_hw()
80625cf1a30Sjl 	 *   scf_shutdown_callb(): halt() or power_down() or reboot_machine()
80725cf1a30Sjl 	 * cpuid should be -1 and state should be SIGST_EXIT.
80825cf1a30Sjl 	 */
80925cf1a30Sjl 	if (state == SIGST_EXIT && cpuid == -1) {
81125cf1a30Sjl 		/*
81225cf1a30Sjl 		 * find the symbol for the SCF panic callback routine in driver
81325cf1a30Sjl 		 */
81425cf1a30Sjl 		if (scf_panic_callback == NULL)
81525cf1a30Sjl 			scf_panic_callback = (void (*)(int))
816e98fafb9Sjl 			    modgetsymvalue("scf_panic_callb", 0);
81725cf1a30Sjl 		if (scf_shutdown_callback == NULL)
81825cf1a30Sjl 			scf_shutdown_callback = (void (*)(int))
819e98fafb9Sjl 			    modgetsymvalue("scf_shutdown_callb", 0);
82125cf1a30Sjl 		switch (sub_state) {
82225cf1a30Sjl 		case SIGSUBST_PANIC:
82325cf1a30Sjl 			if (scf_panic_callback == NULL) {
82425cf1a30Sjl 				cmn_err(CE_NOTE, "!cpu_sgn_update: "
82525cf1a30Sjl 				    "scf_panic_callb not found\n");
82625cf1a30Sjl 				return;
82725cf1a30Sjl 			}
82825cf1a30Sjl 			scf_panic_callback(SIGSUBST_PANIC);
82925cf1a30Sjl 			break;
83125cf1a30Sjl 		case SIGSUBST_HALT:
83225cf1a30Sjl 			if (scf_shutdown_callback == NULL) {
83325cf1a30Sjl 				cmn_err(CE_NOTE, "!cpu_sgn_update: "
83425cf1a30Sjl 				    "scf_shutdown_callb not found\n");
83525cf1a30Sjl 				return;
83625cf1a30Sjl 			}
83725cf1a30Sjl 			scf_shutdown_callback(SIGSUBST_HALT);
83825cf1a30Sjl 			break;
84025cf1a30Sjl 		case SIGSUBST_ENVIRON:
84125cf1a30Sjl 			if (scf_shutdown_callback == NULL) {
84225cf1a30Sjl 				cmn_err(CE_NOTE, "!cpu_sgn_update: "
84325cf1a30Sjl 				    "scf_shutdown_callb not found\n");
84425cf1a30Sjl 				return;
84525cf1a30Sjl 			}
84625cf1a30Sjl 			scf_shutdown_callback(SIGSUBST_ENVIRON);
84725cf1a30Sjl 			break;
84925cf1a30Sjl 		case SIGSUBST_REBOOT:
85025cf1a30Sjl 			if (scf_shutdown_callback == NULL) {
85125cf1a30Sjl 				cmn_err(CE_NOTE, "!cpu_sgn_update: "
85225cf1a30Sjl 				    "scf_shutdown_callb not found\n");
85325cf1a30Sjl 				return;
85425cf1a30Sjl 			}
85525cf1a30Sjl 			scf_shutdown_callback(SIGSUBST_REBOOT);
85625cf1a30Sjl 			break;
85725cf1a30Sjl 		}
85825cf1a30Sjl 	}
85925cf1a30Sjl }
86125cf1a30Sjl /*ARGSUSED*/
86225cf1a30Sjl int
plat_get_mem_unum(int synd_code,uint64_t flt_addr,int flt_bus_id,int flt_in_memory,ushort_t flt_status,char * buf,int buflen,int * lenp)86325cf1a30Sjl plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id,
86425cf1a30Sjl 	int flt_in_memory, ushort_t flt_status,
86525cf1a30Sjl 	char *buf, int buflen, int *lenp)
86625cf1a30Sjl {
86725cf1a30Sjl 	/*
86825cf1a30Sjl 	 * check if it's a Memory error.
86925cf1a30Sjl 	 */
87025cf1a30Sjl 	if (flt_in_memory) {
87125cf1a30Sjl 		if (opl_get_mem_unum != NULL) {
872e98fafb9Sjl 			return (opl_get_mem_unum(synd_code, flt_addr, buf,
873e98fafb9Sjl 			    buflen, lenp));
87425cf1a30Sjl 		} else {
87525cf1a30Sjl 			return (ENOTSUP);
87625cf1a30Sjl 		}
87725cf1a30Sjl 	} else {
87825cf1a30Sjl 		return (ENOTSUP);
87925cf1a30Sjl 	}
88025cf1a30Sjl }
88225cf1a30Sjl /*ARGSUSED*/
88325cf1a30Sjl int
plat_get_cpu_unum(int cpuid,char * buf,int buflen,int * lenp)88425cf1a30Sjl plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp)
88525cf1a30Sjl {
8860cc8ae86Sav 	int	ret = 0;
8873f1fa9a7Sjfrank 	int	sb;
888195196c6Ssubhan 	int	plen;
89025cf1a30Sjl 	sb = opl_get_physical_board(LSB_ID(cpuid));
89125cf1a30Sjl 	if (sb == -1) {
89225cf1a30Sjl 		return (ENXIO);
89325cf1a30Sjl 	}
89572b9fce9Ssubhan 	/*
89672b9fce9Ssubhan 	 * opl_cur_model is assigned here
89772b9fce9Ssubhan 	 */
89872b9fce9Ssubhan 	if (opl_cur_model == NULL) {
89972b9fce9Ssubhan 		set_model_info();
9019b71d8e9Swh 		/*
9029b71d8e9Swh 		 * if not matched, return
9039b71d8e9Swh 		 */
9049b71d8e9Swh 		if (opl_cur_model == NULL)
9059b71d8e9Swh 			return (ENODEV);
90672b9fce9Ssubhan 	}
908195196c6Ssubhan 	ASSERT((opl_cur_model - opl_models) == (opl_cur_model->model_type));
910195196c6Ssubhan 	switch (opl_cur_model->model_type) {
911195196c6Ssubhan 	case FF1:
9120cc8ae86Sav 		plen = snprintf(buf, buflen, "/%s/CPUM%d", "MBU_A",
9130cc8ae86Sav 		    CHIP_ID(cpuid) / 2);
9140cc8ae86Sav 		break;
916195196c6Ssubhan 	case FF2: