125cf1a30Sjl /*
225cf1a30Sjl * CDDL HEADER START
325cf1a30Sjl *
425cf1a30Sjl * The contents of this file are subject to the terms of the
525cf1a30Sjl * Common Development and Distribution License (the "License").
625cf1a30Sjl * You may not use this file except in compliance with the License.
725cf1a30Sjl *
825cf1a30Sjl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
925cf1a30Sjl * or http://www.opensolaris.org/os/licensing.
1025cf1a30Sjl * See the License for the specific language governing permissions
1125cf1a30Sjl * and limitations under the License.
1225cf1a30Sjl *
1325cf1a30Sjl * When distributing Covered Code, include this CDDL HEADER in each
1425cf1a30Sjl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1525cf1a30Sjl * If applicable, add the following below this CDDL HEADER, with the
1625cf1a30Sjl * fields enclosed by brackets "[]" replaced with your own identifying
1725cf1a30Sjl * information: Portions Copyright [yyyy] [name of copyright owner]
1825cf1a30Sjl *
1925cf1a30Sjl * CDDL HEADER END
2025cf1a30Sjl */
2125cf1a30Sjl /*
224cca9c84SDave Plauger * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
2325cf1a30Sjl */
2425cf1a30Sjl
253fe80ca4SDan Cross /*
263fe80ca4SDan Cross * Copyright 2023 Oxide Computer Company
273fe80ca4SDan Cross */
283fe80ca4SDan Cross
2925cf1a30Sjl #include <sys/cpuvar.h>
3025cf1a30Sjl #include <sys/systm.h>
3125cf1a30Sjl #include <sys/sysmacros.h>
3225cf1a30Sjl #include <sys/promif.h>
3325cf1a30Sjl #include <sys/platform_module.h>
3425cf1a30Sjl #include <sys/cmn_err.h>
3525cf1a30Sjl #include <sys/errno.h>
3625cf1a30Sjl #include <sys/machsystm.h>
3725cf1a30Sjl #include <sys/bootconf.h>
3825cf1a30Sjl #include <sys/nvpair.h>
3925cf1a30Sjl #include <sys/kobj.h>
4025cf1a30Sjl #include <sys/mem_cage.h>
4125cf1a30Sjl #include <sys/opl.h>
4225cf1a30Sjl #include <sys/scfd/scfostoescf.h>
4325cf1a30Sjl #include <sys/cpu_sgnblk_defs.h>
4425cf1a30Sjl #include <sys/utsname.h>
4525cf1a30Sjl #include <sys/ddi.h>
4625cf1a30Sjl #include <sys/sunndi.h>
4725cf1a30Sjl #include <sys/lgrp.h>
4825cf1a30Sjl #include <sys/memnode.h>
4925cf1a30Sjl #include <sys/sysmacros.h>
50e603b7d4Spm #include <sys/time.h>
51e603b7d4Spm #include <sys/cpu.h>
52ca3e8d88SDave Plauger #include <sys/dumphdr.h>
5325cf1a30Sjl #include <vm/vm_dep.h>
5425cf1a30Sjl
5525cf1a30Sjl int (*opl_get_mem_unum)(int, uint64_t, char *, int, int *);
560cc8ae86Sav int (*opl_get_mem_sid)(char *unum, char *buf, int buflen, int *lenp);
570cc8ae86Sav int (*opl_get_mem_offset)(uint64_t paddr, uint64_t *offp);
580cc8ae86Sav int (*opl_get_mem_addr)(char *unum, char *sid,
590cc8ae86Sav uint64_t offset, uint64_t *paddr);
6025cf1a30Sjl
6125cf1a30Sjl /* Memory for fcode claims. 16k times # maximum possible IO units */
6225cf1a30Sjl #define EFCODE_SIZE (OPL_MAX_BOARDS * OPL_MAX_IO_UNITS_PER_BOARD * 0x4000)
6325cf1a30Sjl int efcode_size = EFCODE_SIZE;
6425cf1a30Sjl
6525cf1a30Sjl #define OPL_MC_MEMBOARD_SHIFT 38 /* Boards on 256BG boundary */
6625cf1a30Sjl
6725cf1a30Sjl /* Set the maximum number of boards for DR */
6825cf1a30Sjl int opl_boards = OPL_MAX_BOARDS;
6925cf1a30Sjl
7025cf1a30Sjl void sgn_update_all_cpus(ushort_t, uchar_t, uchar_t);
7125cf1a30Sjl
7225cf1a30Sjl extern int tsb_lgrp_affinity;
7325cf1a30Sjl
7425cf1a30Sjl int opl_tsb_spares = (OPL_MAX_BOARDS) * (OPL_MAX_PCICH_UNITS_PER_BOARD) *
7525cf1a30Sjl (OPL_MAX_TSBS_PER_PCICH);
7625cf1a30Sjl
7725cf1a30Sjl pgcnt_t opl_startup_cage_size = 0;
7825cf1a30Sjl
793f1fa9a7Sjfrank /*
803f1fa9a7Sjfrank * The length of the delay in seconds in communication with XSCF after
813f1fa9a7Sjfrank * which the warning message will be logged.
823f1fa9a7Sjfrank */
833f1fa9a7Sjfrank uint_t xscf_connect_delay = 60 * 15;
843f1fa9a7Sjfrank
851e2e7a75Shuah static opl_model_info_t opl_models[] = {
86195196c6Ssubhan { "FF1", OPL_MAX_BOARDS_FF1, FF1, STD_DISPATCH_TABLE },
87195196c6Ssubhan { "FF2", OPL_MAX_BOARDS_FF2, FF2, STD_DISPATCH_TABLE },
88195196c6Ssubhan { "DC1", OPL_MAX_BOARDS_DC1, DC1, STD_DISPATCH_TABLE },
89195196c6Ssubhan { "DC2", OPL_MAX_BOARDS_DC2, DC2, EXT_DISPATCH_TABLE },
90195196c6Ssubhan { "DC3", OPL_MAX_BOARDS_DC3, DC3, EXT_DISPATCH_TABLE },
9178ed97a7Sjl { "IKKAKU", OPL_MAX_BOARDS_IKKAKU, IKKAKU, STD_DISPATCH_TABLE },
921e2e7a75Shuah };
931e2e7a75Shuah static int opl_num_models = sizeof (opl_models)/sizeof (opl_model_info_t);
941e2e7a75Shuah
95195196c6Ssubhan /*
9672b9fce9Ssubhan * opl_cur_model
97195196c6Ssubhan */
9872b9fce9Ssubhan static opl_model_info_t *opl_cur_model = NULL;
991e2e7a75Shuah
10025cf1a30Sjl static struct memlist *opl_memlist_per_board(struct memlist *ml);
1013f1fa9a7Sjfrank static void post_xscf_msg(char *, int);
1023f1fa9a7Sjfrank static void pass2xscf_thread();
10325cf1a30Sjl
104e603b7d4Spm /*
105e603b7d4Spm * Note FF/DC out-of-order instruction engine takes only a
106e603b7d4Spm * single cycle to execute each spin loop
107e603b7d4Spm * for comparison, Panther takes 6 cycles for same loop
108575a7426Spt * OPL_BOFF_SPIN = base spin loop, roughly one memory reference time
109575a7426Spt * OPL_BOFF_TM = approx nsec for OPL sleep instruction (1600 for OPL-C)
110575a7426Spt * OPL_BOFF_SLEEP = approx number of SPIN iterations to equal one sleep
111575a7426Spt * OPL_BOFF_MAX_SCALE - scaling factor for max backoff based on active cpus
112575a7426Spt * Listed values tuned for 2.15GHz to 2.64GHz systems
113e603b7d4Spm * Value may change for future systems
114e603b7d4Spm */
115575a7426Spt #define OPL_BOFF_SPIN 7
116575a7426Spt #define OPL_BOFF_SLEEP 4
117575a7426Spt #define OPL_BOFF_TM 1600
118575a7426Spt #define OPL_BOFF_MAX_SCALE 8
119e603b7d4Spm
1202850d85bSmv #define OPL_CLOCK_TICK_THRESHOLD 128
1212850d85bSmv #define OPL_CLOCK_TICK_NCPUS 64
1222850d85bSmv
1232850d85bSmv extern int clock_tick_threshold;
1242850d85bSmv extern int clock_tick_ncpus;
1252850d85bSmv
12625cf1a30Sjl int
set_platform_max_ncpus(void)12725cf1a30Sjl set_platform_max_ncpus(void)
12825cf1a30Sjl {
12925cf1a30Sjl return (OPL_MAX_CPU_PER_BOARD * OPL_MAX_BOARDS);
13025cf1a30Sjl }
13125cf1a30Sjl
13225cf1a30Sjl int
set_platform_tsb_spares(void)13325cf1a30Sjl set_platform_tsb_spares(void)
13425cf1a30Sjl {
13525cf1a30Sjl return (MIN(opl_tsb_spares, MAX_UPA));
13625cf1a30Sjl }
13725cf1a30Sjl
1381e2e7a75Shuah static void
set_model_info()1391e2e7a75Shuah set_model_info()
1401e2e7a75Shuah {
141195196c6Ssubhan extern int ts_dispatch_extended;
1421e2e7a75Shuah char name[MAXSYSNAME];
1431e2e7a75Shuah int i;
1441e2e7a75Shuah
1451e2e7a75Shuah /*
1461e2e7a75Shuah * Get model name from the root node.
1471e2e7a75Shuah *
1481e2e7a75Shuah * We are using the prom device tree since, at this point,
1491e2e7a75Shuah * the Solaris device tree is not yet setup.
1501e2e7a75Shuah */
1511e2e7a75Shuah (void) prom_getprop(prom_rootnode(), "model", (caddr_t)name);
1521e2e7a75Shuah
1531e2e7a75Shuah for (i = 0; i < opl_num_models; i++) {
1541e2e7a75Shuah if (strncmp(name, opl_models[i].model_name, MAXSYSNAME) == 0) {
1551e2e7a75Shuah opl_cur_model = &opl_models[i];
1561e2e7a75Shuah break;
1571e2e7a75Shuah }
1581e2e7a75Shuah }
159195196c6Ssubhan
1609b71d8e9Swh /*
1619b71d8e9Swh * If model not matched, it's an unknown model.
16278ed97a7Sjl * Just return. It will default to standard dispatch tables.
1639b71d8e9Swh */
1641e2e7a75Shuah if (i == opl_num_models)
1659b71d8e9Swh return;
166195196c6Ssubhan
167195196c6Ssubhan if ((opl_cur_model->model_cmds & EXT_DISPATCH_TABLE) &&
168e98fafb9Sjl (ts_dispatch_extended == -1)) {
169195196c6Ssubhan /*
170195196c6Ssubhan * Based on a platform model, select a dispatch table.
171195196c6Ssubhan * Only DC2 and DC3 systems uses the alternate/extended
172195196c6Ssubhan * TS dispatch table.
17378ed97a7Sjl * IKKAKU, FF1, FF2 and DC1 systems use standard dispatch
17478ed97a7Sjl * tables.
175195196c6Ssubhan */
176195196c6Ssubhan ts_dispatch_extended = 1;
177195196c6Ssubhan }
178195196c6Ssubhan
1791e2e7a75Shuah }
1801e2e7a75Shuah
1811e2e7a75Shuah static void
set_max_mmu_ctxdoms()1821e2e7a75Shuah set_max_mmu_ctxdoms()
1831e2e7a75Shuah {
1841e2e7a75Shuah extern uint_t max_mmu_ctxdoms;
1851e2e7a75Shuah int max_boards;
1861e2e7a75Shuah
1871e2e7a75Shuah /*
1881e2e7a75Shuah * From the model, get the maximum number of boards
1891e2e7a75Shuah * supported and set the value accordingly. If the model
1901e2e7a75Shuah * could not be determined or recognized, we assume the max value.
1911e2e7a75Shuah */
1921e2e7a75Shuah if (opl_cur_model == NULL)
1931e2e7a75Shuah max_boards = OPL_MAX_BOARDS;
1941e2e7a75Shuah else
1951e2e7a75Shuah max_boards = opl_cur_model->model_max_boards;
1961e2e7a75Shuah
1971e2e7a75Shuah /*
1981e2e7a75Shuah * On OPL, cores and MMUs are one-to-one.
1991e2e7a75Shuah */
2001e2e7a75Shuah max_mmu_ctxdoms = OPL_MAX_CORE_UNITS_PER_BOARD * max_boards;
2011e2e7a75Shuah }
2021e2e7a75Shuah
20325cf1a30Sjl #pragma weak mmu_init_large_pages
20425cf1a30Sjl
20525cf1a30Sjl void
set_platform_defaults(void)20625cf1a30Sjl set_platform_defaults(void)
20725cf1a30Sjl {
20825cf1a30Sjl extern char *tod_module_name;
20925cf1a30Sjl extern void cpu_sgn_update(ushort_t, uchar_t, uchar_t, int);
21025cf1a30Sjl extern void mmu_init_large_pages(size_t);
21125cf1a30Sjl
21225cf1a30Sjl /* Set the CPU signature function pointer */
21325cf1a30Sjl cpu_sgn_func = cpu_sgn_update;
21425cf1a30Sjl
21525cf1a30Sjl /* Set appropriate tod module for OPL platform */
21625cf1a30Sjl ASSERT(tod_module_name == NULL);
21725cf1a30Sjl tod_module_name = "todopl";
21825cf1a30Sjl
21925cf1a30Sjl if ((mmu_page_sizes == max_mmu_page_sizes) &&
220e12a8a13Ssusans (mmu_ism_pagesize != DEFAULT_ISM_PAGESIZE)) {
22125cf1a30Sjl if (&mmu_init_large_pages)
22225cf1a30Sjl mmu_init_large_pages(mmu_ism_pagesize);
22325cf1a30Sjl }
22425cf1a30Sjl
22525cf1a30Sjl tsb_lgrp_affinity = 1;
2261e2e7a75Shuah
2271e2e7a75Shuah set_max_mmu_ctxdoms();
228ca3e8d88SDave Plauger
229ca3e8d88SDave Plauger /* set OPL threshold for compressed dumps */
2304cca9c84SDave Plauger dump_plat_mincpu_default = DUMP_PLAT_SUN4U_OPL_MINCPU;
23125cf1a30Sjl }
23225cf1a30Sjl
23325cf1a30Sjl /*
23425cf1a30Sjl * Convert logical a board number to a physical one.
23525cf1a30Sjl */
23625cf1a30Sjl
23725cf1a30Sjl #define LSBPROP "board#"
23825cf1a30Sjl #define PSBPROP "physical-board#"
23925cf1a30Sjl
24025cf1a30Sjl int
opl_get_physical_board(int id)24125cf1a30Sjl opl_get_physical_board(int id)
24225cf1a30Sjl {
24325cf1a30Sjl dev_info_t *root_dip, *dip = NULL;
24425cf1a30Sjl char *dname = NULL;
24525cf1a30Sjl
24625cf1a30Sjl pnode_t pnode;
24725cf1a30Sjl char pname[MAXSYSNAME] = {0};
24825cf1a30Sjl
24925cf1a30Sjl int lsb_id; /* Logical System Board ID */
25025cf1a30Sjl int psb_id; /* Physical System Board ID */
25125cf1a30Sjl
25225cf1a30Sjl
25325cf1a30Sjl /*
25425cf1a30Sjl * This function is called on early stage of bootup when the
25525cf1a30Sjl * kernel device tree is not initialized yet, and also
25625cf1a30Sjl * later on when the device tree is up. We want to try
25725cf1a30Sjl * the fast track first.
25825cf1a30Sjl */
25925cf1a30Sjl root_dip = ddi_root_node();
26025cf1a30Sjl if (root_dip) {
26125cf1a30Sjl /* Get from devinfo node */
2623fe80ca4SDan Cross ndi_devi_enter(root_dip);
26325cf1a30Sjl for (dip = ddi_get_child(root_dip); dip;
26425cf1a30Sjl dip = ddi_get_next_sibling(dip)) {
26525cf1a30Sjl
26625cf1a30Sjl dname = ddi_node_name(dip);
26725cf1a30Sjl if (strncmp(dname, "pseudo-mc", 9) != 0)
26825cf1a30Sjl continue;
26925cf1a30Sjl
27025cf1a30Sjl if ((lsb_id = (int)ddi_getprop(DDI_DEV_T_ANY, dip,
27125cf1a30Sjl DDI_PROP_DONTPASS, LSBPROP, -1)) == -1)
27225cf1a30Sjl continue;
27325cf1a30Sjl
27425cf1a30Sjl if (id == lsb_id) {
27525cf1a30Sjl if ((psb_id = (int)ddi_getprop(DDI_DEV_T_ANY,
27625cf1a30Sjl dip, DDI_PROP_DONTPASS, PSBPROP, -1))
27725cf1a30Sjl == -1) {
2783fe80ca4SDan Cross ndi_devi_exit(root_dip);
27925cf1a30Sjl return (-1);
28025cf1a30Sjl } else {
2813fe80ca4SDan Cross ndi_devi_exit(root_dip);
28225cf1a30Sjl return (psb_id);
28325cf1a30Sjl }
28425cf1a30Sjl }
28525cf1a30Sjl }
2863fe80ca4SDan Cross ndi_devi_exit(root_dip);
28725cf1a30Sjl }
28825cf1a30Sjl
28925cf1a30Sjl /*
29025cf1a30Sjl * We do not have the kernel device tree, or we did not
29125cf1a30Sjl * find the node for some reason (let's say the kernel
29225cf1a30Sjl * device tree was modified), let's try the OBP tree.
29325cf1a30Sjl */
29425cf1a30Sjl pnode = prom_rootnode();
29525cf1a30Sjl for (pnode = prom_childnode(pnode); pnode;
29625cf1a30Sjl pnode = prom_nextnode(pnode)) {
29725cf1a30Sjl
29825cf1a30Sjl if ((prom_getprop(pnode, "name", (caddr_t)pname) == -1) ||
29925cf1a30Sjl (strncmp(pname, "pseudo-mc", 9) != 0))
30025cf1a30Sjl continue;
30125cf1a30Sjl
30225cf1a30Sjl if (prom_getprop(pnode, LSBPROP, (caddr_t)&lsb_id) == -1)
30325cf1a30Sjl continue;
30425cf1a30Sjl
30525cf1a30Sjl if (id == lsb_id) {
30625cf1a30Sjl if (prom_getprop(pnode, PSBPROP,
30725cf1a30Sjl (caddr_t)&psb_id) == -1) {
30825cf1a30Sjl return (-1);
30925cf1a30Sjl } else {
31025cf1a30Sjl return (psb_id);
31125cf1a30Sjl }
31225cf1a30Sjl }
31325cf1a30Sjl }
31425cf1a30Sjl
31525cf1a30Sjl return (-1);
31625cf1a30Sjl }
31725cf1a30Sjl
31825cf1a30Sjl /*
31925cf1a30Sjl * For OPL it's possible that memory from two or more successive boards
32025cf1a30Sjl * will be contiguous across the boards, and therefore represented as a
32125cf1a30Sjl * single chunk.
32225cf1a30Sjl * This function splits such chunks down the board boundaries.
32325cf1a30Sjl */
32425cf1a30Sjl static struct memlist *
opl_memlist_per_board(struct memlist * ml)32525cf1a30Sjl opl_memlist_per_board(struct memlist *ml)
32625cf1a30Sjl {
32725cf1a30Sjl uint64_t ssize, low, high, boundary;
32825cf1a30Sjl struct memlist *head, *tail, *new;
32925cf1a30Sjl
33025cf1a30Sjl ssize = (1ull << OPL_MC_MEMBOARD_SHIFT);
33125cf1a30Sjl
33225cf1a30Sjl head = tail = NULL;
33325cf1a30Sjl
33456f33205SJonathan Adams for (; ml; ml = ml->ml_next) {
33556f33205SJonathan Adams low = (uint64_t)ml->ml_address;
33656f33205SJonathan Adams high = low+(uint64_t)(ml->ml_size);
33725cf1a30Sjl while (low < high) {
33825cf1a30Sjl boundary = roundup(low+1, ssize);
33925cf1a30Sjl boundary = MIN(high, boundary);
34025cf1a30Sjl new = kmem_zalloc(sizeof (struct memlist), KM_SLEEP);
34156f33205SJonathan Adams new->ml_address = low;
34256f33205SJonathan Adams new->ml_size = boundary - low;
34325cf1a30Sjl if (head == NULL)
34425cf1a30Sjl head = new;
34525cf1a30Sjl if (tail) {
34656f33205SJonathan Adams tail->ml_next = new;
34756f33205SJonathan Adams new->ml_prev = tail;
34825cf1a30Sjl }
34925cf1a30Sjl tail = new;
35025cf1a30Sjl low = boundary;
35125cf1a30Sjl }
35225cf1a30Sjl }
35325cf1a30Sjl return (head);
35425cf1a30Sjl }
35525cf1a30Sjl
35625cf1a30Sjl void
set_platform_cage_params(void)35725cf1a30Sjl set_platform_cage_params(void)
35825cf1a30Sjl {
35925cf1a30Sjl extern pgcnt_t total_pages;
36025cf1a30Sjl extern struct memlist *phys_avail;
36125cf1a30Sjl struct memlist *ml, *tml;
36225cf1a30Sjl
36325cf1a30Sjl if (kernel_cage_enable) {
36425cf1a30Sjl pgcnt_t preferred_cage_size;
36525cf1a30Sjl
366e98fafb9Sjl preferred_cage_size = MAX(opl_startup_cage_size,
367e98fafb9Sjl total_pages / 256);
36825cf1a30Sjl
36925cf1a30Sjl ml = opl_memlist_per_board(phys_avail);
37025cf1a30Sjl
37125cf1a30Sjl /*
37225cf1a30Sjl * Note: we are assuming that post has load the
37325cf1a30Sjl * whole show in to the high end of memory. Having
37425cf1a30Sjl * taken this leap, we copy the whole of phys_avail
37525cf1a30Sjl * the glist and arrange for the cage to grow
37625cf1a30Sjl * downward (descending pfns).
37725cf1a30Sjl */
37885f58038Sdp kcage_range_init(ml, KCAGE_DOWN, preferred_cage_size);
37925cf1a30Sjl
38025cf1a30Sjl /* free the memlist */
38125cf1a30Sjl do {
38256f33205SJonathan Adams tml = ml->ml_next;
38325cf1a30Sjl kmem_free(ml, sizeof (struct memlist));
38425cf1a30Sjl ml = tml;
38525cf1a30Sjl } while (ml != NULL);
38625cf1a30Sjl }
38725cf1a30Sjl
38825cf1a30Sjl if (kcage_on)
38925cf1a30Sjl cmn_err(CE_NOTE, "!DR Kernel Cage is ENABLED");
39025cf1a30Sjl else
39125cf1a30Sjl cmn_err(CE_NOTE, "!DR Kernel Cage is DISABLED");
39225cf1a30Sjl }
39325cf1a30Sjl
39425cf1a30Sjl /*ARGSUSED*/
39525cf1a30Sjl int
plat_cpu_poweron(struct cpu * cp)39625cf1a30Sjl plat_cpu_poweron(struct cpu *cp)
39725cf1a30Sjl {
39825cf1a30Sjl int (*opl_cpu_poweron)(struct cpu *) = NULL;
39925cf1a30Sjl
40025cf1a30Sjl opl_cpu_poweron =
40125cf1a30Sjl (int (*)(struct cpu *))kobj_getsymvalue("drmach_cpu_poweron", 0);
40225cf1a30Sjl
40325cf1a30Sjl if (opl_cpu_poweron == NULL)
40425cf1a30Sjl return (ENOTSUP);
40525cf1a30Sjl else
40625cf1a30Sjl return ((opl_cpu_poweron)(cp));
40725cf1a30Sjl
40825cf1a30Sjl }
40925cf1a30Sjl
41025cf1a30Sjl /*ARGSUSED*/
41125cf1a30Sjl int
plat_cpu_poweroff(struct cpu * cp)41225cf1a30Sjl plat_cpu_poweroff(struct cpu *cp)
41325cf1a30Sjl {
41425cf1a30Sjl int (*opl_cpu_poweroff)(struct cpu *) = NULL;
41525cf1a30Sjl
41625cf1a30Sjl opl_cpu_poweroff =
41725cf1a30Sjl (int (*)(struct cpu *))kobj_getsymvalue("drmach_cpu_poweroff", 0);
41825cf1a30Sjl
41925cf1a30Sjl if (opl_cpu_poweroff == NULL)
42025cf1a30Sjl return (ENOTSUP);
42125cf1a30Sjl else
42225cf1a30Sjl return ((opl_cpu_poweroff)(cp));
42325cf1a30Sjl
42425cf1a30Sjl }
42525cf1a30Sjl
42625cf1a30Sjl int
plat_max_boards(void)42725cf1a30Sjl plat_max_boards(void)
42825cf1a30Sjl {
4294af09fceSwh /*
4304af09fceSwh * If the model cannot be determined, default to the max value.
4314af09fceSwh * Otherwise, Ikkaku model only supports 1 system board.
4324af09fceSwh */
4334af09fceSwh if ((opl_cur_model != NULL) && (opl_cur_model->model_type == IKKAKU))
4344af09fceSwh return (OPL_MAX_BOARDS_IKKAKU);
4354af09fceSwh else
4364af09fceSwh return (OPL_MAX_BOARDS);
43725cf1a30Sjl }
43825cf1a30Sjl
43925cf1a30Sjl int
plat_max_cpu_units_per_board(void)44025cf1a30Sjl plat_max_cpu_units_per_board(void)
44125cf1a30Sjl {
44225cf1a30Sjl return (OPL_MAX_CPU_PER_BOARD);
44325cf1a30Sjl }
44425cf1a30Sjl
44525cf1a30Sjl int
plat_max_mem_units_per_board(void)44625cf1a30Sjl plat_max_mem_units_per_board(void)
44725cf1a30Sjl {
44825cf1a30Sjl return (OPL_MAX_MEM_UNITS_PER_BOARD);
44925cf1a30Sjl }
45025cf1a30Sjl
45125cf1a30Sjl int
plat_max_io_units_per_board(void)45225cf1a30Sjl plat_max_io_units_per_board(void)
45325cf1a30Sjl {
45425cf1a30Sjl return (OPL_MAX_IO_UNITS_PER_BOARD);
45525cf1a30Sjl }
45625cf1a30Sjl
45725cf1a30Sjl int
plat_max_cmp_units_per_board(void)45825cf1a30Sjl plat_max_cmp_units_per_board(void)
45925cf1a30Sjl {
46025cf1a30Sjl return (OPL_MAX_CMP_UNITS_PER_BOARD);
46125cf1a30Sjl }
46225cf1a30Sjl
46325cf1a30Sjl int
plat_max_core_units_per_board(void)46425cf1a30Sjl plat_max_core_units_per_board(void)
46525cf1a30Sjl {
46625cf1a30Sjl return (OPL_MAX_CORE_UNITS_PER_BOARD);
46725cf1a30Sjl }
46825cf1a30Sjl
46925cf1a30Sjl int
plat_pfn_to_mem_node(pfn_t pfn)47025cf1a30Sjl plat_pfn_to_mem_node(pfn_t pfn)
47125cf1a30Sjl {
47225cf1a30Sjl return (pfn >> mem_node_pfn_shift);
47325cf1a30Sjl }
47425cf1a30Sjl
47525cf1a30Sjl /* ARGSUSED */
47625cf1a30Sjl void
plat_build_mem_nodes(prom_memlist_t * list,size_t nelems)477986fd29aSsetje plat_build_mem_nodes(prom_memlist_t *list, size_t nelems)
47825cf1a30Sjl {
47925cf1a30Sjl size_t elem;
48025cf1a30Sjl pfn_t basepfn;
48125cf1a30Sjl pgcnt_t npgs;
48225cf1a30Sjl uint64_t boundary, ssize;
48325cf1a30Sjl uint64_t low, high;
48425cf1a30Sjl
48525cf1a30Sjl /*
48625cf1a30Sjl * OPL mem slices are always aligned on a 256GB boundary.
48725cf1a30Sjl */
48825cf1a30Sjl mem_node_pfn_shift = OPL_MC_MEMBOARD_SHIFT - MMU_PAGESHIFT;
48925cf1a30Sjl mem_node_physalign = 0;
49025cf1a30Sjl
49125cf1a30Sjl /*
49225cf1a30Sjl * Boot install lists are arranged <addr, len>, <addr, len>, ...
49325cf1a30Sjl */
49425cf1a30Sjl ssize = (1ull << OPL_MC_MEMBOARD_SHIFT);
495986fd29aSsetje for (elem = 0; elem < nelems; list++, elem++) {
496986fd29aSsetje low = list->addr;
497986fd29aSsetje high = low + list->size;
49825cf1a30Sjl while (low < high) {
49925cf1a30Sjl boundary = roundup(low+1, ssize);
50025cf1a30Sjl boundary = MIN(high, boundary);
50125cf1a30Sjl basepfn = btop(low);
50225cf1a30Sjl npgs = btop(boundary - low);
50325cf1a30Sjl mem_node_add_slice(basepfn, basepfn + npgs - 1);
50425cf1a30Sjl low = boundary;
50525cf1a30Sjl }
50625cf1a30Sjl }
50725cf1a30Sjl }
50825cf1a30Sjl
50925cf1a30Sjl /*
51025cf1a30Sjl * Find the CPU associated with a slice at boot-time.
51125cf1a30Sjl */
51225cf1a30Sjl void
plat_fill_mc(pnode_t nodeid)51325cf1a30Sjl plat_fill_mc(pnode_t nodeid)
51425cf1a30Sjl {
51525cf1a30Sjl int board;
51625cf1a30Sjl int memnode;
51725cf1a30Sjl struct {
51825cf1a30Sjl uint64_t addr;
51925cf1a30Sjl uint64_t size;
52025cf1a30Sjl } mem_range;
52125cf1a30Sjl
52225cf1a30Sjl if (prom_getprop(nodeid, "board#", (caddr_t)&board) < 0) {
52325cf1a30Sjl panic("Can not find board# property in mc node %x", nodeid);
52425cf1a30Sjl }
52525cf1a30Sjl if (prom_getprop(nodeid, "sb-mem-ranges", (caddr_t)&mem_range) < 0) {
52625cf1a30Sjl panic("Can not find sb-mem-ranges property in mc node %x",
527e98fafb9Sjl nodeid);
52825cf1a30Sjl }
52925cf1a30Sjl memnode = mem_range.addr >> OPL_MC_MEMBOARD_SHIFT;
53025cf1a30Sjl plat_assign_lgrphand_to_mem_node(board, memnode);
53125cf1a30Sjl }
53225cf1a30Sjl
53325cf1a30Sjl /*
53425cf1a30Sjl * Return the platform handle for the lgroup containing the given CPU
53525cf1a30Sjl *
53625cf1a30Sjl * For OPL, lgroup platform handle == board #.
53725cf1a30Sjl */
53825cf1a30Sjl
53925cf1a30Sjl extern int mpo_disabled;
54025cf1a30Sjl extern lgrp_handle_t lgrp_default_handle;
54125cf1a30Sjl
54225cf1a30Sjl lgrp_handle_t
plat_lgrp_cpu_to_hand(processorid_t id)54325cf1a30Sjl plat_lgrp_cpu_to_hand(processorid_t id)
54425cf1a30Sjl {
54525cf1a30Sjl lgrp_handle_t plathand;
54625cf1a30Sjl
54725cf1a30Sjl /*
54825cf1a30Sjl * Return the real platform handle for the CPU until
54925cf1a30Sjl * such time as we know that MPO should be disabled.
55025cf1a30Sjl * At that point, we set the "mpo_disabled" flag to true,
55125cf1a30Sjl * and from that point on, return the default handle.
55225cf1a30Sjl *
55325cf1a30Sjl * By the time we know that MPO should be disabled, the
55425cf1a30Sjl * first CPU will have already been added to a leaf
55525cf1a30Sjl * lgroup, but that's ok. The common lgroup code will
55625cf1a30Sjl * double check that the boot CPU is in the correct place,
55725cf1a30Sjl * and in the case where mpo should be disabled, will move
55825cf1a30Sjl * it to the root if necessary.
55925cf1a30Sjl */
56025cf1a30Sjl if (mpo_disabled) {
56125cf1a30Sjl /* If MPO is disabled, return the default (UMA) handle */
56225cf1a30Sjl plathand = lgrp_default_handle;
56325cf1a30Sjl } else
56425cf1a30Sjl plathand = (lgrp_handle_t)LSB_ID(id);
56525cf1a30Sjl return (plathand);
56625cf1a30Sjl }
56725cf1a30Sjl
56825cf1a30Sjl /*
56925cf1a30Sjl * Platform specific lgroup initialization
57025cf1a30Sjl */
57125cf1a30Sjl void
plat_lgrp_init(void)57225cf1a30Sjl plat_lgrp_init(void)
57325cf1a30Sjl {
57425cf1a30Sjl extern uint32_t lgrp_expand_proc_thresh;
57525cf1a30Sjl extern uint32_t lgrp_expand_proc_diff;
576cc85acdaSpm const uint_t m = LGRP_LOADAVG_THREAD_MAX;
57725cf1a30Sjl
57825cf1a30Sjl /*
57925cf1a30Sjl * Set tuneables for the OPL architecture
58025cf1a30Sjl *
581cc85acdaSpm * lgrp_expand_proc_thresh is the threshold load on the set of
582cc85acdaSpm * lgroups a process is currently using on before considering
583cc85acdaSpm * adding another lgroup to the set. For Oly-C and Jupiter
584cc85acdaSpm * systems, there are four sockets per lgroup. Setting
585cc85acdaSpm * lgrp_expand_proc_thresh to add lgroups when the load reaches
586cc85acdaSpm * four threads will spread the load when it exceeds one thread
587cc85acdaSpm * per socket, optimizing memory bandwidth and L2 cache space.
58825cf1a30Sjl *
589cc85acdaSpm * lgrp_expand_proc_diff determines how much less another lgroup
590cc85acdaSpm * must be loaded before shifting the start location of a thread
591cc85acdaSpm * to it.
59225cf1a30Sjl *
593cc85acdaSpm * lgrp_loadavg_tolerance is the threshold where two lgroups are
594cc85acdaSpm * considered to have different loads. It is set to be less than
595cc85acdaSpm * 1% so that even a small residual load will be considered different
596cc85acdaSpm * from no residual load.
597cc85acdaSpm *
598cc85acdaSpm * We note loadavg values are not precise.
599cc85acdaSpm * Every 1/10 of a second loadavg values are reduced by 5%.
600cc85acdaSpm * This adjustment can come in the middle of the lgroup selection
601cc85acdaSpm * process, and for larger parallel apps with many threads can
602cc85acdaSpm * frequently occur between the start of the second thread
603cc85acdaSpm * placement and the finish of the last thread placement.
604cc85acdaSpm * We also must be careful to not use too small of a threshold
605cc85acdaSpm * since the cumulative decay for 1 second idle time is 40%.
606cc85acdaSpm * That is, the residual load from completed threads will still
607cc85acdaSpm * be 60% one second after the proc goes idle or 8% after 5 seconds.
608cc85acdaSpm *
609cc85acdaSpm * To allow for lag time in loadavg calculations
610cc85acdaSpm * remote thresh = 3.75 * LGRP_LOADAVG_THREAD_MAX
611cc85acdaSpm * local thresh = 0.75 * LGRP_LOADAVG_THREAD_MAX
612cc85acdaSpm * tolerance = 0.0078 * LGRP_LOADAVG_THREAD_MAX
613cc85acdaSpm *
614cc85acdaSpm * The load placement algorithms consider LGRP_LOADAVG_THREAD_MAX
615cc85acdaSpm * as the equivalent of a load of 1. To make the code more compact,
616cc85acdaSpm * we set m = LGRP_LOADAVG_THREAD_MAX.
61725cf1a30Sjl */
618cc85acdaSpm lgrp_expand_proc_thresh = (m * 3) + (m >> 1) + (m >> 2);
619cc85acdaSpm lgrp_expand_proc_diff = (m >> 1) + (m >> 2);
620cc85acdaSpm lgrp_loadavg_tolerance = (m >> 7);
62125cf1a30Sjl }
62225cf1a30Sjl
62325cf1a30Sjl /*
62425cf1a30Sjl * Platform notification of lgroup (re)configuration changes
62525cf1a30Sjl */
62625cf1a30Sjl /*ARGSUSED*/
62725cf1a30Sjl void
plat_lgrp_config(lgrp_config_flag_t evt,uintptr_t arg)62825cf1a30Sjl plat_lgrp_config(lgrp_config_flag_t evt, uintptr_t arg)
62925cf1a30Sjl {
63025cf1a30Sjl update_membounds_t *umb;
63125cf1a30Sjl lgrp_config_mem_rename_t lmr;
63225cf1a30Sjl int sbd, tbd;
63325cf1a30Sjl lgrp_handle_t hand, shand, thand;
63425cf1a30Sjl int mnode, snode, tnode;
63525cf1a30Sjl pfn_t start, end;
63625cf1a30Sjl
63725cf1a30Sjl if (mpo_disabled)
63825cf1a30Sjl return;
63925cf1a30Sjl
64025cf1a30Sjl switch (evt) {
64125cf1a30Sjl
64225cf1a30Sjl case LGRP_CONFIG_MEM_ADD:
64325cf1a30Sjl /*
64425cf1a30Sjl * Establish the lgroup handle to memnode translation.
64525cf1a30Sjl */
64625cf1a30Sjl umb = (update_membounds_t *)arg;
64725cf1a30Sjl
64825cf1a30Sjl hand = umb->u_board;
64925cf1a30Sjl mnode = plat_pfn_to_mem_node(umb->u_base >> MMU_PAGESHIFT);
65025cf1a30Sjl plat_assign_lgrphand_to_mem_node(hand, mnode);
65125cf1a30Sjl
65225cf1a30Sjl break;
65325cf1a30Sjl
65425cf1a30Sjl case LGRP_CONFIG_MEM_DEL:
65525cf1a30Sjl /*
65625cf1a30Sjl * Special handling for possible memory holes.
65725cf1a30Sjl */
65825cf1a30Sjl umb = (update_membounds_t *)arg;
65925cf1a30Sjl hand = umb->u_board;
66025cf1a30Sjl if ((mnode = plat_lgrphand_to_mem_node(hand)) != -1) {
66125cf1a30Sjl if (mem_node_config[mnode].exists) {
66225cf1a30Sjl start = mem_node_config[mnode].physbase;
66325cf1a30Sjl end = mem_node_config[mnode].physmax;
6649853d9e8SJason Beloro mem_node_del_slice(start, end);
66525cf1a30Sjl }
66625cf1a30Sjl }
66725cf1a30Sjl
66825cf1a30Sjl break;
66925cf1a30Sjl
67025cf1a30Sjl case LGRP_CONFIG_MEM_RENAME:
67125cf1a30Sjl /*
67225cf1a30Sjl * During a DR copy-rename operation, all of the memory
67325cf1a30Sjl * on one board is moved to another board -- but the
67425cf1a30Sjl * addresses/pfns and memnodes don't change. This means
67525cf1a30Sjl * the memory has changed locations without changing identity.
67625cf1a30Sjl *
67725cf1a30Sjl * Source is where we are copying from and target is where we
67825cf1a30Sjl * are copying to. After source memnode is copied to target
67925cf1a30Sjl * memnode, the physical addresses of the target memnode are
68025cf1a30Sjl * renamed to match what the source memnode had. Then target
68125cf1a30Sjl * memnode can be removed and source memnode can take its
68225cf1a30Sjl * place.
68325cf1a30Sjl *
68425cf1a30Sjl * To do this, swap the lgroup handle to memnode mappings for
68525cf1a30Sjl * the boards, so target lgroup will have source memnode and
68625cf1a30Sjl * source lgroup will have empty target memnode which is where
68725cf1a30Sjl * its memory will go (if any is added to it later).
68825cf1a30Sjl *
68925cf1a30Sjl * Then source memnode needs to be removed from its lgroup
69025cf1a30Sjl * and added to the target lgroup where the memory was living
69125cf1a30Sjl * but under a different name/memnode. The memory was in the
69225cf1a30Sjl * target memnode and now lives in the source memnode with
69325cf1a30Sjl * different physical addresses even though it is the same
69425cf1a30Sjl * memory.
69525cf1a30Sjl */
69625cf1a30Sjl sbd = arg & 0xffff;
69725cf1a30Sjl tbd = (arg & 0xffff0000) >> 16;
69825cf1a30Sjl shand = sbd;
69925cf1a30Sjl thand = tbd;
70025cf1a30Sjl snode = plat_lgrphand_to_mem_node(shand);
70125cf1a30Sjl tnode = plat_lgrphand_to_mem_node(thand);
70225cf1a30Sjl
70325cf1a30Sjl /*
70425cf1a30Sjl * Special handling for possible memory holes.
70525cf1a30Sjl */
70625cf1a30Sjl if (tnode != -1 && mem_node_config[tnode].exists) {
70768ac2337Sjl start = mem_node_config[tnode].physbase;
70868ac2337Sjl end = mem_node_config[tnode].physmax;
7099853d9e8SJason Beloro mem_node_del_slice(start, end);
71025cf1a30Sjl }
71125cf1a30Sjl
71225cf1a30Sjl plat_assign_lgrphand_to_mem_node(thand, snode);
71325cf1a30Sjl plat_assign_lgrphand_to_mem_node(shand, tnode);
71425cf1a30Sjl
71525cf1a30Sjl lmr.lmem_rename_from = shand;
71625cf1a30Sjl lmr.lmem_rename_to = thand;
71725cf1a30Sjl
71825cf1a30Sjl /*
71925cf1a30Sjl * Remove source memnode of copy rename from its lgroup
72025cf1a30Sjl * and add it to its new target lgroup
72125cf1a30Sjl */
72225cf1a30Sjl lgrp_config(LGRP_CONFIG_MEM_RENAME, (uintptr_t)snode,
72325cf1a30Sjl (uintptr_t)&lmr);
72425cf1a30Sjl
72525cf1a30Sjl break;
72625cf1a30Sjl
72725cf1a30Sjl default:
72825cf1a30Sjl break;
72925cf1a30Sjl }
73025cf1a30Sjl }
73125cf1a30Sjl
73225cf1a30Sjl /*
73325cf1a30Sjl * Return latency between "from" and "to" lgroups
73425cf1a30Sjl *
73525cf1a30Sjl * This latency number can only be used for relative comparison
73625cf1a30Sjl * between lgroups on the running system, cannot be used across platforms,
73725cf1a30Sjl * and may not reflect the actual latency. It is platform and implementation
73825cf1a30Sjl * specific, so platform gets to decide its value. It would be nice if the
73925cf1a30Sjl * number was at least proportional to make comparisons more meaningful though.
74025cf1a30Sjl * NOTE: The numbers below are supposed to be load latencies for uncached
74125cf1a30Sjl * memory divided by 10.
74225cf1a30Sjl *
74325cf1a30Sjl */
74425cf1a30Sjl int
plat_lgrp_latency(lgrp_handle_t from,lgrp_handle_t to)74525cf1a30Sjl plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to)
74625cf1a30Sjl {
74725cf1a30Sjl /*
74825cf1a30Sjl * Return min remote latency when there are more than two lgroups
74925cf1a30Sjl * (root and child) and getting latency between two different lgroups
75025cf1a30Sjl * or root is involved
75125cf1a30Sjl */
75225cf1a30Sjl if (lgrp_optimizations() && (from != to ||
75325cf1a30Sjl from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE))
75471b3c2ffShyw return (42);
75525cf1a30Sjl else
75671b3c2ffShyw return (35);
75725cf1a30Sjl }
75825cf1a30Sjl
75925cf1a30Sjl /*
76025cf1a30Sjl * Return platform handle for root lgroup
76125cf1a30Sjl */
76225cf1a30Sjl lgrp_handle_t
plat_lgrp_root_hand(void)76325cf1a30Sjl plat_lgrp_root_hand(void)
76425cf1a30Sjl {
76525cf1a30Sjl if (mpo_disabled)
76625cf1a30Sjl return (lgrp_default_handle);
76725cf1a30Sjl
76825cf1a30Sjl return (LGRP_DEFAULT_HANDLE);
76925cf1a30Sjl }
77025cf1a30Sjl
77125cf1a30Sjl /*ARGSUSED*/
77225cf1a30Sjl void
plat_freelist_process(int mnode)77325cf1a30Sjl plat_freelist_process(int mnode)
77425cf1a30Sjl {
77525cf1a30Sjl }
77625cf1a30Sjl
77725cf1a30Sjl void
load_platform_drivers(void)77825cf1a30Sjl load_platform_drivers(void)
77925cf1a30Sjl {
78025cf1a30Sjl (void) i_ddi_attach_pseudo_node("dr");
78125cf1a30Sjl }
78225cf1a30Sjl
78325cf1a30Sjl /*
78425cf1a30Sjl * No platform drivers on this platform
78525cf1a30Sjl */
78625cf1a30Sjl char *platform_module_list[] = {
78725cf1a30Sjl (char *)0
78825cf1a30Sjl };
78925cf1a30Sjl
79025cf1a30Sjl /*ARGSUSED*/
79125cf1a30Sjl void
plat_tod_fault(enum tod_fault_type tod_bad)79225cf1a30Sjl plat_tod_fault(enum tod_fault_type tod_bad)
79325cf1a30Sjl {
79425cf1a30Sjl }
79525cf1a30Sjl
79625cf1a30Sjl /*ARGSUSED*/
79725cf1a30Sjl void
cpu_sgn_update(ushort_t sgn,uchar_t state,uchar_t sub_state,int cpuid)79825cf1a30Sjl cpu_sgn_update(ushort_t sgn, uchar_t state, uchar_t sub_state, int cpuid)
79925cf1a30Sjl {
80025cf1a30Sjl static void (*scf_panic_callback)(int);
80125cf1a30Sjl static void (*scf_shutdown_callback)(int);
80225cf1a30Sjl
80325cf1a30Sjl /*
80425cf1a30Sjl * This is for notifing system panic/shutdown to SCF.
80525cf1a30Sjl * In case of shutdown and panic, SCF call back
80625cf1a30Sjl * function should be called.
80725cf1a30Sjl * <SCF call back functions>
80825cf1a30Sjl * scf_panic_callb() : panicsys()->panic_quiesce_hw()
80925cf1a30Sjl * scf_shutdown_callb(): halt() or power_down() or reboot_machine()
81025cf1a30Sjl * cpuid should be -1 and state should be SIGST_EXIT.
81125cf1a30Sjl */
81225cf1a30Sjl if (state == SIGST_EXIT && cpuid == -1) {
81325cf1a30Sjl
81425cf1a30Sjl /*
81525cf1a30Sjl * find the symbol for the SCF panic callback routine in driver
81625cf1a30Sjl */
81725cf1a30Sjl if (scf_panic_callback == NULL)
81825cf1a30Sjl scf_panic_callback = (void (*)(int))
819e98fafb9Sjl modgetsymvalue("scf_panic_callb", 0);
82025cf1a30Sjl if (scf_shutdown_callback == NULL)
82125cf1a30Sjl scf_shutdown_callback = (void (*)(int))
822e98fafb9Sjl modgetsymvalue("scf_shutdown_callb", 0);
82325cf1a30Sjl
82425cf1a30Sjl switch (sub_state) {
82525cf1a30Sjl case SIGSUBST_PANIC:
82625cf1a30Sjl if (scf_panic_callback == NULL) {
82725cf1a30Sjl cmn_err(CE_NOTE, "!cpu_sgn_update: "
82825cf1a30Sjl "scf_panic_callb not found\n");
82925cf1a30Sjl return;
83025cf1a30Sjl }
83125cf1a30Sjl scf_panic_callback(SIGSUBST_PANIC);
83225cf1a30Sjl break;
83325cf1a30Sjl
83425cf1a30Sjl case SIGSUBST_HALT:
83525cf1a30Sjl if (scf_shutdown_callback == NULL) {
83625cf1a30Sjl cmn_err(CE_NOTE, "!cpu_sgn_update: "
83725cf1a30Sjl "scf_shutdown_callb not found\n");
83825cf1a30Sjl return;
83925cf1a30Sjl }
84025cf1a30Sjl scf_shutdown_callback(SIGSUBST_HALT);
84125cf1a30Sjl break;
84225cf1a30Sjl
84325cf1a30Sjl case SIGSUBST_ENVIRON:
84425cf1a30Sjl if (scf_shutdown_callback == NULL) {
84525cf1a30Sjl cmn_err(CE_NOTE, "!cpu_sgn_update: "
84625cf1a30Sjl "scf_shutdown_callb not found\n");
84725cf1a30Sjl return;
84825cf1a30Sjl }
84925cf1a30Sjl scf_shutdown_callback(SIGSUBST_ENVIRON);
85025cf1a30Sjl break;
85125cf1a30Sjl
85225cf1a30Sjl case SIGSUBST_REBOOT:
85325cf1a30Sjl if (scf_shutdown_callback == NULL) {
85425cf1a30Sjl cmn_err(CE_NOTE, "!cpu_sgn_update: "
85525cf1a30Sjl "scf_shutdown_callb not found\n");
85625cf1a30Sjl return;
85725cf1a30Sjl }
85825cf1a30Sjl scf_shutdown_callback(SIGSUBST_REBOOT);
85925cf1a30Sjl break;
86025cf1a30Sjl }
86125cf1a30Sjl }
86225cf1a30Sjl }
86325cf1a30Sjl
86425cf1a30Sjl /*ARGSUSED*/
86525cf1a30Sjl int
plat_get_mem_unum(int synd_code,uint64_t flt_addr,int flt_bus_id,int flt_in_memory,ushort_t flt_status,char * buf,int buflen,int * lenp)86625cf1a30Sjl plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id,
867*d5ebc493SDan Cross int flt_in_memory, ushort_t flt_status,
868*d5ebc493SDan Cross char *buf, int buflen, int *lenp)
86925cf1a30Sjl {
87025cf1a30Sjl /*
87125cf1a30Sjl * check if it's a Memory error.
87225cf1a30Sjl */
87325cf1a30Sjl if (flt_in_memory) {
87425cf1a30Sjl if (opl_get_mem_unum != NULL) {
875e98fafb9Sjl return (opl_get_mem_unum(synd_code, flt_addr, buf,
876e98fafb9Sjl buflen, lenp));
87725cf1a30Sjl } else {
87825cf1a30Sjl return (ENOTSUP);
87925cf1a30Sjl }
88025cf1a30Sjl } else {
88125cf1a30Sjl return (ENOTSUP);
88225cf1a30Sjl }
88325cf1a30Sjl }
88425cf1a30Sjl
88525cf1a30Sjl /*ARGSUSED*/
88625cf1a30Sjl int
plat_get_cpu_unum(int cpuid,char * buf,int buflen,int * lenp)88725cf1a30Sjl plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp)
88825cf1a30Sjl {
8890cc8ae86Sav int ret = 0;
8903f1fa9a7Sjfrank int sb;
891195196c6Ssubhan int plen;
89225cf1a30Sjl
89325cf1a30Sjl sb = opl_get_physical_board(LSB_ID(cpuid));
89425cf1a30Sjl if (sb == -1) {
89525cf1a30Sjl return (ENXIO);
89625cf1a30Sjl }
89725cf1a30Sjl
89872b9fce9Ssubhan /*
89972b9fce9Ssubhan * opl_cur_model is assigned here
90072b9fce9Ssubhan */
90172b9fce9Ssubhan if (opl_cur_model == NULL) {
90272b9fce9Ssubhan set_model_info();
9039b71d8e9Swh
9049b71d8e9Swh /*
9059b71d8e9Swh * if not matched, return
9069b71d8e9Swh */
9079b71d8e9Swh if (opl_cur_model == NULL)
9089b71d8e9Swh return (ENODEV);
90972b9fce9Ssubhan }
91072b9fce9Ssubhan
911195196c6Ssubhan ASSERT((opl_cur_model - opl_models) == (opl_cur_model->model_type));
912195196c6Ssubhan
913195196c6Ssubhan switch (opl_cur_model->model_type) {
914195196c6Ssubhan case FF1:
9150cc8ae86Sav plen = snprintf(buf, buflen, "/%s/CPUM%d", "MBU_A",
9160cc8ae86Sav CHIP_ID(cpuid) / 2);
9170cc8ae86Sav break;
9180cc8ae86Sav
919195196c6Ssubhan case FF2:
9200cc8ae86Sav plen = snprintf(buf, buflen, "/%s/CPUM%d", "MBU_B",
92111114147Sav (CHIP_ID(cpuid) / 2) + (sb * 2));
9220cc8ae86Sav break;
9230cc8ae86Sav
924195196c6Ssubhan case DC1:
925195196c6Ssubhan case DC2:
926195196c6Ssubhan case DC3:
9270cc8ae86Sav plen = snprintf(buf, buflen, "/%s%02d/CPUM%d", "CMU", sb,
9280cc8ae86Sav CHIP_ID(cpuid));
9290cc8ae86Sav break;
9300cc8ae86Sav
93178ed97a7Sjl case IKKAKU:
93278ed97a7Sjl plen = snprintf(buf, buflen, "/%s", "MBU_A");
93378ed97a7Sjl break;
93478ed97a7Sjl
9350cc8ae86Sav default:
9360cc8ae86Sav /* This should never happen */
9370cc8ae86Sav return (ENODEV);
9380cc8ae86Sav }
9390cc8ae86Sav
9400cc8ae86Sav if (plen >= buflen) {
9410cc8ae86Sav ret = ENOSPC;
94225cf1a30Sjl } else {
94325cf1a30Sjl if (lenp)
94425cf1a30Sjl *lenp = strlen(buf);
94525cf1a30Sjl }
9460cc8ae86Sav return (ret);
94725cf1a30Sjl }
94825cf1a30Sjl
94925cf1a30Sjl void
plat_nodename_set(void)95025cf1a30Sjl plat_nodename_set(void)
95125cf1a30Sjl {
9523f1fa9a7Sjfrank post_xscf_msg((char *)&utsname, sizeof (struct utsname));
95325cf1a30Sjl }
95425cf1a30Sjl
95525cf1a30Sjl caddr_t efcode_vaddr = NULL;
95625cf1a30Sjl
95725cf1a30Sjl /*
95825cf1a30Sjl * Preallocate enough memory for fcode claims.
95925cf1a30Sjl */
96025cf1a30Sjl
96125cf1a30Sjl caddr_t
efcode_alloc(caddr_t alloc_base)96225cf1a30Sjl efcode_alloc(caddr_t alloc_base)
96325cf1a30Sjl {
96425cf1a30Sjl caddr_t efcode_alloc_base = (caddr_t)roundup((uintptr_t)alloc_base,
96525cf1a30Sjl MMU_PAGESIZE);
96625cf1a30Sjl caddr_t vaddr;
96725cf1a30Sjl
96825cf1a30Sjl /*
96925cf1a30Sjl * allocate the physical memory for the Oberon fcode.
97025cf1a30Sjl */
97125cf1a30Sjl if ((vaddr = (caddr_t)BOP_ALLOC(bootops, efcode_alloc_base,
97225cf1a30Sjl efcode_size, MMU_PAGESIZE)) == NULL)
97325cf1a30Sjl cmn_err(CE_PANIC, "Cannot allocate Efcode Memory");
97425cf1a30Sjl
97525cf1a30Sjl efcode_vaddr = vaddr;
97625cf1a30Sjl
97725cf1a30Sjl return (efcode_alloc_base + efcode_size);
97825cf1a30Sjl }
97925cf1a30Sjl
98025cf1a30Sjl caddr_t
plat_startup_memlist(caddr_t alloc_base)98125cf1a30Sjl plat_startup_memlist(caddr_t alloc_base)
98225cf1a30Sjl {
98325cf1a30Sjl caddr_t tmp_alloc_base;
98425cf1a30Sjl
98525cf1a30Sjl tmp_alloc_base = efcode_alloc(alloc_base);
98625cf1a30Sjl tmp_alloc_base =
98725cf1a30Sjl (caddr_t)roundup((uintptr_t)tmp_alloc_base, ecache_alignsize);
98825cf1a30Sjl return (tmp_alloc_base);
98925cf1a30Sjl }
99025cf1a30Sjl
991575a7426Spt /* need to forward declare these */
992575a7426Spt static void plat_lock_delay(uint_t);
993575a7426Spt
99425cf1a30Sjl void
startup_platform(void)99525cf1a30Sjl startup_platform(void)
99625cf1a30Sjl {
9972850d85bSmv if (clock_tick_threshold == 0)
9982850d85bSmv clock_tick_threshold = OPL_CLOCK_TICK_THRESHOLD;
9992850d85bSmv if (clock_tick_ncpus == 0)
10002850d85bSmv clock_tick_ncpus = OPL_CLOCK_TICK_NCPUS;
1001575a7426Spt mutex_lock_delay = plat_lock_delay;
1002575a7426Spt mutex_cap_factor = OPL_BOFF_MAX_SCALE;
100325cf1a30Sjl }
10040cc8ae86Sav
100504938e8bSjfrank static uint_t
get_mmu_id(processorid_t cpuid)100604938e8bSjfrank get_mmu_id(processorid_t cpuid)
100704938e8bSjfrank {
100804938e8bSjfrank int pb = opl_get_physical_board(LSB_ID(cpuid));
100904938e8bSjfrank
101004938e8bSjfrank if (pb == -1) {
101104938e8bSjfrank cmn_err(CE_PANIC,
101204938e8bSjfrank "opl_get_physical_board failed (cpu %d LSB %u)",
101304938e8bSjfrank cpuid, LSB_ID(cpuid));
101404938e8bSjfrank }
101504938e8bSjfrank return (pb * OPL_MAX_COREID_PER_BOARD) + (CHIP_ID(cpuid) *
101604938e8bSjfrank OPL_MAX_COREID_PER_CMP) + CORE_ID(cpuid);
101704938e8bSjfrank }
101804938e8bSjfrank
10191e2e7a75Shuah void
plat_cpuid_to_mmu_ctx_info(processorid_t cpuid,mmu_ctx_info_t * info)10201e2e7a75Shuah plat_cpuid_to_mmu_ctx_info(processorid_t cpuid, mmu_ctx_info_t *info)
10211e2e7a75Shuah {
10221e2e7a75Shuah int impl;
10231e2e7a75Shuah
10241e2e7a75Shuah impl = cpunodes[cpuid].implementation;
1025e98fafb9Sjl if (IS_OLYMPUS_C(impl) || IS_JUPITER(impl)) {
102604938e8bSjfrank info->mmu_idx = get_mmu_id(cpuid);
10271e2e7a75Shuah info->mmu_nctxs = 8192;
10281e2e7a75Shuah } else {
10291e2e7a75Shuah cmn_err(CE_PANIC, "Unknown processor %d", impl);
10301e2e7a75Shuah }
10311e2e7a75Shuah }
10321e2e7a75Shuah
10330cc8ae86Sav int
plat_get_mem_sid(char * unum,char * buf,int buflen,int * lenp)10340cc8ae86Sav plat_get_mem_sid(char *unum, char *buf, int buflen, int *lenp)
10350cc8ae86Sav {
10360cc8ae86Sav if (opl_get_mem_sid == NULL) {
10370cc8ae86Sav return (ENOTSUP);
10380cc8ae86Sav }
10390cc8ae86Sav return (opl_get_mem_sid(unum, buf, buflen, lenp));
10400cc8ae86Sav }
10410cc8ae86Sav
10420cc8ae86Sav int
plat_get_mem_offset(uint64_t paddr,uint64_t * offp)10430cc8ae86Sav plat_get_mem_offset(uint64_t paddr, uint64_t *offp)
10440cc8ae86Sav {
10450cc8ae86Sav if (opl_get_mem_offset == NULL) {
10460cc8ae86Sav return (ENOTSUP);
10470cc8ae86Sav }
10480cc8ae86Sav return (opl_get_mem_offset(paddr, offp));
10490cc8ae86Sav }
10500cc8ae86Sav
10510cc8ae86Sav int
plat_get_mem_addr(char * unum,char * sid,uint64_t offset,uint64_t * addrp)10520cc8ae86Sav plat_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp)
10530cc8ae86Sav {
10540cc8ae86Sav if (opl_get_mem_addr == NULL) {
10550cc8ae86Sav return (ENOTSUP);
10560cc8ae86Sav }
10570cc8ae86Sav return (opl_get_mem_addr(unum, sid, offset, addrp));
10580cc8ae86Sav }
1059e603b7d4Spm
1060e603b7d4Spm void
plat_lock_delay(uint_t backoff)1061575a7426Spt plat_lock_delay(uint_t backoff)
1062e603b7d4Spm {
1063e603b7d4Spm int i;
1064575a7426Spt uint_t cnt, remcnt;
1065e603b7d4Spm int ctr;
1066575a7426Spt hrtime_t delay_start, rem_delay;
1067e603b7d4Spm /*
1068e603b7d4Spm * Platform specific lock delay code for OPL
1069e603b7d4Spm *
1070e603b7d4Spm * Using staged linear increases in the delay.
1071e603b7d4Spm * The sleep instruction is the preferred method of delay,
1072e603b7d4Spm * but is too large of granularity for the initial backoff.
1073e603b7d4Spm */
1074e603b7d4Spm
1075575a7426Spt if (backoff < 100) {
1076e603b7d4Spm /*
1077e603b7d4Spm * If desired backoff is long enough,
1078e603b7d4Spm * use sleep for most of it
1079e603b7d4Spm */
1080575a7426Spt for (cnt = backoff;
1081575a7426Spt cnt >= OPL_BOFF_SLEEP;
1082e98fafb9Sjl cnt -= OPL_BOFF_SLEEP) {
1083e603b7d4Spm cpu_smt_pause();
1084e603b7d4Spm }
1085e603b7d4Spm /*
1086e603b7d4Spm * spin for small remainder of backoff
1087e603b7d4Spm */
1088e603b7d4Spm for (ctr = cnt * OPL_BOFF_SPIN; ctr; ctr--) {
1089575a7426Spt mutex_delay_default();
1090e603b7d4Spm }
1091e603b7d4Spm } else {
1092575a7426Spt /* backoff is large. Fill it by sleeping */
1093fb81f553Sck delay_start = gethrtime_waitfree();
1094575a7426Spt cnt = backoff / OPL_BOFF_SLEEP;
1095e603b7d4Spm /*
1096e603b7d4Spm * use sleep instructions for delay
1097e603b7d4Spm */
1098e603b7d4Spm for (i = 0; i < cnt; i++) {
1099e603b7d4Spm cpu_smt_pause();
1100e603b7d4Spm }
1101e603b7d4Spm
1102e603b7d4Spm /*
1103e603b7d4Spm * Note: if the other strand executes a sleep instruction,
1104e603b7d4Spm * then the sleep ends immediately with a minimum time of
1105e603b7d4Spm * 42 clocks. We check gethrtime to insure we have
1106e603b7d4Spm * waited long enough. And we include both a short
1107575a7426Spt * spin loop and a sleep for repeated delay times.
1108e603b7d4Spm */
1109e603b7d4Spm
1110fb81f553Sck rem_delay = gethrtime_waitfree() - delay_start;
1111575a7426Spt while (rem_delay < cnt * OPL_BOFF_TM) {
1112575a7426Spt remcnt = cnt - (rem_delay / OPL_BOFF_TM);
1113575a7426Spt for (i = 0; i < remcnt; i++) {
1114575a7426Spt cpu_smt_pause();
1115575a7426Spt for (ctr = OPL_BOFF_SPIN; ctr; ctr--) {
1116575a7426Spt mutex_delay_default();
1117575a7426Spt }
1118e603b7d4Spm }
1119fb81f553Sck rem_delay = gethrtime_waitfree() - delay_start;
1120e603b7d4Spm }
1121e603b7d4Spm }
1122e603b7d4Spm }
11233f1fa9a7Sjfrank
11243f1fa9a7Sjfrank /*
11253f1fa9a7Sjfrank * The following code implements asynchronous call to XSCF to setup the
11263f1fa9a7Sjfrank * domain node name.
11273f1fa9a7Sjfrank */
11283f1fa9a7Sjfrank
11293f1fa9a7Sjfrank #define FREE_MSG(m) kmem_free((m), NM_LEN((m)->len))
11303f1fa9a7Sjfrank
11313f1fa9a7Sjfrank /*
11323f1fa9a7Sjfrank * The following three macros define the all operations on the request
11333f1fa9a7Sjfrank * list we are using here, and hide the details of the list
11343f1fa9a7Sjfrank * implementation from the code.
11353f1fa9a7Sjfrank */
11363f1fa9a7Sjfrank #define PUSH(m) \
11373f1fa9a7Sjfrank { \
11383f1fa9a7Sjfrank (m)->next = ctl_msg.head; \
11393f1fa9a7Sjfrank (m)->prev = NULL; \
11403f1fa9a7Sjfrank if ((m)->next != NULL) \
11413f1fa9a7Sjfrank (m)->next->prev = (m); \
11423f1fa9a7Sjfrank ctl_msg.head = (m); \
11433f1fa9a7Sjfrank }
11443f1fa9a7Sjfrank
11453f1fa9a7Sjfrank #define REMOVE(m) \
11463f1fa9a7Sjfrank { \
11473f1fa9a7Sjfrank if ((m)->prev != NULL) \
11483f1fa9a7Sjfrank (m)->prev->next = (m)->next; \
11493f1fa9a7Sjfrank else \
11503f1fa9a7Sjfrank ctl_msg.head = (m)->next; \
11513f1fa9a7Sjfrank if ((m)->next != NULL) \
11523f1fa9a7Sjfrank (m)->next->prev = (m)->prev; \
11533f1fa9a7Sjfrank }
11543f1fa9a7Sjfrank
11553f1fa9a7Sjfrank #define FREE_THE_TAIL(head) \
11563f1fa9a7Sjfrank { \
11573f1fa9a7Sjfrank nm_msg_t *n_msg, *m; \
11583f1fa9a7Sjfrank m = (head)->next; \
11593f1fa9a7Sjfrank (head)->next = NULL; \
11603f1fa9a7Sjfrank while (m != NULL) { \
11613f1fa9a7Sjfrank n_msg = m->next; \
11623f1fa9a7Sjfrank FREE_MSG(m); \
11633f1fa9a7Sjfrank m = n_msg; \
11643f1fa9a7Sjfrank } \
11653f1fa9a7Sjfrank }
11663f1fa9a7Sjfrank
11673f1fa9a7Sjfrank #define SCF_PUTINFO(f, s, p) \
11683f1fa9a7Sjfrank f(KEY_ESCF, 0x01, 0, s, p)
11693f1fa9a7Sjfrank
11703f1fa9a7Sjfrank #define PASS2XSCF(m, r) ((r = SCF_PUTINFO(ctl_msg.scf_service_function, \
11713f1fa9a7Sjfrank (m)->len, (m)->data)) == 0)
11723f1fa9a7Sjfrank
11733f1fa9a7Sjfrank /*
11743f1fa9a7Sjfrank * The value of the following macro loosely depends on the
11753f1fa9a7Sjfrank * value of the "device busy" timeout used in the SCF driver.
11763f1fa9a7Sjfrank * (See pass2xscf_thread()).
11773f1fa9a7Sjfrank */
11783f1fa9a7Sjfrank #define SCF_DEVBUSY_DELAY 10
11793f1fa9a7Sjfrank
11803f1fa9a7Sjfrank /*
11813f1fa9a7Sjfrank * The default number of attempts to contact the scf driver
11823f1fa9a7Sjfrank * if we cannot fetch any information about the timeout value
11833f1fa9a7Sjfrank * it uses.
11843f1fa9a7Sjfrank */
11853f1fa9a7Sjfrank
11863f1fa9a7Sjfrank #define REPEATS 4
11873f1fa9a7Sjfrank
11883f1fa9a7Sjfrank typedef struct nm_msg {
11893f1fa9a7Sjfrank struct nm_msg *next;
11903f1fa9a7Sjfrank struct nm_msg *prev;
11913f1fa9a7Sjfrank int len;
11923f1fa9a7Sjfrank char data[1];
11933f1fa9a7Sjfrank } nm_msg_t;
11943f1fa9a7Sjfrank
11953f1fa9a7Sjfrank #define NM_LEN(len) (sizeof (nm_msg_t) + (len) - 1)
11963f1fa9a7Sjfrank
11973f1fa9a7Sjfrank static struct ctlmsg {
11983f1fa9a7Sjfrank nm_msg_t *head;
11993f1fa9a7Sjfrank nm_msg_t *now_serving;
12003f1fa9a7Sjfrank kmutex_t nm_lock;
12013f1fa9a7Sjfrank kthread_t *nmt;
12023f1fa9a7Sjfrank int cnt;
12033f1fa9a7Sjfrank int (*scf_service_function)(uint32_t, uint8_t,
12043f1fa9a7Sjfrank uint32_t, uint32_t, void *);
12053f1fa9a7Sjfrank } ctl_msg;
12063f1fa9a7Sjfrank
12073f1fa9a7Sjfrank static void
post_xscf_msg(char * dp,int len)12083f1fa9a7Sjfrank post_xscf_msg(char *dp, int len)
12093f1fa9a7Sjfrank {
12103f1fa9a7Sjfrank nm_msg_t *msg;
12113f1fa9a7Sjfrank
12123f1fa9a7Sjfrank msg = (nm_msg_t *)kmem_zalloc(NM_LEN(len), KM_SLEEP);
12133f1fa9a7Sjfrank
12143f1fa9a7Sjfrank bcopy(dp, msg->data, len);
12153f1fa9a7Sjfrank msg->len = len;
12163f1fa9a7Sjfrank
12173f1fa9a7Sjfrank mutex_enter(&ctl_msg.nm_lock);
12183f1fa9a7Sjfrank if (ctl_msg.nmt == NULL) {
12193f1fa9a7Sjfrank ctl_msg.nmt = thread_create(NULL, 0, pass2xscf_thread,
12203f1fa9a7Sjfrank NULL, 0, &p0, TS_RUN, minclsyspri);
12213f1fa9a7Sjfrank }
12223f1fa9a7Sjfrank
12233f1fa9a7Sjfrank PUSH(msg);
12243f1fa9a7Sjfrank ctl_msg.cnt++;
12253f1fa9a7Sjfrank mutex_exit(&ctl_msg.nm_lock);
12263f1fa9a7Sjfrank }
12273f1fa9a7Sjfrank
12283f1fa9a7Sjfrank static void
pass2xscf_thread()12293f1fa9a7Sjfrank pass2xscf_thread()
12303f1fa9a7Sjfrank {
12313f1fa9a7Sjfrank nm_msg_t *msg;
12323f1fa9a7Sjfrank int ret;
12333f1fa9a7Sjfrank uint_t i, msg_sent, xscf_driver_delay;
12343f1fa9a7Sjfrank static uint_t repeat_cnt;
12353f1fa9a7Sjfrank uint_t *scf_wait_cnt;
12363f1fa9a7Sjfrank
12373f1fa9a7Sjfrank mutex_enter(&ctl_msg.nm_lock);
12383f1fa9a7Sjfrank
12393f1fa9a7Sjfrank /*
12403f1fa9a7Sjfrank * Find the address of the SCF put routine if it's not done yet.
12413f1fa9a7Sjfrank */
12423f1fa9a7Sjfrank if (ctl_msg.scf_service_function == NULL) {
12433f1fa9a7Sjfrank if ((ctl_msg.scf_service_function =
12443f1fa9a7Sjfrank (int (*)(uint32_t, uint8_t, uint32_t, uint32_t, void *))
12453f1fa9a7Sjfrank modgetsymvalue("scf_service_putinfo", 0)) == NULL) {
12463f1fa9a7Sjfrank cmn_err(CE_NOTE, "pass2xscf_thread: "
12473f1fa9a7Sjfrank "scf_service_putinfo not found\n");
12483f1fa9a7Sjfrank ctl_msg.nmt = NULL;
12493f1fa9a7Sjfrank mutex_exit(&ctl_msg.nm_lock);
12503f1fa9a7Sjfrank return;
12513f1fa9a7Sjfrank }
12523f1fa9a7Sjfrank }
12533f1fa9a7Sjfrank
12543f1fa9a7Sjfrank /*
12553f1fa9a7Sjfrank * Calculate the number of attempts to connect XSCF based on the
12563f1fa9a7Sjfrank * scf driver delay (which is
12573f1fa9a7Sjfrank * SCF_DEVBUSY_DELAY*scf_online_wait_rcnt seconds) and the value
12583f1fa9a7Sjfrank * of xscf_connect_delay (the total number of seconds to wait
12593f1fa9a7Sjfrank * till xscf get ready.)
12603f1fa9a7Sjfrank */
12613f1fa9a7Sjfrank if (repeat_cnt == 0) {
12623f1fa9a7Sjfrank if ((scf_wait_cnt =
12633f1fa9a7Sjfrank (uint_t *)
12643f1fa9a7Sjfrank modgetsymvalue("scf_online_wait_rcnt", 0)) == NULL) {
12653f1fa9a7Sjfrank repeat_cnt = REPEATS;
12663f1fa9a7Sjfrank } else {
12673f1fa9a7Sjfrank
12683f1fa9a7Sjfrank xscf_driver_delay = *scf_wait_cnt *
12693f1fa9a7Sjfrank SCF_DEVBUSY_DELAY;
12703f1fa9a7Sjfrank repeat_cnt = (xscf_connect_delay/xscf_driver_delay) + 1;
12713f1fa9a7Sjfrank }
12723f1fa9a7Sjfrank }
12733f1fa9a7Sjfrank
12743f1fa9a7Sjfrank while (ctl_msg.cnt != 0) {
12753f1fa9a7Sjfrank
12763f1fa9a7Sjfrank /*
12773f1fa9a7Sjfrank * Take the very last request from the queue,
12783f1fa9a7Sjfrank */
12793f1fa9a7Sjfrank ctl_msg.now_serving = ctl_msg.head;
12803f1fa9a7Sjfrank ASSERT(ctl_msg.now_serving != NULL);
12813f1fa9a7Sjfrank
12823f1fa9a7Sjfrank /*
12833f1fa9a7Sjfrank * and discard all the others if any.
12843f1fa9a7Sjfrank */
12853f1fa9a7Sjfrank FREE_THE_TAIL(ctl_msg.now_serving);
12863f1fa9a7Sjfrank ctl_msg.cnt = 1;
12873f1fa9a7Sjfrank mutex_exit(&ctl_msg.nm_lock);
12883f1fa9a7Sjfrank
12893f1fa9a7Sjfrank /*
12903f1fa9a7Sjfrank * Pass the name to XSCF. Note please, we do not hold the
12913f1fa9a7Sjfrank * mutex while we are doing this.
12923f1fa9a7Sjfrank */
12933f1fa9a7Sjfrank msg_sent = 0;
12943f1fa9a7Sjfrank for (i = 0; i < repeat_cnt; i++) {
12953f1fa9a7Sjfrank if (PASS2XSCF(ctl_msg.now_serving, ret)) {
12963f1fa9a7Sjfrank msg_sent = 1;
12973f1fa9a7Sjfrank break;
12983f1fa9a7Sjfrank } else {
12993f1fa9a7Sjfrank if (ret != EBUSY) {
13003f1fa9a7Sjfrank cmn_err(CE_NOTE, "pass2xscf_thread:"
13013f1fa9a7Sjfrank " unexpected return code"
13023f1fa9a7Sjfrank " from scf_service_putinfo():"
13033f1fa9a7Sjfrank " %d\n", ret);
13043f1fa9a7Sjfrank }
13053f1fa9a7Sjfrank }
13063f1fa9a7Sjfrank }
13073f1fa9a7Sjfrank
13083f1fa9a7Sjfrank if (msg_sent) {
13093f1fa9a7Sjfrank
13103f1fa9a7Sjfrank /*
13113f1fa9a7Sjfrank * Remove the request from the list
13123f1fa9a7Sjfrank */
13133f1fa9a7Sjfrank mutex_enter(&ctl_msg.nm_lock);
13143f1fa9a7Sjfrank msg = ctl_msg.now_serving;
13153f1fa9a7Sjfrank ctl_msg.now_serving = NULL;
13163f1fa9a7Sjfrank REMOVE(msg);
13173f1fa9a7Sjfrank ctl_msg.cnt--;
13183f1fa9a7Sjfrank mutex_exit(&ctl_msg.nm_lock);
13193f1fa9a7Sjfrank FREE_MSG(msg);
13203f1fa9a7Sjfrank } else {
13213f1fa9a7Sjfrank
13223f1fa9a7Sjfrank /*
13233f1fa9a7Sjfrank * If while we have tried to communicate with
13243f1fa9a7Sjfrank * XSCF there were any other requests we are
13253f1fa9a7Sjfrank * going to drop this one and take the latest
13263f1fa9a7Sjfrank * one. Otherwise we will try to pass this one
13273f1fa9a7Sjfrank * again.
13283f1fa9a7Sjfrank */
13293f1fa9a7Sjfrank cmn_err(CE_NOTE,
13303f1fa9a7Sjfrank "pass2xscf_thread: "
13313f1fa9a7Sjfrank "scf_service_putinfo "
13323f1fa9a7Sjfrank "not responding\n");
13333f1fa9a7Sjfrank }
13343f1fa9a7Sjfrank mutex_enter(&ctl_msg.nm_lock);
13353f1fa9a7Sjfrank }
13363f1fa9a7Sjfrank
13373f1fa9a7Sjfrank /*
13383f1fa9a7Sjfrank * The request queue is empty, exit.
13393f1fa9a7Sjfrank */
13403f1fa9a7Sjfrank ctl_msg.nmt = NULL;
13413f1fa9a7Sjfrank mutex_exit(&ctl_msg.nm_lock);
13423f1fa9a7Sjfrank }
1343