125cf1a30Sjl /*
225cf1a30Sjl * CDDL HEADER START
325cf1a30Sjl *
425cf1a30Sjl * The contents of this file are subject to the terms of the
525cf1a30Sjl * Common Development and Distribution License (the "License").
625cf1a30Sjl * You may not use this file except in compliance with the License.
725cf1a30Sjl *
825cf1a30Sjl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
925cf1a30Sjl * or http://www.opensolaris.org/os/licensing.
1025cf1a30Sjl * See the License for the specific language governing permissions
1125cf1a30Sjl * and limitations under the License.
1225cf1a30Sjl *
1325cf1a30Sjl * When distributing Covered Code, include this CDDL HEADER in each
1425cf1a30Sjl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1525cf1a30Sjl * If applicable, add the following below this CDDL HEADER, with the
1625cf1a30Sjl * fields enclosed by brackets "[]" replaced with your own identifying
1725cf1a30Sjl * information: Portions Copyright [yyyy] [name of copyright owner]
1825cf1a30Sjl *
1925cf1a30Sjl * CDDL HEADER END
2025cf1a30Sjl */
2125cf1a30Sjl /*
2268ac2337Sjl * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
2325cf1a30Sjl * Use is subject to license terms.
2425cf1a30Sjl */
2525cf1a30Sjl
2625cf1a30Sjl #pragma ident "%Z%%M% %I% %E% SMI"
2725cf1a30Sjl
2825cf1a30Sjl
2925cf1a30Sjl /*
3025cf1a30Sjl * This file is through cpp before being used as
3125cf1a30Sjl * an inline. It contains support routines used
3225cf1a30Sjl * only by DR for the copy-rename sequence.
3325cf1a30Sjl */
3425cf1a30Sjl
3525cf1a30Sjl #if defined(lint)
3625cf1a30Sjl #include <sys/types.h>
3725cf1a30Sjl #endif /* lint */
3825cf1a30Sjl
3925cf1a30Sjl #ifndef INLINE
4025cf1a30Sjl
4125cf1a30Sjl #include <sys/asm_linkage.h>
4225cf1a30Sjl
4325cf1a30Sjl #else /* INLINE */
4425cf1a30Sjl
4525cf1a30Sjl #define ENTRY_NP(x) .inline x,0
4625cf1a30Sjl #define retl /* nop */
4725cf1a30Sjl #define SET_SIZE(x) .end
4825cf1a30Sjl
4925cf1a30Sjl #endif /* INLINE */
5025cf1a30Sjl
5125cf1a30Sjl #include <sys/privregs.h>
5225cf1a30Sjl #include <sys/sun4asi.h>
5325cf1a30Sjl #include <sys/machparam.h>
5425cf1a30Sjl
5525cf1a30Sjl #include <sys/intreg.h>
5625cf1a30Sjl #include <sys/opl_olympus_regs.h>
5725cf1a30Sjl
5825cf1a30Sjl /*
5925cf1a30Sjl * Bcopy routine used by DR to copy
6025cf1a30Sjl * between physical addresses.
6125cf1a30Sjl * Borrowed from Starfire DR 2.6.
6225cf1a30Sjl */
6325cf1a30Sjl #if defined(lint)
6425cf1a30Sjl
6525cf1a30Sjl /*ARGSUSED*/
6625cf1a30Sjl void
bcopy32_il(uint64_t paddr1,uint64_t paddr2)6725cf1a30Sjl bcopy32_il(uint64_t paddr1, uint64_t paddr2)
6825cf1a30Sjl {}
6925cf1a30Sjl
7025cf1a30Sjl #else /* lint */
7125cf1a30Sjl
7225cf1a30Sjl ENTRY_NP(bcopy32_il)
7325cf1a30Sjl .register %g2, #scratch
7425cf1a30Sjl .register %g3, #scratch
7525cf1a30Sjl rdpr %pstate, %g0
7625cf1a30Sjl ldxa [%o0]ASI_MEM, %o2
7725cf1a30Sjl add %o0, 8, %o0
7825cf1a30Sjl ldxa [%o0]ASI_MEM, %o3
7925cf1a30Sjl add %o0, 8, %o0
8025cf1a30Sjl ldxa [%o0]ASI_MEM, %g1
8125cf1a30Sjl add %o0, 8, %o0
8225cf1a30Sjl ldxa [%o0]ASI_MEM, %g2
8325cf1a30Sjl
8425cf1a30Sjl stxa %o2, [%o1]ASI_MEM
8525cf1a30Sjl add %o1, 8, %o1
8625cf1a30Sjl stxa %o3, [%o1]ASI_MEM
8725cf1a30Sjl add %o1, 8, %o1
8825cf1a30Sjl stxa %g1, [%o1]ASI_MEM
8925cf1a30Sjl add %o1, 8, %o1
9025cf1a30Sjl stxa %g2, [%o1]ASI_MEM
9125cf1a30Sjl
9225cf1a30Sjl retl
9325cf1a30Sjl nop
9425cf1a30Sjl SET_SIZE(bcopy32_il)
9525cf1a30Sjl
9625cf1a30Sjl #endif /* lint */
9725cf1a30Sjl
9825cf1a30Sjl #if defined(lint)
9925cf1a30Sjl
10025cf1a30Sjl /*ARGSUSED*/
10125cf1a30Sjl void
10225cf1a30Sjl flush_cache_il(void)
10325cf1a30Sjl {}
10425cf1a30Sjl
10525cf1a30Sjl #else /* lint */
10625cf1a30Sjl
10725cf1a30Sjl ENTRY_NP(flush_cache_il)
10825cf1a30Sjl rdpr %pstate, %o3
10925cf1a30Sjl andn %o3, PSTATE_IE, %o4
11025cf1a30Sjl wrpr %g0, %o4, %pstate
11125cf1a30Sjl mov ASI_L2_CTRL_U2_FLUSH, %o4
11225cf1a30Sjl mov ASI_L2_CTRL_RW_ADDR, %o5
11325cf1a30Sjl stxa %o4, [%o5]ASI_L2_CTRL
11425cf1a30Sjl ! retl
11525cf1a30Sjl wrpr %g0, %o3, %pstate ! restore earlier pstate
11625cf1a30Sjl SET_SIZE(flush_cache_il)
11725cf1a30Sjl
11825cf1a30Sjl #endif /* lint */
11925cf1a30Sjl
12025cf1a30Sjl #if defined(lint)
12125cf1a30Sjl /* ARGUSED */
12225cf1a30Sjl uint64_t
drmach_get_stick_il(void)12325cf1a30Sjl drmach_get_stick_il(void)
12425cf1a30Sjl {}
12525cf1a30Sjl
12625cf1a30Sjl #else /* lint */
ENTRY_NP(drmach_get_stick_il)12725cf1a30Sjl ENTRY_NP(drmach_get_stick_il)
12825cf1a30Sjl retl
12925cf1a30Sjl rd STICK, %o0
13025cf1a30Sjl SET_SIZE(drmach_get_stick_il)
13125cf1a30Sjl #endif /* lint */
13225cf1a30Sjl
13325cf1a30Sjl #if defined(lint)
13425cf1a30Sjl /* ARGUSED */
13525cf1a30Sjl void
13625cf1a30Sjl membar_sync_il(void)
13725cf1a30Sjl {}
13825cf1a30Sjl
13925cf1a30Sjl #else /* lint */
14025cf1a30Sjl ENTRY_NP(membar_sync_il)
14125cf1a30Sjl retl
14225cf1a30Sjl membar #Sync
14325cf1a30Sjl SET_SIZE(membar_sync_il)
14425cf1a30Sjl #endif /* lint */
14525cf1a30Sjl
14625cf1a30Sjl
14725cf1a30Sjl #if defined(lint)
14825cf1a30Sjl
14925cf1a30Sjl /* ARGSUSED */
15025cf1a30Sjl void
flush_instr_mem_il(caddr_t vaddr)15125cf1a30Sjl flush_instr_mem_il(caddr_t vaddr)
15225cf1a30Sjl {}
15325cf1a30Sjl
15425cf1a30Sjl #else /* lint */
15525cf1a30Sjl
15625cf1a30Sjl /*
15725cf1a30Sjl * flush_instr_mem:
15825cf1a30Sjl * Flush 1 page of the I-$ starting at vaddr
15925cf1a30Sjl * %o0 vaddr
16025cf1a30Sjl *
16125cf1a30Sjl * SPARC64-VI maintains consistency of the on-chip Instruction Cache with
16225cf1a30Sjl * the stores from all processors so that a FLUSH instruction is only needed
16325cf1a30Sjl * to ensure pipeline is consistent. This means a single flush is sufficient at
16425cf1a30Sjl * the end of a sequence of stores that updates the instruction stream to
16525cf1a30Sjl * ensure correct operation.
16625cf1a30Sjl */
16725cf1a30Sjl
16825cf1a30Sjl ENTRY_NP(flush_instr_mem_il)
169*63360950Smp flush %o0 ! address irrelevant
17025cf1a30Sjl retl
17168ac2337Sjl nop
17225cf1a30Sjl SET_SIZE(flush_instr_mem_il)
17325cf1a30Sjl
17425cf1a30Sjl #endif /* lint */
17525cf1a30Sjl
17625cf1a30Sjl #if defined(lint)
17725cf1a30Sjl
17825cf1a30Sjl /* ARGSUSED */
17925cf1a30Sjl void
18025cf1a30Sjl drmach_sleep_il(void)
18125cf1a30Sjl {}
18225cf1a30Sjl
18325cf1a30Sjl #else /* lint */
18425cf1a30Sjl
18525cf1a30Sjl /*
18625cf1a30Sjl * drmach-sleep_il:
18725cf1a30Sjl *
18825cf1a30Sjl * busy loop wait can affect performance of the sibling strand
18925cf1a30Sjl * the sleep instruction can be used to avoid that.
19025cf1a30Sjl */
19125cf1a30Sjl
19225cf1a30Sjl ENTRY_NP(drmach_sleep_il)
19325cf1a30Sjl .word 0x81b01060
19468ac2337Sjl retl
19568ac2337Sjl nop
19668ac2337Sjl SET_SIZE(drmach_sleep_il)
19768ac2337Sjl
19868ac2337Sjl #endif /* lint */
19968ac2337Sjl
20068ac2337Sjl #if defined(lint)
20168ac2337Sjl
20268ac2337Sjl /* ARGSUSED */
20368ac2337Sjl void
flush_windows_il(void)20468ac2337Sjl flush_windows_il(void)
20568ac2337Sjl {}
20668ac2337Sjl
20768ac2337Sjl #else /* lint */
20868ac2337Sjl
20968ac2337Sjl /*
21068ac2337Sjl * flush_windows_il:
21168ac2337Sjl *
21268ac2337Sjl */
21368ac2337Sjl
21468ac2337Sjl ENTRY_NP(flush_windows_il)
21568ac2337Sjl retl
21668ac2337Sjl flushw
21768ac2337Sjl SET_SIZE(flush_windows_il)
21825cf1a30Sjl
21925cf1a30Sjl #endif /* lint */
220