1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * CMU-CH Interrupt Block 30 */ 31 32 #include <sys/types.h> 33 #include <sys/kmem.h> 34 #include <sys/async.h> 35 #include <sys/systm.h> 36 #include <sys/spl.h> 37 #include <sys/sunddi.h> 38 #include <sys/machsystm.h> 39 #include <sys/ddi_impldefs.h> 40 #include <sys/pcicmu/pcicmu.h> 41 42 static uint_t pcmu_ib_intr_reset(void *arg); 43 44 extern uint64_t xc_tick_jump_limit; 45 46 void 47 pcmu_ib_create(pcmu_t *pcmu_p) 48 { 49 pcmu_ib_t *pib_p; 50 uintptr_t a; 51 int i; 52 53 /* 54 * Allocate interrupt block state structure and link it to 55 * the pci state structure. 56 */ 57 pib_p = kmem_zalloc(sizeof (pcmu_ib_t), KM_SLEEP); 58 pcmu_p->pcmu_ib_p = pib_p; 59 pib_p->pib_pcmu_p = pcmu_p; 60 61 a = pcmu_ib_setup(pib_p); 62 63 /* 64 * Determine virtual addresses of interrupt mapping, clear and diag 65 * registers that have common offsets. 66 */ 67 pib_p->pib_intr_retry_timer_reg = 68 (uint64_t *)(a + PCMU_IB_INTR_RETRY_TIMER_OFFSET); 69 pib_p->pib_obio_intr_state_diag_reg = 70 (uint64_t *)(a + PCMU_IB_OBIO_INTR_STATE_DIAG_REG); 71 72 PCMU_DBG2(PCMU_DBG_ATTACH, pcmu_p->pcmu_dip, 73 "pcmu_ib_create: obio_imr=%x, obio_cir=%x\n", 74 pib_p->pib_obio_intr_map_regs, pib_p->pib_obio_clear_intr_regs); 75 PCMU_DBG2(PCMU_DBG_ATTACH, pcmu_p->pcmu_dip, 76 "pcmu_ib_create: retry_timer=%x, obio_diag=%x\n", 77 pib_p->pib_intr_retry_timer_reg, 78 pib_p->pib_obio_intr_state_diag_reg); 79 80 pib_p->pib_ino_lst = (pcmu_ib_ino_info_t *)NULL; 81 mutex_init(&pib_p->pib_intr_lock, NULL, MUTEX_DRIVER, NULL); 82 mutex_init(&pib_p->pib_ino_lst_mutex, NULL, MUTEX_DRIVER, NULL); 83 84 PCMU_DBG1(PCMU_DBG_ATTACH, pcmu_p->pcmu_dip, 85 "pcmu_ib_create: numproxy=%x\n", pcmu_p->pcmu_numproxy); 86 for (i = 1; i <= pcmu_p->pcmu_numproxy; i++) { 87 set_intr_mapping_reg(pcmu_p->pcmu_id, 88 (uint64_t *)pib_p->pib_upa_imr[i - 1], i); 89 } 90 91 pcmu_ib_configure(pib_p); 92 bus_func_register(BF_TYPE_RESINTR, pcmu_ib_intr_reset, pib_p); 93 } 94 95 void 96 pcmu_ib_destroy(pcmu_t *pcmu_p) 97 { 98 pcmu_ib_t *pib_p = pcmu_p->pcmu_ib_p; 99 100 PCMU_DBG0(PCMU_DBG_IB, pcmu_p->pcmu_dip, "pcmu_ib_destroy\n"); 101 bus_func_unregister(BF_TYPE_RESINTR, pcmu_ib_intr_reset, pib_p); 102 103 intr_dist_rem_weighted(pcmu_ib_intr_dist_all, pib_p); 104 mutex_destroy(&pib_p->pib_ino_lst_mutex); 105 mutex_destroy(&pib_p->pib_intr_lock); 106 107 pcmu_ib_free_ino_all(pib_p); 108 109 kmem_free(pib_p, sizeof (pcmu_ib_t)); 110 pcmu_p->pcmu_ib_p = NULL; 111 } 112 113 void 114 pcmu_ib_configure(pcmu_ib_t *pib_p) 115 { 116 *pib_p->pib_intr_retry_timer_reg = pcmu_intr_retry_intv; 117 } 118 119 /* 120 * can only used for CMU-CH internal interrupts ue, pbm 121 */ 122 void 123 pcmu_ib_intr_enable(pcmu_t *pcmu_p, pcmu_ib_ino_t ino) 124 { 125 pcmu_ib_t *pib_p = pcmu_p->pcmu_ib_p; 126 pcmu_ib_mondo_t mondo = PCMU_IB_INO_TO_MONDO(pib_p, ino); 127 volatile uint64_t *imr_p = ib_intr_map_reg_addr(pib_p, ino); 128 uint_t cpu_id; 129 130 /* 131 * Determine the cpu for the interrupt. 132 */ 133 mutex_enter(&pib_p->pib_intr_lock); 134 cpu_id = intr_dist_cpuid(); 135 cpu_id = u2u_translate_tgtid(pcmu_p, cpu_id, imr_p); 136 PCMU_DBG2(PCMU_DBG_IB, pcmu_p->pcmu_dip, 137 "pcmu_ib_intr_enable: ino=%x cpu_id=%x\n", ino, cpu_id); 138 139 *imr_p = ib_get_map_reg(mondo, cpu_id); 140 PCMU_IB_INO_INTR_CLEAR(ib_clear_intr_reg_addr(pib_p, ino)); 141 mutex_exit(&pib_p->pib_intr_lock); 142 } 143 144 /* 145 * Disable the interrupt via its interrupt mapping register. 146 * Can only be used for internal interrupts: ue, pbm. 147 * If called under interrupt context, wait should be set to 0 148 */ 149 void 150 pcmu_ib_intr_disable(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino, int wait) 151 { 152 volatile uint64_t *imr_p = ib_intr_map_reg_addr(pib_p, ino); 153 volatile uint64_t *state_reg_p = PCMU_IB_INO_INTR_STATE_REG(pib_p, ino); 154 hrtime_t start_time; 155 hrtime_t prev, curr, interval, jump; 156 hrtime_t intr_timeout; 157 158 /* disable the interrupt */ 159 mutex_enter(&pib_p->pib_intr_lock); 160 PCMU_IB_INO_INTR_OFF(imr_p); 161 *imr_p; /* flush previous write */ 162 mutex_exit(&pib_p->pib_intr_lock); 163 164 if (!wait) 165 goto wait_done; 166 167 intr_timeout = pcmu_intrpend_timeout; 168 jump = TICK_TO_NSEC(xc_tick_jump_limit); 169 start_time = curr = gethrtime(); 170 /* busy wait if there is interrupt being processed */ 171 while (PCMU_IB_INO_INTR_PENDING(state_reg_p, ino) && !panicstr) { 172 /* 173 * If we have a really large jump in hrtime, it is most 174 * probably because we entered the debugger (or OBP, 175 * in general). So, we adjust the timeout accordingly 176 * to prevent declaring an interrupt timeout. The 177 * master-interrupt mechanism in OBP should deliver 178 * the interrupts properly. 179 */ 180 prev = curr; 181 curr = gethrtime(); 182 interval = curr - prev; 183 if (interval > jump) 184 intr_timeout += interval; 185 if (curr - start_time > intr_timeout) { 186 pcmu_pbm_t *pcbm_p = pib_p->pib_pcmu_p->pcmu_pcbm_p; 187 cmn_err(CE_WARN, 188 "%s:%s: pcmu_ib_intr_disable timeout %x", 189 pcbm_p->pcbm_nameinst_str, 190 pcbm_p->pcbm_nameaddr_str, ino); 191 break; 192 } 193 } 194 wait_done: 195 PCMU_IB_INO_INTR_PEND(ib_clear_intr_reg_addr(pib_p, ino)); 196 u2u_ittrans_cleanup((u2u_ittrans_data_t *) 197 (PCMU_IB2CB(pib_p)->pcb_ittrans_cookie), imr_p); 198 } 199 200 /* can only used for CMU-CH internal interrupts ue, pbm */ 201 void 202 pcmu_ib_nintr_clear(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino) 203 { 204 uint64_t *clr_reg = ib_clear_intr_reg_addr(pib_p, ino); 205 PCMU_IB_INO_INTR_CLEAR(clr_reg); 206 } 207 208 /* 209 * distribute PBM and UPA interrupts. ino is set to 0 by caller if we 210 * are dealing with UPA interrupts (without inos). 211 */ 212 void 213 pcmu_ib_intr_dist_nintr(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino, 214 volatile uint64_t *imr_p) 215 { 216 volatile uint64_t imr = *imr_p; 217 uint32_t cpu_id; 218 219 if (!PCMU_IB_INO_INTR_ISON(imr)) 220 return; 221 222 cpu_id = intr_dist_cpuid(); 223 224 if (ino) { 225 cpu_id = u2u_translate_tgtid(pib_p->pib_pcmu_p, cpu_id, imr_p); 226 } 227 228 if (ib_map_reg_get_cpu(*imr_p) == cpu_id) { 229 return; 230 } 231 *imr_p = ib_get_map_reg(PCMU_IB_IMR2MONDO(imr), cpu_id); 232 imr = *imr_p; /* flush previous write */ 233 } 234 235 static void 236 pcmu_ib_intr_dist(pcmu_ib_t *pib_p, pcmu_ib_ino_info_t *ino_p) 237 { 238 uint32_t cpu_id = ino_p->pino_cpuid; 239 pcmu_ib_ino_t ino = ino_p->pino_ino; 240 volatile uint64_t imr, *imr_p, *state_reg; 241 hrtime_t start_time; 242 hrtime_t prev, curr, interval, jump; 243 hrtime_t intr_timeout; 244 245 ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex)); 246 imr_p = ib_intr_map_reg_addr(pib_p, ino); 247 state_reg = PCMU_IB_INO_INTR_STATE_REG(pib_p, ino); 248 249 /* disable interrupt, this could disrupt devices sharing our slot */ 250 PCMU_IB_INO_INTR_OFF(imr_p); 251 imr = *imr_p; /* flush previous write */ 252 253 /* busy wait if there is interrupt being processed */ 254 intr_timeout = pcmu_intrpend_timeout; 255 jump = TICK_TO_NSEC(xc_tick_jump_limit); 256 start_time = curr = gethrtime(); 257 while (PCMU_IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) { 258 /* 259 * If we have a really large jump in hrtime, it is most 260 * probably because we entered the debugger (or OBP, 261 * in general). So, we adjust the timeout accordingly 262 * to prevent declaring an interrupt timeout. The 263 * master-interrupt mechanism in OBP should deliver 264 * the interrupts properly. 265 */ 266 prev = curr; 267 curr = gethrtime(); 268 interval = curr - prev; 269 if (interval > jump) 270 intr_timeout += interval; 271 if (curr - start_time > intr_timeout) { 272 pcmu_pbm_t *pcbm_p = pib_p->pib_pcmu_p->pcmu_pcbm_p; 273 cmn_err(CE_WARN, 274 "%s:%s: pcmu_ib_intr_dist(%p,%x) timeout", 275 pcbm_p->pcbm_nameinst_str, 276 pcbm_p->pcbm_nameaddr_str, 277 imr_p, PCMU_IB_INO_TO_MONDO(pib_p, ino)); 278 break; 279 } 280 } 281 cpu_id = u2u_translate_tgtid(pib_p->pib_pcmu_p, cpu_id, imr_p); 282 *imr_p = ib_get_map_reg(PCMU_IB_IMR2MONDO(imr), cpu_id); 283 imr = *imr_p; /* flush previous write */ 284 } 285 286 /* 287 * Redistribute interrupts of the specified weight. The first call has a weight 288 * of weight_max, which can be used to trigger initialization for 289 * redistribution. The inos with weight [weight_max, inf.) should be processed 290 * on the "weight == weight_max" call. This first call is followed by calls 291 * of decreasing weights, inos of that weight should be processed. The final 292 * call specifies a weight of zero, this can be used to trigger processing of 293 * stragglers. 294 */ 295 void 296 pcmu_ib_intr_dist_all(void *arg, int32_t weight_max, int32_t weight) 297 { 298 pcmu_ib_t *pib_p = (pcmu_ib_t *)arg; 299 pcmu_ib_ino_info_t *ino_p; 300 ih_t *ih_lst; 301 int32_t dweight; 302 int i; 303 304 mutex_enter(&pib_p->pib_ino_lst_mutex); 305 306 /* Perform special processing for first call of a redistribution. */ 307 if (weight == weight_max) { 308 for (ino_p = pib_p->pib_ino_lst; ino_p; 309 ino_p = ino_p->pino_next) { 310 311 /* 312 * Clear pino_established of each ino on first call. 313 * The pino_established field may be used by a pci 314 * nexus driver's pcmu_intr_dist_cpuid implementation 315 * when detection of established pci slot-cpu binding 316 * for multi function pci cards. 317 */ 318 ino_p->pino_established = 0; 319 320 /* 321 * recompute the pino_intr_weight based on the device 322 * weight of all devinfo nodes sharing the ino (this 323 * will allow us to pick up new weights established by 324 * i_ddi_set_intr_weight()). 325 */ 326 ino_p->pino_intr_weight = 0; 327 for (i = 0, ih_lst = ino_p->pino_ih_head; 328 i < ino_p->pino_ih_size; 329 i++, ih_lst = ih_lst->ih_next) { 330 dweight = i_ddi_get_intr_weight(ih_lst->ih_dip); 331 if (dweight > 0) 332 ino_p->pino_intr_weight += dweight; 333 } 334 } 335 } 336 337 for (ino_p = pib_p->pib_ino_lst; ino_p; ino_p = ino_p->pino_next) { 338 /* 339 * Get the weight of the ino and determine if we are going to 340 * process call. We wait until an pcmu_ib_intr_dist_all call of 341 * the proper weight occurs to support redistribution of all 342 * heavy weighted interrupts first (across all nexus driver 343 * instances). This is done to ensure optimal 344 * INTR_WEIGHTED_DIST behavior. 345 */ 346 if ((weight == ino_p->pino_intr_weight) || 347 ((weight >= weight_max) && 348 (ino_p->pino_intr_weight >= weight_max))) { 349 /* select cpuid to target and mark ino established */ 350 ino_p->pino_cpuid = pcmu_intr_dist_cpuid(pib_p, ino_p); 351 ino_p->pino_established = 1; 352 353 /* Add device weight of ino devinfos to targeted cpu. */ 354 for (i = 0, ih_lst = ino_p->pino_ih_head; 355 i < ino_p->pino_ih_size; 356 i++, ih_lst = ih_lst->ih_next) { 357 dweight = i_ddi_get_intr_weight(ih_lst->ih_dip); 358 intr_dist_cpuid_add_device_weight( 359 ino_p->pino_cpuid, ih_lst->ih_dip, dweight); 360 } 361 362 /* program the hardware */ 363 pcmu_ib_intr_dist(pib_p, ino_p); 364 } 365 } 366 mutex_exit(&pib_p->pib_ino_lst_mutex); 367 } 368 369 /* 370 * Reset interrupts to IDLE. This function is called during 371 * panic handling after redistributing interrupts; it's needed to 372 * support dumping to network devices after 'sync' from OBP. 373 * 374 * N.B. This routine runs in a context where all other threads 375 * are permanently suspended. 376 */ 377 static uint_t 378 pcmu_ib_intr_reset(void *arg) 379 { 380 pcmu_ib_t *pib_p = (pcmu_ib_t *)arg; 381 pcmu_ib_ino_t ino; 382 uint64_t *clr_reg; 383 384 /* 385 * Note that we only actually care about interrupts that are 386 * potentially from network devices. 387 */ 388 for (ino = 0; ino <= pib_p->pib_max_ino; ino++) { 389 clr_reg = ib_clear_intr_reg_addr(pib_p, ino); 390 PCMU_IB_INO_INTR_CLEAR(clr_reg); 391 } 392 return (BF_NONE); 393 } 394 395 void 396 pcmu_ib_suspend(pcmu_ib_t *pib_p) 397 { 398 pcmu_ib_ino_info_t *ip; 399 400 /* save ino_lst interrupts' mapping registers content */ 401 mutex_enter(&pib_p->pib_ino_lst_mutex); 402 for (ip = pib_p->pib_ino_lst; ip; ip = ip->pino_next) { 403 ip->pino_map_reg_save = *ip->pino_map_reg; 404 } 405 mutex_exit(&pib_p->pib_ino_lst_mutex); 406 } 407 408 void 409 pcmu_ib_resume(pcmu_ib_t *pib_p) 410 { 411 pcmu_ib_ino_info_t *ip; 412 413 /* restore ino_lst interrupts' mapping registers content */ 414 mutex_enter(&pib_p->pib_ino_lst_mutex); 415 for (ip = pib_p->pib_ino_lst; ip; ip = ip->pino_next) { 416 PCMU_IB_INO_INTR_CLEAR(ip->pino_clr_reg); /* set intr to idle */ 417 *ip->pino_map_reg = ip->pino_map_reg_save; /* restore IMR */ 418 } 419 mutex_exit(&pib_p->pib_ino_lst_mutex); 420 } 421 422 /* 423 * locate ino_info structure on pib_p->pib_ino_lst according to ino# 424 * returns NULL if not found. 425 */ 426 pcmu_ib_ino_info_t * 427 pcmu_ib_locate_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino_num) 428 { 429 pcmu_ib_ino_info_t *ino_p = pib_p->pib_ino_lst; 430 ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex)); 431 432 for (; ino_p && ino_p->pino_ino != ino_num; ino_p = ino_p->pino_next); 433 return (ino_p); 434 } 435 436 #define PCMU_IB_INO_TO_SLOT(ino) \ 437 (PCMU_IB_IS_OBIO_INO(ino) ? 0xff : ((ino) & 0x1f) >> 2) 438 439 pcmu_ib_ino_info_t * 440 pcmu_ib_new_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino_num, ih_t *ih_p) 441 { 442 pcmu_ib_ino_info_t *ino_p = kmem_alloc(sizeof (pcmu_ib_ino_info_t), 443 KM_SLEEP); 444 ino_p->pino_ino = ino_num; 445 ino_p->pino_slot_no = PCMU_IB_INO_TO_SLOT(ino_num); 446 ino_p->pino_ib_p = pib_p; 447 ino_p->pino_clr_reg = ib_clear_intr_reg_addr(pib_p, ino_num); 448 ino_p->pino_map_reg = ib_intr_map_reg_addr(pib_p, ino_num); 449 ino_p->pino_unclaimed = 0; 450 451 /* 452 * cannot disable interrupt since we might share slot 453 * PCMU_IB_INO_INTR_OFF(ino_p->pino_map_reg); 454 */ 455 456 ih_p->ih_next = ih_p; 457 ino_p->pino_ih_head = ih_p; 458 ino_p->pino_ih_tail = ih_p; 459 ino_p->pino_ih_start = ih_p; 460 ino_p->pino_ih_size = 1; 461 462 ino_p->pino_next = pib_p->pib_ino_lst; 463 pib_p->pib_ino_lst = ino_p; 464 return (ino_p); 465 } 466 467 /* the ino_p is retrieved by previous call to pcmu_ib_locate_ino() */ 468 void 469 pcmu_ib_delete_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_info_t *ino_p) 470 { 471 pcmu_ib_ino_info_t *list = pib_p->pib_ino_lst; 472 ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex)); 473 if (list == ino_p) { 474 pib_p->pib_ino_lst = list->pino_next; 475 } else { 476 for (; list->pino_next != ino_p; list = list->pino_next); 477 list->pino_next = ino_p->pino_next; 478 } 479 } 480 481 /* free all ino when we are detaching */ 482 void 483 pcmu_ib_free_ino_all(pcmu_ib_t *pib_p) 484 { 485 pcmu_ib_ino_info_t *tmp = pib_p->pib_ino_lst; 486 pcmu_ib_ino_info_t *next = NULL; 487 while (tmp) { 488 next = tmp->pino_next; 489 kmem_free(tmp, sizeof (pcmu_ib_ino_info_t)); 490 tmp = next; 491 } 492 } 493 494 void 495 pcmu_ib_ino_add_intr(pcmu_t *pcmu_p, pcmu_ib_ino_info_t *ino_p, ih_t *ih_p) 496 { 497 pcmu_ib_ino_t ino = ino_p->pino_ino; 498 pcmu_ib_t *pib_p = ino_p->pino_ib_p; 499 volatile uint64_t *state_reg = PCMU_IB_INO_INTR_STATE_REG(pib_p, ino); 500 hrtime_t start_time; 501 hrtime_t prev, curr, interval, jump; 502 hrtime_t intr_timeout; 503 504 ASSERT(pib_p == pcmu_p->pcmu_ib_p); 505 ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex)); 506 507 /* disable interrupt, this could disrupt devices sharing our slot */ 508 PCMU_IB_INO_INTR_OFF(ino_p->pino_map_reg); 509 *ino_p->pino_map_reg; 510 511 /* do NOT modify the link list until after the busy wait */ 512 513 /* 514 * busy wait if there is interrupt being processed. 515 * either the pending state will be cleared by the interrupt wrapper 516 * or the interrupt will be marked as blocked indicating that it was 517 * jabbering. 518 */ 519 intr_timeout = pcmu_intrpend_timeout; 520 jump = TICK_TO_NSEC(xc_tick_jump_limit); 521 start_time = curr = gethrtime(); 522 while ((ino_p->pino_unclaimed <= pcmu_unclaimed_intr_max) && 523 PCMU_IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) { 524 /* 525 * If we have a really large jump in hrtime, it is most 526 * probably because we entered the debugger (or OBP, 527 * in general). So, we adjust the timeout accordingly 528 * to prevent declaring an interrupt timeout. The 529 * master-interrupt mechanism in OBP should deliver 530 * the interrupts properly. 531 */ 532 prev = curr; 533 curr = gethrtime(); 534 interval = curr - prev; 535 if (interval > jump) 536 intr_timeout += interval; 537 if (curr - start_time > intr_timeout) { 538 pcmu_pbm_t *pcbm_p = pcmu_p->pcmu_pcbm_p; 539 cmn_err(CE_WARN, 540 "%s:%s: pcmu_ib_ino_add_intr %x timeout", 541 pcbm_p->pcbm_nameinst_str, 542 pcbm_p->pcbm_nameaddr_str, ino); 543 break; 544 } 545 } 546 547 /* link up pcmu_ispec_t portion of the ppd */ 548 ih_p->ih_next = ino_p->pino_ih_head; 549 ino_p->pino_ih_tail->ih_next = ih_p; 550 ino_p->pino_ih_tail = ih_p; 551 552 ino_p->pino_ih_start = ino_p->pino_ih_head; 553 ino_p->pino_ih_size++; 554 555 /* 556 * if the interrupt was previously blocked (left in pending state) 557 * because of jabber we need to clear the pending state in case the 558 * jabber has gone away. 559 */ 560 if (ino_p->pino_unclaimed > pcmu_unclaimed_intr_max) { 561 cmn_err(CE_WARN, 562 "%s%d: pcmu_ib_ino_add_intr: ino 0x%x has been unblocked", 563 ddi_driver_name(pcmu_p->pcmu_dip), 564 ddi_get_instance(pcmu_p->pcmu_dip), 565 ino_p->pino_ino); 566 ino_p->pino_unclaimed = 0; 567 PCMU_IB_INO_INTR_CLEAR(ino_p->pino_clr_reg); 568 } 569 570 /* re-enable interrupt */ 571 PCMU_IB_INO_INTR_ON(ino_p->pino_map_reg); 572 *ino_p->pino_map_reg; 573 } 574 575 /* 576 * removes pcmu_ispec_t from the ino's link list. 577 * uses hardware mutex to lock out interrupt threads. 578 * Side effects: interrupt belongs to that ino is turned off on return. 579 * if we are sharing PCI slot with other inos, the caller needs 580 * to turn it back on. 581 */ 582 void 583 pcmu_ib_ino_rem_intr(pcmu_t *pcmu_p, pcmu_ib_ino_info_t *ino_p, ih_t *ih_p) 584 { 585 int i; 586 pcmu_ib_ino_t ino = ino_p->pino_ino; 587 ih_t *ih_lst = ino_p->pino_ih_head; 588 volatile uint64_t *state_reg = 589 PCMU_IB_INO_INTR_STATE_REG(ino_p->pino_ib_p, ino); 590 hrtime_t start_time; 591 hrtime_t prev, curr, interval, jump; 592 hrtime_t intr_timeout; 593 594 ASSERT(MUTEX_HELD(&ino_p->pino_ib_p->pib_ino_lst_mutex)); 595 /* disable interrupt, this could disrupt devices sharing our slot */ 596 PCMU_IB_INO_INTR_OFF(ino_p->pino_map_reg); 597 *ino_p->pino_map_reg; 598 599 /* do NOT modify the link list until after the busy wait */ 600 601 /* 602 * busy wait if there is interrupt being processed. 603 * either the pending state will be cleared by the interrupt wrapper 604 * or the interrupt will be marked as blocked indicating that it was 605 * jabbering. 606 */ 607 intr_timeout = pcmu_intrpend_timeout; 608 jump = TICK_TO_NSEC(xc_tick_jump_limit); 609 start_time = curr = gethrtime(); 610 while ((ino_p->pino_unclaimed <= pcmu_unclaimed_intr_max) && 611 PCMU_IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) { 612 /* 613 * If we have a really large jump in hrtime, it is most 614 * probably because we entered the debugger (or OBP, 615 * in general). So, we adjust the timeout accordingly 616 * to prevent declaring an interrupt timeout. The 617 * master-interrupt mechanism in OBP should deliver 618 * the interrupts properly. 619 */ 620 prev = curr; 621 curr = gethrtime(); 622 interval = curr - prev; 623 if (interval > jump) 624 intr_timeout += interval; 625 if (curr - start_time > intr_timeout) { 626 pcmu_pbm_t *pcbm_p = pcmu_p->pcmu_pcbm_p; 627 cmn_err(CE_WARN, 628 "%s:%s: pcmu_ib_ino_rem_intr %x timeout", 629 pcbm_p->pcbm_nameinst_str, 630 pcbm_p->pcbm_nameaddr_str, ino); 631 break; 632 } 633 } 634 635 if (ino_p->pino_ih_size == 1) { 636 if (ih_lst != ih_p) 637 goto not_found; 638 /* no need to set head/tail as ino_p will be freed */ 639 goto reset; 640 } 641 642 /* 643 * if the interrupt was previously blocked (left in pending state) 644 * because of jabber we need to clear the pending state in case the 645 * jabber has gone away. 646 */ 647 if (ino_p->pino_unclaimed > pcmu_unclaimed_intr_max) { 648 cmn_err(CE_WARN, 649 "%s%d: pcmu_ib_ino_rem_intr: ino 0x%x has been unblocked", 650 ddi_driver_name(pcmu_p->pcmu_dip), 651 ddi_get_instance(pcmu_p->pcmu_dip), 652 ino_p->pino_ino); 653 ino_p->pino_unclaimed = 0; 654 PCMU_IB_INO_INTR_CLEAR(ino_p->pino_clr_reg); 655 } 656 657 /* search the link list for ih_p */ 658 for (i = 0; (i < ino_p->pino_ih_size) && (ih_lst->ih_next != ih_p); 659 i++, ih_lst = ih_lst->ih_next); 660 if (ih_lst->ih_next != ih_p) { 661 goto not_found; 662 } 663 664 /* remove ih_p from the link list and maintain the head/tail */ 665 ih_lst->ih_next = ih_p->ih_next; 666 if (ino_p->pino_ih_head == ih_p) { 667 ino_p->pino_ih_head = ih_p->ih_next; 668 } 669 if (ino_p->pino_ih_tail == ih_p) { 670 ino_p->pino_ih_tail = ih_lst; 671 } 672 ino_p->pino_ih_start = ino_p->pino_ih_head; 673 reset: 674 if (ih_p->ih_config_handle) { 675 pci_config_teardown(&ih_p->ih_config_handle); 676 } 677 kmem_free(ih_p, sizeof (ih_t)); 678 ino_p->pino_ih_size--; 679 680 return; 681 not_found: 682 PCMU_DBG2(PCMU_DBG_R_INTX, ino_p->pino_ib_p->pib_pcmu_p->pcmu_dip, 683 "ino_p=%x does not have ih_p=%x\n", ino_p, ih_p); 684 } 685 686 ih_t * 687 pcmu_ib_ino_locate_intr(pcmu_ib_ino_info_t *ino_p, 688 dev_info_t *rdip, uint32_t inum) 689 { 690 ih_t *ih_lst = ino_p->pino_ih_head; 691 int i; 692 for (i = 0; i < ino_p->pino_ih_size; i++, ih_lst = ih_lst->ih_next) { 693 if (ih_lst->ih_dip == rdip && ih_lst->ih_inum == inum) { 694 return (ih_lst); 695 } 696 } 697 return ((ih_t *)NULL); 698 } 699 700 ih_t * 701 pcmu_ib_alloc_ih(dev_info_t *rdip, uint32_t inum, 702 uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2), 703 caddr_t int_handler_arg1, 704 caddr_t int_handler_arg2) 705 { 706 ih_t *ih_p; 707 708 ih_p = kmem_alloc(sizeof (ih_t), KM_SLEEP); 709 ih_p->ih_dip = rdip; 710 ih_p->ih_inum = inum; 711 ih_p->ih_intr_state = PCMU_INTR_STATE_DISABLE; 712 ih_p->ih_handler = int_handler; 713 ih_p->ih_handler_arg1 = int_handler_arg1; 714 ih_p->ih_handler_arg2 = int_handler_arg2; 715 ih_p->ih_config_handle = NULL; 716 return (ih_p); 717 } 718 719 int 720 pcmu_ib_update_intr_state(pcmu_t *pcmu_p, dev_info_t *rdip, 721 ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state) 722 { 723 pcmu_ib_t *pib_p = pcmu_p->pcmu_ib_p; 724 pcmu_ib_ino_info_t *ino_p; 725 pcmu_ib_mondo_t mondo; 726 ih_t *ih_p; 727 int ret = DDI_FAILURE; 728 729 mutex_enter(&pib_p->pib_ino_lst_mutex); 730 731 if ((mondo = PCMU_IB_INO_TO_MONDO(pcmu_p->pcmu_ib_p, 732 PCMU_IB_MONDO_TO_INO((int32_t)hdlp->ih_vector))) == 0) { 733 mutex_exit(&pib_p->pib_ino_lst_mutex); 734 return (ret); 735 } 736 737 if (ino_p = pcmu_ib_locate_ino(pib_p, PCMU_IB_MONDO_TO_INO(mondo))) { 738 if (ih_p = pcmu_ib_ino_locate_intr(ino_p, 739 rdip, hdlp->ih_inum)) { 740 ih_p->ih_intr_state = new_intr_state; 741 ret = DDI_SUCCESS; 742 } 743 } 744 mutex_exit(&pib_p->pib_ino_lst_mutex); 745 return (ret); 746 } 747