1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 /*
29  * CMU-CH Interrupt Block
30  */
31 
32 #include <sys/types.h>
33 #include <sys/kmem.h>
34 #include <sys/async.h>
35 #include <sys/systm.h>
36 #include <sys/spl.h>
37 #include <sys/sunddi.h>
38 #include <sys/machsystm.h>
39 #include <sys/ddi_impldefs.h>
40 #include <sys/pcicmu/pcicmu.h>
41 
42 /*LINTLIBRARY*/
43 static uint_t pcmu_ib_intr_reset(void *arg);
44 
45 extern uint64_t	xc_tick_jump_limit;
46 
47 void
48 pcmu_ib_create(pcmu_t *pcmu_p)
49 {
50 	pcmu_ib_t *pib_p;
51 	uintptr_t a;
52 	int i;
53 
54 	/*
55 	 * Allocate interrupt block state structure and link it to
56 	 * the pci state structure.
57 	 */
58 	pib_p = kmem_zalloc(sizeof (pcmu_ib_t), KM_SLEEP);
59 	pcmu_p->pcmu_ib_p = pib_p;
60 	pib_p->pib_pcmu_p = pcmu_p;
61 
62 	a = pcmu_ib_setup(pib_p);
63 
64 	/*
65 	 * Determine virtual addresses of interrupt mapping, clear and diag
66 	 * registers that have common offsets.
67 	 */
68 	pib_p->pib_intr_retry_timer_reg =
69 		(uint64_t *)(a + PCMU_IB_INTR_RETRY_TIMER_OFFSET);
70 	pib_p->pib_obio_intr_state_diag_reg =
71 		(uint64_t *)(a + PCMU_IB_OBIO_INTR_STATE_DIAG_REG);
72 
73 	PCMU_DBG2(PCMU_DBG_ATTACH, pcmu_p->pcmu_dip,
74 	    "pcmu_ib_create: obio_imr=%x, obio_cir=%x\n",
75 	    pib_p->pib_obio_intr_map_regs, pib_p->pib_obio_clear_intr_regs);
76 	PCMU_DBG2(PCMU_DBG_ATTACH, pcmu_p->pcmu_dip,
77 	    "pcmu_ib_create: retry_timer=%x, obio_diag=%x\n",
78 	    pib_p->pib_intr_retry_timer_reg,
79 	    pib_p->pib_obio_intr_state_diag_reg);
80 
81 	pib_p->pib_ino_lst = (pcmu_ib_ino_info_t *)NULL;
82 	mutex_init(&pib_p->pib_intr_lock, NULL, MUTEX_DRIVER, NULL);
83 	mutex_init(&pib_p->pib_ino_lst_mutex, NULL, MUTEX_DRIVER, NULL);
84 
85 	PCMU_DBG1(PCMU_DBG_ATTACH, pcmu_p->pcmu_dip,
86 	    "pcmu_ib_create: numproxy=%x\n", pcmu_p->pcmu_numproxy);
87 	for (i = 1; i <= pcmu_p->pcmu_numproxy; i++) {
88 		set_intr_mapping_reg(pcmu_p->pcmu_id,
89 			(uint64_t *)pib_p->pib_upa_imr[i - 1], i);
90 	}
91 
92 	pcmu_ib_configure(pib_p);
93 	bus_func_register(BF_TYPE_RESINTR, pcmu_ib_intr_reset, pib_p);
94 }
95 
96 void
97 pcmu_ib_destroy(pcmu_t *pcmu_p)
98 {
99 	pcmu_ib_t *pib_p = pcmu_p->pcmu_ib_p;
100 
101 	PCMU_DBG0(PCMU_DBG_IB, pcmu_p->pcmu_dip, "pcmu_ib_destroy\n");
102 	bus_func_unregister(BF_TYPE_RESINTR, pcmu_ib_intr_reset, pib_p);
103 
104 	intr_dist_rem_weighted(pcmu_ib_intr_dist_all, pib_p);
105 	mutex_destroy(&pib_p->pib_ino_lst_mutex);
106 	mutex_destroy(&pib_p->pib_intr_lock);
107 
108 	pcmu_ib_free_ino_all(pib_p);
109 
110 	kmem_free(pib_p, sizeof (pcmu_ib_t));
111 	pcmu_p->pcmu_ib_p = NULL;
112 }
113 
114 void
115 pcmu_ib_configure(pcmu_ib_t *pib_p)
116 {
117 	*pib_p->pib_intr_retry_timer_reg = pcmu_intr_retry_intv;
118 }
119 
120 /*
121  * can only used for CMU-CH internal interrupts ue, pbm
122  */
123 void
124 pcmu_ib_intr_enable(pcmu_t *pcmu_p, pcmu_ib_ino_t ino)
125 {
126 	pcmu_ib_t *pib_p = pcmu_p->pcmu_ib_p;
127 	pcmu_ib_mondo_t mondo = PCMU_IB_INO_TO_MONDO(pib_p, ino);
128 	volatile uint64_t *imr_p = ib_intr_map_reg_addr(pib_p, ino);
129 	uint_t cpu_id;
130 
131 	/*
132 	 * Determine the cpu for the interrupt.
133 	 */
134 	mutex_enter(&pib_p->pib_intr_lock);
135 	cpu_id = intr_dist_cpuid();
136 	cpu_id = u2u_translate_tgtid(pcmu_p, cpu_id, imr_p);
137 	PCMU_DBG2(PCMU_DBG_IB, pcmu_p->pcmu_dip,
138 	    "pcmu_ib_intr_enable: ino=%x cpu_id=%x\n", ino, cpu_id);
139 
140 	*imr_p = ib_get_map_reg(mondo, cpu_id);
141 	PCMU_IB_INO_INTR_CLEAR(ib_clear_intr_reg_addr(pib_p, ino));
142 	mutex_exit(&pib_p->pib_intr_lock);
143 }
144 
145 /*
146  * Disable the interrupt via its interrupt mapping register.
147  * Can only be used for internal interrupts: ue, pbm.
148  * If called under interrupt context, wait should be set to 0
149  */
150 void
151 pcmu_ib_intr_disable(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino, int wait)
152 {
153 	volatile uint64_t *imr_p = ib_intr_map_reg_addr(pib_p, ino);
154 	volatile uint64_t *state_reg_p = PCMU_IB_INO_INTR_STATE_REG(pib_p, ino);
155 	hrtime_t start_time;
156 	hrtime_t prev, curr, interval, jump;
157 	hrtime_t intr_timeout;
158 
159 	/* disable the interrupt */
160 	mutex_enter(&pib_p->pib_intr_lock);
161 	PCMU_IB_INO_INTR_OFF(imr_p);
162 	*imr_p;	/* flush previous write */
163 	mutex_exit(&pib_p->pib_intr_lock);
164 
165 	if (!wait)
166 		goto wait_done;
167 
168 	intr_timeout = pcmu_intrpend_timeout;
169 	jump = TICK_TO_NSEC(xc_tick_jump_limit);
170 	start_time = curr = gethrtime();
171 	/* busy wait if there is interrupt being processed */
172 	while (PCMU_IB_INO_INTR_PENDING(state_reg_p, ino) && !panicstr) {
173 		/*
174 		 * If we have a really large jump in hrtime, it is most
175 		 * probably because we entered the debugger (or OBP,
176 		 * in general). So, we adjust the timeout accordingly
177 		 * to prevent declaring an interrupt timeout. The
178 		 * master-interrupt mechanism in OBP should deliver
179 		 * the interrupts properly.
180 		 */
181 		prev = curr;
182 		curr = gethrtime();
183 		interval = curr - prev;
184 		if (interval > jump)
185 			intr_timeout += interval;
186 		if (curr - start_time > intr_timeout) {
187 			pcmu_pbm_t *pcbm_p = pib_p->pib_pcmu_p->pcmu_pcbm_p;
188 			cmn_err(CE_WARN,
189 			    "%s:%s: pcmu_ib_intr_disable timeout %x",
190 			    pcbm_p->pcbm_nameinst_str,
191 			    pcbm_p->pcbm_nameaddr_str, ino);
192 			break;
193 		}
194 	}
195 wait_done:
196 	PCMU_IB_INO_INTR_PEND(ib_clear_intr_reg_addr(pib_p, ino));
197 	u2u_ittrans_cleanup((u2u_ittrans_data_t *)
198 	    (PCMU_IB2CB(pib_p)->pcb_ittrans_cookie), imr_p);
199 }
200 
201 /* can only used for CMU-CH internal interrupts ue, pbm */
202 void
203 pcmu_ib_nintr_clear(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino)
204 {
205 	uint64_t *clr_reg = ib_clear_intr_reg_addr(pib_p, ino);
206 	PCMU_IB_INO_INTR_CLEAR(clr_reg);
207 }
208 
209 /*
210  * distribute PBM and UPA interrupts. ino is set to 0 by caller if we
211  * are dealing with UPA interrupts (without inos).
212  */
213 void
214 pcmu_ib_intr_dist_nintr(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino,
215     volatile uint64_t *imr_p)
216 {
217 	volatile uint64_t imr = *imr_p;
218 	uint32_t cpu_id;
219 
220 	if (!PCMU_IB_INO_INTR_ISON(imr))
221 		return;
222 
223 	cpu_id = intr_dist_cpuid();
224 
225 	if (ino) {
226 		cpu_id = u2u_translate_tgtid(pib_p->pib_pcmu_p, cpu_id, imr_p);
227 	}
228 
229 	if (ib_map_reg_get_cpu(*imr_p) == cpu_id) {
230 		return;
231 	}
232 	*imr_p = ib_get_map_reg(PCMU_IB_IMR2MONDO(imr), cpu_id);
233 	imr = *imr_p;	/* flush previous write */
234 }
235 
236 static void
237 pcmu_ib_intr_dist(pcmu_ib_t *pib_p, pcmu_ib_ino_info_t *ino_p)
238 {
239 	uint32_t cpu_id = ino_p->pino_cpuid;
240 	pcmu_ib_ino_t ino = ino_p->pino_ino;
241 	volatile uint64_t imr, *imr_p, *state_reg;
242 	hrtime_t start_time;
243 	hrtime_t prev, curr, interval, jump;
244 	hrtime_t intr_timeout;
245 
246 	ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex));
247 	imr_p = ib_intr_map_reg_addr(pib_p, ino);
248 	state_reg = PCMU_IB_INO_INTR_STATE_REG(pib_p, ino);
249 
250 	/* disable interrupt, this could disrupt devices sharing our slot */
251 	PCMU_IB_INO_INTR_OFF(imr_p);
252 	imr = *imr_p;	/* flush previous write */
253 
254 	/* busy wait if there is interrupt being processed */
255 	intr_timeout = pcmu_intrpend_timeout;
256 	jump = TICK_TO_NSEC(xc_tick_jump_limit);
257 	start_time = curr = gethrtime();
258 	while (PCMU_IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) {
259 		/*
260 		 * If we have a really large jump in hrtime, it is most
261 		 * probably because we entered the debugger (or OBP,
262 		 * in general). So, we adjust the timeout accordingly
263 		 * to prevent declaring an interrupt timeout. The
264 		 * master-interrupt mechanism in OBP should deliver
265 		 * the interrupts properly.
266 		 */
267 		prev = curr;
268 		curr = gethrtime();
269 		interval = curr - prev;
270 		if (interval > jump)
271 			intr_timeout += interval;
272 		if (curr - start_time > intr_timeout) {
273 			pcmu_pbm_t *pcbm_p = pib_p->pib_pcmu_p->pcmu_pcbm_p;
274 			cmn_err(CE_WARN,
275 			    "%s:%s: pcmu_ib_intr_dist(%p,%x) timeout",
276 			    pcbm_p->pcbm_nameinst_str,
277 			    pcbm_p->pcbm_nameaddr_str,
278 			    imr_p, PCMU_IB_INO_TO_MONDO(pib_p, ino));
279 			break;
280 		}
281 	}
282 	cpu_id = u2u_translate_tgtid(pib_p->pib_pcmu_p, cpu_id, imr_p);
283 	*imr_p = ib_get_map_reg(PCMU_IB_IMR2MONDO(imr), cpu_id);
284 	imr = *imr_p;	/* flush previous write */
285 }
286 
287 /*
288  * Redistribute interrupts of the specified weight. The first call has a weight
289  * of weight_max, which can be used to trigger initialization for
290  * redistribution. The inos with weight [weight_max, inf.) should be processed
291  * on the "weight == weight_max" call.  This first call is followed by calls
292  * of decreasing weights, inos of that weight should be processed.  The final
293  * call specifies a weight of zero, this can be used to trigger processing of
294  * stragglers.
295  */
296 void
297 pcmu_ib_intr_dist_all(void *arg, int32_t weight_max, int32_t weight)
298 {
299 	pcmu_ib_t *pib_p = (pcmu_ib_t *)arg;
300 	pcmu_ib_ino_info_t *ino_p;
301 	ih_t *ih_lst;
302 	int32_t dweight;
303 	int i;
304 
305 	mutex_enter(&pib_p->pib_ino_lst_mutex);
306 
307 	/* Perform special processing for first call of a redistribution. */
308 	if (weight == weight_max) {
309 		for (ino_p = pib_p->pib_ino_lst; ino_p;
310 		    ino_p = ino_p->pino_next) {
311 
312 			/*
313 			 * Clear pino_established of each ino on first call.
314 			 * The pino_established field may be used by a pci
315 			 * nexus driver's pcmu_intr_dist_cpuid implementation
316 			 * when detection of established pci slot-cpu binding
317 			 * for multi function pci cards.
318 			 */
319 			ino_p->pino_established = 0;
320 
321 			/*
322 			 * recompute the pino_intr_weight based on the device
323 			 * weight of all devinfo nodes sharing the ino (this
324 			 * will allow us to pick up new weights established by
325 			 * i_ddi_set_intr_weight()).
326 			 */
327 			ino_p->pino_intr_weight = 0;
328 			for (i = 0, ih_lst = ino_p->pino_ih_head;
329 			    i < ino_p->pino_ih_size;
330 			    i++, ih_lst = ih_lst->ih_next) {
331 				dweight = i_ddi_get_intr_weight(ih_lst->ih_dip);
332 				if (dweight > 0)
333 					ino_p->pino_intr_weight += dweight;
334 			}
335 		}
336 	}
337 
338 	for (ino_p = pib_p->pib_ino_lst; ino_p; ino_p = ino_p->pino_next) {
339 		/*
340 		 * Get the weight of the ino and determine if we are going to
341 		 * process call.  We wait until an pcmu_ib_intr_dist_all call of
342 		 * the proper weight occurs to support redistribution of all
343 		 * heavy weighted interrupts first (across all nexus driver
344 		 * instances).  This is done to ensure optimal
345 		 * INTR_WEIGHTED_DIST behavior.
346 		 */
347 		if ((weight == ino_p->pino_intr_weight) ||
348 		    ((weight >= weight_max) &&
349 		    (ino_p->pino_intr_weight >= weight_max))) {
350 			/* select cpuid to target and mark ino established */
351 			ino_p->pino_cpuid = pcmu_intr_dist_cpuid(pib_p, ino_p);
352 			ino_p->pino_established = 1;
353 
354 			/* Add device weight of ino devinfos to targeted cpu. */
355 			for (i = 0, ih_lst = ino_p->pino_ih_head;
356 			    i < ino_p->pino_ih_size;
357 			    i++, ih_lst = ih_lst->ih_next) {
358 				dweight = i_ddi_get_intr_weight(ih_lst->ih_dip);
359 				intr_dist_cpuid_add_device_weight(
360 				    ino_p->pino_cpuid, ih_lst->ih_dip, dweight);
361 			}
362 
363 			/* program the hardware */
364 			pcmu_ib_intr_dist(pib_p, ino_p);
365 		}
366 	}
367 	mutex_exit(&pib_p->pib_ino_lst_mutex);
368 }
369 
370 /*
371  * Reset interrupts to IDLE.  This function is called during
372  * panic handling after redistributing interrupts; it's needed to
373  * support dumping to network devices after 'sync' from OBP.
374  *
375  * N.B.  This routine runs in a context where all other threads
376  * are permanently suspended.
377  */
378 static uint_t
379 pcmu_ib_intr_reset(void *arg)
380 {
381 	pcmu_ib_t *pib_p = (pcmu_ib_t *)arg;
382 	pcmu_ib_ino_t ino;
383 	uint64_t *clr_reg;
384 
385 	/*
386 	 * Note that we only actually care about interrupts that are
387 	 * potentially from network devices.
388 	 */
389 	for (ino = 0; ino <= pib_p->pib_max_ino; ino++) {
390 		clr_reg = ib_clear_intr_reg_addr(pib_p, ino);
391 		PCMU_IB_INO_INTR_CLEAR(clr_reg);
392 	}
393 	return (BF_NONE);
394 }
395 
396 void
397 pcmu_ib_suspend(pcmu_ib_t *pib_p)
398 {
399 	pcmu_ib_ino_info_t *ip;
400 
401 	/* save ino_lst interrupts' mapping registers content */
402 	mutex_enter(&pib_p->pib_ino_lst_mutex);
403 	for (ip = pib_p->pib_ino_lst; ip; ip = ip->pino_next) {
404 		ip->pino_map_reg_save = *ip->pino_map_reg;
405 	}
406 	mutex_exit(&pib_p->pib_ino_lst_mutex);
407 }
408 
409 void
410 pcmu_ib_resume(pcmu_ib_t *pib_p)
411 {
412 	pcmu_ib_ino_info_t *ip;
413 
414 	/* restore ino_lst interrupts' mapping registers content */
415 	mutex_enter(&pib_p->pib_ino_lst_mutex);
416 	for (ip = pib_p->pib_ino_lst; ip; ip = ip->pino_next) {
417 		PCMU_IB_INO_INTR_CLEAR(ip->pino_clr_reg); /* set intr to idle */
418 		*ip->pino_map_reg = ip->pino_map_reg_save; /* restore IMR */
419 	}
420 	mutex_exit(&pib_p->pib_ino_lst_mutex);
421 }
422 
423 /*
424  * locate ino_info structure on pib_p->pib_ino_lst according to ino#
425  * returns NULL if not found.
426  */
427 pcmu_ib_ino_info_t *
428 pcmu_ib_locate_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino_num)
429 {
430 	pcmu_ib_ino_info_t *ino_p = pib_p->pib_ino_lst;
431 	ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex));
432 
433 	for (; ino_p && ino_p->pino_ino != ino_num; ino_p = ino_p->pino_next);
434 	return (ino_p);
435 }
436 
437 #define	PCMU_IB_INO_TO_SLOT(ino)		\
438 	(PCMU_IB_IS_OBIO_INO(ino) ? 0xff : ((ino) & 0x1f) >> 2)
439 
440 pcmu_ib_ino_info_t *
441 pcmu_ib_new_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino_num, ih_t *ih_p)
442 {
443 	pcmu_ib_ino_info_t *ino_p = kmem_alloc(sizeof (pcmu_ib_ino_info_t),
444 	    KM_SLEEP);
445 	ino_p->pino_ino = ino_num;
446 	ino_p->pino_slot_no = PCMU_IB_INO_TO_SLOT(ino_num);
447 	ino_p->pino_ib_p = pib_p;
448 	ino_p->pino_clr_reg = ib_clear_intr_reg_addr(pib_p, ino_num);
449 	ino_p->pino_map_reg = ib_intr_map_reg_addr(pib_p, ino_num);
450 	ino_p->pino_unclaimed = 0;
451 
452 	/*
453 	 * cannot disable interrupt since we might share slot
454 	 * PCMU_IB_INO_INTR_OFF(ino_p->pino_map_reg);
455 	 */
456 
457 	ih_p->ih_next = ih_p;
458 	ino_p->pino_ih_head = ih_p;
459 	ino_p->pino_ih_tail = ih_p;
460 	ino_p->pino_ih_start = ih_p;
461 	ino_p->pino_ih_size = 1;
462 
463 	ino_p->pino_next = pib_p->pib_ino_lst;
464 	pib_p->pib_ino_lst = ino_p;
465 	return (ino_p);
466 }
467 
468 /* the ino_p is retrieved by previous call to pcmu_ib_locate_ino() */
469 void
470 pcmu_ib_delete_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_info_t *ino_p)
471 {
472 	pcmu_ib_ino_info_t *list = pib_p->pib_ino_lst;
473 	ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex));
474 	if (list == ino_p) {
475 		pib_p->pib_ino_lst = list->pino_next;
476 	} else {
477 		for (; list->pino_next != ino_p; list = list->pino_next);
478 		list->pino_next = ino_p->pino_next;
479 	}
480 }
481 
482 /* free all ino when we are detaching */
483 void
484 pcmu_ib_free_ino_all(pcmu_ib_t *pib_p)
485 {
486 	pcmu_ib_ino_info_t *tmp = pib_p->pib_ino_lst;
487 	pcmu_ib_ino_info_t *next = NULL;
488 	while (tmp) {
489 		next = tmp->pino_next;
490 		kmem_free(tmp, sizeof (pcmu_ib_ino_info_t));
491 		tmp = next;
492 	}
493 }
494 
495 void
496 pcmu_ib_ino_add_intr(pcmu_t *pcmu_p, pcmu_ib_ino_info_t *ino_p, ih_t *ih_p)
497 {
498 	pcmu_ib_ino_t ino = ino_p->pino_ino;
499 	pcmu_ib_t *pib_p = ino_p->pino_ib_p;
500 	volatile uint64_t *state_reg = PCMU_IB_INO_INTR_STATE_REG(pib_p, ino);
501 	hrtime_t start_time;
502 	hrtime_t prev, curr, interval, jump;
503 	hrtime_t intr_timeout;
504 
505 	ASSERT(pib_p == pcmu_p->pcmu_ib_p);
506 	ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex));
507 
508 	/* disable interrupt, this could disrupt devices sharing our slot */
509 	PCMU_IB_INO_INTR_OFF(ino_p->pino_map_reg);
510 	*ino_p->pino_map_reg;
511 
512 	/* do NOT modify the link list until after the busy wait */
513 
514 	/*
515 	 * busy wait if there is interrupt being processed.
516 	 * either the pending state will be cleared by the interrupt wrapper
517 	 * or the interrupt will be marked as blocked indicating that it was
518 	 * jabbering.
519 	 */
520 	intr_timeout = pcmu_intrpend_timeout;
521 	jump = TICK_TO_NSEC(xc_tick_jump_limit);
522 	start_time = curr = gethrtime();
523 	while ((ino_p->pino_unclaimed <= pcmu_unclaimed_intr_max) &&
524 		PCMU_IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) {
525 		/*
526 		 * If we have a really large jump in hrtime, it is most
527 		 * probably because we entered the debugger (or OBP,
528 		 * in general). So, we adjust the timeout accordingly
529 		 * to prevent declaring an interrupt timeout. The
530 		 * master-interrupt mechanism in OBP should deliver
531 		 * the interrupts properly.
532 		 */
533 		prev = curr;
534 		curr = gethrtime();
535 		interval = curr - prev;
536 		if (interval > jump)
537 			intr_timeout += interval;
538 		if (curr - start_time > intr_timeout) {
539 			pcmu_pbm_t *pcbm_p = pcmu_p->pcmu_pcbm_p;
540 			cmn_err(CE_WARN,
541 			    "%s:%s: pcmu_ib_ino_add_intr %x timeout",
542 			    pcbm_p->pcbm_nameinst_str,
543 			    pcbm_p->pcbm_nameaddr_str, ino);
544 			break;
545 		}
546 	}
547 
548 	/* link up pcmu_ispec_t portion of the ppd */
549 	ih_p->ih_next = ino_p->pino_ih_head;
550 	ino_p->pino_ih_tail->ih_next = ih_p;
551 	ino_p->pino_ih_tail = ih_p;
552 
553 	ino_p->pino_ih_start = ino_p->pino_ih_head;
554 	ino_p->pino_ih_size++;
555 
556 	/*
557 	 * if the interrupt was previously blocked (left in pending state)
558 	 * because of jabber we need to clear the pending state in case the
559 	 * jabber has gone away.
560 	 */
561 	if (ino_p->pino_unclaimed > pcmu_unclaimed_intr_max) {
562 		cmn_err(CE_WARN,
563 		    "%s%d: pcmu_ib_ino_add_intr: ino 0x%x has been unblocked",
564 		    ddi_driver_name(pcmu_p->pcmu_dip),
565 		    ddi_get_instance(pcmu_p->pcmu_dip),
566 		    ino_p->pino_ino);
567 		ino_p->pino_unclaimed = 0;
568 		PCMU_IB_INO_INTR_CLEAR(ino_p->pino_clr_reg);
569 	}
570 
571 	/* re-enable interrupt */
572 	PCMU_IB_INO_INTR_ON(ino_p->pino_map_reg);
573 	*ino_p->pino_map_reg;
574 }
575 
576 /*
577  * removes pcmu_ispec_t from the ino's link list.
578  * uses hardware mutex to lock out interrupt threads.
579  * Side effects: interrupt belongs to that ino is turned off on return.
580  * if we are sharing PCI slot with other inos, the caller needs
581  * to turn it back on.
582  */
583 void
584 pcmu_ib_ino_rem_intr(pcmu_t *pcmu_p, pcmu_ib_ino_info_t *ino_p, ih_t *ih_p)
585 {
586 	int i;
587 	pcmu_ib_ino_t ino = ino_p->pino_ino;
588 	ih_t *ih_lst = ino_p->pino_ih_head;
589 	volatile uint64_t *state_reg =
590 		PCMU_IB_INO_INTR_STATE_REG(ino_p->pino_ib_p, ino);
591 	hrtime_t start_time;
592 	hrtime_t prev, curr, interval, jump;
593 	hrtime_t intr_timeout;
594 
595 	ASSERT(MUTEX_HELD(&ino_p->pino_ib_p->pib_ino_lst_mutex));
596 	/* disable interrupt, this could disrupt devices sharing our slot */
597 	PCMU_IB_INO_INTR_OFF(ino_p->pino_map_reg);
598 	*ino_p->pino_map_reg;
599 
600 	/* do NOT modify the link list until after the busy wait */
601 
602 	/*
603 	 * busy wait if there is interrupt being processed.
604 	 * either the pending state will be cleared by the interrupt wrapper
605 	 * or the interrupt will be marked as blocked indicating that it was
606 	 * jabbering.
607 	 */
608 	intr_timeout = pcmu_intrpend_timeout;
609 	jump = TICK_TO_NSEC(xc_tick_jump_limit);
610 	start_time = curr = gethrtime();
611 	while ((ino_p->pino_unclaimed <= pcmu_unclaimed_intr_max) &&
612 		PCMU_IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) {
613 		/*
614 		 * If we have a really large jump in hrtime, it is most
615 		 * probably because we entered the debugger (or OBP,
616 		 * in general). So, we adjust the timeout accordingly
617 		 * to prevent declaring an interrupt timeout. The
618 		 * master-interrupt mechanism in OBP should deliver
619 		 * the interrupts properly.
620 		 */
621 		prev = curr;
622 		curr = gethrtime();
623 		interval = curr - prev;
624 		if (interval > jump)
625 			intr_timeout += interval;
626 		if (curr - start_time > intr_timeout) {
627 			pcmu_pbm_t *pcbm_p = pcmu_p->pcmu_pcbm_p;
628 			cmn_err(CE_WARN,
629 			    "%s:%s: pcmu_ib_ino_rem_intr %x timeout",
630 			    pcbm_p->pcbm_nameinst_str,
631 			    pcbm_p->pcbm_nameaddr_str, ino);
632 			break;
633 		}
634 	}
635 
636 	if (ino_p->pino_ih_size == 1) {
637 		if (ih_lst != ih_p)
638 			goto not_found;
639 		/* no need to set head/tail as ino_p will be freed */
640 		goto reset;
641 	}
642 
643 	/*
644 	 * if the interrupt was previously blocked (left in pending state)
645 	 * because of jabber we need to clear the pending state in case the
646 	 * jabber has gone away.
647 	 */
648 	if (ino_p->pino_unclaimed > pcmu_unclaimed_intr_max) {
649 		cmn_err(CE_WARN,
650 		    "%s%d: pcmu_ib_ino_rem_intr: ino 0x%x has been unblocked",
651 		    ddi_driver_name(pcmu_p->pcmu_dip),
652 		    ddi_get_instance(pcmu_p->pcmu_dip),
653 		    ino_p->pino_ino);
654 		ino_p->pino_unclaimed = 0;
655 		PCMU_IB_INO_INTR_CLEAR(ino_p->pino_clr_reg);
656 	}
657 
658 	/* search the link list for ih_p */
659 	for (i = 0; (i < ino_p->pino_ih_size) && (ih_lst->ih_next != ih_p);
660 	    i++, ih_lst = ih_lst->ih_next);
661 	if (ih_lst->ih_next != ih_p) {
662 		goto not_found;
663 	}
664 
665 	/* remove ih_p from the link list and maintain the head/tail */
666 	ih_lst->ih_next = ih_p->ih_next;
667 	if (ino_p->pino_ih_head == ih_p) {
668 		ino_p->pino_ih_head = ih_p->ih_next;
669 	}
670 	if (ino_p->pino_ih_tail == ih_p) {
671 		ino_p->pino_ih_tail = ih_lst;
672 	}
673 	ino_p->pino_ih_start = ino_p->pino_ih_head;
674 reset:
675 	if (ih_p->ih_config_handle) {
676 		pci_config_teardown(&ih_p->ih_config_handle);
677 	}
678 	kmem_free(ih_p, sizeof (ih_t));
679 	ino_p->pino_ih_size--;
680 
681 	return;
682 not_found:
683 	PCMU_DBG2(PCMU_DBG_R_INTX, ino_p->pino_ib_p->pib_pcmu_p->pcmu_dip,
684 	    "ino_p=%x does not have ih_p=%x\n", ino_p, ih_p);
685 }
686 
687 ih_t *
688 pcmu_ib_ino_locate_intr(pcmu_ib_ino_info_t *ino_p,
689     dev_info_t *rdip, uint32_t inum)
690 {
691 	ih_t *ih_lst = ino_p->pino_ih_head;
692 	int i;
693 	for (i = 0; i < ino_p->pino_ih_size; i++, ih_lst = ih_lst->ih_next) {
694 		if (ih_lst->ih_dip == rdip && ih_lst->ih_inum == inum) {
695 			return (ih_lst);
696 		}
697 	}
698 	return ((ih_t *)NULL);
699 }
700 
701 ih_t *
702 pcmu_ib_alloc_ih(dev_info_t *rdip, uint32_t inum,
703     uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2),
704     caddr_t int_handler_arg1,
705     caddr_t int_handler_arg2)
706 {
707 	ih_t *ih_p;
708 
709 	ih_p = kmem_alloc(sizeof (ih_t), KM_SLEEP);
710 	ih_p->ih_dip = rdip;
711 	ih_p->ih_inum = inum;
712 	ih_p->ih_intr_state = PCMU_INTR_STATE_DISABLE;
713 	ih_p->ih_handler = int_handler;
714 	ih_p->ih_handler_arg1 = int_handler_arg1;
715 	ih_p->ih_handler_arg2 = int_handler_arg2;
716 	ih_p->ih_config_handle = NULL;
717 	return (ih_p);
718 }
719 
720 int
721 pcmu_ib_update_intr_state(pcmu_t *pcmu_p, dev_info_t *rdip,
722     ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state)
723 {
724 	pcmu_ib_t		*pib_p = pcmu_p->pcmu_ib_p;
725 	pcmu_ib_ino_info_t	*ino_p;
726 	pcmu_ib_mondo_t	mondo;
727 	ih_t		*ih_p;
728 	int		ret = DDI_FAILURE;
729 
730 	mutex_enter(&pib_p->pib_ino_lst_mutex);
731 
732 	if ((mondo = PCMU_IB_INO_TO_MONDO(pcmu_p->pcmu_ib_p,
733 	    PCMU_IB_MONDO_TO_INO((int32_t)hdlp->ih_vector))) == 0) {
734 		mutex_exit(&pib_p->pib_ino_lst_mutex);
735 		return (ret);
736 	}
737 
738 	if (ino_p = pcmu_ib_locate_ino(pib_p, PCMU_IB_MONDO_TO_INO(mondo))) {
739 		if (ih_p = pcmu_ib_ino_locate_intr(ino_p,
740 		    rdip, hdlp->ih_inum)) {
741 			ih_p->ih_intr_state = new_intr_state;
742 			ret = DDI_SUCCESS;
743 		}
744 	}
745 	mutex_exit(&pib_p->pib_ino_lst_mutex);
746 	return (ret);
747 }
748