1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24 * Use is subject to license terms.
25 */
26
27/*
28 * CMU-CH Interrupt Block
29 */
30
31#include <sys/types.h>
32#include <sys/kmem.h>
33#include <sys/async.h>
34#include <sys/systm.h>
35#include <sys/spl.h>
36#include <sys/sunddi.h>
37#include <sys/machsystm.h>
38#include <sys/ddi_impldefs.h>
39#include <sys/pcicmu/pcicmu.h>
40
41static uint_t pcmu_ib_intr_reset(void *arg);
42
43extern uint64_t	xc_tick_jump_limit;
44
45void
46pcmu_ib_create(pcmu_t *pcmu_p)
47{
48	pcmu_ib_t *pib_p;
49	uintptr_t a;
50	int i;
51
52	/*
53	 * Allocate interrupt block state structure and link it to
54	 * the pci state structure.
55	 */
56	pib_p = kmem_zalloc(sizeof (pcmu_ib_t), KM_SLEEP);
57	pcmu_p->pcmu_ib_p = pib_p;
58	pib_p->pib_pcmu_p = pcmu_p;
59
60	a = pcmu_ib_setup(pib_p);
61
62	/*
63	 * Determine virtual addresses of interrupt mapping, clear and diag
64	 * registers that have common offsets.
65	 */
66	pib_p->pib_intr_retry_timer_reg =
67	    (uint64_t *)(a + PCMU_IB_INTR_RETRY_TIMER_OFFSET);
68	pib_p->pib_obio_intr_state_diag_reg =
69	    (uint64_t *)(a + PCMU_IB_OBIO_INTR_STATE_DIAG_REG);
70
71	PCMU_DBG2(PCMU_DBG_ATTACH, pcmu_p->pcmu_dip,
72	    "pcmu_ib_create: obio_imr=%x, obio_cir=%x\n",
73	    pib_p->pib_obio_intr_map_regs, pib_p->pib_obio_clear_intr_regs);
74	PCMU_DBG2(PCMU_DBG_ATTACH, pcmu_p->pcmu_dip,
75	    "pcmu_ib_create: retry_timer=%x, obio_diag=%x\n",
76	    pib_p->pib_intr_retry_timer_reg,
77	    pib_p->pib_obio_intr_state_diag_reg);
78
79	pib_p->pib_ino_lst = (pcmu_ib_ino_info_t *)NULL;
80	mutex_init(&pib_p->pib_intr_lock, NULL, MUTEX_DRIVER, NULL);
81	mutex_init(&pib_p->pib_ino_lst_mutex, NULL, MUTEX_DRIVER, NULL);
82
83	PCMU_DBG1(PCMU_DBG_ATTACH, pcmu_p->pcmu_dip,
84	    "pcmu_ib_create: numproxy=%x\n", pcmu_p->pcmu_numproxy);
85	for (i = 1; i <= pcmu_p->pcmu_numproxy; i++) {
86		set_intr_mapping_reg(pcmu_p->pcmu_id,
87		    (uint64_t *)pib_p->pib_upa_imr[i - 1], i);
88	}
89
90	pcmu_ib_configure(pib_p);
91	bus_func_register(BF_TYPE_RESINTR, pcmu_ib_intr_reset, pib_p);
92}
93
94void
95pcmu_ib_destroy(pcmu_t *pcmu_p)
96{
97	pcmu_ib_t *pib_p = pcmu_p->pcmu_ib_p;
98
99	PCMU_DBG0(PCMU_DBG_IB, pcmu_p->pcmu_dip, "pcmu_ib_destroy\n");
100	bus_func_unregister(BF_TYPE_RESINTR, pcmu_ib_intr_reset, pib_p);
101
102	intr_dist_rem_weighted(pcmu_ib_intr_dist_all, pib_p);
103	mutex_destroy(&pib_p->pib_ino_lst_mutex);
104	mutex_destroy(&pib_p->pib_intr_lock);
105
106	pcmu_ib_free_ino_all(pib_p);
107
108	kmem_free(pib_p, sizeof (pcmu_ib_t));
109	pcmu_p->pcmu_ib_p = NULL;
110}
111
112void
113pcmu_ib_configure(pcmu_ib_t *pib_p)
114{
115	*pib_p->pib_intr_retry_timer_reg = pcmu_intr_retry_intv;
116}
117
118/*
119 * can only used for CMU-CH internal interrupts ue, pbm
120 */
121void
122pcmu_ib_intr_enable(pcmu_t *pcmu_p, pcmu_ib_ino_t ino)
123{
124	pcmu_ib_t *pib_p = pcmu_p->pcmu_ib_p;
125	pcmu_ib_mondo_t mondo = PCMU_IB_INO_TO_MONDO(pib_p, ino);
126	volatile uint64_t *imr_p = ib_intr_map_reg_addr(pib_p, ino);
127	uint_t cpu_id;
128
129	/*
130	 * Determine the cpu for the interrupt.
131	 */
132	mutex_enter(&pib_p->pib_intr_lock);
133	cpu_id = intr_dist_cpuid();
134	cpu_id = u2u_translate_tgtid(pcmu_p, cpu_id, imr_p);
135	PCMU_DBG2(PCMU_DBG_IB, pcmu_p->pcmu_dip,
136	    "pcmu_ib_intr_enable: ino=%x cpu_id=%x\n", ino, cpu_id);
137
138	*imr_p = ib_get_map_reg(mondo, cpu_id);
139	PCMU_IB_INO_INTR_CLEAR(ib_clear_intr_reg_addr(pib_p, ino));
140	mutex_exit(&pib_p->pib_intr_lock);
141}
142
143/*
144 * Disable the interrupt via its interrupt mapping register.
145 * Can only be used for internal interrupts: ue, pbm.
146 * If called under interrupt context, wait should be set to 0
147 */
148void
149pcmu_ib_intr_disable(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino, int wait)
150{
151	volatile uint64_t *imr_p = ib_intr_map_reg_addr(pib_p, ino);
152	volatile uint64_t *state_reg_p = PCMU_IB_INO_INTR_STATE_REG(pib_p, ino);
153	hrtime_t start_time;
154	hrtime_t prev, curr, interval, jump;
155	hrtime_t intr_timeout;
156
157	/* disable the interrupt */
158	mutex_enter(&pib_p->pib_intr_lock);
159	PCMU_IB_INO_INTR_OFF(imr_p);
160	*imr_p;	/* flush previous write */
161	mutex_exit(&pib_p->pib_intr_lock);
162
163	if (!wait)
164		goto wait_done;
165
166	intr_timeout = pcmu_intrpend_timeout;
167	jump = TICK_TO_NSEC(xc_tick_jump_limit);
168	start_time = curr = gethrtime();
169	/* busy wait if there is interrupt being processed */
170	while (PCMU_IB_INO_INTR_PENDING(state_reg_p, ino) && !panicstr) {
171		/*
172		 * If we have a really large jump in hrtime, it is most
173		 * probably because we entered the debugger (or OBP,
174		 * in general). So, we adjust the timeout accordingly
175		 * to prevent declaring an interrupt timeout. The
176		 * master-interrupt mechanism in OBP should deliver
177		 * the interrupts properly.
178		 */
179		prev = curr;
180		curr = gethrtime();
181		interval = curr - prev;
182		if (interval > jump)
183			intr_timeout += interval;
184		if (curr - start_time > intr_timeout) {
185			pcmu_pbm_t *pcbm_p = pib_p->pib_pcmu_p->pcmu_pcbm_p;
186			cmn_err(CE_WARN,
187			    "%s:%s: pcmu_ib_intr_disable timeout %x",
188			    pcbm_p->pcbm_nameinst_str,
189			    pcbm_p->pcbm_nameaddr_str, ino);
190			break;
191		}
192	}
193wait_done:
194	PCMU_IB_INO_INTR_PEND(ib_clear_intr_reg_addr(pib_p, ino));
195	u2u_ittrans_cleanup((u2u_ittrans_data_t *)
196	    (PCMU_IB2CB(pib_p)->pcb_ittrans_cookie), imr_p);
197}
198
199/* can only used for CMU-CH internal interrupts ue, pbm */
200void
201pcmu_ib_nintr_clear(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino)
202{
203	uint64_t *clr_reg = ib_clear_intr_reg_addr(pib_p, ino);
204	PCMU_IB_INO_INTR_CLEAR(clr_reg);
205}
206
207/*
208 * distribute PBM and UPA interrupts. ino is set to 0 by caller if we
209 * are dealing with UPA interrupts (without inos).
210 */
211void
212pcmu_ib_intr_dist_nintr(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino,
213    volatile uint64_t *imr_p)
214{
215	volatile uint64_t imr = *imr_p;
216	uint32_t cpu_id;
217
218	if (!PCMU_IB_INO_INTR_ISON(imr))
219		return;
220
221	cpu_id = intr_dist_cpuid();
222
223	if (ino) {
224		cpu_id = u2u_translate_tgtid(pib_p->pib_pcmu_p, cpu_id, imr_p);
225	}
226
227	if (ib_map_reg_get_cpu(*imr_p) == cpu_id) {
228		return;
229	}
230	*imr_p = ib_get_map_reg(PCMU_IB_IMR2MONDO(imr), cpu_id);
231	imr = *imr_p;	/* flush previous write */
232}
233
234static void
235pcmu_ib_intr_dist(pcmu_ib_t *pib_p, pcmu_ib_ino_info_t *ino_p)
236{
237	uint32_t cpu_id = ino_p->pino_cpuid;
238	pcmu_ib_ino_t ino = ino_p->pino_ino;
239	volatile uint64_t imr, *imr_p, *state_reg;
240	hrtime_t start_time;
241	hrtime_t prev, curr, interval, jump;
242	hrtime_t intr_timeout;
243
244	ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex));
245	imr_p = ib_intr_map_reg_addr(pib_p, ino);
246	state_reg = PCMU_IB_INO_INTR_STATE_REG(pib_p, ino);
247
248	/* disable interrupt, this could disrupt devices sharing our slot */
249	PCMU_IB_INO_INTR_OFF(imr_p);
250	imr = *imr_p;	/* flush previous write */
251
252	/* busy wait if there is interrupt being processed */
253	intr_timeout = pcmu_intrpend_timeout;
254	jump = TICK_TO_NSEC(xc_tick_jump_limit);
255	start_time = curr = gethrtime();
256	while (PCMU_IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) {
257		/*
258		 * If we have a really large jump in hrtime, it is most
259		 * probably because we entered the debugger (or OBP,
260		 * in general). So, we adjust the timeout accordingly
261		 * to prevent declaring an interrupt timeout. The
262		 * master-interrupt mechanism in OBP should deliver
263		 * the interrupts properly.
264		 */
265		prev = curr;
266		curr = gethrtime();
267		interval = curr - prev;
268		if (interval > jump)
269			intr_timeout += interval;
270		if (curr - start_time > intr_timeout) {
271			pcmu_pbm_t *pcbm_p = pib_p->pib_pcmu_p->pcmu_pcbm_p;
272			cmn_err(CE_WARN,
273			    "%s:%s: pcmu_ib_intr_dist(%p,%x) timeout",
274			    pcbm_p->pcbm_nameinst_str,
275			    pcbm_p->pcbm_nameaddr_str,
276			    (void *)imr_p, PCMU_IB_INO_TO_MONDO(pib_p, ino));
277			break;
278		}
279	}
280	cpu_id = u2u_translate_tgtid(pib_p->pib_pcmu_p, cpu_id, imr_p);
281	*imr_p = ib_get_map_reg(PCMU_IB_IMR2MONDO(imr), cpu_id);
282	imr = *imr_p;	/* flush previous write */
283}
284
285/*
286 * Redistribute interrupts of the specified weight. The first call has a weight
287 * of weight_max, which can be used to trigger initialization for
288 * redistribution. The inos with weight [weight_max, inf.) should be processed
289 * on the "weight == weight_max" call.  This first call is followed by calls
290 * of decreasing weights, inos of that weight should be processed.  The final
291 * call specifies a weight of zero, this can be used to trigger processing of
292 * stragglers.
293 */
294void
295pcmu_ib_intr_dist_all(void *arg, int32_t weight_max, int32_t weight)
296{
297	pcmu_ib_t *pib_p = (pcmu_ib_t *)arg;
298	pcmu_ib_ino_info_t *ino_p;
299	ih_t *ih_lst;
300	int32_t dweight;
301	int i;
302
303	mutex_enter(&pib_p->pib_ino_lst_mutex);
304
305	/* Perform special processing for first call of a redistribution. */
306	if (weight == weight_max) {
307		for (ino_p = pib_p->pib_ino_lst; ino_p;
308		    ino_p = ino_p->pino_next) {
309
310			/*
311			 * Clear pino_established of each ino on first call.
312			 * The pino_established field may be used by a pci
313			 * nexus driver's pcmu_intr_dist_cpuid implementation
314			 * when detection of established pci slot-cpu binding
315			 * for multi function pci cards.
316			 */
317			ino_p->pino_established = 0;
318
319			/*
320			 * recompute the pino_intr_weight based on the device
321			 * weight of all devinfo nodes sharing the ino (this
322			 * will allow us to pick up new weights established by
323			 * i_ddi_set_intr_weight()).
324			 */
325			ino_p->pino_intr_weight = 0;
326			for (i = 0, ih_lst = ino_p->pino_ih_head;
327			    i < ino_p->pino_ih_size;
328			    i++, ih_lst = ih_lst->ih_next) {
329				dweight = i_ddi_get_intr_weight(ih_lst->ih_dip);
330				if (dweight > 0)
331					ino_p->pino_intr_weight += dweight;
332			}
333		}
334	}
335
336	for (ino_p = pib_p->pib_ino_lst; ino_p; ino_p = ino_p->pino_next) {
337		/*
338		 * Get the weight of the ino and determine if we are going to
339		 * process call.  We wait until an pcmu_ib_intr_dist_all call of
340		 * the proper weight occurs to support redistribution of all
341		 * heavy weighted interrupts first (across all nexus driver
342		 * instances).  This is done to ensure optimal
343		 * INTR_WEIGHTED_DIST behavior.
344		 */
345		if ((weight == ino_p->pino_intr_weight) ||
346		    ((weight >= weight_max) &&
347		    (ino_p->pino_intr_weight >= weight_max))) {
348			/* select cpuid to target and mark ino established */
349			ino_p->pino_cpuid = pcmu_intr_dist_cpuid(pib_p, ino_p);
350			ino_p->pino_established = 1;
351
352			/* Add device weight of ino devinfos to targeted cpu. */
353			for (i = 0, ih_lst = ino_p->pino_ih_head;
354			    i < ino_p->pino_ih_size;
355			    i++, ih_lst = ih_lst->ih_next) {
356				dweight = i_ddi_get_intr_weight(ih_lst->ih_dip);
357				intr_dist_cpuid_add_device_weight(
358				    ino_p->pino_cpuid, ih_lst->ih_dip, dweight);
359			}
360
361			/* program the hardware */
362			pcmu_ib_intr_dist(pib_p, ino_p);
363		}
364	}
365	mutex_exit(&pib_p->pib_ino_lst_mutex);
366}
367
368/*
369 * Reset interrupts to IDLE.  This function is called during
370 * panic handling after redistributing interrupts; it's needed to
371 * support dumping to network devices after 'sync' from OBP.
372 *
373 * N.B.  This routine runs in a context where all other threads
374 * are permanently suspended.
375 */
376static uint_t
377pcmu_ib_intr_reset(void *arg)
378{
379	pcmu_ib_t *pib_p = (pcmu_ib_t *)arg;
380	pcmu_ib_ino_t ino;
381	uint64_t *clr_reg;
382
383	/*
384	 * Note that we only actually care about interrupts that are
385	 * potentially from network devices.
386	 */
387	for (ino = 0; ino <= pib_p->pib_max_ino; ino++) {
388		clr_reg = ib_clear_intr_reg_addr(pib_p, ino);
389		PCMU_IB_INO_INTR_CLEAR(clr_reg);
390	}
391	return (BF_NONE);
392}
393
394void
395pcmu_ib_suspend(pcmu_ib_t *pib_p)
396{
397	pcmu_ib_ino_info_t *ip;
398
399	/* save ino_lst interrupts' mapping registers content */
400	mutex_enter(&pib_p->pib_ino_lst_mutex);
401	for (ip = pib_p->pib_ino_lst; ip; ip = ip->pino_next) {
402		ip->pino_map_reg_save = *ip->pino_map_reg;
403	}
404	mutex_exit(&pib_p->pib_ino_lst_mutex);
405}
406
407void
408pcmu_ib_resume(pcmu_ib_t *pib_p)
409{
410	pcmu_ib_ino_info_t *ip;
411
412	/* restore ino_lst interrupts' mapping registers content */
413	mutex_enter(&pib_p->pib_ino_lst_mutex);
414	for (ip = pib_p->pib_ino_lst; ip; ip = ip->pino_next) {
415		PCMU_IB_INO_INTR_CLEAR(ip->pino_clr_reg); /* set intr to idle */
416		*ip->pino_map_reg = ip->pino_map_reg_save; /* restore IMR */
417	}
418	mutex_exit(&pib_p->pib_ino_lst_mutex);
419}
420
421/*
422 * locate ino_info structure on pib_p->pib_ino_lst according to ino#
423 * returns NULL if not found.
424 */
425pcmu_ib_ino_info_t *
426pcmu_ib_locate_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino_num)
427{
428	pcmu_ib_ino_info_t *ino_p = pib_p->pib_ino_lst;
429	ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex));
430
431	for (; ino_p && ino_p->pino_ino != ino_num; ino_p = ino_p->pino_next)
432		;
433	return (ino_p);
434}
435
436#define	PCMU_IB_INO_TO_SLOT(ino)		\
437	(PCMU_IB_IS_OBIO_INO(ino) ? 0xff : ((ino) & 0x1f) >> 2)
438
439pcmu_ib_ino_info_t *
440pcmu_ib_new_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino_num, ih_t *ih_p)
441{
442	pcmu_ib_ino_info_t *ino_p = kmem_alloc(sizeof (pcmu_ib_ino_info_t),
443	    KM_SLEEP);
444	ino_p->pino_ino = ino_num;
445	ino_p->pino_slot_no = PCMU_IB_INO_TO_SLOT(ino_num);
446	ino_p->pino_ib_p = pib_p;
447	ino_p->pino_clr_reg = ib_clear_intr_reg_addr(pib_p, ino_num);
448	ino_p->pino_map_reg = ib_intr_map_reg_addr(pib_p, ino_num);
449	ino_p->pino_unclaimed = 0;
450
451	/*
452	 * cannot disable interrupt since we might share slot
453	 * PCMU_IB_INO_INTR_OFF(ino_p->pino_map_reg);
454	 */
455
456	ih_p->ih_next = ih_p;
457	ino_p->pino_ih_head = ih_p;
458	ino_p->pino_ih_tail = ih_p;
459	ino_p->pino_ih_start = ih_p;
460	ino_p->pino_ih_size = 1;
461
462	ino_p->pino_next = pib_p->pib_ino_lst;
463	pib_p->pib_ino_lst = ino_p;
464	return (ino_p);
465}
466
467/* the ino_p is retrieved by previous call to pcmu_ib_locate_ino() */
468void
469pcmu_ib_delete_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_info_t *ino_p)
470{
471	pcmu_ib_ino_info_t *list = pib_p->pib_ino_lst;
472	ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex));
473	if (list == ino_p) {
474		pib_p->pib_ino_lst = list->pino_next;
475	} else {
476		for (; list->pino_next != ino_p; list = list->pino_next)
477			;
478		list->pino_next = ino_p->pino_next;
479	}
480}
481
482/* free all ino when we are detaching */
483void
484pcmu_ib_free_ino_all(pcmu_ib_t *pib_p)
485{
486	pcmu_ib_ino_info_t *tmp = pib_p->pib_ino_lst;
487	pcmu_ib_ino_info_t *next = NULL;
488	while (tmp) {
489		next = tmp->pino_next;
490		kmem_free(tmp, sizeof (pcmu_ib_ino_info_t));
491		tmp = next;
492	}
493}
494
495void
496pcmu_ib_ino_add_intr(pcmu_t *pcmu_p, pcmu_ib_ino_info_t *ino_p, ih_t *ih_p)
497{
498	pcmu_ib_ino_t ino = ino_p->pino_ino;
499	pcmu_ib_t *pib_p = ino_p->pino_ib_p;
500	volatile uint64_t *state_reg = PCMU_IB_INO_INTR_STATE_REG(pib_p, ino);
501	hrtime_t start_time;
502	hrtime_t prev, curr, interval, jump;
503	hrtime_t intr_timeout;
504
505	ASSERT(pib_p == pcmu_p->pcmu_ib_p);
506	ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex));
507
508	/* disable interrupt, this could disrupt devices sharing our slot */
509	PCMU_IB_INO_INTR_OFF(ino_p->pino_map_reg);
510	*ino_p->pino_map_reg;
511
512	/* do NOT modify the link list until after the busy wait */
513
514	/*
515	 * busy wait if there is interrupt being processed.
516	 * either the pending state will be cleared by the interrupt wrapper
517	 * or the interrupt will be marked as blocked indicating that it was
518	 * jabbering.
519	 */
520	intr_timeout = pcmu_intrpend_timeout;
521	jump = TICK_TO_NSEC(xc_tick_jump_limit);
522	start_time = curr = gethrtime();
523	while ((ino_p->pino_unclaimed <= pcmu_unclaimed_intr_max) &&
524	    PCMU_IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) {
525		/*
526		 * If we have a really large jump in hrtime, it is most
527		 * probably because we entered the debugger (or OBP,
528		 * in general). So, we adjust the timeout accordingly
529		 * to prevent declaring an interrupt timeout. The
530		 * master-interrupt mechanism in OBP should deliver
531		 * the interrupts properly.
532		 */
533		prev = curr;
534		curr = gethrtime();
535		interval = curr - prev;
536		if (interval > jump)
537			intr_timeout += interval;
538		if (curr - start_time > intr_timeout) {
539			pcmu_pbm_t *pcbm_p = pcmu_p->pcmu_pcbm_p;
540			cmn_err(CE_WARN,
541			    "%s:%s: pcmu_ib_ino_add_intr %x timeout",
542			    pcbm_p->pcbm_nameinst_str,
543			    pcbm_p->pcbm_nameaddr_str, ino);
544			break;
545		}
546	}
547
548	/* link up pcmu_ispec_t portion of the ppd */
549	ih_p->ih_next = ino_p->pino_ih_head;
550	ino_p->pino_ih_tail->ih_next = ih_p;
551	ino_p->pino_ih_tail = ih_p;
552
553	ino_p->pino_ih_start = ino_p->pino_ih_head;
554	ino_p->pino_ih_size++;
555
556	/*
557	 * if the interrupt was previously blocked (left in pending state)
558	 * because of jabber we need to clear the pending state in case the
559	 * jabber has gone away.
560	 */
561	if (ino_p->pino_unclaimed > pcmu_unclaimed_intr_max) {
562		cmn_err(CE_WARN,
563		    "%s%d: pcmu_ib_ino_add_intr: ino 0x%x has been unblocked",
564		    ddi_driver_name(pcmu_p->pcmu_dip),
565		    ddi_get_instance(pcmu_p->pcmu_dip),
566		    ino_p->pino_ino);
567		ino_p->pino_unclaimed = 0;
568		PCMU_IB_INO_INTR_CLEAR(ino_p->pino_clr_reg);
569	}
570
571	/* re-enable interrupt */
572	PCMU_IB_INO_INTR_ON(ino_p->pino_map_reg);
573	*ino_p->pino_map_reg;
574}
575
576/*
577 * removes pcmu_ispec_t from the ino's link list.
578 * uses hardware mutex to lock out interrupt threads.
579 * Side effects: interrupt belongs to that ino is turned off on return.
580 * if we are sharing PCI slot with other inos, the caller needs
581 * to turn it back on.
582 */
583int
584pcmu_ib_ino_rem_intr(pcmu_t *pcmu_p, pcmu_ib_ino_info_t *ino_p, ih_t *ih_p)
585{
586	int i;
587	pcmu_ib_ino_t ino = ino_p->pino_ino;
588	ih_t *ih_lst = ino_p->pino_ih_head;
589	volatile uint64_t *state_reg =
590	    PCMU_IB_INO_INTR_STATE_REG(ino_p->pino_ib_p, ino);
591	hrtime_t start_time;
592	hrtime_t prev, curr, interval, jump;
593	hrtime_t intr_timeout;
594
595	ASSERT(MUTEX_HELD(&ino_p->pino_ib_p->pib_ino_lst_mutex));
596	/* disable interrupt, this could disrupt devices sharing our slot */
597	PCMU_IB_INO_INTR_OFF(ino_p->pino_map_reg);
598	*ino_p->pino_map_reg;
599
600	/* do NOT modify the link list until after the busy wait */
601
602	/*
603	 * busy wait if there is interrupt being processed.
604	 * either the pending state will be cleared by the interrupt wrapper
605	 * or the interrupt will be marked as blocked indicating that it was
606	 * jabbering.
607	 */
608	intr_timeout = pcmu_intrpend_timeout;
609	jump = TICK_TO_NSEC(xc_tick_jump_limit);
610	start_time = curr = gethrtime();
611	while ((ino_p->pino_unclaimed <= pcmu_unclaimed_intr_max) &&
612	    PCMU_IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) {
613		/*
614		 * If we have a really large jump in hrtime, it is most
615		 * probably because we entered the debugger (or OBP,
616		 * in general). So, we adjust the timeout accordingly
617		 * to prevent declaring an interrupt timeout. The
618		 * master-interrupt mechanism in OBP should deliver
619		 * the interrupts properly.
620		 */
621		prev = curr;
622		curr = gethrtime();
623		interval = curr - prev;
624		if (interval > jump)
625			intr_timeout += interval;
626		if (curr - start_time > intr_timeout) {
627			pcmu_pbm_t *pcbm_p = pcmu_p->pcmu_pcbm_p;
628			cmn_err(CE_WARN,
629			    "%s:%s: pcmu_ib_ino_rem_intr %x timeout",
630			    pcbm_p->pcbm_nameinst_str,
631			    pcbm_p->pcbm_nameaddr_str, ino);
632			PCMU_IB_INO_INTR_ON(ino_p->pino_map_reg);
633			*ino_p->pino_map_reg;
634			return (DDI_FAILURE);
635		}
636	}
637
638	if (ino_p->pino_ih_size == 1) {
639		if (ih_lst != ih_p)
640			goto not_found;
641		/* no need to set head/tail as ino_p will be freed */
642		goto reset;
643	}
644
645	/*
646	 * if the interrupt was previously blocked (left in pending state)
647	 * because of jabber we need to clear the pending state in case the
648	 * jabber has gone away.
649	 */
650	if (ino_p->pino_unclaimed > pcmu_unclaimed_intr_max) {
651		cmn_err(CE_WARN,
652		    "%s%d: pcmu_ib_ino_rem_intr: ino 0x%x has been unblocked",
653		    ddi_driver_name(pcmu_p->pcmu_dip),
654		    ddi_get_instance(pcmu_p->pcmu_dip),
655		    ino_p->pino_ino);
656		ino_p->pino_unclaimed = 0;
657		PCMU_IB_INO_INTR_CLEAR(ino_p->pino_clr_reg);
658	}
659
660	/* search the link list for ih_p */
661	for (i = 0; (i < ino_p->pino_ih_size) && (ih_lst->ih_next != ih_p);
662	    i++, ih_lst = ih_lst->ih_next)
663		;
664	if (ih_lst->ih_next != ih_p) {
665		goto not_found;
666	}
667
668	/* remove ih_p from the link list and maintain the head/tail */
669	ih_lst->ih_next = ih_p->ih_next;
670	if (ino_p->pino_ih_head == ih_p) {
671		ino_p->pino_ih_head = ih_p->ih_next;
672	}
673	if (ino_p->pino_ih_tail == ih_p) {
674		ino_p->pino_ih_tail = ih_lst;
675	}
676	ino_p->pino_ih_start = ino_p->pino_ih_head;
677reset:
678	if (ih_p->ih_config_handle) {
679		pci_config_teardown(&ih_p->ih_config_handle);
680	}
681	kmem_free(ih_p, sizeof (ih_t));
682	ino_p->pino_ih_size--;
683
684	return (DDI_SUCCESS);
685not_found:
686	PCMU_DBG2(PCMU_DBG_R_INTX, ino_p->pino_ib_p->pib_pcmu_p->pcmu_dip,
687	    "ino_p=%x does not have ih_p=%x\n", ino_p, ih_p);
688	return (DDI_SUCCESS);
689}
690
691ih_t *
692pcmu_ib_ino_locate_intr(pcmu_ib_ino_info_t *ino_p,
693    dev_info_t *rdip, uint32_t inum)
694{
695	ih_t *ih_lst = ino_p->pino_ih_head;
696	int i;
697	for (i = 0; i < ino_p->pino_ih_size; i++, ih_lst = ih_lst->ih_next) {
698		if (ih_lst->ih_dip == rdip && ih_lst->ih_inum == inum) {
699			return (ih_lst);
700		}
701	}
702	return ((ih_t *)NULL);
703}
704
705ih_t *
706pcmu_ib_alloc_ih(dev_info_t *rdip, uint32_t inum,
707    uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2),
708    caddr_t int_handler_arg1,
709    caddr_t int_handler_arg2)
710{
711	ih_t *ih_p;
712
713	ih_p = kmem_alloc(sizeof (ih_t), KM_SLEEP);
714	ih_p->ih_dip = rdip;
715	ih_p->ih_inum = inum;
716	ih_p->ih_intr_state = PCMU_INTR_STATE_DISABLE;
717	ih_p->ih_handler = int_handler;
718	ih_p->ih_handler_arg1 = int_handler_arg1;
719	ih_p->ih_handler_arg2 = int_handler_arg2;
720	ih_p->ih_config_handle = NULL;
721	return (ih_p);
722}
723
724int
725pcmu_ib_update_intr_state(pcmu_t *pcmu_p, dev_info_t *rdip,
726    ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state)
727{
728	pcmu_ib_t		*pib_p = pcmu_p->pcmu_ib_p;
729	pcmu_ib_ino_info_t	*ino_p;
730	pcmu_ib_mondo_t	mondo;
731	ih_t		*ih_p;
732	int		ret = DDI_FAILURE;
733
734	mutex_enter(&pib_p->pib_ino_lst_mutex);
735
736	if ((mondo = PCMU_IB_INO_TO_MONDO(pcmu_p->pcmu_ib_p,
737	    PCMU_IB_MONDO_TO_INO((int32_t)hdlp->ih_vector))) == 0) {
738		mutex_exit(&pib_p->pib_ino_lst_mutex);
739		return (ret);
740	}
741
742	if (ino_p = pcmu_ib_locate_ino(pib_p, PCMU_IB_MONDO_TO_INO(mondo))) {
743		if (ih_p = pcmu_ib_ino_locate_intr(ino_p,
744		    rdip, hdlp->ih_inum)) {
745			ih_p->ih_intr_state = new_intr_state;
746			ret = DDI_SUCCESS;
747		}
748	}
749	mutex_exit(&pib_p->pib_ino_lst_mutex);
750	return (ret);
751}
752