125cf1a30Sjl /* 225cf1a30Sjl * CDDL HEADER START 325cf1a30Sjl * 425cf1a30Sjl * The contents of this file are subject to the terms of the 525cf1a30Sjl * Common Development and Distribution License (the "License"). 625cf1a30Sjl * You may not use this file except in compliance with the License. 725cf1a30Sjl * 825cf1a30Sjl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 925cf1a30Sjl * or http://www.opensolaris.org/os/licensing. 1025cf1a30Sjl * See the License for the specific language governing permissions 1125cf1a30Sjl * and limitations under the License. 1225cf1a30Sjl * 1325cf1a30Sjl * When distributing Covered Code, include this CDDL HEADER in each 1425cf1a30Sjl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1525cf1a30Sjl * If applicable, add the following below this CDDL HEADER, with the 1625cf1a30Sjl * fields enclosed by brackets "[]" replaced with your own identifying 1725cf1a30Sjl * information: Portions Copyright [yyyy] [name of copyright owner] 1825cf1a30Sjl * 1925cf1a30Sjl * CDDL HEADER END 2025cf1a30Sjl */ 211e2e7a75Shuah /* 221e2e7a75Shuah * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 231e2e7a75Shuah * Use is subject to license terms. 241e2e7a75Shuah */ 2525cf1a30Sjl /* 2625cf1a30Sjl * All Rights Reserved, Copyright (c) FUJITSU LIMITED 2006 2725cf1a30Sjl */ 2825cf1a30Sjl 2925cf1a30Sjl #pragma ident "%Z%%M% %I% %E% SMI" 3025cf1a30Sjl 3125cf1a30Sjl #include <sys/types.h> 3225cf1a30Sjl #include <sys/sysmacros.h> 3325cf1a30Sjl #include <sys/conf.h> 3425cf1a30Sjl #include <sys/modctl.h> 3525cf1a30Sjl #include <sys/stat.h> 3625cf1a30Sjl #include <sys/async.h> 371e2e7a75Shuah #include <sys/machcpuvar.h> 3825cf1a30Sjl #include <sys/machsystm.h> 390cc8ae86Sav #include <sys/promif.h> 4025cf1a30Sjl #include <sys/ksynch.h> 4125cf1a30Sjl #include <sys/ddi.h> 4225cf1a30Sjl #include <sys/sunddi.h> 4325cf1a30Sjl #include <sys/ddifm.h> 4425cf1a30Sjl #include <sys/fm/protocol.h> 4525cf1a30Sjl #include <sys/fm/util.h> 4625cf1a30Sjl #include <sys/kmem.h> 4725cf1a30Sjl #include <sys/fm/io/opl_mc_fm.h> 4825cf1a30Sjl #include <sys/memlist.h> 4925cf1a30Sjl #include <sys/param.h> 500cc8ae86Sav #include <sys/disp.h> 5125cf1a30Sjl #include <vm/page.h> 5225cf1a30Sjl #include <sys/mc-opl.h> 530cc8ae86Sav #include <sys/opl.h> 540cc8ae86Sav #include <sys/opl_dimm.h> 550cc8ae86Sav #include <sys/scfd/scfostoescf.h> 56cfb9e062Shyw #include <sys/cpu_module.h> 57cfb9e062Shyw #include <vm/seg_kmem.h> 58cfb9e062Shyw #include <sys/vmem.h> 59cfb9e062Shyw #include <vm/hat_sfmmu.h> 60cfb9e062Shyw #include <sys/vmsystm.h> 6125cf1a30Sjl 6225cf1a30Sjl /* 6325cf1a30Sjl * Function prototypes 6425cf1a30Sjl */ 6525cf1a30Sjl static int mc_open(dev_t *, int, int, cred_t *); 6625cf1a30Sjl static int mc_close(dev_t, int, int, cred_t *); 6725cf1a30Sjl static int mc_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 6825cf1a30Sjl static int mc_attach(dev_info_t *, ddi_attach_cmd_t); 6925cf1a30Sjl static int mc_detach(dev_info_t *, ddi_detach_cmd_t); 7025cf1a30Sjl 710cc8ae86Sav static int mc_poll_init(void); 720cc8ae86Sav static void mc_poll_fini(void); 7325cf1a30Sjl static int mc_board_add(mc_opl_t *mcp); 7425cf1a30Sjl static int mc_board_del(mc_opl_t *mcp); 7525cf1a30Sjl static int mc_suspend(mc_opl_t *mcp, uint32_t flag); 7625cf1a30Sjl static int mc_resume(mc_opl_t *mcp, uint32_t flag); 770cc8ae86Sav int opl_mc_suspend(void); 780cc8ae86Sav int opl_mc_resume(void); 7925cf1a30Sjl 8025cf1a30Sjl static void insert_mcp(mc_opl_t *mcp); 8125cf1a30Sjl static void delete_mcp(mc_opl_t *mcp); 8225cf1a30Sjl 8325cf1a30Sjl static int pa_to_maddr(mc_opl_t *mcp, uint64_t pa, mc_addr_t *maddr); 8425cf1a30Sjl 8525cf1a30Sjl static int mc_valid_pa(mc_opl_t *mcp, uint64_t pa); 8625cf1a30Sjl 8725cf1a30Sjl int mc_get_mem_unum(int, uint64_t, char *, int, int *); 880cc8ae86Sav int mc_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *paddr); 890cc8ae86Sav int mc_get_mem_offset(uint64_t paddr, uint64_t *offp); 900cc8ae86Sav int mc_get_mem_sid(char *unum, char *buf, int buflen, int *lenp); 910cc8ae86Sav int mc_get_mem_sid_dimm(mc_opl_t *mcp, char *dname, char *buf, 920cc8ae86Sav int buflen, int *lenp); 930cc8ae86Sav mc_dimm_info_t *mc_get_dimm_list(mc_opl_t *mcp); 940cc8ae86Sav mc_dimm_info_t *mc_prepare_dimmlist(board_dimm_info_t *bd_dimmp); 950cc8ae86Sav int mc_set_mem_sid(mc_opl_t *mcp, char *buf, int buflen, int lsb, int bank, 960cc8ae86Sav uint32_t mf_type, uint32_t d_slot); 970cc8ae86Sav static void mc_free_dimm_list(mc_dimm_info_t *d); 9825cf1a30Sjl static void mc_get_mlist(mc_opl_t *); 990cc8ae86Sav static void mc_polling(void); 1000cc8ae86Sav static int mc_opl_get_physical_board(int); 1010cc8ae86Sav 1020cc8ae86Sav #ifdef DEBUG 1030cc8ae86Sav static int mc_ioctl_debug(dev_t, int, intptr_t, int, cred_t *, int *); 1040cc8ae86Sav void mc_dump_dimm(char *buf, int dnamesz, int serialsz, int partnumsz); 1050cc8ae86Sav void mc_dump_dimm_info(board_dimm_info_t *bd_dimmp); 1060cc8ae86Sav #endif 10725cf1a30Sjl 10825cf1a30Sjl #pragma weak opl_get_physical_board 10925cf1a30Sjl extern int opl_get_physical_board(int); 1100cc8ae86Sav extern int plat_max_boards(void); 11125cf1a30Sjl 11225cf1a30Sjl /* 11325cf1a30Sjl * Configuration data structures 11425cf1a30Sjl */ 11525cf1a30Sjl static struct cb_ops mc_cb_ops = { 11625cf1a30Sjl mc_open, /* open */ 11725cf1a30Sjl mc_close, /* close */ 11825cf1a30Sjl nulldev, /* strategy */ 11925cf1a30Sjl nulldev, /* print */ 12025cf1a30Sjl nodev, /* dump */ 12125cf1a30Sjl nulldev, /* read */ 12225cf1a30Sjl nulldev, /* write */ 12325cf1a30Sjl mc_ioctl, /* ioctl */ 12425cf1a30Sjl nodev, /* devmap */ 12525cf1a30Sjl nodev, /* mmap */ 12625cf1a30Sjl nodev, /* segmap */ 12725cf1a30Sjl nochpoll, /* poll */ 12825cf1a30Sjl ddi_prop_op, /* cb_prop_op */ 12925cf1a30Sjl 0, /* streamtab */ 13025cf1a30Sjl D_MP | D_NEW | D_HOTPLUG, /* Driver compatibility flag */ 13125cf1a30Sjl CB_REV, /* rev */ 13225cf1a30Sjl nodev, /* cb_aread */ 13325cf1a30Sjl nodev /* cb_awrite */ 13425cf1a30Sjl }; 13525cf1a30Sjl 13625cf1a30Sjl static struct dev_ops mc_ops = { 13725cf1a30Sjl DEVO_REV, /* rev */ 13825cf1a30Sjl 0, /* refcnt */ 13925cf1a30Sjl ddi_getinfo_1to1, /* getinfo */ 14025cf1a30Sjl nulldev, /* identify */ 14125cf1a30Sjl nulldev, /* probe */ 14225cf1a30Sjl mc_attach, /* attach */ 14325cf1a30Sjl mc_detach, /* detach */ 14425cf1a30Sjl nulldev, /* reset */ 14525cf1a30Sjl &mc_cb_ops, /* cb_ops */ 14625cf1a30Sjl (struct bus_ops *)0, /* bus_ops */ 14725cf1a30Sjl nulldev /* power */ 14825cf1a30Sjl }; 14925cf1a30Sjl 15025cf1a30Sjl /* 15125cf1a30Sjl * Driver globals 15225cf1a30Sjl */ 15325cf1a30Sjl 1540cc8ae86Sav static enum { 1550cc8ae86Sav MODEL_FF1 = 0, 1560cc8ae86Sav MODEL_FF2 = 1, 1570cc8ae86Sav MODEL_DC = 2 1580cc8ae86Sav } plat_model = MODEL_DC; /* The default behaviour is DC */ 1590cc8ae86Sav 1600cc8ae86Sav static struct plat_model_names { 1610cc8ae86Sav const char *unit_name; 1620cc8ae86Sav const char *mem_name; 1630cc8ae86Sav } model_names[] = { 1640cc8ae86Sav { "MBU_A", "MEMB" }, 1650cc8ae86Sav { "MBU_B", "MEMB" }, 1660cc8ae86Sav { "CMU", "" } 1670cc8ae86Sav }; 16825cf1a30Sjl 1690cc8ae86Sav /* 1700cc8ae86Sav * The DIMM Names for DC platform. 1710cc8ae86Sav * The index into this table is made up of (bank, dslot), 1720cc8ae86Sav * Where dslot occupies bits 0-1 and bank occupies 2-4. 1730cc8ae86Sav */ 1740cc8ae86Sav static char *mc_dc_dimm_unum_table[OPL_MAX_DIMMS] = { 1750cc8ae86Sav /* --------CMUnn----------- */ 1760cc8ae86Sav /* --CS0-----|--CS1------ */ 1770cc8ae86Sav /* -H-|--L-- | -H- | -L-- */ 178*c964b0e6Sraghuram "03A", "02A", "03B", "02B", /* Bank 0 (MAC 0 bank 0) */ 179*c964b0e6Sraghuram "13A", "12A", "13B", "12B", /* Bank 1 (MAC 0 bank 1) */ 180*c964b0e6Sraghuram "23A", "22A", "23B", "22B", /* Bank 2 (MAC 1 bank 0) */ 181*c964b0e6Sraghuram "33A", "32A", "33B", "32B", /* Bank 3 (MAC 1 bank 1) */ 182*c964b0e6Sraghuram "01A", "00A", "01B", "00B", /* Bank 4 (MAC 2 bank 0) */ 183*c964b0e6Sraghuram "11A", "10A", "11B", "10B", /* Bank 5 (MAC 2 bank 1) */ 184*c964b0e6Sraghuram "21A", "20A", "21B", "20B", /* Bank 6 (MAC 3 bank 0) */ 185*c964b0e6Sraghuram "31A", "30A", "31B", "30B" /* Bank 7 (MAC 3 bank 1) */ 1860cc8ae86Sav }; 1870cc8ae86Sav 1880cc8ae86Sav /* 1890cc8ae86Sav * The DIMM Names for FF1/FF2 platforms. 1900cc8ae86Sav * The index into this table is made up of (board, bank, dslot), 1910cc8ae86Sav * Where dslot occupies bits 0-1, bank occupies 2-4 and 1920cc8ae86Sav * board occupies the bit 5. 1930cc8ae86Sav */ 1940cc8ae86Sav static char *mc_ff_dimm_unum_table[2 * OPL_MAX_DIMMS] = { 1950cc8ae86Sav /* --------CMU0---------- */ 1960cc8ae86Sav /* --CS0-----|--CS1------ */ 1970cc8ae86Sav /* -H-|--L-- | -H- | -L-- */ 198*c964b0e6Sraghuram "03A", "02A", "03B", "02B", /* Bank 0 (MAC 0 bank 0) */ 199*c964b0e6Sraghuram "01A", "00A", "01B", "00B", /* Bank 1 (MAC 0 bank 1) */ 200*c964b0e6Sraghuram "13A", "12A", "13B", "12B", /* Bank 2 (MAC 1 bank 0) */ 201*c964b0e6Sraghuram "11A", "10A", "11B", "10B", /* Bank 3 (MAC 1 bank 1) */ 202*c964b0e6Sraghuram "23A", "22A", "23B", "22B", /* Bank 4 (MAC 2 bank 0) */ 203*c964b0e6Sraghuram "21A", "20A", "21B", "20B", /* Bank 5 (MAC 2 bank 1) */ 204*c964b0e6Sraghuram "33A", "32A", "33B", "32B", /* Bank 6 (MAC 3 bank 0) */ 205*c964b0e6Sraghuram "31A", "30A", "31B", "30B", /* Bank 7 (MAC 3 bank 1) */ 2060cc8ae86Sav /* --------CMU1---------- */ 2070cc8ae86Sav /* --CS0-----|--CS1------ */ 2080cc8ae86Sav /* -H-|--L-- | -H- | -L-- */ 209*c964b0e6Sraghuram "43A", "42A", "43B", "42B", /* Bank 0 (MAC 0 bank 0) */ 210*c964b0e6Sraghuram "41A", "40A", "41B", "40B", /* Bank 1 (MAC 0 bank 1) */ 211*c964b0e6Sraghuram "53A", "52A", "53B", "52B", /* Bank 2 (MAC 1 bank 0) */ 212*c964b0e6Sraghuram "51A", "50A", "51B", "50B", /* Bank 3 (MAC 1 bank 1) */ 213*c964b0e6Sraghuram "63A", "62A", "63B", "62B", /* Bank 4 (MAC 2 bank 0) */ 214*c964b0e6Sraghuram "61A", "60A", "61B", "60B", /* Bank 5 (MAC 2 bank 1) */ 215*c964b0e6Sraghuram "73A", "72A", "73B", "72B", /* Bank 6 (MAC 3 bank 0) */ 216*c964b0e6Sraghuram "71A", "70A", "71B", "70B" /* Bank 7 (MAC 3 bank 1) */ 2170cc8ae86Sav }; 2180cc8ae86Sav 2190cc8ae86Sav #define BD_BK_SLOT_TO_INDEX(bd, bk, s) \ 2200cc8ae86Sav (((bd & 0x01) << 5) | ((bk & 0x07) << 2) | (s & 0x03)) 2210cc8ae86Sav 2220cc8ae86Sav #define INDEX_TO_BANK(i) (((i) & 0x1C) >> 2) 2230cc8ae86Sav #define INDEX_TO_SLOT(i) ((i) & 0x03) 2240cc8ae86Sav 2250cc8ae86Sav /* Isolation unit size is 64 MB */ 2260cc8ae86Sav #define MC_ISOLATION_BSIZE (64 * 1024 * 1024) 2270cc8ae86Sav 2280cc8ae86Sav #define MC_MAX_SPEEDS 7 2290cc8ae86Sav 2300cc8ae86Sav typedef struct { 2310cc8ae86Sav uint32_t mc_speeds; 2320cc8ae86Sav uint32_t mc_period; 2330cc8ae86Sav } mc_scan_speed_t; 2340cc8ae86Sav 2350cc8ae86Sav #define MC_CNTL_SPEED_SHIFT 26 2360cc8ae86Sav 2370cc8ae86Sav static mc_scan_speed_t mc_scan_speeds[MC_MAX_SPEEDS] = { 2380cc8ae86Sav {0x6 << MC_CNTL_SPEED_SHIFT, 0}, 2390cc8ae86Sav {0x5 << MC_CNTL_SPEED_SHIFT, 32}, 2400cc8ae86Sav {0x4 << MC_CNTL_SPEED_SHIFT, 64}, 2410cc8ae86Sav {0x3 << MC_CNTL_SPEED_SHIFT, 128}, 2420cc8ae86Sav {0x2 << MC_CNTL_SPEED_SHIFT, 256}, 2430cc8ae86Sav {0x1 << MC_CNTL_SPEED_SHIFT, 512}, 2440cc8ae86Sav {0x0 << MC_CNTL_SPEED_SHIFT, 1024} 2450cc8ae86Sav }; 2460cc8ae86Sav 2470cc8ae86Sav static uint32_t mc_max_speed = (0x6 << 26); 2480cc8ae86Sav 2490cc8ae86Sav int mc_isolation_bsize = MC_ISOLATION_BSIZE; 2500cc8ae86Sav int mc_patrol_interval_sec = MC_PATROL_INTERVAL_SEC; 2510cc8ae86Sav int mc_max_scf_retry = 16; 2520cc8ae86Sav int mc_max_scf_logs = 64; 2530cc8ae86Sav int mc_max_errlog_processed = BANKNUM_PER_SB*2; 2540cc8ae86Sav int mc_scan_period = 12 * 60 * 60; /* 12 hours period */ 2550cc8ae86Sav int mc_max_rewrite_loop = 100; 2560cc8ae86Sav int mc_rewrite_delay = 10; 2570cc8ae86Sav /* 2580cc8ae86Sav * it takes SCF about 300 m.s. to process a requst. We can bail out 2590cc8ae86Sav * if it is busy. It does not pay to wait for it too long. 2600cc8ae86Sav */ 2610cc8ae86Sav int mc_max_scf_loop = 2; 2620cc8ae86Sav int mc_scf_delay = 100; 2630cc8ae86Sav int mc_pce_dropped = 0; 2640cc8ae86Sav int mc_poll_priority = MINCLSYSPRI; 26525cf1a30Sjl 2660cc8ae86Sav 2670cc8ae86Sav /* 2680cc8ae86Sav * Mutex heierachy in mc-opl 2690cc8ae86Sav * If both mcmutex and mc_lock must be held, 2700cc8ae86Sav * mcmutex must be acquired first, and then mc_lock. 2710cc8ae86Sav */ 2720cc8ae86Sav 2730cc8ae86Sav static kmutex_t mcmutex; 2740cc8ae86Sav mc_opl_t *mc_instances[OPL_MAX_BOARDS]; 2750cc8ae86Sav 2760cc8ae86Sav static kmutex_t mc_polling_lock; 2770cc8ae86Sav static kcondvar_t mc_polling_cv; 2780cc8ae86Sav static kcondvar_t mc_poll_exit_cv; 2790cc8ae86Sav static int mc_poll_cmd = 0; 2800cc8ae86Sav static int mc_pollthr_running = 0; 2810cc8ae86Sav int mc_timeout_period = 0; /* this is in m.s. */ 28225cf1a30Sjl void *mc_statep; 28325cf1a30Sjl 28425cf1a30Sjl #ifdef DEBUG 2852742aa22Shyw int oplmc_debug = 0; 28625cf1a30Sjl #endif 28725cf1a30Sjl 2880cc8ae86Sav static int mc_debug_show_all = 0; 28925cf1a30Sjl 29025cf1a30Sjl extern struct mod_ops mod_driverops; 29125cf1a30Sjl 29225cf1a30Sjl static struct modldrv modldrv = { 29325cf1a30Sjl &mod_driverops, /* module type, this one is a driver */ 2940cc8ae86Sav "OPL Memory-controller %I%", /* module name */ 29525cf1a30Sjl &mc_ops, /* driver ops */ 29625cf1a30Sjl }; 29725cf1a30Sjl 29825cf1a30Sjl static struct modlinkage modlinkage = { 29925cf1a30Sjl MODREV_1, /* rev */ 30025cf1a30Sjl (void *)&modldrv, 30125cf1a30Sjl NULL 30225cf1a30Sjl }; 30325cf1a30Sjl 30425cf1a30Sjl #pragma weak opl_get_mem_unum 3050cc8ae86Sav #pragma weak opl_get_mem_sid 3060cc8ae86Sav #pragma weak opl_get_mem_offset 3070cc8ae86Sav #pragma weak opl_get_mem_addr 3080cc8ae86Sav 30925cf1a30Sjl extern int (*opl_get_mem_unum)(int, uint64_t, char *, int, int *); 3100cc8ae86Sav extern int (*opl_get_mem_sid)(char *unum, char *buf, int buflen, int *lenp); 3110cc8ae86Sav extern int (*opl_get_mem_offset)(uint64_t paddr, uint64_t *offp); 3120cc8ae86Sav extern int (*opl_get_mem_addr)(char *unum, char *sid, uint64_t offset, 3130cc8ae86Sav uint64_t *paddr); 3140cc8ae86Sav 31525cf1a30Sjl 31625cf1a30Sjl /* 31725cf1a30Sjl * pseudo-mc node portid format 31825cf1a30Sjl * 31925cf1a30Sjl * [10] = 0 32025cf1a30Sjl * [9] = 1 32125cf1a30Sjl * [8] = LSB_ID[4] = 0 32225cf1a30Sjl * [7:4] = LSB_ID[3:0] 32325cf1a30Sjl * [3:0] = 0 32425cf1a30Sjl * 32525cf1a30Sjl */ 32625cf1a30Sjl 32725cf1a30Sjl /* 32825cf1a30Sjl * These are the module initialization routines. 32925cf1a30Sjl */ 33025cf1a30Sjl int 33125cf1a30Sjl _init(void) 33225cf1a30Sjl { 3330cc8ae86Sav int error; 3340cc8ae86Sav int plen; 3350cc8ae86Sav char model[20]; 3360cc8ae86Sav pnode_t node; 33725cf1a30Sjl 33825cf1a30Sjl 33925cf1a30Sjl if ((error = ddi_soft_state_init(&mc_statep, 34025cf1a30Sjl sizeof (mc_opl_t), 1)) != 0) 34125cf1a30Sjl return (error); 34225cf1a30Sjl 3430cc8ae86Sav if ((error = mc_poll_init()) != 0) { 3440cc8ae86Sav ddi_soft_state_fini(&mc_statep); 3450cc8ae86Sav return (error); 3460cc8ae86Sav } 3470cc8ae86Sav 34825cf1a30Sjl mutex_init(&mcmutex, NULL, MUTEX_DRIVER, NULL); 34925cf1a30Sjl if (&opl_get_mem_unum) 35025cf1a30Sjl opl_get_mem_unum = mc_get_mem_unum; 3510cc8ae86Sav if (&opl_get_mem_sid) 3520cc8ae86Sav opl_get_mem_sid = mc_get_mem_sid; 3530cc8ae86Sav if (&opl_get_mem_offset) 3540cc8ae86Sav opl_get_mem_offset = mc_get_mem_offset; 3550cc8ae86Sav if (&opl_get_mem_addr) 3560cc8ae86Sav opl_get_mem_addr = mc_get_mem_addr; 3570cc8ae86Sav 3580cc8ae86Sav node = prom_rootnode(); 3590cc8ae86Sav plen = prom_getproplen(node, "model"); 3600cc8ae86Sav 3610cc8ae86Sav if (plen > 0 && plen < sizeof (model)) { 3620cc8ae86Sav (void) prom_getprop(node, "model", model); 3630cc8ae86Sav model[plen] = '\0'; 3640cc8ae86Sav if (strcmp(model, "FF1") == 0) 3650cc8ae86Sav plat_model = MODEL_FF1; 3660cc8ae86Sav else if (strcmp(model, "FF2") == 0) 3670cc8ae86Sav plat_model = MODEL_FF2; 3680cc8ae86Sav else if (strncmp(model, "DC", 2) == 0) 3690cc8ae86Sav plat_model = MODEL_DC; 3700cc8ae86Sav } 37125cf1a30Sjl 37225cf1a30Sjl error = mod_install(&modlinkage); 37325cf1a30Sjl if (error != 0) { 37425cf1a30Sjl if (&opl_get_mem_unum) 37525cf1a30Sjl opl_get_mem_unum = NULL; 3760cc8ae86Sav if (&opl_get_mem_sid) 3770cc8ae86Sav opl_get_mem_sid = NULL; 3780cc8ae86Sav if (&opl_get_mem_offset) 3790cc8ae86Sav opl_get_mem_offset = NULL; 3800cc8ae86Sav if (&opl_get_mem_addr) 3810cc8ae86Sav opl_get_mem_addr = NULL; 38225cf1a30Sjl mutex_destroy(&mcmutex); 3830cc8ae86Sav mc_poll_fini(); 38425cf1a30Sjl ddi_soft_state_fini(&mc_statep); 38525cf1a30Sjl } 38625cf1a30Sjl return (error); 38725cf1a30Sjl } 38825cf1a30Sjl 38925cf1a30Sjl int 39025cf1a30Sjl _fini(void) 39125cf1a30Sjl { 39225cf1a30Sjl int error; 39325cf1a30Sjl 39425cf1a30Sjl if ((error = mod_remove(&modlinkage)) != 0) 39525cf1a30Sjl return (error); 39625cf1a30Sjl 39725cf1a30Sjl if (&opl_get_mem_unum) 39825cf1a30Sjl opl_get_mem_unum = NULL; 3990cc8ae86Sav if (&opl_get_mem_sid) 4000cc8ae86Sav opl_get_mem_sid = NULL; 4010cc8ae86Sav if (&opl_get_mem_offset) 4020cc8ae86Sav opl_get_mem_offset = NULL; 4030cc8ae86Sav if (&opl_get_mem_addr) 4040cc8ae86Sav opl_get_mem_addr = NULL; 40525cf1a30Sjl 4060cc8ae86Sav mutex_destroy(&mcmutex); 4070cc8ae86Sav mc_poll_fini(); 40825cf1a30Sjl ddi_soft_state_fini(&mc_statep); 40925cf1a30Sjl 41025cf1a30Sjl return (0); 41125cf1a30Sjl } 41225cf1a30Sjl 41325cf1a30Sjl int 41425cf1a30Sjl _info(struct modinfo *modinfop) 41525cf1a30Sjl { 41625cf1a30Sjl return (mod_info(&modlinkage, modinfop)); 41725cf1a30Sjl } 41825cf1a30Sjl 4190cc8ae86Sav static void 4200cc8ae86Sav mc_polling_thread() 4210cc8ae86Sav { 4220cc8ae86Sav mutex_enter(&mc_polling_lock); 4230cc8ae86Sav mc_pollthr_running = 1; 4240cc8ae86Sav while (!(mc_poll_cmd & MC_POLL_EXIT)) { 4250cc8ae86Sav mc_polling(); 4260cc8ae86Sav cv_timedwait(&mc_polling_cv, &mc_polling_lock, 4270cc8ae86Sav ddi_get_lbolt() + mc_timeout_period); 4280cc8ae86Sav } 4290cc8ae86Sav mc_pollthr_running = 0; 4300cc8ae86Sav 4310cc8ae86Sav /* 4320cc8ae86Sav * signal if any one is waiting for this thread to exit. 4330cc8ae86Sav */ 4340cc8ae86Sav cv_signal(&mc_poll_exit_cv); 4350cc8ae86Sav mutex_exit(&mc_polling_lock); 4360cc8ae86Sav thread_exit(); 4370cc8ae86Sav /* NOTREACHED */ 4380cc8ae86Sav } 4390cc8ae86Sav 4400cc8ae86Sav static int 4410cc8ae86Sav mc_poll_init() 4420cc8ae86Sav { 4430cc8ae86Sav mutex_init(&mc_polling_lock, NULL, MUTEX_DRIVER, NULL); 4440cc8ae86Sav cv_init(&mc_polling_cv, NULL, CV_DRIVER, NULL); 4450cc8ae86Sav cv_init(&mc_poll_exit_cv, NULL, CV_DRIVER, NULL); 4460cc8ae86Sav return (0); 4470cc8ae86Sav } 4480cc8ae86Sav 4490cc8ae86Sav static void 4500cc8ae86Sav mc_poll_fini() 4510cc8ae86Sav { 4520cc8ae86Sav mutex_enter(&mc_polling_lock); 4530cc8ae86Sav if (mc_pollthr_running) { 4540cc8ae86Sav mc_poll_cmd = MC_POLL_EXIT; 4550cc8ae86Sav cv_signal(&mc_polling_cv); 4560cc8ae86Sav while (mc_pollthr_running) { 4570cc8ae86Sav cv_wait(&mc_poll_exit_cv, &mc_polling_lock); 4580cc8ae86Sav } 4590cc8ae86Sav } 4600cc8ae86Sav mutex_exit(&mc_polling_lock); 4610cc8ae86Sav mutex_destroy(&mc_polling_lock); 4620cc8ae86Sav cv_destroy(&mc_polling_cv); 4630cc8ae86Sav cv_destroy(&mc_poll_exit_cv); 4640cc8ae86Sav } 4650cc8ae86Sav 46625cf1a30Sjl static int 46725cf1a30Sjl mc_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 46825cf1a30Sjl { 46925cf1a30Sjl mc_opl_t *mcp; 47025cf1a30Sjl int instance; 4710cc8ae86Sav int rv; 47225cf1a30Sjl 47325cf1a30Sjl /* get the instance of this devi */ 47425cf1a30Sjl instance = ddi_get_instance(devi); 47525cf1a30Sjl 47625cf1a30Sjl switch (cmd) { 47725cf1a30Sjl case DDI_ATTACH: 47825cf1a30Sjl break; 47925cf1a30Sjl case DDI_RESUME: 48025cf1a30Sjl mcp = ddi_get_soft_state(mc_statep, instance); 4810cc8ae86Sav rv = mc_resume(mcp, MC_DRIVER_SUSPENDED); 4820cc8ae86Sav return (rv); 48325cf1a30Sjl default: 48425cf1a30Sjl return (DDI_FAILURE); 48525cf1a30Sjl } 48625cf1a30Sjl 48725cf1a30Sjl if (ddi_soft_state_zalloc(mc_statep, instance) != DDI_SUCCESS) 48825cf1a30Sjl return (DDI_FAILURE); 48925cf1a30Sjl 49025cf1a30Sjl if ((mcp = ddi_get_soft_state(mc_statep, instance)) == NULL) { 49125cf1a30Sjl goto bad; 49225cf1a30Sjl } 49325cf1a30Sjl 4940cc8ae86Sav if (mc_timeout_period == 0) { 4950cc8ae86Sav mc_patrol_interval_sec = (int)ddi_getprop(DDI_DEV_T_ANY, devi, 4960cc8ae86Sav DDI_PROP_DONTPASS, "mc-timeout-interval-sec", 4970cc8ae86Sav mc_patrol_interval_sec); 4980cc8ae86Sav mc_timeout_period = drv_usectohz( 4990cc8ae86Sav 1000000 * mc_patrol_interval_sec / OPL_MAX_BOARDS); 5000cc8ae86Sav } 5010cc8ae86Sav 50225cf1a30Sjl /* set informations in mc state */ 50325cf1a30Sjl mcp->mc_dip = devi; 50425cf1a30Sjl 50525cf1a30Sjl if (mc_board_add(mcp)) 50625cf1a30Sjl goto bad; 50725cf1a30Sjl 50825cf1a30Sjl insert_mcp(mcp); 5090cc8ae86Sav 5100cc8ae86Sav /* 5110cc8ae86Sav * Start the polling thread if it is not running already. 5120cc8ae86Sav */ 5130cc8ae86Sav mutex_enter(&mc_polling_lock); 5140cc8ae86Sav if (!mc_pollthr_running) { 5150cc8ae86Sav (void) thread_create(NULL, 0, (void (*)())mc_polling_thread, 5160cc8ae86Sav NULL, 0, &p0, TS_RUN, mc_poll_priority); 5170cc8ae86Sav } 5180cc8ae86Sav mutex_exit(&mc_polling_lock); 51925cf1a30Sjl ddi_report_dev(devi); 52025cf1a30Sjl 52125cf1a30Sjl return (DDI_SUCCESS); 52225cf1a30Sjl 52325cf1a30Sjl bad: 52425cf1a30Sjl ddi_soft_state_free(mc_statep, instance); 52525cf1a30Sjl return (DDI_FAILURE); 52625cf1a30Sjl } 52725cf1a30Sjl 52825cf1a30Sjl /* ARGSUSED */ 52925cf1a30Sjl static int 53025cf1a30Sjl mc_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 53125cf1a30Sjl { 5320cc8ae86Sav int rv; 53325cf1a30Sjl int instance; 53425cf1a30Sjl mc_opl_t *mcp; 53525cf1a30Sjl 53625cf1a30Sjl /* get the instance of this devi */ 53725cf1a30Sjl instance = ddi_get_instance(devi); 53825cf1a30Sjl if ((mcp = ddi_get_soft_state(mc_statep, instance)) == NULL) { 53925cf1a30Sjl return (DDI_FAILURE); 54025cf1a30Sjl } 54125cf1a30Sjl 54225cf1a30Sjl switch (cmd) { 54325cf1a30Sjl case DDI_SUSPEND: 5440cc8ae86Sav rv = mc_suspend(mcp, MC_DRIVER_SUSPENDED); 5450cc8ae86Sav return (rv); 54625cf1a30Sjl case DDI_DETACH: 54725cf1a30Sjl break; 54825cf1a30Sjl default: 54925cf1a30Sjl return (DDI_FAILURE); 55025cf1a30Sjl } 55125cf1a30Sjl 5520cc8ae86Sav delete_mcp(mcp); 55325cf1a30Sjl if (mc_board_del(mcp) != DDI_SUCCESS) { 55425cf1a30Sjl return (DDI_FAILURE); 55525cf1a30Sjl } 55625cf1a30Sjl 55725cf1a30Sjl /* free up the soft state */ 55825cf1a30Sjl ddi_soft_state_free(mc_statep, instance); 55925cf1a30Sjl 56025cf1a30Sjl return (DDI_SUCCESS); 56125cf1a30Sjl } 56225cf1a30Sjl 56325cf1a30Sjl /* ARGSUSED */ 56425cf1a30Sjl static int 56525cf1a30Sjl mc_open(dev_t *devp, int flag, int otyp, cred_t *credp) 56625cf1a30Sjl { 56725cf1a30Sjl return (0); 56825cf1a30Sjl } 56925cf1a30Sjl 57025cf1a30Sjl /* ARGSUSED */ 57125cf1a30Sjl static int 57225cf1a30Sjl mc_close(dev_t devp, int flag, int otyp, cred_t *credp) 57325cf1a30Sjl { 57425cf1a30Sjl return (0); 57525cf1a30Sjl } 57625cf1a30Sjl 57725cf1a30Sjl /* ARGSUSED */ 57825cf1a30Sjl static int 57925cf1a30Sjl mc_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 58025cf1a30Sjl int *rvalp) 58125cf1a30Sjl { 5820cc8ae86Sav #ifdef DEBUG 5830cc8ae86Sav return (mc_ioctl_debug(dev, cmd, arg, mode, credp, rvalp)); 5840cc8ae86Sav #else 58525cf1a30Sjl return (ENXIO); 5860cc8ae86Sav #endif 58725cf1a30Sjl } 58825cf1a30Sjl 58925cf1a30Sjl /* 59025cf1a30Sjl * PA validity check: 59125cf1a30Sjl * This function return 1 if the PA is valid, otherwise 59225cf1a30Sjl * return 0. 59325cf1a30Sjl */ 59425cf1a30Sjl 59525cf1a30Sjl /* ARGSUSED */ 59625cf1a30Sjl static int 59725cf1a30Sjl pa_is_valid(mc_opl_t *mcp, uint64_t addr) 59825cf1a30Sjl { 59925cf1a30Sjl /* 60025cf1a30Sjl * Check if the addr is on the board. 60125cf1a30Sjl */ 60225cf1a30Sjl if ((addr < mcp->mc_start_address) || 60325cf1a30Sjl (mcp->mc_start_address + mcp->mc_size <= addr)) 60425cf1a30Sjl return (0); 60525cf1a30Sjl 60625cf1a30Sjl if (mcp->mlist == NULL) 60725cf1a30Sjl mc_get_mlist(mcp); 60825cf1a30Sjl 60925cf1a30Sjl if (mcp->mlist && address_in_memlist(mcp->mlist, addr, 0)) { 61025cf1a30Sjl return (1); 61125cf1a30Sjl } 61225cf1a30Sjl return (0); 61325cf1a30Sjl } 61425cf1a30Sjl 61525cf1a30Sjl /* 61625cf1a30Sjl * mac-pa translation routines. 61725cf1a30Sjl * 61825cf1a30Sjl * Input: mc driver state, (LSB#, Bank#, DIMM address) 61925cf1a30Sjl * Output: physical address 62025cf1a30Sjl * 62125cf1a30Sjl * Valid - return value: 0 62225cf1a30Sjl * Invalid - return value: -1 62325cf1a30Sjl */ 62425cf1a30Sjl static int 62525cf1a30Sjl mcaddr_to_pa(mc_opl_t *mcp, mc_addr_t *maddr, uint64_t *pa) 62625cf1a30Sjl { 62725cf1a30Sjl int i; 62825cf1a30Sjl uint64_t pa_offset = 0; 62925cf1a30Sjl int cs = (maddr->ma_dimm_addr >> CS_SHIFT) & 1; 63025cf1a30Sjl int bank = maddr->ma_bank; 63125cf1a30Sjl mc_addr_t maddr1; 63225cf1a30Sjl int bank0, bank1; 63325cf1a30Sjl 63425cf1a30Sjl MC_LOG("mcaddr /LSB%d/B%d/%x\n", maddr->ma_bd, bank, 63525cf1a30Sjl maddr->ma_dimm_addr); 63625cf1a30Sjl 63725cf1a30Sjl /* loc validity check */ 63825cf1a30Sjl ASSERT(maddr->ma_bd >= 0 && OPL_BOARD_MAX > maddr->ma_bd); 63925cf1a30Sjl ASSERT(bank >= 0 && OPL_BANK_MAX > bank); 64025cf1a30Sjl 64125cf1a30Sjl /* Do translation */ 64225cf1a30Sjl for (i = 0; i < PA_BITS_FOR_MAC; i++) { 64325cf1a30Sjl int pa_bit = 0; 64425cf1a30Sjl int mc_bit = mcp->mc_trans_table[cs][i]; 64525cf1a30Sjl if (mc_bit < MC_ADDRESS_BITS) { 64625cf1a30Sjl pa_bit = (maddr->ma_dimm_addr >> mc_bit) & 1; 64725cf1a30Sjl } else if (mc_bit == MP_NONE) { 64825cf1a30Sjl pa_bit = 0; 64925cf1a30Sjl } else if (mc_bit == MP_BANK_0) { 65025cf1a30Sjl pa_bit = bank & 1; 65125cf1a30Sjl } else if (mc_bit == MP_BANK_1) { 65225cf1a30Sjl pa_bit = (bank >> 1) & 1; 65325cf1a30Sjl } else if (mc_bit == MP_BANK_2) { 65425cf1a30Sjl pa_bit = (bank >> 2) & 1; 65525cf1a30Sjl } 65625cf1a30Sjl pa_offset |= ((uint64_t)pa_bit) << i; 65725cf1a30Sjl } 65825cf1a30Sjl *pa = mcp->mc_start_address + pa_offset; 65925cf1a30Sjl MC_LOG("pa = %lx\n", *pa); 66025cf1a30Sjl 66125cf1a30Sjl if (pa_to_maddr(mcp, *pa, &maddr1) == -1) { 6620cc8ae86Sav cmn_err(CE_WARN, "mcaddr_to_pa: /LSB%d/B%d/%x failed to " 6630cc8ae86Sav "convert PA %lx\n", maddr->ma_bd, bank, 6640cc8ae86Sav maddr->ma_dimm_addr, *pa); 66525cf1a30Sjl return (-1); 66625cf1a30Sjl } 66725cf1a30Sjl 6680cc8ae86Sav /* 6690cc8ae86Sav * In mirror mode, PA is always translated to the even bank. 6700cc8ae86Sav */ 67125cf1a30Sjl if (IS_MIRROR(mcp, maddr->ma_bank)) { 67225cf1a30Sjl bank0 = maddr->ma_bank & ~(1); 67325cf1a30Sjl bank1 = maddr1.ma_bank & ~(1); 67425cf1a30Sjl } else { 67525cf1a30Sjl bank0 = maddr->ma_bank; 67625cf1a30Sjl bank1 = maddr1.ma_bank; 67725cf1a30Sjl } 67825cf1a30Sjl /* 67925cf1a30Sjl * there is no need to check ma_bd because it is generated from 68025cf1a30Sjl * mcp. They are the same. 68125cf1a30Sjl */ 68225cf1a30Sjl if ((bank0 == bank1) && 68325cf1a30Sjl (maddr->ma_dimm_addr == maddr1.ma_dimm_addr)) { 68425cf1a30Sjl return (0); 68525cf1a30Sjl } else { 68625cf1a30Sjl cmn_err(CE_WARN, "Translation error source /LSB%d/B%d/%x, " 68725cf1a30Sjl "PA %lx, target /LSB%d/B%d/%x\n", 68825cf1a30Sjl maddr->ma_bd, bank, maddr->ma_dimm_addr, 68925cf1a30Sjl *pa, maddr1.ma_bd, maddr1.ma_bank, 69025cf1a30Sjl maddr1.ma_dimm_addr); 69125cf1a30Sjl return (-1); 69225cf1a30Sjl } 69325cf1a30Sjl } 69425cf1a30Sjl 69525cf1a30Sjl /* 69625cf1a30Sjl * PA to CS (used by pa_to_maddr). 69725cf1a30Sjl */ 69825cf1a30Sjl static int 69925cf1a30Sjl pa_to_cs(mc_opl_t *mcp, uint64_t pa_offset) 70025cf1a30Sjl { 70125cf1a30Sjl int i; 70225cf1a30Sjl int cs = 0; 70325cf1a30Sjl 70425cf1a30Sjl for (i = 0; i < PA_BITS_FOR_MAC; i++) { 70525cf1a30Sjl /* MAC address bit<29> is arranged on the same PA bit */ 70625cf1a30Sjl /* on both table. So we may use any table. */ 70725cf1a30Sjl if (mcp->mc_trans_table[0][i] == CS_SHIFT) { 70825cf1a30Sjl cs = (pa_offset >> i) & 1; 70925cf1a30Sjl break; 71025cf1a30Sjl } 71125cf1a30Sjl } 71225cf1a30Sjl return (cs); 71325cf1a30Sjl } 71425cf1a30Sjl 71525cf1a30Sjl /* 71625cf1a30Sjl * PA to DIMM (used by pa_to_maddr). 71725cf1a30Sjl */ 71825cf1a30Sjl /* ARGSUSED */ 71925cf1a30Sjl static uint32_t 72025cf1a30Sjl pa_to_dimm(mc_opl_t *mcp, uint64_t pa_offset) 72125cf1a30Sjl { 72225cf1a30Sjl int i; 72325cf1a30Sjl int cs = pa_to_cs(mcp, pa_offset); 72425cf1a30Sjl uint32_t dimm_addr = 0; 72525cf1a30Sjl 72625cf1a30Sjl for (i = 0; i < PA_BITS_FOR_MAC; i++) { 72725cf1a30Sjl int pa_bit_value = (pa_offset >> i) & 1; 72825cf1a30Sjl int mc_bit = mcp->mc_trans_table[cs][i]; 72925cf1a30Sjl if (mc_bit < MC_ADDRESS_BITS) { 73025cf1a30Sjl dimm_addr |= pa_bit_value << mc_bit; 73125cf1a30Sjl } 73225cf1a30Sjl } 73325cf1a30Sjl return (dimm_addr); 73425cf1a30Sjl } 73525cf1a30Sjl 73625cf1a30Sjl /* 73725cf1a30Sjl * PA to Bank (used by pa_to_maddr). 73825cf1a30Sjl */ 73925cf1a30Sjl static int 74025cf1a30Sjl pa_to_bank(mc_opl_t *mcp, uint64_t pa_offset) 74125cf1a30Sjl { 74225cf1a30Sjl int i; 74325cf1a30Sjl int cs = pa_to_cs(mcp, pa_offset); 74425cf1a30Sjl int bankno = mcp->mc_trans_table[cs][INDEX_OF_BANK_SUPPLEMENT_BIT]; 74525cf1a30Sjl 74625cf1a30Sjl 74725cf1a30Sjl for (i = 0; i < PA_BITS_FOR_MAC; i++) { 74825cf1a30Sjl int pa_bit_value = (pa_offset >> i) & 1; 74925cf1a30Sjl int mc_bit = mcp->mc_trans_table[cs][i]; 75025cf1a30Sjl switch (mc_bit) { 75125cf1a30Sjl case MP_BANK_0: 75225cf1a30Sjl bankno |= pa_bit_value; 75325cf1a30Sjl break; 75425cf1a30Sjl case MP_BANK_1: 75525cf1a30Sjl bankno |= pa_bit_value << 1; 75625cf1a30Sjl break; 75725cf1a30Sjl case MP_BANK_2: 75825cf1a30Sjl bankno |= pa_bit_value << 2; 75925cf1a30Sjl break; 76025cf1a30Sjl } 76125cf1a30Sjl } 76225cf1a30Sjl 76325cf1a30Sjl return (bankno); 76425cf1a30Sjl } 76525cf1a30Sjl 76625cf1a30Sjl /* 76725cf1a30Sjl * PA to MAC address translation 76825cf1a30Sjl * 76925cf1a30Sjl * Input: MAC driver state, physicall adress 77025cf1a30Sjl * Output: LSB#, Bank id, mac address 77125cf1a30Sjl * 77225cf1a30Sjl * Valid - return value: 0 77325cf1a30Sjl * Invalid - return value: -1 77425cf1a30Sjl */ 77525cf1a30Sjl 77625cf1a30Sjl int 77725cf1a30Sjl pa_to_maddr(mc_opl_t *mcp, uint64_t pa, mc_addr_t *maddr) 77825cf1a30Sjl { 77925cf1a30Sjl uint64_t pa_offset; 78025cf1a30Sjl 78125cf1a30Sjl /* PA validity check */ 78225cf1a30Sjl if (!pa_is_valid(mcp, pa)) 78325cf1a30Sjl return (-1); 78425cf1a30Sjl 78525cf1a30Sjl 78625cf1a30Sjl /* Do translation */ 78725cf1a30Sjl pa_offset = pa - mcp->mc_start_address; 78825cf1a30Sjl 78925cf1a30Sjl maddr->ma_bd = mcp->mc_board_num; 79025cf1a30Sjl maddr->ma_bank = pa_to_bank(mcp, pa_offset); 79125cf1a30Sjl maddr->ma_dimm_addr = pa_to_dimm(mcp, pa_offset); 79225cf1a30Sjl MC_LOG("pa %lx -> mcaddr /LSB%d/B%d/%x\n", 79325cf1a30Sjl pa_offset, maddr->ma_bd, maddr->ma_bank, maddr->ma_dimm_addr); 79425cf1a30Sjl return (0); 79525cf1a30Sjl } 79625cf1a30Sjl 7970cc8ae86Sav /* 7980cc8ae86Sav * UNUM format for DC is "/CMUnn/MEMxyZ", where 7990cc8ae86Sav * nn = 00..03 for DC1 and 00..07 for DC2 and 00..15 for DC3. 8000cc8ae86Sav * x = MAC 0..3 8010cc8ae86Sav * y = 0..3 (slot info). 8020cc8ae86Sav * Z = 'A' or 'B' 8030cc8ae86Sav * 8040cc8ae86Sav * UNUM format for FF1 is "/MBU_A/MEMBx/MEMyZ", where 8050cc8ae86Sav * x = 0..3 (MEMB number) 8060cc8ae86Sav * y = 0..3 (slot info). 8070cc8ae86Sav * Z = 'A' or 'B' 8080cc8ae86Sav * 8090cc8ae86Sav * UNUM format for FF2 is "/MBU_B/MEMBx/MEMyZ" 8100cc8ae86Sav * x = 0..7 (MEMB number) 8110cc8ae86Sav * y = 0..3 (slot info). 8120cc8ae86Sav * Z = 'A' or 'B' 8130cc8ae86Sav */ 8140cc8ae86Sav int 8150cc8ae86Sav mc_set_mem_unum(char *buf, int buflen, int lsb, int bank, 8160cc8ae86Sav uint32_t mf_type, uint32_t d_slot) 8170cc8ae86Sav { 8180cc8ae86Sav char *dimmnm; 8190cc8ae86Sav char memb_num; 8200cc8ae86Sav int sb; 8210cc8ae86Sav int i; 8220cc8ae86Sav 8230cc8ae86Sav if ((sb = mc_opl_get_physical_board(lsb)) < 0) 8240cc8ae86Sav return (ENODEV); 8250cc8ae86Sav 8260cc8ae86Sav if (plat_model == MODEL_DC) { 8270cc8ae86Sav if (mf_type == FLT_TYPE_PERMANENT_CE) { 8280cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(0, bank, d_slot); 8290cc8ae86Sav dimmnm = mc_dc_dimm_unum_table[i]; 8300cc8ae86Sav snprintf(buf, buflen, "/%s%02d/MEM%s", 8310cc8ae86Sav model_names[plat_model].unit_name, sb, dimmnm); 8320cc8ae86Sav } else { 8330cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(0, bank, 0); 8340cc8ae86Sav snprintf(buf, buflen, "/%s%02d/MEM%s MEM%s MEM%s MEM%s", 8350cc8ae86Sav model_names[plat_model].unit_name, sb, 8360cc8ae86Sav mc_dc_dimm_unum_table[i], 8370cc8ae86Sav mc_dc_dimm_unum_table[i + 1], 8380cc8ae86Sav mc_dc_dimm_unum_table[i + 2], 8390cc8ae86Sav mc_dc_dimm_unum_table[i + 3]); 8400cc8ae86Sav } 8410cc8ae86Sav } else { 8420cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot); 8430cc8ae86Sav if (mf_type == FLT_TYPE_PERMANENT_CE) { 8440cc8ae86Sav dimmnm = mc_ff_dimm_unum_table[i]; 8450cc8ae86Sav memb_num = dimmnm[0]; 8460cc8ae86Sav snprintf(buf, buflen, "/%s/%s%c/MEM%s", 8470cc8ae86Sav model_names[plat_model].unit_name, 8480cc8ae86Sav model_names[plat_model].mem_name, 8490cc8ae86Sav memb_num, &dimmnm[1]); 8500cc8ae86Sav } else { 8510cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(sb, bank, 0); 8520cc8ae86Sav memb_num = mc_ff_dimm_unum_table[i][0], 8530cc8ae86Sav snprintf(buf, buflen, 8540cc8ae86Sav "/%s/%s%c/MEM%s MEM%s MEM%s MEM%s", 8550cc8ae86Sav model_names[plat_model].unit_name, 8560cc8ae86Sav model_names[plat_model].mem_name, memb_num, 8570cc8ae86Sav &mc_ff_dimm_unum_table[i][1], 8580cc8ae86Sav &mc_ff_dimm_unum_table[i + 1][1], 8590cc8ae86Sav &mc_ff_dimm_unum_table[i + 2][1], 8600cc8ae86Sav &mc_ff_dimm_unum_table[i + 3][1]); 8610cc8ae86Sav } 8620cc8ae86Sav } 8630cc8ae86Sav return (0); 8640cc8ae86Sav } 8650cc8ae86Sav 86625cf1a30Sjl static void 86725cf1a30Sjl mc_ereport_post(mc_aflt_t *mc_aflt) 86825cf1a30Sjl { 86925cf1a30Sjl char buf[FM_MAX_CLASS]; 87025cf1a30Sjl char device_path[MAXPATHLEN]; 8710cc8ae86Sav char sid[MAXPATHLEN]; 87225cf1a30Sjl nv_alloc_t *nva = NULL; 87325cf1a30Sjl nvlist_t *ereport, *detector, *resource; 87425cf1a30Sjl errorq_elem_t *eqep; 87525cf1a30Sjl int nflts; 87625cf1a30Sjl mc_flt_stat_t *flt_stat; 8770cc8ae86Sav int i, n; 8780cc8ae86Sav int blen = MAXPATHLEN; 8790cc8ae86Sav char *p, *s = NULL; 88025cf1a30Sjl uint32_t values[2], synd[2], dslot[2]; 8810cc8ae86Sav uint64_t offset = (uint64_t)-1; 8820cc8ae86Sav int ret = -1; 88325cf1a30Sjl 88425cf1a30Sjl if (panicstr) { 88525cf1a30Sjl eqep = errorq_reserve(ereport_errorq); 88625cf1a30Sjl if (eqep == NULL) 88725cf1a30Sjl return; 88825cf1a30Sjl ereport = errorq_elem_nvl(ereport_errorq, eqep); 88925cf1a30Sjl nva = errorq_elem_nva(ereport_errorq, eqep); 89025cf1a30Sjl } else { 89125cf1a30Sjl ereport = fm_nvlist_create(nva); 89225cf1a30Sjl } 89325cf1a30Sjl 89425cf1a30Sjl /* 89525cf1a30Sjl * Create the scheme "dev" FMRI. 89625cf1a30Sjl */ 89725cf1a30Sjl detector = fm_nvlist_create(nva); 89825cf1a30Sjl resource = fm_nvlist_create(nva); 89925cf1a30Sjl 90025cf1a30Sjl nflts = mc_aflt->mflt_nflts; 90125cf1a30Sjl 90225cf1a30Sjl ASSERT(nflts >= 1 && nflts <= 2); 90325cf1a30Sjl 90425cf1a30Sjl flt_stat = mc_aflt->mflt_stat[0]; 90525cf1a30Sjl (void) ddi_pathname(mc_aflt->mflt_mcp->mc_dip, device_path); 90625cf1a30Sjl (void) fm_fmri_dev_set(detector, FM_DEV_SCHEME_VERSION, NULL, 90725cf1a30Sjl device_path, NULL); 90825cf1a30Sjl 90925cf1a30Sjl /* 91025cf1a30Sjl * Encode all the common data into the ereport. 91125cf1a30Sjl */ 91225cf1a30Sjl (void) snprintf(buf, FM_MAX_CLASS, "%s.%s-%s", 91325cf1a30Sjl MC_OPL_ERROR_CLASS, 91425cf1a30Sjl mc_aflt->mflt_is_ptrl ? MC_OPL_PTRL_SUBCLASS : 91525cf1a30Sjl MC_OPL_MI_SUBCLASS, 91625cf1a30Sjl mc_aflt->mflt_erpt_class); 91725cf1a30Sjl 91825cf1a30Sjl MC_LOG("mc_ereport_post: ereport %s\n", buf); 91925cf1a30Sjl 92025cf1a30Sjl 92125cf1a30Sjl fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, 92225cf1a30Sjl fm_ena_generate(mc_aflt->mflt_id, FM_ENA_FMT1), 92325cf1a30Sjl detector, NULL); 92425cf1a30Sjl 92525cf1a30Sjl /* 92625cf1a30Sjl * Set payload. 92725cf1a30Sjl */ 92825cf1a30Sjl fm_payload_set(ereport, MC_OPL_BOARD, DATA_TYPE_UINT32, 92925cf1a30Sjl flt_stat->mf_flt_maddr.ma_bd, NULL); 93025cf1a30Sjl 93125cf1a30Sjl fm_payload_set(ereport, MC_OPL_PA, DATA_TYPE_UINT64, 93225cf1a30Sjl flt_stat->mf_flt_paddr, NULL); 93325cf1a30Sjl 93425cf1a30Sjl if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) { 93525cf1a30Sjl fm_payload_set(ereport, MC_OPL_FLT_TYPE, 93625cf1a30Sjl DATA_TYPE_UINT8, ECC_STICKY, NULL); 93725cf1a30Sjl } 93825cf1a30Sjl 93925cf1a30Sjl for (i = 0; i < nflts; i++) 94025cf1a30Sjl values[i] = mc_aflt->mflt_stat[i]->mf_flt_maddr.ma_bank; 94125cf1a30Sjl 94225cf1a30Sjl fm_payload_set(ereport, MC_OPL_BANK, DATA_TYPE_UINT32_ARRAY, 94325cf1a30Sjl nflts, values, NULL); 94425cf1a30Sjl 94525cf1a30Sjl for (i = 0; i < nflts; i++) 94625cf1a30Sjl values[i] = mc_aflt->mflt_stat[i]->mf_cntl; 94725cf1a30Sjl 94825cf1a30Sjl fm_payload_set(ereport, MC_OPL_STATUS, DATA_TYPE_UINT32_ARRAY, 94925cf1a30Sjl nflts, values, NULL); 95025cf1a30Sjl 95125cf1a30Sjl for (i = 0; i < nflts; i++) 95225cf1a30Sjl values[i] = mc_aflt->mflt_stat[i]->mf_err_add; 95325cf1a30Sjl 9540cc8ae86Sav /* offset is set only for PCE */ 9550cc8ae86Sav if (mc_aflt->mflt_stat[0]->mf_type == FLT_TYPE_PERMANENT_CE) { 9560cc8ae86Sav offset = values[0]; 9570cc8ae86Sav 9580cc8ae86Sav } 95925cf1a30Sjl fm_payload_set(ereport, MC_OPL_ERR_ADD, DATA_TYPE_UINT32_ARRAY, 96025cf1a30Sjl nflts, values, NULL); 96125cf1a30Sjl 96225cf1a30Sjl for (i = 0; i < nflts; i++) 96325cf1a30Sjl values[i] = mc_aflt->mflt_stat[i]->mf_err_log; 96425cf1a30Sjl 96525cf1a30Sjl fm_payload_set(ereport, MC_OPL_ERR_LOG, DATA_TYPE_UINT32_ARRAY, 96625cf1a30Sjl nflts, values, NULL); 96725cf1a30Sjl 96825cf1a30Sjl for (i = 0; i < nflts; i++) { 96925cf1a30Sjl flt_stat = mc_aflt->mflt_stat[i]; 97025cf1a30Sjl if (flt_stat->mf_errlog_valid) { 97125cf1a30Sjl synd[i] = flt_stat->mf_synd; 97225cf1a30Sjl dslot[i] = flt_stat->mf_dimm_slot; 97325cf1a30Sjl values[i] = flt_stat->mf_dram_place; 97425cf1a30Sjl } else { 97525cf1a30Sjl synd[i] = 0; 97625cf1a30Sjl dslot[i] = 0; 97725cf1a30Sjl values[i] = 0; 97825cf1a30Sjl } 97925cf1a30Sjl } 98025cf1a30Sjl 98125cf1a30Sjl fm_payload_set(ereport, MC_OPL_ERR_SYND, 98225cf1a30Sjl DATA_TYPE_UINT32_ARRAY, nflts, synd, NULL); 98325cf1a30Sjl 98425cf1a30Sjl fm_payload_set(ereport, MC_OPL_ERR_DIMMSLOT, 98525cf1a30Sjl DATA_TYPE_UINT32_ARRAY, nflts, dslot, NULL); 98625cf1a30Sjl 98725cf1a30Sjl fm_payload_set(ereport, MC_OPL_ERR_DRAM, 98825cf1a30Sjl DATA_TYPE_UINT32_ARRAY, nflts, values, NULL); 98925cf1a30Sjl 99025cf1a30Sjl device_path[0] = 0; 99125cf1a30Sjl p = &device_path[0]; 9920cc8ae86Sav sid[0] = 0; 9930cc8ae86Sav s = &sid[0]; 9940cc8ae86Sav ret = 0; 99525cf1a30Sjl 99625cf1a30Sjl for (i = 0; i < nflts; i++) { 9970cc8ae86Sav int bank; 99825cf1a30Sjl 99925cf1a30Sjl flt_stat = mc_aflt->mflt_stat[i]; 10000cc8ae86Sav bank = flt_stat->mf_flt_maddr.ma_bank; 10010cc8ae86Sav ret = mc_set_mem_unum(p + strlen(p), blen, 10020cc8ae86Sav flt_stat->mf_flt_maddr.ma_bd, bank, flt_stat->mf_type, 10030cc8ae86Sav flt_stat->mf_dimm_slot); 10040cc8ae86Sav 10050cc8ae86Sav if (ret != 0) { 10060cc8ae86Sav cmn_err(CE_WARN, 10070cc8ae86Sav "mc_ereport_post: Failed to determine the unum " 10080cc8ae86Sav "for board=%d bank=%d type=0x%x slot=0x%x", 10090cc8ae86Sav flt_stat->mf_flt_maddr.ma_bd, bank, 10100cc8ae86Sav flt_stat->mf_type, flt_stat->mf_dimm_slot); 10110cc8ae86Sav continue; 101225cf1a30Sjl } 10130cc8ae86Sav n = strlen(device_path); 101425cf1a30Sjl blen = MAXPATHLEN - n; 101525cf1a30Sjl p = &device_path[n]; 101625cf1a30Sjl if (i < (nflts - 1)) { 101725cf1a30Sjl snprintf(p, blen, " "); 10180cc8ae86Sav blen--; 10190cc8ae86Sav p++; 10200cc8ae86Sav } 10210cc8ae86Sav 10220cc8ae86Sav if (ret == 0) { 10230cc8ae86Sav ret = mc_set_mem_sid(mc_aflt->mflt_mcp, s + strlen(s), 10240cc8ae86Sav blen, flt_stat->mf_flt_maddr.ma_bd, bank, 10250cc8ae86Sav flt_stat->mf_type, flt_stat->mf_dimm_slot); 10260cc8ae86Sav 102725cf1a30Sjl } 102825cf1a30Sjl } 102925cf1a30Sjl 103025cf1a30Sjl (void) fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, 10310cc8ae86Sav NULL, device_path, (ret == 0) ? sid : NULL, 10320cc8ae86Sav (ret == 0) ? offset : (uint64_t)-1); 103325cf1a30Sjl 103425cf1a30Sjl fm_payload_set(ereport, MC_OPL_RESOURCE, DATA_TYPE_NVLIST, 103525cf1a30Sjl resource, NULL); 103625cf1a30Sjl 103725cf1a30Sjl if (panicstr) { 103825cf1a30Sjl errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC); 103925cf1a30Sjl } else { 104025cf1a30Sjl (void) fm_ereport_post(ereport, EVCH_TRYHARD); 104125cf1a30Sjl fm_nvlist_destroy(ereport, FM_NVA_FREE); 104225cf1a30Sjl fm_nvlist_destroy(detector, FM_NVA_FREE); 104325cf1a30Sjl fm_nvlist_destroy(resource, FM_NVA_FREE); 104425cf1a30Sjl } 104525cf1a30Sjl } 104625cf1a30Sjl 10470cc8ae86Sav 104825cf1a30Sjl static void 104925cf1a30Sjl mc_err_drain(mc_aflt_t *mc_aflt) 105025cf1a30Sjl { 105125cf1a30Sjl int rv; 105225cf1a30Sjl uint64_t pa = (uint64_t)(-1); 10530cc8ae86Sav int i; 105425cf1a30Sjl 105525cf1a30Sjl MC_LOG("mc_err_drain: %s\n", 105625cf1a30Sjl mc_aflt->mflt_erpt_class); 105725cf1a30Sjl /* 105825cf1a30Sjl * we come here only when we have: 105925cf1a30Sjl * In mirror mode: CMPE, MUE, SUE 106025cf1a30Sjl * In normal mode: UE, Permanent CE 106125cf1a30Sjl */ 10620cc8ae86Sav for (i = 0; i < mc_aflt->mflt_nflts; i++) { 10630cc8ae86Sav rv = mcaddr_to_pa(mc_aflt->mflt_mcp, 10640cc8ae86Sav &(mc_aflt->mflt_stat[i]->mf_flt_maddr), &pa); 10650cc8ae86Sav if (rv == 0) 10660cc8ae86Sav mc_aflt->mflt_stat[i]->mf_flt_paddr = pa; 10670cc8ae86Sav else 10680cc8ae86Sav mc_aflt->mflt_stat[i]->mf_flt_paddr = (uint64_t)-1; 10690cc8ae86Sav } 10700cc8ae86Sav 10710cc8ae86Sav if (mc_aflt->mflt_stat[0]->mf_type != FLT_TYPE_PERMANENT_CE) { 1072cfb9e062Shyw uint64_t errors = 0; 1073cfb9e062Shyw 107425cf1a30Sjl MC_LOG("mc_err_drain:pa = %lx\n", pa); 107525cf1a30Sjl 1076cfb9e062Shyw if (page_retire_check(pa, &errors) == 0) { 1077cfb9e062Shyw MC_LOG("Page retired\n"); 1078cfb9e062Shyw return; 1079cfb9e062Shyw } 1080cfb9e062Shyw if ((errors & mc_aflt->mflt_pr) == mc_aflt->mflt_pr) { 1081cfb9e062Shyw MC_LOG("errors %lx, mflt_pr %x\n", 1082cfb9e062Shyw errors, mc_aflt->mflt_pr); 1083cfb9e062Shyw return; 108425cf1a30Sjl } 1085cfb9e062Shyw MC_LOG("offline page at pa %lx error %x\n", pa, 1086cfb9e062Shyw mc_aflt->mflt_pr); 1087cfb9e062Shyw (void) page_retire(pa, mc_aflt->mflt_pr); 108825cf1a30Sjl } 108925cf1a30Sjl 10900cc8ae86Sav for (i = 0; i < mc_aflt->mflt_nflts; i++) { 10910cc8ae86Sav mc_aflt_t mc_aflt0; 10920cc8ae86Sav if (mc_aflt->mflt_stat[i]->mf_flt_paddr != (uint64_t)-1) { 10930cc8ae86Sav mc_aflt0 = *mc_aflt; 10940cc8ae86Sav mc_aflt0.mflt_nflts = 1; 10950cc8ae86Sav mc_aflt0.mflt_stat[0] = mc_aflt->mflt_stat[i]; 10960cc8ae86Sav mc_ereport_post(&mc_aflt0); 10970cc8ae86Sav } 10980cc8ae86Sav } 10990cc8ae86Sav } 110025cf1a30Sjl 110125cf1a30Sjl /* 110225cf1a30Sjl * The restart address is actually defined in unit of PA[37:6] 110325cf1a30Sjl * the mac patrol will convert that to dimm offset. If the 110425cf1a30Sjl * address is not in the bank, it will continue to search for 110525cf1a30Sjl * the next PA that is within the bank. 110625cf1a30Sjl * 110725cf1a30Sjl * Also the mac patrol scans the dimms based on PA, not 110825cf1a30Sjl * dimm offset. 110925cf1a30Sjl */ 111025cf1a30Sjl static int 111125cf1a30Sjl restart_patrol(mc_opl_t *mcp, int bank, mc_addr_info_t *maddr_info) 111225cf1a30Sjl { 111325cf1a30Sjl uint64_t pa; 111425cf1a30Sjl int rv; 111525cf1a30Sjl int loop_count = 0; 111625cf1a30Sjl 111725cf1a30Sjl if (maddr_info == NULL || (maddr_info->mi_valid == 0)) { 111825cf1a30Sjl MAC_PTRL_START(mcp, bank); 111925cf1a30Sjl return (0); 112025cf1a30Sjl } 112125cf1a30Sjl 112225cf1a30Sjl rv = mcaddr_to_pa(mcp, &maddr_info->mi_maddr, &pa); 112325cf1a30Sjl if (rv != 0) { 112425cf1a30Sjl MC_LOG("cannot convert mcaddr to pa. use auto restart\n"); 112525cf1a30Sjl MAC_PTRL_START(mcp, bank); 112625cf1a30Sjl return (0); 112725cf1a30Sjl } 112825cf1a30Sjl 112925cf1a30Sjl /* 113025cf1a30Sjl * pa is the last address scanned by the mac patrol 113125cf1a30Sjl * we calculate the next restart address as follows: 113225cf1a30Sjl * first we always advance it by 64 byte. Then begin the loop. 113325cf1a30Sjl * loop { 113425cf1a30Sjl * if it is not in phys_install, we advance to next 64 MB boundary 113525cf1a30Sjl * if it is not backed by a page structure, done 113625cf1a30Sjl * if the page is bad, advance to the next page boundary. 113725cf1a30Sjl * else done 113825cf1a30Sjl * if the new address exceeds the board, wrap around. 113925cf1a30Sjl * } <stop if we come back to the same page> 114025cf1a30Sjl */ 114125cf1a30Sjl 114225cf1a30Sjl if (pa < mcp->mc_start_address || pa >= (mcp->mc_start_address 114325cf1a30Sjl + mcp->mc_size)) { 114425cf1a30Sjl /* pa is not on this board, just retry */ 114525cf1a30Sjl cmn_err(CE_WARN, "restart_patrol: invalid address %lx " 114625cf1a30Sjl "on board %d\n", pa, mcp->mc_board_num); 114725cf1a30Sjl MAC_PTRL_START(mcp, bank); 114825cf1a30Sjl return (0); 114925cf1a30Sjl } 115025cf1a30Sjl 115125cf1a30Sjl MC_LOG("restart_patrol: pa = %lx\n", pa); 115225cf1a30Sjl if (maddr_info->mi_advance) { 115325cf1a30Sjl uint64_t new_pa; 115425cf1a30Sjl 115525cf1a30Sjl if (IS_MIRROR(mcp, bank)) 115625cf1a30Sjl new_pa = pa + 64 * 2; 115725cf1a30Sjl else 115825cf1a30Sjl new_pa = pa + 64; 115925cf1a30Sjl 116025cf1a30Sjl if (!mc_valid_pa(mcp, new_pa)) { 116125cf1a30Sjl MC_LOG("Invalid PA\n"); 11620cc8ae86Sav pa = roundup(new_pa + 1, mc_isolation_bsize); 116325cf1a30Sjl } else { 1164cfb9e062Shyw uint64_t errors = 0; 1165cfb9e062Shyw if (page_retire_check(new_pa, &errors) && 1166cfb9e062Shyw (errors == 0)) { 1167cfb9e062Shyw MC_LOG("Page has no error\n"); 11680cc8ae86Sav pa = new_pa; 11690cc8ae86Sav goto done; 117025cf1a30Sjl } 1171cfb9e062Shyw /* 1172cfb9e062Shyw * skip bad pages 1173cfb9e062Shyw * and let the following loop to take care 1174cfb9e062Shyw */ 1175cfb9e062Shyw pa = roundup(new_pa + 1, PAGESIZE); 1176cfb9e062Shyw MC_LOG("Skipping bad page to %lx\n", pa); 117725cf1a30Sjl } 117825cf1a30Sjl } 117925cf1a30Sjl 118025cf1a30Sjl /* 118125cf1a30Sjl * if we wrap around twice, we just give up and let 118225cf1a30Sjl * mac patrol decide. 118325cf1a30Sjl */ 118425cf1a30Sjl MC_LOG("pa is now %lx\n", pa); 118525cf1a30Sjl while (loop_count <= 1) { 118625cf1a30Sjl if (!mc_valid_pa(mcp, pa)) { 118725cf1a30Sjl MC_LOG("pa is not valid. round up to 64 MB\n"); 118825cf1a30Sjl pa = roundup(pa + 1, 64 * 1024 * 1024); 118925cf1a30Sjl } else { 1190cfb9e062Shyw uint64_t errors = 0; 1191cfb9e062Shyw if (page_retire_check(pa, &errors) && 1192cfb9e062Shyw (errors == 0)) { 1193cfb9e062Shyw MC_LOG("Page has no error\n"); 119425cf1a30Sjl break; 119525cf1a30Sjl } 1196cfb9e062Shyw /* skip bad pages */ 1197cfb9e062Shyw pa = roundup(pa + 1, PAGESIZE); 1198cfb9e062Shyw MC_LOG("Skipping bad page to %lx\n", pa); 119925cf1a30Sjl } 120025cf1a30Sjl if (pa >= (mcp->mc_start_address + mcp->mc_size)) { 120125cf1a30Sjl MC_LOG("Wrap around\n"); 120225cf1a30Sjl pa = mcp->mc_start_address; 120325cf1a30Sjl loop_count++; 120425cf1a30Sjl } 120525cf1a30Sjl } 120625cf1a30Sjl 12070cc8ae86Sav done: 120825cf1a30Sjl /* retstart MAC patrol: PA[37:6] */ 120925cf1a30Sjl MC_LOG("restart at pa = %lx\n", pa); 121025cf1a30Sjl ST_MAC_REG(MAC_RESTART_ADD(mcp, bank), MAC_RESTART_PA(pa)); 121125cf1a30Sjl MAC_PTRL_START_ADD(mcp, bank); 121225cf1a30Sjl 121325cf1a30Sjl return (0); 121425cf1a30Sjl } 121525cf1a30Sjl 121625cf1a30Sjl /* 121725cf1a30Sjl * Rewriting is used for two purposes. 121825cf1a30Sjl * - to correct the error in memory. 121925cf1a30Sjl * - to determine whether the error is permanent or intermittent. 122025cf1a30Sjl * It's done by writing the address in MAC_BANKm_REWRITE_ADD 122125cf1a30Sjl * and issuing REW_REQ command in MAC_BANKm_PTRL_CNRL. After that, 122225cf1a30Sjl * REW_END (and REW_CE/REW_UE if some error detected) is set when 122325cf1a30Sjl * rewrite operation is done. See 4.7.3 and 4.7.11 in Columbus2 PRM. 122425cf1a30Sjl * 122525cf1a30Sjl * Note that rewrite operation doesn't change RAW_UE to Marked UE. 122625cf1a30Sjl * Therefore, we use it only CE case. 122725cf1a30Sjl */ 122825cf1a30Sjl static uint32_t 122925cf1a30Sjl do_rewrite(mc_opl_t *mcp, int bank, uint32_t dimm_addr) 123025cf1a30Sjl { 123125cf1a30Sjl uint32_t cntl; 123225cf1a30Sjl int count = 0; 123325cf1a30Sjl 123425cf1a30Sjl /* first wait to make sure PTRL_STATUS is 0 */ 12350cc8ae86Sav while (count++ < mc_max_rewrite_loop) { 123625cf1a30Sjl cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 123725cf1a30Sjl if (!(cntl & MAC_CNTL_PTRL_STATUS)) 123825cf1a30Sjl break; 12390cc8ae86Sav drv_usecwait(mc_rewrite_delay); 124025cf1a30Sjl } 12410cc8ae86Sav if (count >= mc_max_rewrite_loop) 124225cf1a30Sjl goto bad; 124325cf1a30Sjl 124425cf1a30Sjl count = 0; 124525cf1a30Sjl 124625cf1a30Sjl ST_MAC_REG(MAC_REWRITE_ADD(mcp, bank), dimm_addr); 124725cf1a30Sjl MAC_REW_REQ(mcp, bank); 124825cf1a30Sjl 124925cf1a30Sjl do { 125025cf1a30Sjl cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 12510cc8ae86Sav if (count++ >= mc_max_rewrite_loop) { 125225cf1a30Sjl goto bad; 12530cc8ae86Sav } else { 12540cc8ae86Sav drv_usecwait(mc_rewrite_delay); 12550cc8ae86Sav } 125625cf1a30Sjl /* 125725cf1a30Sjl * If there are other MEMORY or PCI activities, this 125825cf1a30Sjl * will be BUSY, else it should be set immediately 125925cf1a30Sjl */ 126025cf1a30Sjl } while (!(cntl & MAC_CNTL_REW_END)); 126125cf1a30Sjl 126225cf1a30Sjl MAC_CLEAR_ERRS(mcp, bank, MAC_CNTL_REW_ERRS); 126325cf1a30Sjl return (cntl); 126425cf1a30Sjl bad: 126525cf1a30Sjl /* This is bad. Just reset the circuit */ 126625cf1a30Sjl cmn_err(CE_WARN, "mc-opl rewrite timeout on /LSB%d/B%d\n", 126725cf1a30Sjl mcp->mc_board_num, bank); 126825cf1a30Sjl cntl = MAC_CNTL_REW_END; 126925cf1a30Sjl MAC_CMD(mcp, bank, MAC_CNTL_PTRL_RESET); 127025cf1a30Sjl MAC_CLEAR_ERRS(mcp, bank, MAC_CNTL_REW_ERRS); 127125cf1a30Sjl return (cntl); 127225cf1a30Sjl } 127325cf1a30Sjl void 127425cf1a30Sjl mc_process_scf_log(mc_opl_t *mcp) 127525cf1a30Sjl { 12760cc8ae86Sav int count; 12770cc8ae86Sav int n = 0; 127825cf1a30Sjl scf_log_t *p; 127925cf1a30Sjl int bank; 128025cf1a30Sjl 12810cc8ae86Sav for (bank = 0; bank < BANKNUM_PER_SB; bank++) { 12820cc8ae86Sav while ((p = mcp->mc_scf_log[bank]) != NULL && 12830cc8ae86Sav (n < mc_max_errlog_processed)) { 12840cc8ae86Sav ASSERT(bank == p->sl_bank); 12850cc8ae86Sav count = 0; 128625cf1a30Sjl while ((LD_MAC_REG(MAC_STATIC_ERR_ADD(mcp, p->sl_bank)) 128725cf1a30Sjl & MAC_STATIC_ERR_VLD)) { 12880cc8ae86Sav if (count++ >= (mc_max_scf_loop)) { 128925cf1a30Sjl break; 129025cf1a30Sjl } 12910cc8ae86Sav drv_usecwait(mc_scf_delay); 129225cf1a30Sjl } 129325cf1a30Sjl 12940cc8ae86Sav if (count < mc_max_scf_loop) { 129525cf1a30Sjl ST_MAC_REG(MAC_STATIC_ERR_LOG(mcp, p->sl_bank), 129625cf1a30Sjl p->sl_err_log); 129725cf1a30Sjl 129825cf1a30Sjl ST_MAC_REG(MAC_STATIC_ERR_ADD(mcp, p->sl_bank), 129925cf1a30Sjl p->sl_err_add|MAC_STATIC_ERR_VLD); 130025cf1a30Sjl mcp->mc_scf_retry[bank] = 0; 130125cf1a30Sjl } else { 130225cf1a30Sjl /* if we try too many times, just drop the req */ 13030cc8ae86Sav if (mcp->mc_scf_retry[bank]++ <= mc_max_scf_retry) { 130425cf1a30Sjl return; 130525cf1a30Sjl } else { 13060cc8ae86Sav if ((++mc_pce_dropped & 0xff) == 0) { 13070cc8ae86Sav cmn_err(CE_WARN, 13080cc8ae86Sav "Cannot report Permanent CE to SCF\n"); 13090cc8ae86Sav } 131025cf1a30Sjl } 131125cf1a30Sjl } 13120cc8ae86Sav n++; 13130cc8ae86Sav mcp->mc_scf_log[bank] = p->sl_next; 13140cc8ae86Sav mcp->mc_scf_total[bank]--; 13150cc8ae86Sav ASSERT(mcp->mc_scf_total[bank] >= 0); 131625cf1a30Sjl kmem_free(p, sizeof (scf_log_t)); 13170cc8ae86Sav } 131825cf1a30Sjl } 131925cf1a30Sjl } 132025cf1a30Sjl void 132125cf1a30Sjl mc_queue_scf_log(mc_opl_t *mcp, mc_flt_stat_t *flt_stat, int bank) 132225cf1a30Sjl { 132325cf1a30Sjl scf_log_t *p; 132425cf1a30Sjl 13250cc8ae86Sav if (mcp->mc_scf_total[bank] >= mc_max_scf_logs) { 13260cc8ae86Sav if ((++mc_pce_dropped & 0xff) == 0) { 13270cc8ae86Sav cmn_err(CE_WARN, "Too many Permanent CE requests.\n"); 13280cc8ae86Sav } 132925cf1a30Sjl return; 133025cf1a30Sjl } 133125cf1a30Sjl p = kmem_zalloc(sizeof (scf_log_t), KM_SLEEP); 133225cf1a30Sjl p->sl_next = 0; 133325cf1a30Sjl p->sl_err_add = flt_stat->mf_err_add; 133425cf1a30Sjl p->sl_err_log = flt_stat->mf_err_log; 133525cf1a30Sjl p->sl_bank = bank; 133625cf1a30Sjl 13370cc8ae86Sav if (mcp->mc_scf_log[bank] == NULL) { 133825cf1a30Sjl /* 133925cf1a30Sjl * we rely on mc_scf_log to detect NULL queue. 134025cf1a30Sjl * mc_scf_log_tail is irrelevant is such case. 134125cf1a30Sjl */ 13420cc8ae86Sav mcp->mc_scf_log_tail[bank] = mcp->mc_scf_log[bank] = p; 134325cf1a30Sjl } else { 13440cc8ae86Sav mcp->mc_scf_log_tail[bank]->sl_next = p; 13450cc8ae86Sav mcp->mc_scf_log_tail[bank] = p; 134625cf1a30Sjl } 13470cc8ae86Sav mcp->mc_scf_total[bank]++; 134825cf1a30Sjl } 134925cf1a30Sjl /* 135025cf1a30Sjl * This routine determines what kind of CE happens, intermittent 135125cf1a30Sjl * or permanent as follows. (See 4.7.3 in Columbus2 PRM.) 135225cf1a30Sjl * - Do rewrite by issuing REW_REQ command to MAC_PTRL_CNTL register. 135325cf1a30Sjl * - If CE is still detected on the same address even after doing 135425cf1a30Sjl * rewrite operation twice, it is determined as permanent error. 135525cf1a30Sjl * - If error is not detected anymore, it is determined as intermittent 135625cf1a30Sjl * error. 135725cf1a30Sjl * - If UE is detected due to rewrite operation, it should be treated 135825cf1a30Sjl * as UE. 135925cf1a30Sjl */ 136025cf1a30Sjl 136125cf1a30Sjl /* ARGSUSED */ 136225cf1a30Sjl static void 136325cf1a30Sjl mc_scrub_ce(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat, int ptrl_error) 136425cf1a30Sjl { 136525cf1a30Sjl uint32_t cntl; 136625cf1a30Sjl int i; 136725cf1a30Sjl 136825cf1a30Sjl flt_stat->mf_type = FLT_TYPE_PERMANENT_CE; 136925cf1a30Sjl /* 137025cf1a30Sjl * rewrite request 1st time reads and correct error data 137125cf1a30Sjl * and write to DIMM. 2nd rewrite request must be issued 137225cf1a30Sjl * after REW_CE/UE/END is 0. When the 2nd request is completed, 137325cf1a30Sjl * if REW_CE = 1, then it is permanent CE. 137425cf1a30Sjl */ 137525cf1a30Sjl for (i = 0; i < 2; i++) { 137625cf1a30Sjl cntl = do_rewrite(mcp, bank, flt_stat->mf_err_add); 137725cf1a30Sjl /* 137825cf1a30Sjl * If the error becomes UE or CMPE 137925cf1a30Sjl * we return to the caller immediately. 138025cf1a30Sjl */ 138125cf1a30Sjl if (cntl & MAC_CNTL_REW_UE) { 138225cf1a30Sjl if (ptrl_error) 138325cf1a30Sjl flt_stat->mf_cntl |= MAC_CNTL_PTRL_UE; 138425cf1a30Sjl else 138525cf1a30Sjl flt_stat->mf_cntl |= MAC_CNTL_MI_UE; 138625cf1a30Sjl flt_stat->mf_type = FLT_TYPE_UE; 138725cf1a30Sjl return; 138825cf1a30Sjl } 138925cf1a30Sjl if (cntl & MAC_CNTL_REW_CMPE) { 139025cf1a30Sjl if (ptrl_error) 139125cf1a30Sjl flt_stat->mf_cntl |= MAC_CNTL_PTRL_CMPE; 139225cf1a30Sjl else 139325cf1a30Sjl flt_stat->mf_cntl |= MAC_CNTL_MI_CMPE; 139425cf1a30Sjl flt_stat->mf_type = FLT_TYPE_CMPE; 139525cf1a30Sjl return; 139625cf1a30Sjl } 139725cf1a30Sjl } 139825cf1a30Sjl if (!(cntl & MAC_CNTL_REW_CE)) { 139925cf1a30Sjl flt_stat->mf_type = FLT_TYPE_INTERMITTENT_CE; 140025cf1a30Sjl } 140125cf1a30Sjl 140225cf1a30Sjl if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) { 140325cf1a30Sjl /* report PERMANENT_CE to SP via SCF */ 140425cf1a30Sjl if (!(flt_stat->mf_err_log & MAC_ERR_LOG_INVALID)) { 140525cf1a30Sjl mc_queue_scf_log(mcp, flt_stat, bank); 140625cf1a30Sjl } 140725cf1a30Sjl } 140825cf1a30Sjl } 140925cf1a30Sjl 141025cf1a30Sjl #define IS_CMPE(cntl, f) ((cntl) & ((f) ? MAC_CNTL_PTRL_CMPE :\ 141125cf1a30Sjl MAC_CNTL_MI_CMPE)) 141225cf1a30Sjl #define IS_UE(cntl, f) ((cntl) & ((f) ? MAC_CNTL_PTRL_UE : MAC_CNTL_MI_UE)) 141325cf1a30Sjl #define IS_CE(cntl, f) ((cntl) & ((f) ? MAC_CNTL_PTRL_CE : MAC_CNTL_MI_CE)) 141425cf1a30Sjl #define IS_OK(cntl, f) (!((cntl) & ((f) ? MAC_CNTL_PTRL_ERRS : \ 141525cf1a30Sjl MAC_CNTL_MI_ERRS))) 141625cf1a30Sjl 141725cf1a30Sjl 141825cf1a30Sjl static int 141925cf1a30Sjl IS_CE_ONLY(uint32_t cntl, int ptrl_error) 142025cf1a30Sjl { 142125cf1a30Sjl if (ptrl_error) { 142225cf1a30Sjl return ((cntl & MAC_CNTL_PTRL_ERRS) == MAC_CNTL_PTRL_CE); 142325cf1a30Sjl } else { 142425cf1a30Sjl return ((cntl & MAC_CNTL_MI_ERRS) == MAC_CNTL_MI_CE); 142525cf1a30Sjl } 142625cf1a30Sjl } 142725cf1a30Sjl 142825cf1a30Sjl void 142925cf1a30Sjl mc_write_cntl(mc_opl_t *mcp, int bank, uint32_t value) 143025cf1a30Sjl { 14310cc8ae86Sav if (mcp->mc_speedup_period[bank] > 0) 14320cc8ae86Sav value |= mc_max_speed; 14330cc8ae86Sav else 14340cc8ae86Sav value |= mcp->mc_speed; 143525cf1a30Sjl ST_MAC_REG(MAC_PTRL_CNTL(mcp, bank), value); 143625cf1a30Sjl } 143725cf1a30Sjl 143825cf1a30Sjl static void 143925cf1a30Sjl mc_read_ptrl_reg(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat) 144025cf1a30Sjl { 144125cf1a30Sjl flt_stat->mf_cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & 144225cf1a30Sjl MAC_CNTL_PTRL_ERRS; 144325cf1a30Sjl flt_stat->mf_err_add = LD_MAC_REG(MAC_PTRL_ERR_ADD(mcp, bank)); 144425cf1a30Sjl flt_stat->mf_err_log = LD_MAC_REG(MAC_PTRL_ERR_LOG(mcp, bank)); 144525cf1a30Sjl flt_stat->mf_flt_maddr.ma_bd = mcp->mc_board_num; 144625cf1a30Sjl flt_stat->mf_flt_maddr.ma_bank = bank; 144725cf1a30Sjl flt_stat->mf_flt_maddr.ma_dimm_addr = flt_stat->mf_err_add; 144825cf1a30Sjl } 144925cf1a30Sjl 145025cf1a30Sjl static void 145125cf1a30Sjl mc_read_mi_reg(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat) 145225cf1a30Sjl { 145325cf1a30Sjl uint32_t status, old_status; 145425cf1a30Sjl 145525cf1a30Sjl status = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & 145625cf1a30Sjl MAC_CNTL_MI_ERRS; 145725cf1a30Sjl old_status = 0; 145825cf1a30Sjl 145925cf1a30Sjl /* we keep reading until the status is stable */ 146025cf1a30Sjl while (old_status != status) { 146125cf1a30Sjl old_status = status; 146225cf1a30Sjl flt_stat->mf_err_add = 146325cf1a30Sjl LD_MAC_REG(MAC_MI_ERR_ADD(mcp, bank)); 146425cf1a30Sjl flt_stat->mf_err_log = 146525cf1a30Sjl LD_MAC_REG(MAC_MI_ERR_LOG(mcp, bank)); 146625cf1a30Sjl status = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & 146725cf1a30Sjl MAC_CNTL_MI_ERRS; 146825cf1a30Sjl if (status == old_status) { 146925cf1a30Sjl break; 147025cf1a30Sjl } 147125cf1a30Sjl } 147225cf1a30Sjl 147325cf1a30Sjl flt_stat->mf_cntl = status; 147425cf1a30Sjl flt_stat->mf_flt_maddr.ma_bd = mcp->mc_board_num; 147525cf1a30Sjl flt_stat->mf_flt_maddr.ma_bank = bank; 147625cf1a30Sjl flt_stat->mf_flt_maddr.ma_dimm_addr = flt_stat->mf_err_add; 147725cf1a30Sjl } 147825cf1a30Sjl 147925cf1a30Sjl 148025cf1a30Sjl /* 148125cf1a30Sjl * Error philosophy for mirror mode: 148225cf1a30Sjl * 148325cf1a30Sjl * PTRL (The error address for both banks are same, since ptrl stops if it 148425cf1a30Sjl * detects error.) 148525cf1a30Sjl * - Compaire error Report CMPE. 148625cf1a30Sjl * 148725cf1a30Sjl * - UE-UE Report MUE. No rewrite. 148825cf1a30Sjl * 148925cf1a30Sjl * - UE-* UE-(CE/OK). Rewrite to scrub UE. Report SUE. 149025cf1a30Sjl * 149125cf1a30Sjl * - CE-* CE-(CE/OK). Scrub to determine if CE is permanent. 149225cf1a30Sjl * If CE is permanent, inform SCF. Once for each 149325cf1a30Sjl * Dimm. If CE becomes UE or CMPE, go back to above. 149425cf1a30Sjl * 149525cf1a30Sjl * 149625cf1a30Sjl * MI (The error addresses for each bank are the same or different.) 149725cf1a30Sjl * - Compair error If addresses are the same. Just CMPE. 149825cf1a30Sjl * If addresses are different (this could happen 149925cf1a30Sjl * as a result of scrubbing. Report each seperately. 150025cf1a30Sjl * Only report error info on each side. 150125cf1a30Sjl * 150225cf1a30Sjl * - UE-UE Addresses are the same. Report MUE. 150325cf1a30Sjl * Addresses are different. Report SUE on each bank. 150425cf1a30Sjl * Rewrite to clear UE. 150525cf1a30Sjl * 150625cf1a30Sjl * - UE-* UE-(CE/OK) 150725cf1a30Sjl * Rewrite to clear UE. Report SUE for the bank. 150825cf1a30Sjl * 150925cf1a30Sjl * - CE-* CE-(CE/OK). Scrub to determine if CE is permanent. 151025cf1a30Sjl * If CE becomes UE or CMPE, go back to above. 151125cf1a30Sjl * 151225cf1a30Sjl */ 151325cf1a30Sjl 151425cf1a30Sjl static int 151525cf1a30Sjl mc_process_error_mir(mc_opl_t *mcp, mc_aflt_t *mc_aflt, mc_flt_stat_t *flt_stat) 151625cf1a30Sjl { 151725cf1a30Sjl int ptrl_error = mc_aflt->mflt_is_ptrl; 151825cf1a30Sjl int i; 151925cf1a30Sjl int rv = 0; 152025cf1a30Sjl 152125cf1a30Sjl MC_LOG("process mirror errors cntl[0] = %x, cntl[1] = %x\n", 152225cf1a30Sjl flt_stat[0].mf_cntl, flt_stat[1].mf_cntl); 152325cf1a30Sjl 152425cf1a30Sjl if (ptrl_error) { 152525cf1a30Sjl if (((flt_stat[0].mf_cntl | flt_stat[1].mf_cntl) 152625cf1a30Sjl & MAC_CNTL_PTRL_ERRS) == 0) 152725cf1a30Sjl return (0); 152825cf1a30Sjl } else { 152925cf1a30Sjl if (((flt_stat[0].mf_cntl | flt_stat[1].mf_cntl) 153025cf1a30Sjl & MAC_CNTL_MI_ERRS) == 0) 153125cf1a30Sjl return (0); 153225cf1a30Sjl } 153325cf1a30Sjl 153425cf1a30Sjl /* 153525cf1a30Sjl * First we take care of the case of CE 153625cf1a30Sjl * because they can become UE or CMPE 153725cf1a30Sjl */ 153825cf1a30Sjl for (i = 0; i < 2; i++) { 153925cf1a30Sjl if (IS_CE_ONLY(flt_stat[i].mf_cntl, ptrl_error)) { 154025cf1a30Sjl MC_LOG("CE detected on bank %d\n", 154125cf1a30Sjl flt_stat[i].mf_flt_maddr.ma_bank); 154225cf1a30Sjl mc_scrub_ce(mcp, flt_stat[i].mf_flt_maddr.ma_bank, 154325cf1a30Sjl &flt_stat[i], ptrl_error); 154425cf1a30Sjl rv = 1; 154525cf1a30Sjl } 154625cf1a30Sjl } 154725cf1a30Sjl 154825cf1a30Sjl /* The above scrubbing can turn CE into UE or CMPE */ 154925cf1a30Sjl 155025cf1a30Sjl /* 155125cf1a30Sjl * Now we distinguish two cases: same address or not 155225cf1a30Sjl * the same address. It might seem more intuitive to 155325cf1a30Sjl * distinguish PTRL v.s. MI error but it is more 155425cf1a30Sjl * complicated that way. 155525cf1a30Sjl */ 155625cf1a30Sjl 155725cf1a30Sjl if (flt_stat[0].mf_err_add == flt_stat[1].mf_err_add) { 155825cf1a30Sjl 155925cf1a30Sjl if (IS_CMPE(flt_stat[0].mf_cntl, ptrl_error) || 156025cf1a30Sjl IS_CMPE(flt_stat[1].mf_cntl, ptrl_error)) { 156125cf1a30Sjl flt_stat[0].mf_type = FLT_TYPE_CMPE; 156225cf1a30Sjl flt_stat[1].mf_type = FLT_TYPE_CMPE; 156325cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_CMPE; 156425cf1a30Sjl MC_LOG("cmpe error detected\n"); 156525cf1a30Sjl mc_aflt->mflt_nflts = 2; 156625cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[0]; 156725cf1a30Sjl mc_aflt->mflt_stat[1] = &flt_stat[1]; 156825cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 156925cf1a30Sjl mc_err_drain(mc_aflt); 157025cf1a30Sjl return (1); 157125cf1a30Sjl } 157225cf1a30Sjl 157325cf1a30Sjl if (IS_UE(flt_stat[0].mf_cntl, ptrl_error) && 157425cf1a30Sjl IS_UE(flt_stat[1].mf_cntl, ptrl_error)) { 157525cf1a30Sjl /* Both side are UE's */ 157625cf1a30Sjl 157725cf1a30Sjl MAC_SET_ERRLOG_INFO(&flt_stat[0]); 157825cf1a30Sjl MAC_SET_ERRLOG_INFO(&flt_stat[1]); 157925cf1a30Sjl MC_LOG("MUE detected\n"); 15800cc8ae86Sav flt_stat[0].mf_type = FLT_TYPE_MUE; 15810cc8ae86Sav flt_stat[1].mf_type = FLT_TYPE_MUE; 158225cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_MUE; 158325cf1a30Sjl mc_aflt->mflt_nflts = 2; 158425cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[0]; 158525cf1a30Sjl mc_aflt->mflt_stat[1] = &flt_stat[1]; 158625cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 158725cf1a30Sjl mc_err_drain(mc_aflt); 158825cf1a30Sjl return (1); 158925cf1a30Sjl } 159025cf1a30Sjl 159125cf1a30Sjl /* Now the only case is UE/CE, UE/OK, or don't care */ 159225cf1a30Sjl for (i = 0; i < 2; i++) { 159325cf1a30Sjl if (IS_UE(flt_stat[i].mf_cntl, ptrl_error)) { 15940cc8ae86Sav 15950cc8ae86Sav /* rewrite can clear the one side UE error */ 15960cc8ae86Sav 159725cf1a30Sjl if (IS_OK(flt_stat[i^1].mf_cntl, ptrl_error)) { 159825cf1a30Sjl (void) do_rewrite(mcp, 159925cf1a30Sjl flt_stat[i].mf_flt_maddr.ma_bank, 160025cf1a30Sjl flt_stat[i].mf_flt_maddr.ma_dimm_addr); 160125cf1a30Sjl } 160225cf1a30Sjl flt_stat[i].mf_type = FLT_TYPE_UE; 160325cf1a30Sjl MAC_SET_ERRLOG_INFO(&flt_stat[i]); 160425cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_SUE; 160525cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[i]; 160625cf1a30Sjl mc_aflt->mflt_nflts = 1; 160725cf1a30Sjl mc_aflt->mflt_pr = PR_MCE; 160825cf1a30Sjl mc_err_drain(mc_aflt); 160925cf1a30Sjl /* Once we hit a UE/CE or UE/OK case, done */ 161025cf1a30Sjl return (1); 161125cf1a30Sjl } 161225cf1a30Sjl } 161325cf1a30Sjl 161425cf1a30Sjl } else { 161525cf1a30Sjl /* 161625cf1a30Sjl * addresses are different. That means errors 161725cf1a30Sjl * on the 2 banks are not related at all. 161825cf1a30Sjl */ 161925cf1a30Sjl for (i = 0; i < 2; i++) { 162025cf1a30Sjl if (IS_CMPE(flt_stat[i].mf_cntl, ptrl_error)) { 162125cf1a30Sjl flt_stat[i].mf_type = FLT_TYPE_CMPE; 162225cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_CMPE; 162325cf1a30Sjl MC_LOG("cmpe error detected\n"); 162425cf1a30Sjl mc_aflt->mflt_nflts = 1; 162525cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[i]; 162625cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 162725cf1a30Sjl mc_err_drain(mc_aflt); 162825cf1a30Sjl /* no more report on this bank */ 162925cf1a30Sjl flt_stat[i].mf_cntl = 0; 163025cf1a30Sjl rv = 1; 163125cf1a30Sjl } 163225cf1a30Sjl } 163325cf1a30Sjl 16340cc8ae86Sav /* rewrite can clear the one side UE error */ 16350cc8ae86Sav 163625cf1a30Sjl for (i = 0; i < 2; i++) { 163725cf1a30Sjl if (IS_UE(flt_stat[i].mf_cntl, ptrl_error)) { 163825cf1a30Sjl (void) do_rewrite(mcp, 163925cf1a30Sjl flt_stat[i].mf_flt_maddr.ma_bank, 164025cf1a30Sjl flt_stat[i].mf_flt_maddr.ma_dimm_addr); 164125cf1a30Sjl flt_stat[i].mf_type = FLT_TYPE_UE; 164225cf1a30Sjl MAC_SET_ERRLOG_INFO(&flt_stat[i]); 164325cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_SUE; 164425cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[i]; 164525cf1a30Sjl mc_aflt->mflt_nflts = 1; 164625cf1a30Sjl mc_aflt->mflt_pr = PR_MCE; 164725cf1a30Sjl mc_err_drain(mc_aflt); 164825cf1a30Sjl rv = 1; 164925cf1a30Sjl } 165025cf1a30Sjl } 165125cf1a30Sjl } 165225cf1a30Sjl return (rv); 165325cf1a30Sjl } 165425cf1a30Sjl static void 165525cf1a30Sjl mc_error_handler_mir(mc_opl_t *mcp, int bank, mc_addr_info_t *maddr) 165625cf1a30Sjl { 165725cf1a30Sjl mc_aflt_t mc_aflt; 165825cf1a30Sjl mc_flt_stat_t flt_stat[2], mi_flt_stat[2]; 16590cc8ae86Sav int i; 16600cc8ae86Sav int mi_valid; 166125cf1a30Sjl 166225cf1a30Sjl bzero(&mc_aflt, sizeof (mc_aflt_t)); 166325cf1a30Sjl bzero(&flt_stat, 2 * sizeof (mc_flt_stat_t)); 166425cf1a30Sjl bzero(&mi_flt_stat, 2 * sizeof (mc_flt_stat_t)); 166525cf1a30Sjl 166625cf1a30Sjl mc_aflt.mflt_mcp = mcp; 166725cf1a30Sjl mc_aflt.mflt_id = gethrtime(); 166825cf1a30Sjl 166925cf1a30Sjl /* Now read all the registers into flt_stat */ 167025cf1a30Sjl 16710cc8ae86Sav for (i = 0; i < 2; i++) { 16720cc8ae86Sav MC_LOG("Reading registers of bank %d\n", bank); 16730cc8ae86Sav /* patrol registers */ 16740cc8ae86Sav mc_read_ptrl_reg(mcp, bank, &flt_stat[i]); 167525cf1a30Sjl 16760cc8ae86Sav ASSERT(maddr); 16770cc8ae86Sav maddr->mi_maddr = flt_stat[i].mf_flt_maddr; 167825cf1a30Sjl 16790cc8ae86Sav MC_LOG("ptrl registers cntl %x add %x log %x\n", 16800cc8ae86Sav flt_stat[i].mf_cntl, 16810cc8ae86Sav flt_stat[i].mf_err_add, 16820cc8ae86Sav flt_stat[i].mf_err_log); 168325cf1a30Sjl 16840cc8ae86Sav /* MI registers */ 16850cc8ae86Sav mc_read_mi_reg(mcp, bank, &mi_flt_stat[i]); 168625cf1a30Sjl 16870cc8ae86Sav MC_LOG("MI registers cntl %x add %x log %x\n", 16880cc8ae86Sav mi_flt_stat[i].mf_cntl, 16890cc8ae86Sav mi_flt_stat[i].mf_err_add, 16900cc8ae86Sav mi_flt_stat[i].mf_err_log); 169125cf1a30Sjl 16920cc8ae86Sav bank = bank^1; 16930cc8ae86Sav } 169425cf1a30Sjl 169525cf1a30Sjl /* clear errors once we read all the registers */ 16960cc8ae86Sav MAC_CLEAR_ERRS(mcp, bank, 169725cf1a30Sjl (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS)); 169825cf1a30Sjl 16990cc8ae86Sav MAC_CLEAR_ERRS(mcp, bank ^ 1, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS)); 17000cc8ae86Sav 17010cc8ae86Sav /* Process MI errors first */ 170225cf1a30Sjl 17030cc8ae86Sav /* if not error mode, cntl1 is 0 */ 17040cc8ae86Sav if ((mi_flt_stat[0].mf_err_add & MAC_ERR_ADD_INVALID) || 17050cc8ae86Sav (mi_flt_stat[0].mf_err_log & MAC_ERR_LOG_INVALID)) 17060cc8ae86Sav mi_flt_stat[0].mf_cntl = 0; 17070cc8ae86Sav 17080cc8ae86Sav if ((mi_flt_stat[1].mf_err_add & MAC_ERR_ADD_INVALID) || 17090cc8ae86Sav (mi_flt_stat[1].mf_err_log & MAC_ERR_LOG_INVALID)) 17100cc8ae86Sav mi_flt_stat[1].mf_cntl = 0; 171125cf1a30Sjl 17120cc8ae86Sav mc_aflt.mflt_is_ptrl = 0; 17130cc8ae86Sav mi_valid = mc_process_error_mir(mcp, &mc_aflt, &mi_flt_stat[0]); 17140cc8ae86Sav 17150cc8ae86Sav if ((((flt_stat[0].mf_cntl & MAC_CNTL_PTRL_ERRS) >> 17160cc8ae86Sav MAC_CNTL_PTRL_ERR_SHIFT) == 17170cc8ae86Sav ((mi_flt_stat[0].mf_cntl & MAC_CNTL_MI_ERRS) >> 17180cc8ae86Sav MAC_CNTL_MI_ERR_SHIFT)) && 17190cc8ae86Sav (flt_stat[0].mf_err_add == mi_flt_stat[0].mf_err_add) && 17200cc8ae86Sav (((flt_stat[1].mf_cntl & MAC_CNTL_PTRL_ERRS) >> 17210cc8ae86Sav MAC_CNTL_PTRL_ERR_SHIFT) == 17220cc8ae86Sav ((mi_flt_stat[1].mf_cntl & MAC_CNTL_MI_ERRS) >> 17230cc8ae86Sav MAC_CNTL_MI_ERR_SHIFT)) && 17240cc8ae86Sav (flt_stat[1].mf_err_add == mi_flt_stat[1].mf_err_add)) { 17250cc8ae86Sav #ifdef DEBUG 17260cc8ae86Sav MC_LOG("discarding PTRL error because " 17270cc8ae86Sav "it is the same as MI\n"); 17280cc8ae86Sav #endif 17290cc8ae86Sav maddr->mi_valid = mi_valid; 17300cc8ae86Sav return; 17310cc8ae86Sav } 173225cf1a30Sjl /* if not error mode, cntl1 is 0 */ 173325cf1a30Sjl if ((flt_stat[0].mf_err_add & MAC_ERR_ADD_INVALID) || 173425cf1a30Sjl (flt_stat[0].mf_err_log & MAC_ERR_LOG_INVALID)) 173525cf1a30Sjl flt_stat[0].mf_cntl = 0; 173625cf1a30Sjl 173725cf1a30Sjl if ((flt_stat[1].mf_err_add & MAC_ERR_ADD_INVALID) || 173825cf1a30Sjl (flt_stat[1].mf_err_log & MAC_ERR_LOG_INVALID)) 173925cf1a30Sjl flt_stat[1].mf_cntl = 0; 174025cf1a30Sjl 174125cf1a30Sjl mc_aflt.mflt_is_ptrl = 1; 174225cf1a30Sjl maddr->mi_valid = mc_process_error_mir(mcp, &mc_aflt, &flt_stat[0]); 174325cf1a30Sjl } 174425cf1a30Sjl static int 174525cf1a30Sjl mc_process_error(mc_opl_t *mcp, int bank, mc_aflt_t *mc_aflt, 174625cf1a30Sjl mc_flt_stat_t *flt_stat) 174725cf1a30Sjl { 174825cf1a30Sjl int ptrl_error = mc_aflt->mflt_is_ptrl; 174925cf1a30Sjl int rv = 0; 175025cf1a30Sjl 175125cf1a30Sjl mc_aflt->mflt_erpt_class = NULL; 175225cf1a30Sjl if (IS_UE(flt_stat->mf_cntl, ptrl_error)) { 175325cf1a30Sjl MC_LOG("UE deteceted\n"); 175425cf1a30Sjl flt_stat->mf_type = FLT_TYPE_UE; 175525cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_UE; 175625cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 175725cf1a30Sjl MAC_SET_ERRLOG_INFO(flt_stat); 175825cf1a30Sjl rv = 1; 175925cf1a30Sjl } else if (IS_CE(flt_stat->mf_cntl, ptrl_error)) { 176025cf1a30Sjl MC_LOG("CE deteceted\n"); 176125cf1a30Sjl MAC_SET_ERRLOG_INFO(flt_stat); 176225cf1a30Sjl 176325cf1a30Sjl /* Error type can change after scrubing */ 176425cf1a30Sjl mc_scrub_ce(mcp, bank, flt_stat, ptrl_error); 176525cf1a30Sjl 176625cf1a30Sjl if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) { 176725cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_CE; 176825cf1a30Sjl mc_aflt->mflt_pr = PR_MCE; 176925cf1a30Sjl } else if (flt_stat->mf_type == FLT_TYPE_UE) { 177025cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_UE; 177125cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 177225cf1a30Sjl } 177325cf1a30Sjl rv = 1; 177425cf1a30Sjl } 177525cf1a30Sjl MC_LOG("mc_process_error: fault type %x erpt %s\n", 177625cf1a30Sjl flt_stat->mf_type, 177725cf1a30Sjl mc_aflt->mflt_erpt_class); 177825cf1a30Sjl if (mc_aflt->mflt_erpt_class) { 177925cf1a30Sjl mc_aflt->mflt_stat[0] = flt_stat; 178025cf1a30Sjl mc_aflt->mflt_nflts = 1; 178125cf1a30Sjl mc_err_drain(mc_aflt); 178225cf1a30Sjl } 178325cf1a30Sjl return (rv); 178425cf1a30Sjl } 178525cf1a30Sjl 178625cf1a30Sjl static void 178725cf1a30Sjl mc_error_handler(mc_opl_t *mcp, int bank, mc_addr_info_t *maddr) 178825cf1a30Sjl { 178925cf1a30Sjl mc_aflt_t mc_aflt; 179025cf1a30Sjl mc_flt_stat_t flt_stat, mi_flt_stat; 17910cc8ae86Sav int mi_valid; 179225cf1a30Sjl 179325cf1a30Sjl bzero(&mc_aflt, sizeof (mc_aflt_t)); 179425cf1a30Sjl bzero(&flt_stat, sizeof (mc_flt_stat_t)); 179525cf1a30Sjl bzero(&mi_flt_stat, sizeof (mc_flt_stat_t)); 179625cf1a30Sjl 179725cf1a30Sjl mc_aflt.mflt_mcp = mcp; 179825cf1a30Sjl mc_aflt.mflt_id = gethrtime(); 179925cf1a30Sjl 180025cf1a30Sjl /* patrol registers */ 180125cf1a30Sjl mc_read_ptrl_reg(mcp, bank, &flt_stat); 180225cf1a30Sjl 180325cf1a30Sjl ASSERT(maddr); 180425cf1a30Sjl maddr->mi_maddr = flt_stat.mf_flt_maddr; 180525cf1a30Sjl 180625cf1a30Sjl MC_LOG("ptrl registers cntl %x add %x log %x\n", 180725cf1a30Sjl flt_stat.mf_cntl, 180825cf1a30Sjl flt_stat.mf_err_add, 180925cf1a30Sjl flt_stat.mf_err_log); 181025cf1a30Sjl 181125cf1a30Sjl /* MI registers */ 181225cf1a30Sjl mc_read_mi_reg(mcp, bank, &mi_flt_stat); 181325cf1a30Sjl 18140cc8ae86Sav 181525cf1a30Sjl MC_LOG("MI registers cntl %x add %x log %x\n", 181625cf1a30Sjl mi_flt_stat.mf_cntl, 181725cf1a30Sjl mi_flt_stat.mf_err_add, 181825cf1a30Sjl mi_flt_stat.mf_err_log); 181925cf1a30Sjl 182025cf1a30Sjl /* clear errors once we read all the registers */ 182125cf1a30Sjl MAC_CLEAR_ERRS(mcp, bank, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS)); 182225cf1a30Sjl 18230cc8ae86Sav mc_aflt.mflt_is_ptrl = 0; 18240cc8ae86Sav if ((mi_flt_stat.mf_cntl & MAC_CNTL_MI_ERRS) && 18250cc8ae86Sav ((mi_flt_stat.mf_err_add & MAC_ERR_ADD_INVALID) == 0) && 18260cc8ae86Sav ((mi_flt_stat.mf_err_log & MAC_ERR_LOG_INVALID) == 0)) { 18270cc8ae86Sav mi_valid = mc_process_error(mcp, bank, &mc_aflt, &mi_flt_stat); 18280cc8ae86Sav } 18290cc8ae86Sav 18300cc8ae86Sav if ((((flt_stat.mf_cntl & MAC_CNTL_PTRL_ERRS) >> 18310cc8ae86Sav MAC_CNTL_PTRL_ERR_SHIFT) == 18320cc8ae86Sav ((mi_flt_stat.mf_cntl & MAC_CNTL_MI_ERRS) >> 18330cc8ae86Sav MAC_CNTL_MI_ERR_SHIFT)) && 18340cc8ae86Sav (flt_stat.mf_err_add == mi_flt_stat.mf_err_add)) { 18350cc8ae86Sav #ifdef DEBUG 18360cc8ae86Sav MC_LOG("discarding PTRL error because " 18370cc8ae86Sav "it is the same as MI\n"); 18380cc8ae86Sav #endif 18390cc8ae86Sav maddr->mi_valid = mi_valid; 18400cc8ae86Sav return; 18410cc8ae86Sav } 18420cc8ae86Sav 184325cf1a30Sjl mc_aflt.mflt_is_ptrl = 1; 184425cf1a30Sjl if ((flt_stat.mf_cntl & MAC_CNTL_PTRL_ERRS) && 184525cf1a30Sjl ((flt_stat.mf_err_add & MAC_ERR_ADD_INVALID) == 0) && 184625cf1a30Sjl ((flt_stat.mf_err_log & MAC_ERR_LOG_INVALID) == 0)) { 184725cf1a30Sjl maddr->mi_valid = mc_process_error(mcp, bank, 184825cf1a30Sjl &mc_aflt, &flt_stat); 184925cf1a30Sjl } 185025cf1a30Sjl } 185125cf1a30Sjl /* 185225cf1a30Sjl * memory patrol error handling algorithm: 185325cf1a30Sjl * timeout() is used to do periodic polling 185425cf1a30Sjl * This is the flow chart. 185525cf1a30Sjl * timeout -> 185625cf1a30Sjl * mc_check_errors() 185725cf1a30Sjl * if memory bank is installed, read the status register 185825cf1a30Sjl * if any error bit is set, 185925cf1a30Sjl * -> mc_error_handler() 186025cf1a30Sjl * -> read all error regsiters 186125cf1a30Sjl * -> mc_process_error() 186225cf1a30Sjl * determine error type 186325cf1a30Sjl * rewrite to clear error or scrub to determine CE type 186425cf1a30Sjl * inform SCF on permanent CE 186525cf1a30Sjl * -> mc_err_drain 186625cf1a30Sjl * page offline processing 186725cf1a30Sjl * -> mc_ereport_post() 186825cf1a30Sjl */ 186925cf1a30Sjl 187025cf1a30Sjl static void 187125cf1a30Sjl mc_check_errors_func(mc_opl_t *mcp) 187225cf1a30Sjl { 187325cf1a30Sjl mc_addr_info_t maddr_info; 187425cf1a30Sjl int i, error_count = 0; 187525cf1a30Sjl uint32_t stat, cntl; 18760cc8ae86Sav int running; 1877cfb9e062Shyw int wrapped; 187825cf1a30Sjl 187925cf1a30Sjl /* 188025cf1a30Sjl * scan errors. 188125cf1a30Sjl */ 18820cc8ae86Sav if (mcp->mc_status & MC_MEMORYLESS) 18830cc8ae86Sav return; 18840cc8ae86Sav 188525cf1a30Sjl for (i = 0; i < BANKNUM_PER_SB; i++) { 188625cf1a30Sjl if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) { 188725cf1a30Sjl stat = ldphysio(MAC_PTRL_STAT(mcp, i)); 188825cf1a30Sjl cntl = ldphysio(MAC_PTRL_CNTL(mcp, i)); 18890cc8ae86Sav running = cntl & MAC_CNTL_PTRL_START; 1890cfb9e062Shyw wrapped = cntl & MAC_CNTL_PTRL_ADD_MAX; 18910cc8ae86Sav 1892cfb9e062Shyw if (mc_debug_show_all || stat) { 1893cfb9e062Shyw MC_LOG("/LSB%d/B%d stat %x cntl %x\n", 1894cfb9e062Shyw mcp->mc_board_num, i, 1895cfb9e062Shyw stat, cntl); 1896cfb9e062Shyw } 1897cfb9e062Shyw 1898cfb9e062Shyw /* 1899cfb9e062Shyw * Update stats and reset flag if the HW patrol 1900cfb9e062Shyw * wrapped around in its scan. 1901cfb9e062Shyw */ 1902cfb9e062Shyw if (wrapped) { 19030cc8ae86Sav mcp->mc_period[i]++; 190425cf1a30Sjl MC_LOG("mc period %ld on " 19050cc8ae86Sav "/LSB%d/B%d\n", mcp->mc_period[i], 190625cf1a30Sjl mcp->mc_board_num, i); 190725cf1a30Sjl MAC_CLEAR_MAX(mcp, i); 190825cf1a30Sjl } 1909cfb9e062Shyw 1910cfb9e062Shyw if (running) { 1911cfb9e062Shyw /* 1912cfb9e062Shyw * Mac patrol HW is still running. 1913cfb9e062Shyw * Normally when an error is detected, 1914cfb9e062Shyw * the HW patrol will stop so that we 1915cfb9e062Shyw * can collect error data for reporting. 1916cfb9e062Shyw * Certain errors (MI errors) detected may not 1917cfb9e062Shyw * cause the HW patrol to stop which is a 1918cfb9e062Shyw * problem since we cannot read error data while 1919cfb9e062Shyw * the HW patrol is running. SW is not allowed 1920cfb9e062Shyw * to stop the HW patrol while it is running 1921cfb9e062Shyw * as it may cause HW inconsistency. This is 1922cfb9e062Shyw * described in a HW errata. 1923cfb9e062Shyw * In situations where we detected errors 1924cfb9e062Shyw * that may not cause the HW patrol to stop. 1925cfb9e062Shyw * We speed up the HW patrol scanning in 1926cfb9e062Shyw * the hope that it will find the 'real' PTRL 1927cfb9e062Shyw * errors associated with the previous errors 1928cfb9e062Shyw * causing the HW to finally stop so that we 1929cfb9e062Shyw * can do the reporting. 1930cfb9e062Shyw */ 1931cfb9e062Shyw /* 1932cfb9e062Shyw * Check to see if we did speed up 1933cfb9e062Shyw * the HW patrol due to previous errors 1934cfb9e062Shyw * detected that did not cause the patrol 1935cfb9e062Shyw * to stop. We only do it if HW patrol scan 1936cfb9e062Shyw * wrapped (counted as completing a 'period'). 1937cfb9e062Shyw */ 1938cfb9e062Shyw if (mcp->mc_speedup_period[i] > 0) { 1939cfb9e062Shyw if (wrapped && 1940cfb9e062Shyw (--mcp->mc_speedup_period[i] == 0)) { 1941cfb9e062Shyw /* 1942cfb9e062Shyw * We did try to speed up. 1943cfb9e062Shyw * The speed up period has expired 1944cfb9e062Shyw * and the HW patrol is still running. 1945cfb9e062Shyw * The errors must be intermittent. 1946cfb9e062Shyw * We have no choice but to ignore 1947cfb9e062Shyw * them, reset the scan speed to normal 1948cfb9e062Shyw * and clear the MI error bits. 1949cfb9e062Shyw */ 1950cfb9e062Shyw MC_LOG("Clearing MI errors\n"); 1951cfb9e062Shyw MAC_CLEAR_ERRS(mcp, i, 1952cfb9e062Shyw MAC_CNTL_MI_ERRS); 1953cfb9e062Shyw } 1954cfb9e062Shyw } else if (stat & MAC_STAT_MI_ERRS) { 1955cfb9e062Shyw /* 1956cfb9e062Shyw * MI errors detected but we cannot 1957cfb9e062Shyw * report them since the HW patrol 1958cfb9e062Shyw * is still running. 1959cfb9e062Shyw * We will attempt to speed up the 1960cfb9e062Shyw * scanning and hopefully the HW 1961cfb9e062Shyw * can detect PRTL errors at the same 1962cfb9e062Shyw * location that cause the HW patrol 1963cfb9e062Shyw * to stop. 1964cfb9e062Shyw */ 19650cc8ae86Sav mcp->mc_speedup_period[i] = 2; 19660cc8ae86Sav MAC_CMD(mcp, i, 0); 19670cc8ae86Sav } 1968cfb9e062Shyw } else if (stat & (MAC_STAT_PTRL_ERRS | 1969cfb9e062Shyw MAC_STAT_MI_ERRS)) { 1970cfb9e062Shyw /* 1971cfb9e062Shyw * HW Patrol has stopped and we found errors. 1972cfb9e062Shyw * Proceed to collect and report error info. 1973cfb9e062Shyw */ 1974cfb9e062Shyw mcp->mc_speedup_period[i] = 0; 1975cfb9e062Shyw maddr_info.mi_valid = 0; 1976cfb9e062Shyw maddr_info.mi_advance = 1; 1977cfb9e062Shyw if (IS_MIRROR(mcp, i)) 1978cfb9e062Shyw mc_error_handler_mir(mcp, i, &maddr_info); 1979cfb9e062Shyw else 1980cfb9e062Shyw mc_error_handler(mcp, i, &maddr_info); 1981cfb9e062Shyw 1982cfb9e062Shyw error_count++; 1983cfb9e062Shyw restart_patrol(mcp, i, &maddr_info); 198425cf1a30Sjl } else { 1985cfb9e062Shyw /* 1986cfb9e062Shyw * HW patrol scan has apparently stopped 1987cfb9e062Shyw * but no errors detected/flagged. 1988cfb9e062Shyw * Restart the HW patrol just to be sure. 1989cfb9e062Shyw */ 199025cf1a30Sjl restart_patrol(mcp, i, NULL); 199125cf1a30Sjl } 199225cf1a30Sjl } 199325cf1a30Sjl } 199425cf1a30Sjl if (error_count > 0) 199525cf1a30Sjl mcp->mc_last_error += error_count; 199625cf1a30Sjl else 199725cf1a30Sjl mcp->mc_last_error = 0; 199825cf1a30Sjl } 199925cf1a30Sjl 20000cc8ae86Sav /* 20010cc8ae86Sav * mc_polling -- Check errors for only one instance, 20020cc8ae86Sav * but process errors for all instances to make sure we drain the errors 20030cc8ae86Sav * faster than they can be accumulated. 20040cc8ae86Sav * 20050cc8ae86Sav * Polling on each board should be done only once per each 20060cc8ae86Sav * mc_patrol_interval_sec. This is equivalent to setting mc_tick_left 20070cc8ae86Sav * to OPL_MAX_BOARDS and decrement by 1 on each timeout. 20080cc8ae86Sav * Once mc_tick_left becomes negative, the board becomes a candidate 20090cc8ae86Sav * for polling because it has waited for at least 20100cc8ae86Sav * mc_patrol_interval_sec's long. If mc_timeout_period is calculated 20110cc8ae86Sav * differently, this has to beupdated accordingly. 20120cc8ae86Sav */ 201325cf1a30Sjl 201425cf1a30Sjl static void 20150cc8ae86Sav mc_polling(void) 201625cf1a30Sjl { 20170cc8ae86Sav int i, scan_error; 20180cc8ae86Sav mc_opl_t *mcp; 201925cf1a30Sjl 202025cf1a30Sjl 20210cc8ae86Sav scan_error = 1; 20220cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 20230cc8ae86Sav mutex_enter(&mcmutex); 20240cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) { 20250cc8ae86Sav mutex_exit(&mcmutex); 20260cc8ae86Sav continue; 20270cc8ae86Sav } 20280cc8ae86Sav mutex_enter(&mcp->mc_lock); 20290cc8ae86Sav mutex_exit(&mcmutex); 20300cc8ae86Sav if (scan_error && mcp->mc_tick_left <= 0) { 20310cc8ae86Sav mc_check_errors_func((void *)mcp); 20320cc8ae86Sav mcp->mc_tick_left = OPL_MAX_BOARDS; 20330cc8ae86Sav scan_error = 0; 20340cc8ae86Sav } else { 20350cc8ae86Sav mcp->mc_tick_left--; 20360cc8ae86Sav } 20370cc8ae86Sav mc_process_scf_log(mcp); 20380cc8ae86Sav mutex_exit(&mcp->mc_lock); 203925cf1a30Sjl } 204025cf1a30Sjl } 204125cf1a30Sjl 204225cf1a30Sjl static void 204325cf1a30Sjl get_ptrl_start_address(mc_opl_t *mcp, int bank, mc_addr_t *maddr) 204425cf1a30Sjl { 204525cf1a30Sjl maddr->ma_bd = mcp->mc_board_num; 204625cf1a30Sjl maddr->ma_bank = bank; 204725cf1a30Sjl maddr->ma_dimm_addr = 0; 204825cf1a30Sjl } 204925cf1a30Sjl 205025cf1a30Sjl typedef struct mc_mem_range { 205125cf1a30Sjl uint64_t addr; 205225cf1a30Sjl uint64_t size; 205325cf1a30Sjl } mc_mem_range_t; 205425cf1a30Sjl 205525cf1a30Sjl static int 205625cf1a30Sjl get_base_address(mc_opl_t *mcp) 205725cf1a30Sjl { 205825cf1a30Sjl mc_mem_range_t *mem_range; 205925cf1a30Sjl int len; 206025cf1a30Sjl 206125cf1a30Sjl if (ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS, 206225cf1a30Sjl "sb-mem-ranges", (caddr_t)&mem_range, &len) != DDI_SUCCESS) { 206325cf1a30Sjl return (DDI_FAILURE); 206425cf1a30Sjl } 206525cf1a30Sjl 206625cf1a30Sjl mcp->mc_start_address = mem_range->addr; 206725cf1a30Sjl mcp->mc_size = mem_range->size; 206825cf1a30Sjl 206925cf1a30Sjl kmem_free(mem_range, len); 207025cf1a30Sjl return (DDI_SUCCESS); 207125cf1a30Sjl } 207225cf1a30Sjl 207325cf1a30Sjl struct mc_addr_spec { 207425cf1a30Sjl uint32_t bank; 207525cf1a30Sjl uint32_t phys_hi; 207625cf1a30Sjl uint32_t phys_lo; 207725cf1a30Sjl }; 207825cf1a30Sjl 207925cf1a30Sjl #define REGS_PA(m, i) ((((uint64_t)m[i].phys_hi)<<32) | m[i].phys_lo) 208025cf1a30Sjl 208125cf1a30Sjl static char *mc_tbl_name[] = { 208225cf1a30Sjl "cs0-mc-pa-trans-table", 208325cf1a30Sjl "cs1-mc-pa-trans-table" 208425cf1a30Sjl }; 208525cf1a30Sjl 208625cf1a30Sjl static int 208725cf1a30Sjl mc_valid_pa(mc_opl_t *mcp, uint64_t pa) 208825cf1a30Sjl { 208925cf1a30Sjl struct memlist *ml; 209025cf1a30Sjl 209125cf1a30Sjl if (mcp->mlist == NULL) 209225cf1a30Sjl mc_get_mlist(mcp); 209325cf1a30Sjl 209425cf1a30Sjl for (ml = mcp->mlist; ml; ml = ml->next) { 209525cf1a30Sjl if (ml->address <= pa && pa < (ml->address + ml->size)) 209625cf1a30Sjl return (1); 209725cf1a30Sjl } 209825cf1a30Sjl return (0); 209925cf1a30Sjl } 210025cf1a30Sjl 210125cf1a30Sjl static void 210225cf1a30Sjl mc_memlist_delete(struct memlist *mlist) 210325cf1a30Sjl { 210425cf1a30Sjl struct memlist *ml; 210525cf1a30Sjl 210625cf1a30Sjl for (ml = mlist; ml; ml = mlist) { 210725cf1a30Sjl mlist = ml->next; 210825cf1a30Sjl kmem_free(ml, sizeof (struct memlist)); 210925cf1a30Sjl } 211025cf1a30Sjl } 211125cf1a30Sjl 211225cf1a30Sjl static struct memlist * 211325cf1a30Sjl mc_memlist_dup(struct memlist *mlist) 211425cf1a30Sjl { 211525cf1a30Sjl struct memlist *hl = NULL, *tl, **mlp; 211625cf1a30Sjl 211725cf1a30Sjl if (mlist == NULL) 211825cf1a30Sjl return (NULL); 211925cf1a30Sjl 212025cf1a30Sjl mlp = &hl; 212125cf1a30Sjl tl = *mlp; 212225cf1a30Sjl for (; mlist; mlist = mlist->next) { 212325cf1a30Sjl *mlp = kmem_alloc(sizeof (struct memlist), KM_SLEEP); 212425cf1a30Sjl (*mlp)->address = mlist->address; 212525cf1a30Sjl (*mlp)->size = mlist->size; 212625cf1a30Sjl (*mlp)->prev = tl; 212725cf1a30Sjl tl = *mlp; 212825cf1a30Sjl mlp = &((*mlp)->next); 212925cf1a30Sjl } 213025cf1a30Sjl *mlp = NULL; 213125cf1a30Sjl 213225cf1a30Sjl return (hl); 213325cf1a30Sjl } 213425cf1a30Sjl 213525cf1a30Sjl 213625cf1a30Sjl static struct memlist * 213725cf1a30Sjl mc_memlist_del_span(struct memlist *mlist, uint64_t base, uint64_t len) 213825cf1a30Sjl { 213925cf1a30Sjl uint64_t end; 214025cf1a30Sjl struct memlist *ml, *tl, *nlp; 214125cf1a30Sjl 214225cf1a30Sjl if (mlist == NULL) 214325cf1a30Sjl return (NULL); 214425cf1a30Sjl 214525cf1a30Sjl end = base + len; 214625cf1a30Sjl if ((end <= mlist->address) || (base == end)) 214725cf1a30Sjl return (mlist); 214825cf1a30Sjl 214925cf1a30Sjl for (tl = ml = mlist; ml; tl = ml, ml = nlp) { 215025cf1a30Sjl uint64_t mend; 215125cf1a30Sjl 215225cf1a30Sjl nlp = ml->next; 215325cf1a30Sjl 215425cf1a30Sjl if (end <= ml->address) 215525cf1a30Sjl break; 215625cf1a30Sjl 215725cf1a30Sjl mend = ml->address + ml->size; 215825cf1a30Sjl if (base < mend) { 215925cf1a30Sjl if (base <= ml->address) { 216025cf1a30Sjl ml->address = end; 216125cf1a30Sjl if (end >= mend) 216225cf1a30Sjl ml->size = 0ull; 216325cf1a30Sjl else 216425cf1a30Sjl ml->size = mend - ml->address; 216525cf1a30Sjl } else { 216625cf1a30Sjl ml->size = base - ml->address; 216725cf1a30Sjl if (end < mend) { 216825cf1a30Sjl struct memlist *nl; 216925cf1a30Sjl /* 217025cf1a30Sjl * splitting an memlist entry. 217125cf1a30Sjl */ 217225cf1a30Sjl nl = kmem_alloc(sizeof (struct memlist), 217325cf1a30Sjl KM_SLEEP); 217425cf1a30Sjl nl->address = end; 217525cf1a30Sjl nl->size = mend - nl->address; 217625cf1a30Sjl if ((nl->next = nlp) != NULL) 217725cf1a30Sjl nlp->prev = nl; 217825cf1a30Sjl nl->prev = ml; 217925cf1a30Sjl ml->next = nl; 218025cf1a30Sjl nlp = nl; 218125cf1a30Sjl } 218225cf1a30Sjl } 218325cf1a30Sjl if (ml->size == 0ull) { 218425cf1a30Sjl if (ml == mlist) { 218525cf1a30Sjl if ((mlist = nlp) != NULL) 218625cf1a30Sjl nlp->prev = NULL; 218725cf1a30Sjl kmem_free(ml, sizeof (struct memlist)); 218825cf1a30Sjl if (mlist == NULL) 218925cf1a30Sjl break; 219025cf1a30Sjl ml = nlp; 219125cf1a30Sjl } else { 219225cf1a30Sjl if ((tl->next = nlp) != NULL) 219325cf1a30Sjl nlp->prev = tl; 219425cf1a30Sjl kmem_free(ml, sizeof (struct memlist)); 219525cf1a30Sjl ml = tl; 219625cf1a30Sjl } 219725cf1a30Sjl } 219825cf1a30Sjl } 219925cf1a30Sjl } 220025cf1a30Sjl 220125cf1a30Sjl return (mlist); 220225cf1a30Sjl } 220325cf1a30Sjl 220425cf1a30Sjl static void 220525cf1a30Sjl mc_get_mlist(mc_opl_t *mcp) 220625cf1a30Sjl { 220725cf1a30Sjl struct memlist *mlist; 220825cf1a30Sjl 220925cf1a30Sjl memlist_read_lock(); 221025cf1a30Sjl mlist = mc_memlist_dup(phys_install); 221125cf1a30Sjl memlist_read_unlock(); 221225cf1a30Sjl 221325cf1a30Sjl if (mlist) { 221425cf1a30Sjl mlist = mc_memlist_del_span(mlist, 0ull, mcp->mc_start_address); 221525cf1a30Sjl } 221625cf1a30Sjl 221725cf1a30Sjl if (mlist) { 221825cf1a30Sjl uint64_t startpa, endpa; 221925cf1a30Sjl 222025cf1a30Sjl startpa = mcp->mc_start_address + mcp->mc_size; 222125cf1a30Sjl endpa = ptob(physmax + 1); 222225cf1a30Sjl if (endpa > startpa) { 222325cf1a30Sjl mlist = mc_memlist_del_span(mlist, 222425cf1a30Sjl startpa, endpa - startpa); 222525cf1a30Sjl } 222625cf1a30Sjl } 222725cf1a30Sjl 222825cf1a30Sjl if (mlist) { 222925cf1a30Sjl mcp->mlist = mlist; 223025cf1a30Sjl } 223125cf1a30Sjl } 223225cf1a30Sjl 223325cf1a30Sjl int 223425cf1a30Sjl mc_board_add(mc_opl_t *mcp) 223525cf1a30Sjl { 223625cf1a30Sjl struct mc_addr_spec *macaddr; 22370cc8ae86Sav cs_status_t *cs_status; 22380cc8ae86Sav int len, len1, i, bk, cc; 223925cf1a30Sjl mc_addr_info_t maddr; 224025cf1a30Sjl uint32_t mirr; 22410cc8ae86Sav int nbanks = 0; 22420cc8ae86Sav uint64_t nbytes = 0; 224325cf1a30Sjl 224425cf1a30Sjl /* 224525cf1a30Sjl * Get configurations from "pseudo-mc" node which includes: 224625cf1a30Sjl * board# : LSB number 224725cf1a30Sjl * mac-addr : physical base address of MAC registers 224825cf1a30Sjl * csX-mac-pa-trans-table: translation table from DIMM address 224925cf1a30Sjl * to physical address or vice versa. 225025cf1a30Sjl */ 225125cf1a30Sjl mcp->mc_board_num = (int)ddi_getprop(DDI_DEV_T_ANY, mcp->mc_dip, 225225cf1a30Sjl DDI_PROP_DONTPASS, "board#", -1); 225325cf1a30Sjl 22540cc8ae86Sav if (mcp->mc_board_num == -1) { 22550cc8ae86Sav return (DDI_FAILURE); 22560cc8ae86Sav } 22570cc8ae86Sav 225825cf1a30Sjl /* 225925cf1a30Sjl * Get start address in this CAB. It can be gotten from 226025cf1a30Sjl * "sb-mem-ranges" property. 226125cf1a30Sjl */ 226225cf1a30Sjl 226325cf1a30Sjl if (get_base_address(mcp) == DDI_FAILURE) { 226425cf1a30Sjl return (DDI_FAILURE); 226525cf1a30Sjl } 226625cf1a30Sjl /* get mac-pa trans tables */ 226725cf1a30Sjl for (i = 0; i < MC_TT_CS; i++) { 226825cf1a30Sjl len = MC_TT_ENTRIES; 226925cf1a30Sjl cc = ddi_getlongprop_buf(DDI_DEV_T_ANY, mcp->mc_dip, 227025cf1a30Sjl DDI_PROP_DONTPASS, mc_tbl_name[i], 227125cf1a30Sjl (caddr_t)mcp->mc_trans_table[i], &len); 227225cf1a30Sjl 227325cf1a30Sjl if (cc != DDI_SUCCESS) { 227425cf1a30Sjl bzero(mcp->mc_trans_table[i], MC_TT_ENTRIES); 227525cf1a30Sjl } 227625cf1a30Sjl } 227725cf1a30Sjl mcp->mlist = NULL; 227825cf1a30Sjl 227925cf1a30Sjl mc_get_mlist(mcp); 228025cf1a30Sjl 228125cf1a30Sjl /* initialize bank informations */ 228225cf1a30Sjl cc = ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS, 228325cf1a30Sjl "mc-addr", (caddr_t)&macaddr, &len); 228425cf1a30Sjl if (cc != DDI_SUCCESS) { 228525cf1a30Sjl cmn_err(CE_WARN, "Cannot get mc-addr. err=%d\n", cc); 228625cf1a30Sjl return (DDI_FAILURE); 228725cf1a30Sjl } 228825cf1a30Sjl 22890cc8ae86Sav cc = ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS, 22900cc8ae86Sav "cs-status", (caddr_t)&cs_status, &len1); 229125cf1a30Sjl 22920cc8ae86Sav if (cc != DDI_SUCCESS) { 22930cc8ae86Sav if (len > 0) 22940cc8ae86Sav kmem_free(macaddr, len); 22950cc8ae86Sav cmn_err(CE_WARN, "Cannot get cs-status. err=%d\n", cc); 22960cc8ae86Sav return (DDI_FAILURE); 22970cc8ae86Sav } 229825cf1a30Sjl 22990cc8ae86Sav mutex_init(&mcp->mc_lock, NULL, MUTEX_DRIVER, NULL); 23000cc8ae86Sav 23010cc8ae86Sav for (i = 0; i < len1 / sizeof (cs_status_t); i++) { 23020cc8ae86Sav nbytes += ((uint64_t)cs_status[i].cs_avail_hi << 32) | 23030cc8ae86Sav ((uint64_t)cs_status[i].cs_avail_low); 23040cc8ae86Sav } 23050cc8ae86Sav if (len1 > 0) 23060cc8ae86Sav kmem_free(cs_status, len1); 23070cc8ae86Sav nbanks = len / sizeof (struct mc_addr_spec); 23080cc8ae86Sav 23090cc8ae86Sav if (nbanks > 0) 23100cc8ae86Sav nbytes /= nbanks; 23110cc8ae86Sav else { 23120cc8ae86Sav /* No need to free macaddr because len must be 0 */ 23130cc8ae86Sav mcp->mc_status |= MC_MEMORYLESS; 23140cc8ae86Sav return (DDI_SUCCESS); 23150cc8ae86Sav } 23160cc8ae86Sav 23170cc8ae86Sav for (i = 0; i < BANKNUM_PER_SB; i++) { 23180cc8ae86Sav mcp->mc_scf_retry[i] = 0; 23190cc8ae86Sav mcp->mc_period[i] = 0; 23200cc8ae86Sav mcp->mc_speedup_period[i] = 0; 23210cc8ae86Sav } 23220cc8ae86Sav 23230cc8ae86Sav /* 23240cc8ae86Sav * Get the memory size here. Let it be B (bytes). 23250cc8ae86Sav * Let T be the time in u.s. to scan 64 bytes. 23260cc8ae86Sav * If we want to complete 1 round of scanning in P seconds. 23270cc8ae86Sav * 23280cc8ae86Sav * B * T * 10^(-6) = P 23290cc8ae86Sav * --------------- 23300cc8ae86Sav * 64 23310cc8ae86Sav * 23320cc8ae86Sav * T = P * 64 * 10^6 23330cc8ae86Sav * ------------- 23340cc8ae86Sav * B 23350cc8ae86Sav * 23360cc8ae86Sav * = P * 64 * 10^6 23370cc8ae86Sav * ------------- 23380cc8ae86Sav * B 23390cc8ae86Sav * 23400cc8ae86Sav * The timing bits are set in PTRL_CNTL[28:26] where 23410cc8ae86Sav * 23420cc8ae86Sav * 0 - 1 m.s 23430cc8ae86Sav * 1 - 512 u.s. 23440cc8ae86Sav * 10 - 256 u.s. 23450cc8ae86Sav * 11 - 128 u.s. 23460cc8ae86Sav * 100 - 64 u.s. 23470cc8ae86Sav * 101 - 32 u.s. 23480cc8ae86Sav * 110 - 0 u.s. 23490cc8ae86Sav * 111 - reserved. 23500cc8ae86Sav * 23510cc8ae86Sav * 23520cc8ae86Sav * a[0] = 110, a[1] = 101, ... a[6] = 0 23530cc8ae86Sav * 23540cc8ae86Sav * cs-status property is int x 7 23550cc8ae86Sav * 0 - cs# 23560cc8ae86Sav * 1 - cs-status 23570cc8ae86Sav * 2 - cs-avail.hi 23580cc8ae86Sav * 3 - cs-avail.lo 23590cc8ae86Sav * 4 - dimm-capa.hi 23600cc8ae86Sav * 5 - dimm-capa.lo 23610cc8ae86Sav * 6 - #of dimms 23620cc8ae86Sav */ 23630cc8ae86Sav 23640cc8ae86Sav if (nbytes > 0) { 23650cc8ae86Sav int i; 23660cc8ae86Sav uint64_t ms; 23670cc8ae86Sav ms = ((uint64_t)mc_scan_period * 64 * 1000000)/nbytes; 23680cc8ae86Sav mcp->mc_speed = mc_scan_speeds[MC_MAX_SPEEDS - 1].mc_speeds; 23690cc8ae86Sav for (i = 0; i < MC_MAX_SPEEDS - 1; i++) { 23700cc8ae86Sav if (ms < mc_scan_speeds[i + 1].mc_period) { 23710cc8ae86Sav mcp->mc_speed = mc_scan_speeds[i].mc_speeds; 23720cc8ae86Sav break; 23730cc8ae86Sav } 23740cc8ae86Sav } 23750cc8ae86Sav } else 23760cc8ae86Sav mcp->mc_speed = 0; 23770cc8ae86Sav 23780cc8ae86Sav 23790cc8ae86Sav for (i = 0; i < len / sizeof (struct mc_addr_spec); i++) { 23800cc8ae86Sav struct mc_bank *bankp; 23810cc8ae86Sav uint32_t reg; 23820cc8ae86Sav 23830cc8ae86Sav /* 23840cc8ae86Sav * setup bank 23850cc8ae86Sav */ 23860cc8ae86Sav bk = macaddr[i].bank; 23870cc8ae86Sav bankp = &(mcp->mc_bank[bk]); 23880cc8ae86Sav bankp->mcb_status = BANK_INSTALLED; 23890cc8ae86Sav bankp->mcb_reg_base = REGS_PA(macaddr, i); 23900cc8ae86Sav 23910cc8ae86Sav reg = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bk)); 23920cc8ae86Sav bankp->mcb_ptrl_cntl = (reg & MAC_CNTL_PTRL_PRESERVE_BITS); 239325cf1a30Sjl 239425cf1a30Sjl /* 239525cf1a30Sjl * check if mirror mode 239625cf1a30Sjl */ 239725cf1a30Sjl mirr = LD_MAC_REG(MAC_MIRR(mcp, bk)); 239825cf1a30Sjl 239925cf1a30Sjl if (mirr & MAC_MIRR_MIRROR_MODE) { 240025cf1a30Sjl MC_LOG("Mirror -> /LSB%d/B%d\n", 240125cf1a30Sjl mcp->mc_board_num, bk); 240225cf1a30Sjl bankp->mcb_status |= BANK_MIRROR_MODE; 240325cf1a30Sjl /* 240425cf1a30Sjl * The following bit is only used for 240525cf1a30Sjl * error injection. We should clear it 240625cf1a30Sjl */ 240725cf1a30Sjl if (mirr & MAC_MIRR_BANK_EXCLUSIVE) 240825cf1a30Sjl ST_MAC_REG(MAC_MIRR(mcp, bk), 240925cf1a30Sjl 0); 241025cf1a30Sjl } 241125cf1a30Sjl 241225cf1a30Sjl /* 241325cf1a30Sjl * restart if not mirror mode or the other bank 241425cf1a30Sjl * of the mirror is not running 241525cf1a30Sjl */ 241625cf1a30Sjl if (!(mirr & MAC_MIRR_MIRROR_MODE) || 241725cf1a30Sjl !(mcp->mc_bank[bk^1].mcb_status & 241825cf1a30Sjl BANK_PTRL_RUNNING)) { 241925cf1a30Sjl MC_LOG("Starting up /LSB%d/B%d\n", 242025cf1a30Sjl mcp->mc_board_num, bk); 242125cf1a30Sjl get_ptrl_start_address(mcp, bk, &maddr.mi_maddr); 24220cc8ae86Sav maddr.mi_maddr.ma_bd = mcp->mc_board_num; 24230cc8ae86Sav maddr.mi_maddr.ma_bank = bk; 24240cc8ae86Sav maddr.mi_maddr.ma_dimm_addr = 0; 24250cc8ae86Sav maddr.mi_valid = 0; 242625cf1a30Sjl maddr.mi_advance = 0; 242725cf1a30Sjl restart_patrol(mcp, bk, &maddr); 242825cf1a30Sjl } else { 242925cf1a30Sjl MC_LOG("Not starting up /LSB%d/B%d\n", 243025cf1a30Sjl mcp->mc_board_num, bk); 243125cf1a30Sjl } 243225cf1a30Sjl bankp->mcb_status |= BANK_PTRL_RUNNING; 243325cf1a30Sjl } 24340cc8ae86Sav if (len > 0) 24350cc8ae86Sav kmem_free(macaddr, len); 24360cc8ae86Sav 24370cc8ae86Sav mcp->mc_dimm_list = mc_get_dimm_list(mcp); 243825cf1a30Sjl 243925cf1a30Sjl /* 244025cf1a30Sjl * set interval in HZ. 244125cf1a30Sjl */ 244225cf1a30Sjl mcp->mc_last_error = 0; 244325cf1a30Sjl 244425cf1a30Sjl /* restart memory patrol checking */ 244525cf1a30Sjl mcp->mc_status |= MC_POLL_RUNNING; 244625cf1a30Sjl 244725cf1a30Sjl return (DDI_SUCCESS); 244825cf1a30Sjl } 244925cf1a30Sjl 245025cf1a30Sjl int 245125cf1a30Sjl mc_board_del(mc_opl_t *mcp) 245225cf1a30Sjl { 245325cf1a30Sjl int i; 245425cf1a30Sjl scf_log_t *p; 245525cf1a30Sjl 245625cf1a30Sjl /* 245725cf1a30Sjl * cleanup mac state 245825cf1a30Sjl */ 245925cf1a30Sjl mutex_enter(&mcp->mc_lock); 24600cc8ae86Sav if (mcp->mc_status & MC_MEMORYLESS) { 24610cc8ae86Sav mutex_exit(&mcp->mc_lock); 24620cc8ae86Sav mutex_destroy(&mcp->mc_lock); 24630cc8ae86Sav return (DDI_SUCCESS); 24640cc8ae86Sav } 246525cf1a30Sjl for (i = 0; i < BANKNUM_PER_SB; i++) { 246625cf1a30Sjl if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) { 246725cf1a30Sjl mcp->mc_bank[i].mcb_status &= ~BANK_INSTALLED; 246825cf1a30Sjl } 246925cf1a30Sjl } 247025cf1a30Sjl 247125cf1a30Sjl /* stop memory patrol checking */ 247225cf1a30Sjl if (mcp->mc_status & MC_POLL_RUNNING) { 247325cf1a30Sjl mcp->mc_status &= ~MC_POLL_RUNNING; 247425cf1a30Sjl } 247525cf1a30Sjl 247625cf1a30Sjl /* just throw away all the scf logs */ 24770cc8ae86Sav for (i = 0; i < BANKNUM_PER_SB; i++) { 24780cc8ae86Sav while ((p = mcp->mc_scf_log[i]) != NULL) { 24790cc8ae86Sav mcp->mc_scf_log[i] = p->sl_next; 24800cc8ae86Sav mcp->mc_scf_total[i]--; 248125cf1a30Sjl kmem_free(p, sizeof (scf_log_t)); 24820cc8ae86Sav } 248325cf1a30Sjl } 248425cf1a30Sjl 248525cf1a30Sjl if (mcp->mlist) 248625cf1a30Sjl mc_memlist_delete(mcp->mlist); 248725cf1a30Sjl 24880cc8ae86Sav if (mcp->mc_dimm_list) 24890cc8ae86Sav mc_free_dimm_list(mcp->mc_dimm_list); 24900cc8ae86Sav 249125cf1a30Sjl mutex_exit(&mcp->mc_lock); 249225cf1a30Sjl 249325cf1a30Sjl mutex_destroy(&mcp->mc_lock); 249425cf1a30Sjl return (DDI_SUCCESS); 249525cf1a30Sjl } 249625cf1a30Sjl 249725cf1a30Sjl int 249825cf1a30Sjl mc_suspend(mc_opl_t *mcp, uint32_t flag) 249925cf1a30Sjl { 250025cf1a30Sjl /* stop memory patrol checking */ 250125cf1a30Sjl mutex_enter(&mcp->mc_lock); 25020cc8ae86Sav if (mcp->mc_status & MC_MEMORYLESS) { 25030cc8ae86Sav mutex_exit(&mcp->mc_lock); 25040cc8ae86Sav return (DDI_SUCCESS); 25050cc8ae86Sav } 25060cc8ae86Sav 250725cf1a30Sjl if (mcp->mc_status & MC_POLL_RUNNING) { 250825cf1a30Sjl mcp->mc_status &= ~MC_POLL_RUNNING; 250925cf1a30Sjl } 251025cf1a30Sjl mcp->mc_status |= flag; 251125cf1a30Sjl mutex_exit(&mcp->mc_lock); 251225cf1a30Sjl 251325cf1a30Sjl return (DDI_SUCCESS); 251425cf1a30Sjl } 251525cf1a30Sjl 251625cf1a30Sjl /* caller must clear the SUSPEND bits or this will do nothing */ 251725cf1a30Sjl 251825cf1a30Sjl int 251925cf1a30Sjl mc_resume(mc_opl_t *mcp, uint32_t flag) 252025cf1a30Sjl { 252125cf1a30Sjl int i; 252225cf1a30Sjl uint64_t basepa; 252325cf1a30Sjl 252425cf1a30Sjl mutex_enter(&mcp->mc_lock); 25250cc8ae86Sav if (mcp->mc_status & MC_MEMORYLESS) { 25260cc8ae86Sav mutex_exit(&mcp->mc_lock); 25270cc8ae86Sav return (DDI_SUCCESS); 25280cc8ae86Sav } 252925cf1a30Sjl basepa = mcp->mc_start_address; 253025cf1a30Sjl if (get_base_address(mcp) == DDI_FAILURE) { 253125cf1a30Sjl mutex_exit(&mcp->mc_lock); 253225cf1a30Sjl return (DDI_FAILURE); 253325cf1a30Sjl } 253425cf1a30Sjl 253525cf1a30Sjl if (basepa != mcp->mc_start_address) { 253625cf1a30Sjl if (mcp->mlist) 253725cf1a30Sjl mc_memlist_delete(mcp->mlist); 253825cf1a30Sjl mcp->mlist = NULL; 253925cf1a30Sjl mc_get_mlist(mcp); 254025cf1a30Sjl } 254125cf1a30Sjl 254225cf1a30Sjl mcp->mc_status &= ~flag; 254325cf1a30Sjl 254425cf1a30Sjl if (mcp->mc_status & (MC_SOFT_SUSPENDED | MC_DRIVER_SUSPENDED)) { 254525cf1a30Sjl mutex_exit(&mcp->mc_lock); 254625cf1a30Sjl return (DDI_SUCCESS); 254725cf1a30Sjl } 254825cf1a30Sjl 254925cf1a30Sjl if (!(mcp->mc_status & MC_POLL_RUNNING)) { 255025cf1a30Sjl /* restart memory patrol checking */ 255125cf1a30Sjl mcp->mc_status |= MC_POLL_RUNNING; 255225cf1a30Sjl for (i = 0; i < BANKNUM_PER_SB; i++) { 255325cf1a30Sjl if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) { 255425cf1a30Sjl restart_patrol(mcp, i, NULL); 255525cf1a30Sjl } 255625cf1a30Sjl } 255725cf1a30Sjl } 255825cf1a30Sjl mutex_exit(&mcp->mc_lock); 255925cf1a30Sjl 256025cf1a30Sjl return (DDI_SUCCESS); 256125cf1a30Sjl } 256225cf1a30Sjl 256325cf1a30Sjl static mc_opl_t * 256425cf1a30Sjl mc_pa_to_mcp(uint64_t pa) 256525cf1a30Sjl { 25660cc8ae86Sav mc_opl_t *mcp; 25670cc8ae86Sav int i; 25680cc8ae86Sav 256925cf1a30Sjl ASSERT(MUTEX_HELD(&mcmutex)); 25700cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 25710cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 25720cc8ae86Sav continue; 257325cf1a30Sjl /* if mac patrol is suspended, we cannot rely on it */ 25740cc8ae86Sav if (!(mcp->mc_status & MC_POLL_RUNNING) || 25750cc8ae86Sav (mcp->mc_status & MC_SOFT_SUSPENDED)) 257625cf1a30Sjl continue; 25770cc8ae86Sav if ((mcp->mc_start_address <= pa) && 25780cc8ae86Sav (pa < (mcp->mc_start_address + mcp->mc_size))) { 25790cc8ae86Sav return (mcp); 258025cf1a30Sjl } 258125cf1a30Sjl } 258225cf1a30Sjl return (NULL); 258325cf1a30Sjl } 258425cf1a30Sjl 258525cf1a30Sjl /* 258625cf1a30Sjl * Get Physical Board number from Logical one. 258725cf1a30Sjl */ 258825cf1a30Sjl static int 258925cf1a30Sjl mc_opl_get_physical_board(int sb) 259025cf1a30Sjl { 259125cf1a30Sjl if (&opl_get_physical_board) { 259225cf1a30Sjl return (opl_get_physical_board(sb)); 259325cf1a30Sjl } 259425cf1a30Sjl 259525cf1a30Sjl cmn_err(CE_NOTE, "!opl_get_physical_board() not loaded\n"); 259625cf1a30Sjl return (-1); 259725cf1a30Sjl } 259825cf1a30Sjl 259925cf1a30Sjl /* ARGSUSED */ 260025cf1a30Sjl int 260125cf1a30Sjl mc_get_mem_unum(int synd_code, uint64_t flt_addr, char *buf, int buflen, 260225cf1a30Sjl int *lenp) 260325cf1a30Sjl { 26040cc8ae86Sav int i; 260525cf1a30Sjl int sb; 26060cc8ae86Sav int bank; 26070cc8ae86Sav mc_opl_t *mcp; 26080cc8ae86Sav char memb_num; 260925cf1a30Sjl 261025cf1a30Sjl mutex_enter(&mcmutex); 261125cf1a30Sjl 261225cf1a30Sjl if (((mcp = mc_pa_to_mcp(flt_addr)) == NULL) || 261325cf1a30Sjl (!pa_is_valid(mcp, flt_addr))) { 261425cf1a30Sjl mutex_exit(&mcmutex); 261525cf1a30Sjl if (snprintf(buf, buflen, "UNKNOWN") >= buflen) { 261625cf1a30Sjl return (ENOSPC); 261725cf1a30Sjl } else { 261825cf1a30Sjl if (lenp) 261925cf1a30Sjl *lenp = strlen(buf); 262025cf1a30Sjl } 262125cf1a30Sjl return (0); 262225cf1a30Sjl } 262325cf1a30Sjl 262425cf1a30Sjl bank = pa_to_bank(mcp, flt_addr - mcp->mc_start_address); 262525cf1a30Sjl sb = mc_opl_get_physical_board(mcp->mc_board_num); 262625cf1a30Sjl 262725cf1a30Sjl if (sb == -1) { 262825cf1a30Sjl mutex_exit(&mcmutex); 262925cf1a30Sjl return (ENXIO); 263025cf1a30Sjl } 263125cf1a30Sjl 26320cc8ae86Sav if (plat_model == MODEL_DC) { 26330cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(0, bank, 0); 26340cc8ae86Sav snprintf(buf, buflen, "/%s%02d/MEM%s MEM%s MEM%s MEM%s", 26350cc8ae86Sav model_names[plat_model].unit_name, sb, 26360cc8ae86Sav mc_dc_dimm_unum_table[i], mc_dc_dimm_unum_table[i + 1], 26370cc8ae86Sav mc_dc_dimm_unum_table[i + 2], mc_dc_dimm_unum_table[i + 3]); 263825cf1a30Sjl } else { 26390cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(sb, bank, 0); 26400cc8ae86Sav memb_num = mc_ff_dimm_unum_table[i][0]; 26410cc8ae86Sav snprintf(buf, buflen, "/%s/%s%c/MEM%s MEM%s MEM%s MEM%s", 26420cc8ae86Sav model_names[plat_model].unit_name, 26430cc8ae86Sav model_names[plat_model].mem_name, memb_num, 26440cc8ae86Sav &mc_ff_dimm_unum_table[i][1], 26450cc8ae86Sav 26460cc8ae86Sav &mc_ff_dimm_unum_table[i + 1][1], 26470cc8ae86Sav &mc_ff_dimm_unum_table[i + 2][1], 26480cc8ae86Sav &mc_ff_dimm_unum_table[i + 3][1]); 26490cc8ae86Sav } 26500cc8ae86Sav if (lenp) { 26510cc8ae86Sav *lenp = strlen(buf); 265225cf1a30Sjl } 265325cf1a30Sjl mutex_exit(&mcmutex); 265425cf1a30Sjl return (0); 265525cf1a30Sjl } 265625cf1a30Sjl 265725cf1a30Sjl int 26580cc8ae86Sav opl_mc_suspend(void) 265925cf1a30Sjl { 266025cf1a30Sjl mc_opl_t *mcp; 26610cc8ae86Sav int i; 266225cf1a30Sjl 266325cf1a30Sjl mutex_enter(&mcmutex); 26640cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 26650cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 26660cc8ae86Sav continue; 26670cc8ae86Sav mc_suspend(mcp, MC_SOFT_SUSPENDED); 266825cf1a30Sjl } 266925cf1a30Sjl mutex_exit(&mcmutex); 26700cc8ae86Sav 267125cf1a30Sjl return (0); 267225cf1a30Sjl } 267325cf1a30Sjl 267425cf1a30Sjl int 26750cc8ae86Sav opl_mc_resume(void) 267625cf1a30Sjl { 267725cf1a30Sjl mc_opl_t *mcp; 26780cc8ae86Sav int i; 267925cf1a30Sjl 268025cf1a30Sjl mutex_enter(&mcmutex); 26810cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 26820cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 26830cc8ae86Sav continue; 26840cc8ae86Sav mc_resume(mcp, MC_SOFT_SUSPENDED); 268525cf1a30Sjl } 268625cf1a30Sjl mutex_exit(&mcmutex); 26870cc8ae86Sav 268825cf1a30Sjl return (0); 268925cf1a30Sjl } 269025cf1a30Sjl static void 269125cf1a30Sjl insert_mcp(mc_opl_t *mcp) 269225cf1a30Sjl { 269325cf1a30Sjl mutex_enter(&mcmutex); 26940cc8ae86Sav if (mc_instances[mcp->mc_board_num] != NULL) { 26950cc8ae86Sav MC_LOG("mc-opl instance for board# %d already exists\n", 26960cc8ae86Sav mcp->mc_board_num); 26970cc8ae86Sav } 26980cc8ae86Sav mc_instances[mcp->mc_board_num] = mcp; 269925cf1a30Sjl mutex_exit(&mcmutex); 270025cf1a30Sjl } 270125cf1a30Sjl 270225cf1a30Sjl static void 270325cf1a30Sjl delete_mcp(mc_opl_t *mcp) 270425cf1a30Sjl { 27050cc8ae86Sav mutex_enter(&mcmutex); 27060cc8ae86Sav mc_instances[mcp->mc_board_num] = 0; 27070cc8ae86Sav mutex_exit(&mcmutex); 270825cf1a30Sjl } 270925cf1a30Sjl 271025cf1a30Sjl /* Error injection interface */ 271125cf1a30Sjl 2712cfb9e062Shyw static void 2713cfb9e062Shyw mc_lock_va(uint64_t pa, caddr_t new_va) 2714cfb9e062Shyw { 2715cfb9e062Shyw tte_t tte; 2716cfb9e062Shyw 2717cfb9e062Shyw vtag_flushpage(new_va, KCONTEXT); 2718cfb9e062Shyw sfmmu_memtte(&tte, pa >> PAGESHIFT, 2719cfb9e062Shyw PROC_DATA|HAT_NOSYNC, TTE8K); 2720cfb9e062Shyw tte.tte_intlo |= TTE_LCK_INT; 2721cfb9e062Shyw sfmmu_dtlb_ld_kva(new_va, &tte); 2722cfb9e062Shyw } 2723cfb9e062Shyw 2724cfb9e062Shyw static void 2725cfb9e062Shyw mc_unlock_va(caddr_t va) 2726cfb9e062Shyw { 2727cfb9e062Shyw vtag_flushpage(va, (uint64_t)ksfmmup); 2728cfb9e062Shyw } 2729cfb9e062Shyw 273025cf1a30Sjl /* ARGSUSED */ 273125cf1a30Sjl int 273225cf1a30Sjl mc_inject_error(int error_type, uint64_t pa, uint32_t flags) 273325cf1a30Sjl { 273425cf1a30Sjl mc_opl_t *mcp; 273525cf1a30Sjl int bank; 273625cf1a30Sjl uint32_t dimm_addr; 273725cf1a30Sjl uint32_t cntl; 273825cf1a30Sjl mc_addr_info_t maddr; 273925cf1a30Sjl uint32_t data, stat; 274025cf1a30Sjl int both_sides = 0; 274125cf1a30Sjl uint64_t pa0; 2742cfb9e062Shyw int extra_injection_needed = 0; 274325cf1a30Sjl extern void cpu_flush_ecache(void); 274425cf1a30Sjl 274525cf1a30Sjl MC_LOG("HW mc_inject_error(%x, %lx, %x)\n", error_type, pa, flags); 274625cf1a30Sjl 274725cf1a30Sjl mutex_enter(&mcmutex); 274825cf1a30Sjl if ((mcp = mc_pa_to_mcp(pa)) == NULL) { 274925cf1a30Sjl mutex_exit(&mcmutex); 275025cf1a30Sjl MC_LOG("mc_inject_error: invalid pa\n"); 275125cf1a30Sjl return (ENOTSUP); 275225cf1a30Sjl } 275325cf1a30Sjl 275425cf1a30Sjl mutex_enter(&mcp->mc_lock); 275525cf1a30Sjl mutex_exit(&mcmutex); 275625cf1a30Sjl 275725cf1a30Sjl if (mcp->mc_status & (MC_SOFT_SUSPENDED | MC_DRIVER_SUSPENDED)) { 275825cf1a30Sjl mutex_exit(&mcp->mc_lock); 275925cf1a30Sjl MC_LOG("mc-opl has been suspended. No error injection.\n"); 276025cf1a30Sjl return (EBUSY); 276125cf1a30Sjl } 276225cf1a30Sjl 276325cf1a30Sjl /* convert pa to offset within the board */ 276425cf1a30Sjl MC_LOG("pa %lx, offset %lx\n", pa, pa - mcp->mc_start_address); 276525cf1a30Sjl 276625cf1a30Sjl if (!pa_is_valid(mcp, pa)) { 276725cf1a30Sjl mutex_exit(&mcp->mc_lock); 276825cf1a30Sjl return (EINVAL); 276925cf1a30Sjl } 277025cf1a30Sjl 277125cf1a30Sjl pa0 = pa - mcp->mc_start_address; 277225cf1a30Sjl 277325cf1a30Sjl bank = pa_to_bank(mcp, pa0); 277425cf1a30Sjl 277525cf1a30Sjl if (flags & MC_INJECT_FLAG_OTHER) 277625cf1a30Sjl bank = bank ^ 1; 277725cf1a30Sjl 277825cf1a30Sjl if (MC_INJECT_MIRROR(error_type) && !IS_MIRROR(mcp, bank)) { 277925cf1a30Sjl mutex_exit(&mcp->mc_lock); 278025cf1a30Sjl MC_LOG("Not mirror mode\n"); 278125cf1a30Sjl return (EINVAL); 278225cf1a30Sjl } 278325cf1a30Sjl 278425cf1a30Sjl dimm_addr = pa_to_dimm(mcp, pa0); 278525cf1a30Sjl 2786cfb9e062Shyw MC_LOG("injecting error to /LSB%d/B%d/%x\n", 278725cf1a30Sjl mcp->mc_board_num, bank, dimm_addr); 278825cf1a30Sjl 278925cf1a30Sjl 279025cf1a30Sjl switch (error_type) { 279125cf1a30Sjl case MC_INJECT_INTERMITTENT_MCE: 279225cf1a30Sjl case MC_INJECT_PERMANENT_MCE: 279325cf1a30Sjl case MC_INJECT_MUE: 279425cf1a30Sjl both_sides = 1; 279525cf1a30Sjl } 279625cf1a30Sjl 279725cf1a30Sjl if (flags & MC_INJECT_FLAG_RESET) 279825cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank), 0); 279925cf1a30Sjl 280025cf1a30Sjl ST_MAC_REG(MAC_EG_ADD(mcp, bank), dimm_addr & MAC_EG_ADD_MASK); 280125cf1a30Sjl 280225cf1a30Sjl if (both_sides) { 280325cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), 0); 280425cf1a30Sjl ST_MAC_REG(MAC_EG_ADD(mcp, bank^1), 280525cf1a30Sjl dimm_addr & MAC_EG_ADD_MASK); 280625cf1a30Sjl } 280725cf1a30Sjl 280825cf1a30Sjl switch (error_type) { 280925cf1a30Sjl case MC_INJECT_SUE: 2810cfb9e062Shyw extra_injection_needed = 1; 2811cfb9e062Shyw /*FALLTHROUGH*/ 2812cfb9e062Shyw case MC_INJECT_UE: 281325cf1a30Sjl case MC_INJECT_MUE: 281425cf1a30Sjl if (flags & MC_INJECT_FLAG_PATH) { 281525cf1a30Sjl cntl = MAC_EG_ADD_FIX 281625cf1a30Sjl |MAC_EG_FORCE_READ00|MAC_EG_FORCE_READ16 28170cc8ae86Sav |MAC_EG_RDERR_ONCE; 281825cf1a30Sjl } else { 281925cf1a30Sjl cntl = MAC_EG_ADD_FIX|MAC_EG_FORCE_DERR00 282025cf1a30Sjl |MAC_EG_FORCE_DERR16|MAC_EG_DERR_ONCE; 282125cf1a30Sjl } 282225cf1a30Sjl flags |= MC_INJECT_FLAG_ST; 282325cf1a30Sjl break; 282425cf1a30Sjl case MC_INJECT_INTERMITTENT_CE: 282525cf1a30Sjl case MC_INJECT_INTERMITTENT_MCE: 282625cf1a30Sjl if (flags & MC_INJECT_FLAG_PATH) { 282725cf1a30Sjl cntl = MAC_EG_ADD_FIX 282825cf1a30Sjl |MAC_EG_FORCE_READ00 28290cc8ae86Sav |MAC_EG_RDERR_ONCE; 283025cf1a30Sjl } else { 283125cf1a30Sjl cntl = MAC_EG_ADD_FIX 283225cf1a30Sjl |MAC_EG_FORCE_DERR16 283325cf1a30Sjl |MAC_EG_DERR_ONCE; 283425cf1a30Sjl } 2835cfb9e062Shyw extra_injection_needed = 1; 283625cf1a30Sjl flags |= MC_INJECT_FLAG_ST; 283725cf1a30Sjl break; 283825cf1a30Sjl case MC_INJECT_PERMANENT_CE: 283925cf1a30Sjl case MC_INJECT_PERMANENT_MCE: 284025cf1a30Sjl if (flags & MC_INJECT_FLAG_PATH) { 284125cf1a30Sjl cntl = MAC_EG_ADD_FIX 284225cf1a30Sjl |MAC_EG_FORCE_READ00 28430cc8ae86Sav |MAC_EG_RDERR_ALWAYS; 284425cf1a30Sjl } else { 284525cf1a30Sjl cntl = MAC_EG_ADD_FIX 284625cf1a30Sjl |MAC_EG_FORCE_DERR16 284725cf1a30Sjl |MAC_EG_DERR_ALWAYS; 284825cf1a30Sjl } 284925cf1a30Sjl flags |= MC_INJECT_FLAG_ST; 285025cf1a30Sjl break; 285125cf1a30Sjl case MC_INJECT_CMPE: 285225cf1a30Sjl data = 0xabcdefab; 285325cf1a30Sjl stphys(pa, data); 285425cf1a30Sjl cpu_flush_ecache(); 285525cf1a30Sjl MC_LOG("CMPE: writing data %x to %lx\n", data, pa); 285625cf1a30Sjl ST_MAC_REG(MAC_MIRR(mcp, bank), MAC_MIRR_BANK_EXCLUSIVE); 285725cf1a30Sjl stphys(pa, data ^ 0xffffffff); 285825cf1a30Sjl cpu_flush_ecache(); 285925cf1a30Sjl ST_MAC_REG(MAC_MIRR(mcp, bank), 0); 286025cf1a30Sjl MC_LOG("CMPE: write new data %xto %lx\n", data, pa); 286125cf1a30Sjl cntl = 0; 286225cf1a30Sjl break; 286325cf1a30Sjl case MC_INJECT_NOP: 286425cf1a30Sjl cntl = 0; 286525cf1a30Sjl break; 286625cf1a30Sjl default: 286725cf1a30Sjl MC_LOG("mc_inject_error: invalid option\n"); 286825cf1a30Sjl cntl = 0; 286925cf1a30Sjl } 287025cf1a30Sjl 287125cf1a30Sjl if (cntl) { 287225cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl & MAC_EG_SETUP_MASK); 287325cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl); 287425cf1a30Sjl 287525cf1a30Sjl if (both_sides) { 287625cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl & 287725cf1a30Sjl MAC_EG_SETUP_MASK); 287825cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl); 287925cf1a30Sjl } 288025cf1a30Sjl } 288125cf1a30Sjl 288225cf1a30Sjl /* 288325cf1a30Sjl * For all injection cases except compare error, we 288425cf1a30Sjl * must write to the PA to trigger the error. 288525cf1a30Sjl */ 288625cf1a30Sjl 288725cf1a30Sjl if (flags & MC_INJECT_FLAG_ST) { 288825cf1a30Sjl data = 0xf0e0d0c0; 288925cf1a30Sjl MC_LOG("Writing %x to %lx\n", data, pa); 289025cf1a30Sjl stphys(pa, data); 289125cf1a30Sjl cpu_flush_ecache(); 289225cf1a30Sjl } 289325cf1a30Sjl 289425cf1a30Sjl 289525cf1a30Sjl if (flags & MC_INJECT_FLAG_LD) { 2896cfb9e062Shyw if (flags & MC_INJECT_FLAG_PREFETCH) { 2897cfb9e062Shyw /* 2898cfb9e062Shyw * Use strong prefetch operation to 2899cfb9e062Shyw * inject MI errors. 2900cfb9e062Shyw */ 2901cfb9e062Shyw page_t *pp; 2902cfb9e062Shyw extern void mc_prefetch(caddr_t); 2903cfb9e062Shyw 2904cfb9e062Shyw MC_LOG("prefetch\n"); 2905cfb9e062Shyw 2906cfb9e062Shyw pp = page_numtopp_nolock(pa >> PAGESHIFT); 2907cfb9e062Shyw if (pp != NULL) { 2908cfb9e062Shyw caddr_t va, va1; 2909cfb9e062Shyw 2910cfb9e062Shyw va = ppmapin(pp, PROT_READ|PROT_WRITE, 2911cfb9e062Shyw (caddr_t)-1); 2912cfb9e062Shyw kpreempt_disable(); 2913cfb9e062Shyw mc_lock_va((uint64_t)pa, va); 2914cfb9e062Shyw va1 = va + (pa & (PAGESIZE - 1)); 2915cfb9e062Shyw mc_prefetch(va1); 2916cfb9e062Shyw mc_unlock_va(va); 2917cfb9e062Shyw kpreempt_enable(); 2918cfb9e062Shyw ppmapout(va); 2919cfb9e062Shyw 2920cfb9e062Shyw /* 2921cfb9e062Shyw * For MI errors, we need one extra 2922cfb9e062Shyw * injection for HW patrol to stop. 2923cfb9e062Shyw */ 2924cfb9e062Shyw extra_injection_needed = 1; 292525cf1a30Sjl } else { 2926cfb9e062Shyw cmn_err(CE_WARN, "Cannot find page structure" 2927cfb9e062Shyw " for PA %lx\n", pa); 292825cf1a30Sjl } 292925cf1a30Sjl } else { 293025cf1a30Sjl MC_LOG("Reading from %lx\n", pa); 293125cf1a30Sjl data = ldphys(pa); 293225cf1a30Sjl MC_LOG("data = %x\n", data); 293325cf1a30Sjl } 2934cfb9e062Shyw 2935cfb9e062Shyw if (extra_injection_needed) { 2936cfb9e062Shyw /* 2937cfb9e062Shyw * These are the injection cases where the 2938cfb9e062Shyw * requested injected errors will not cause the HW 2939cfb9e062Shyw * patrol to stop. For these cases, we need to inject 2940cfb9e062Shyw * an extra 'real' PTRL error to force the 2941cfb9e062Shyw * HW patrol to stop so that we can report the 2942cfb9e062Shyw * errors injected. Note that we cannot read 2943cfb9e062Shyw * and report error status while the HW patrol 2944cfb9e062Shyw * is running. 2945cfb9e062Shyw */ 2946cfb9e062Shyw ST_MAC_REG(MAC_EG_CNTL(mcp, bank), 2947cfb9e062Shyw cntl & MAC_EG_SETUP_MASK); 2948cfb9e062Shyw ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl); 2949cfb9e062Shyw 2950cfb9e062Shyw if (both_sides) { 2951cfb9e062Shyw ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl & 2952cfb9e062Shyw MAC_EG_SETUP_MASK); 2953cfb9e062Shyw ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl); 2954cfb9e062Shyw } 2955cfb9e062Shyw data = 0xf0e0d0c0; 2956cfb9e062Shyw MC_LOG("Writing %x to %lx\n", data, pa); 2957cfb9e062Shyw stphys(pa, data); 2958cfb9e062Shyw cpu_flush_ecache(); 2959cfb9e062Shyw } 296025cf1a30Sjl } 296125cf1a30Sjl 296225cf1a30Sjl if (flags & MC_INJECT_FLAG_RESTART) { 296325cf1a30Sjl MC_LOG("Restart patrol\n"); 296425cf1a30Sjl maddr.mi_maddr.ma_bd = mcp->mc_board_num; 296525cf1a30Sjl maddr.mi_maddr.ma_bank = bank; 296625cf1a30Sjl maddr.mi_maddr.ma_dimm_addr = dimm_addr; 296725cf1a30Sjl maddr.mi_valid = 1; 296825cf1a30Sjl maddr.mi_advance = 0; 296925cf1a30Sjl restart_patrol(mcp, bank, &maddr); 297025cf1a30Sjl } 297125cf1a30Sjl 297225cf1a30Sjl if (flags & MC_INJECT_FLAG_POLL) { 29730cc8ae86Sav int running; 297425cf1a30Sjl 297525cf1a30Sjl MC_LOG("Poll patrol error\n"); 297625cf1a30Sjl stat = LD_MAC_REG(MAC_PTRL_STAT(mcp, bank)); 297725cf1a30Sjl cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 29780cc8ae86Sav running = cntl & MAC_CNTL_PTRL_START; 297925cf1a30Sjl 2980cfb9e062Shyw if (!running && 2981cfb9e062Shyw (stat & (MAC_STAT_PTRL_ERRS|MAC_STAT_MI_ERRS))) { 2982cfb9e062Shyw /* 2983cfb9e062Shyw * HW patrol stopped and we have errors to 2984cfb9e062Shyw * report. Do it. 2985cfb9e062Shyw */ 2986cfb9e062Shyw mcp->mc_speedup_period[bank] = 0; 2987cfb9e062Shyw maddr.mi_valid = 0; 2988cfb9e062Shyw maddr.mi_advance = 1; 2989cfb9e062Shyw if (IS_MIRROR(mcp, bank)) 2990cfb9e062Shyw mc_error_handler_mir(mcp, bank, &maddr); 2991cfb9e062Shyw else 2992cfb9e062Shyw mc_error_handler(mcp, bank, &maddr); 2993cfb9e062Shyw 2994cfb9e062Shyw restart_patrol(mcp, bank, &maddr); 2995cfb9e062Shyw } else { 2996cfb9e062Shyw /* 2997cfb9e062Shyw * We are expecting to report injected 2998cfb9e062Shyw * errors but the HW patrol is still running. 2999cfb9e062Shyw * Speed up the scanning 3000cfb9e062Shyw */ 3001cfb9e062Shyw mcp->mc_speedup_period[bank] = 2; 3002cfb9e062Shyw MAC_CMD(mcp, bank, 0); 300325cf1a30Sjl restart_patrol(mcp, bank, NULL); 3004cfb9e062Shyw } 300525cf1a30Sjl } 300625cf1a30Sjl 300725cf1a30Sjl mutex_exit(&mcp->mc_lock); 300825cf1a30Sjl return (0); 300925cf1a30Sjl } 3010cfb9e062Shyw 301125cf1a30Sjl void 301225cf1a30Sjl mc_stphysio(uint64_t pa, uint32_t data) 301325cf1a30Sjl { 301425cf1a30Sjl MC_LOG("0x%x -> pa(%lx)\n", data, pa); 301525cf1a30Sjl stphysio(pa, data); 30160cc8ae86Sav 30170cc8ae86Sav /* force the above write to be processed by mac patrol */ 3018cfb9e062Shyw data = ldphysio(pa); 3019cfb9e062Shyw MC_LOG("pa(%lx) = 0x%x\n", pa, data); 302025cf1a30Sjl } 302125cf1a30Sjl 302225cf1a30Sjl uint32_t 302325cf1a30Sjl mc_ldphysio(uint64_t pa) 302425cf1a30Sjl { 302525cf1a30Sjl uint32_t rv; 302625cf1a30Sjl 302725cf1a30Sjl rv = ldphysio(pa); 302825cf1a30Sjl MC_LOG("pa(%lx) = 0x%x\n", pa, rv); 302925cf1a30Sjl return (rv); 303025cf1a30Sjl } 30310cc8ae86Sav 30320cc8ae86Sav #define isdigit(ch) ((ch) >= '0' && (ch) <= '9') 30330cc8ae86Sav 30340cc8ae86Sav /* 30350cc8ae86Sav * parse_unum_memory -- extract the board number and the DIMM name from 30360cc8ae86Sav * the unum. 30370cc8ae86Sav * 30380cc8ae86Sav * Return 0 for success and non-zero for a failure. 30390cc8ae86Sav */ 30400cc8ae86Sav int 30410cc8ae86Sav parse_unum_memory(char *unum, int *board, char *dname) 30420cc8ae86Sav { 30430cc8ae86Sav char *c; 30440cc8ae86Sav char x, y, z; 30450cc8ae86Sav 30460cc8ae86Sav if ((c = strstr(unum, "CMU")) != NULL) { 30470cc8ae86Sav /* DC Model */ 30480cc8ae86Sav c += 3; 30490cc8ae86Sav *board = (uint8_t)stoi(&c); 30500cc8ae86Sav if ((c = strstr(c, "MEM")) == NULL) { 30510cc8ae86Sav return (1); 30520cc8ae86Sav } 30530cc8ae86Sav c += 3; 30540cc8ae86Sav if (strlen(c) < 3) { 30550cc8ae86Sav return (2); 30560cc8ae86Sav } 30570cc8ae86Sav if ((!isdigit(c[0])) || (!(isdigit(c[1]))) || 30580cc8ae86Sav ((c[2] != 'A') && (c[2] != 'B'))) { 30590cc8ae86Sav return (3); 30600cc8ae86Sav } 30610cc8ae86Sav x = c[0]; 30620cc8ae86Sav y = c[1]; 30630cc8ae86Sav z = c[2]; 30640cc8ae86Sav } else if ((c = strstr(unum, "MBU_")) != NULL) { 30650cc8ae86Sav /* FF1/FF2 Model */ 30660cc8ae86Sav c += 4; 30670cc8ae86Sav if ((c[0] != 'A') && (c[0] != 'B')) { 30680cc8ae86Sav return (4); 30690cc8ae86Sav } 30700cc8ae86Sav if ((c = strstr(c, "MEMB")) == NULL) { 30710cc8ae86Sav return (5); 30720cc8ae86Sav } 30730cc8ae86Sav c += 4; 30740cc8ae86Sav 30750cc8ae86Sav x = c[0]; 30760cc8ae86Sav *board = ((uint8_t)stoi(&c)) / 4; 30770cc8ae86Sav if ((c = strstr(c, "MEM")) == NULL) { 30780cc8ae86Sav return (6); 30790cc8ae86Sav } 30800cc8ae86Sav c += 3; 30810cc8ae86Sav if (strlen(c) < 2) { 30820cc8ae86Sav return (7); 30830cc8ae86Sav } 30840cc8ae86Sav if ((!isdigit(c[0])) || ((c[1] != 'A') && (c[1] != 'B'))) { 30850cc8ae86Sav return (8); 30860cc8ae86Sav } 30870cc8ae86Sav y = c[0]; 30880cc8ae86Sav z = c[1]; 30890cc8ae86Sav } else { 30900cc8ae86Sav return (9); 30910cc8ae86Sav } 30920cc8ae86Sav if (*board < 0) { 30930cc8ae86Sav return (10); 30940cc8ae86Sav } 30950cc8ae86Sav dname[0] = x; 30960cc8ae86Sav dname[1] = y; 30970cc8ae86Sav dname[2] = z; 30980cc8ae86Sav dname[3] = '\0'; 30990cc8ae86Sav return (0); 31000cc8ae86Sav } 31010cc8ae86Sav 31020cc8ae86Sav /* 31030cc8ae86Sav * mc_get_mem_sid_dimm -- Get the serial-ID for a given board and 31040cc8ae86Sav * the DIMM name. 31050cc8ae86Sav */ 31060cc8ae86Sav int 31070cc8ae86Sav mc_get_mem_sid_dimm(mc_opl_t *mcp, char *dname, char *buf, 31080cc8ae86Sav int buflen, int *lenp) 31090cc8ae86Sav { 31100cc8ae86Sav int ret = ENODEV; 31110cc8ae86Sav mc_dimm_info_t *d = NULL; 31120cc8ae86Sav 31130cc8ae86Sav if ((d = mcp->mc_dimm_list) == NULL) 31140cc8ae86Sav return (ENOTSUP); 31150cc8ae86Sav 31160cc8ae86Sav for (; d != NULL; d = d->md_next) { 31170cc8ae86Sav if (strcmp(d->md_dimmname, dname) == 0) { 31180cc8ae86Sav break; 31190cc8ae86Sav } 31200cc8ae86Sav } 31210cc8ae86Sav if (d != NULL) { 31220cc8ae86Sav *lenp = strlen(d->md_serial) + strlen(d->md_partnum); 31230cc8ae86Sav if (buflen <= *lenp) { 31240cc8ae86Sav cmn_err(CE_WARN, "mc_get_mem_sid_dimm: " 31250cc8ae86Sav "buflen is smaller than %d\n", *lenp); 31260cc8ae86Sav ret = ENOSPC; 31270cc8ae86Sav } else { 31280cc8ae86Sav snprintf(buf, buflen, "%s:%s", 31290cc8ae86Sav d->md_serial, d->md_partnum); 31300cc8ae86Sav ret = 0; 31310cc8ae86Sav } 31320cc8ae86Sav } 31330cc8ae86Sav MC_LOG("mc_get_mem_sid_dimm: Ret=%d Name=%s Serial-ID=%s\n", 31340cc8ae86Sav ret, dname, (ret == 0) ? buf : ""); 31350cc8ae86Sav return (ret); 31360cc8ae86Sav } 31370cc8ae86Sav 31380cc8ae86Sav int 31390cc8ae86Sav mc_set_mem_sid(mc_opl_t *mcp, char *buf, int buflen, int lsb, 31400cc8ae86Sav int bank, uint32_t mf_type, uint32_t d_slot) 31410cc8ae86Sav { 31420cc8ae86Sav int sb; 31430cc8ae86Sav int lenp = buflen; 31440cc8ae86Sav int id; 31450cc8ae86Sav int ret; 31460cc8ae86Sav char *dimmnm; 31470cc8ae86Sav 31480cc8ae86Sav if ((sb = mc_opl_get_physical_board(lsb)) < 0) { 31490cc8ae86Sav return (ENODEV); 31500cc8ae86Sav } 31510cc8ae86Sav 31520cc8ae86Sav if (mf_type == FLT_TYPE_PERMANENT_CE) { 31530cc8ae86Sav if (plat_model == MODEL_DC) { 31540cc8ae86Sav id = BD_BK_SLOT_TO_INDEX(0, bank, d_slot); 31550cc8ae86Sav } else { 31560cc8ae86Sav id = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot); 31570cc8ae86Sav } 31580cc8ae86Sav dimmnm = mc_dc_dimm_unum_table[id]; 31590cc8ae86Sav if ((ret = mc_get_mem_sid_dimm(mcp, dimmnm, buf, buflen, 31600cc8ae86Sav &lenp)) != 0) { 31610cc8ae86Sav return (ret); 31620cc8ae86Sav } 31630cc8ae86Sav } else { 31640cc8ae86Sav return (1); 31650cc8ae86Sav } 31660cc8ae86Sav 31670cc8ae86Sav return (0); 31680cc8ae86Sav } 31690cc8ae86Sav 31700cc8ae86Sav /* 31710cc8ae86Sav * mc_get_mem_sid -- get the DIMM serial-ID corresponding to the unum. 31720cc8ae86Sav */ 31730cc8ae86Sav int 31740cc8ae86Sav mc_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 31750cc8ae86Sav { 31760cc8ae86Sav int i; 31770cc8ae86Sav int ret = ENODEV; 31780cc8ae86Sav int board; 31790cc8ae86Sav char dname[MCOPL_MAX_DIMMNAME + 1]; 31800cc8ae86Sav mc_opl_t *mcp; 31810cc8ae86Sav 31820cc8ae86Sav MC_LOG("mc_get_mem_sid: unum=%s buflen=%d\n", unum, buflen); 31830cc8ae86Sav if ((ret = parse_unum_memory(unum, &board, dname)) != 0) { 31840cc8ae86Sav MC_LOG("mc_get_mem_sid: unum(%s) parsing failed ret=%d\n", 31850cc8ae86Sav unum, ret); 31860cc8ae86Sav return (EINVAL); 31870cc8ae86Sav } 31880cc8ae86Sav 31890cc8ae86Sav if (board < 0) { 31900cc8ae86Sav MC_LOG("mc_get_mem_sid: Invalid board=%d dimm=%s\n", 31910cc8ae86Sav board, dname); 31920cc8ae86Sav return (EINVAL); 31930cc8ae86Sav } 31940cc8ae86Sav 31950cc8ae86Sav mutex_enter(&mcmutex); 31960cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 31970cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 31980cc8ae86Sav continue; 31990cc8ae86Sav mutex_enter(&mcp->mc_lock); 32000cc8ae86Sav if (mcp->mc_board_num == board) { 32010cc8ae86Sav ret = mc_get_mem_sid_dimm(mcp, dname, buf, 32020cc8ae86Sav buflen, lenp); 32030cc8ae86Sav mutex_exit(&mcp->mc_lock); 32040cc8ae86Sav break; 32050cc8ae86Sav } 32060cc8ae86Sav mutex_exit(&mcp->mc_lock); 32070cc8ae86Sav } 32080cc8ae86Sav mutex_exit(&mcmutex); 32090cc8ae86Sav return (ret); 32100cc8ae86Sav } 32110cc8ae86Sav 32120cc8ae86Sav /* 32130cc8ae86Sav * mc_get_mem_offset -- get the offset in a DIMM for a given physical address. 32140cc8ae86Sav */ 32150cc8ae86Sav int 32160cc8ae86Sav mc_get_mem_offset(uint64_t paddr, uint64_t *offp) 32170cc8ae86Sav { 32180cc8ae86Sav int i; 32190cc8ae86Sav int ret = ENODEV; 32200cc8ae86Sav mc_addr_t maddr; 32210cc8ae86Sav mc_opl_t *mcp; 32220cc8ae86Sav 32230cc8ae86Sav mutex_enter(&mcmutex); 3224*c964b0e6Sraghuram for (i = 0; ((i < OPL_MAX_BOARDS) && (ret != 0)); i++) { 32250cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 32260cc8ae86Sav continue; 32270cc8ae86Sav mutex_enter(&mcp->mc_lock); 32280cc8ae86Sav if (!pa_is_valid(mcp, paddr)) { 32290cc8ae86Sav mutex_exit(&mcp->mc_lock); 32300cc8ae86Sav continue; 32310cc8ae86Sav } 32320cc8ae86Sav if (pa_to_maddr(mcp, paddr, &maddr) == 0) { 32330cc8ae86Sav *offp = maddr.ma_dimm_addr; 32340cc8ae86Sav ret = 0; 32350cc8ae86Sav } 32360cc8ae86Sav mutex_exit(&mcp->mc_lock); 32370cc8ae86Sav } 32380cc8ae86Sav mutex_exit(&mcmutex); 32390cc8ae86Sav MC_LOG("mc_get_mem_offset: Ret=%d paddr=0x%lx offset=0x%lx\n", 32400cc8ae86Sav ret, paddr, *offp); 32410cc8ae86Sav return (ret); 32420cc8ae86Sav } 32430cc8ae86Sav 32440cc8ae86Sav /* 32450cc8ae86Sav * dname_to_bankslot - Get the bank and slot number from the DIMM name. 32460cc8ae86Sav */ 32470cc8ae86Sav int 32480cc8ae86Sav dname_to_bankslot(char *dname, int *bank, int *slot) 32490cc8ae86Sav { 32500cc8ae86Sav int i; 32510cc8ae86Sav int tsz; 32520cc8ae86Sav char **tbl; 32530cc8ae86Sav 32540cc8ae86Sav if (plat_model == MODEL_DC) { /* DC */ 32550cc8ae86Sav tbl = mc_dc_dimm_unum_table; 32560cc8ae86Sav tsz = OPL_MAX_DIMMS; 32570cc8ae86Sav } else { 32580cc8ae86Sav tbl = mc_ff_dimm_unum_table; 32590cc8ae86Sav tsz = 2 * OPL_MAX_DIMMS; 32600cc8ae86Sav } 32610cc8ae86Sav 32620cc8ae86Sav for (i = 0; i < tsz; i++) { 32630cc8ae86Sav if (strcmp(dname, tbl[i]) == 0) { 32640cc8ae86Sav break; 32650cc8ae86Sav } 32660cc8ae86Sav } 32670cc8ae86Sav if (i == tsz) { 32680cc8ae86Sav return (1); 32690cc8ae86Sav } 32700cc8ae86Sav *bank = INDEX_TO_BANK(i); 32710cc8ae86Sav *slot = INDEX_TO_SLOT(i); 32720cc8ae86Sav return (0); 32730cc8ae86Sav } 32740cc8ae86Sav 32750cc8ae86Sav /* 32760cc8ae86Sav * mc_get_mem_addr -- get the physical address of a DIMM corresponding 32770cc8ae86Sav * to the unum and sid. 32780cc8ae86Sav */ 32790cc8ae86Sav int 32800cc8ae86Sav mc_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *paddr) 32810cc8ae86Sav { 32820cc8ae86Sav int board; 32830cc8ae86Sav int bank; 32840cc8ae86Sav int slot; 32850cc8ae86Sav int i; 32860cc8ae86Sav int ret = ENODEV; 32870cc8ae86Sav char dname[MCOPL_MAX_DIMMNAME + 1]; 32880cc8ae86Sav mc_addr_t maddr; 32890cc8ae86Sav mc_opl_t *mcp; 32900cc8ae86Sav 32910cc8ae86Sav MC_LOG("mc_get_mem_addr: unum=%s sid=%s offset=0x%lx\n", 32920cc8ae86Sav unum, sid, offset); 32930cc8ae86Sav if (parse_unum_memory(unum, &board, dname) != 0) { 32940cc8ae86Sav MC_LOG("mc_get_mem_sid: unum(%s) parsing failed ret=%d\n", 32950cc8ae86Sav unum, ret); 32960cc8ae86Sav return (EINVAL); 32970cc8ae86Sav } 32980cc8ae86Sav 32990cc8ae86Sav if (board < 0) { 33000cc8ae86Sav MC_LOG("mc_get_mem_addr: Invalid board=%d dimm=%s\n", 33010cc8ae86Sav board, dname); 33020cc8ae86Sav return (EINVAL); 33030cc8ae86Sav } 33040cc8ae86Sav 33050cc8ae86Sav mutex_enter(&mcmutex); 33060cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 33070cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 33080cc8ae86Sav continue; 33090cc8ae86Sav mutex_enter(&mcp->mc_lock); 33100cc8ae86Sav if (mcp->mc_board_num != board) { 33110cc8ae86Sav mutex_exit(&mcp->mc_lock); 33120cc8ae86Sav continue; 33130cc8ae86Sav } 33140cc8ae86Sav 33150cc8ae86Sav ret = dname_to_bankslot(dname, &bank, &slot); 33160cc8ae86Sav MC_LOG("mc_get_mem_addr: bank=%d slot=%d\n", bank, slot); 33170cc8ae86Sav if (ret != 0) { 33180cc8ae86Sav MC_LOG("mc_get_mem_addr: dname_to_bankslot failed\n"); 33190cc8ae86Sav ret = ENODEV; 33200cc8ae86Sav } else { 33210cc8ae86Sav maddr.ma_bd = board; 33220cc8ae86Sav maddr.ma_bank = bank; 33230cc8ae86Sav maddr.ma_dimm_addr = offset; 33240cc8ae86Sav ret = mcaddr_to_pa(mcp, &maddr, paddr); 33250cc8ae86Sav if (ret != 0) { 33260cc8ae86Sav MC_LOG("mc_get_mem_addr: " 33270cc8ae86Sav "mcaddr_to_pa failed\n"); 33280cc8ae86Sav ret = ENODEV; 33290cc8ae86Sav } 33300cc8ae86Sav } 33310cc8ae86Sav mutex_exit(&mcp->mc_lock); 33320cc8ae86Sav } 33330cc8ae86Sav mutex_exit(&mcmutex); 33340cc8ae86Sav MC_LOG("mc_get_mem_addr: Ret=%d, Paddr=0x%lx\n", ret, *paddr); 33350cc8ae86Sav return (ret); 33360cc8ae86Sav } 33370cc8ae86Sav 33380cc8ae86Sav static void 33390cc8ae86Sav mc_free_dimm_list(mc_dimm_info_t *d) 33400cc8ae86Sav { 33410cc8ae86Sav mc_dimm_info_t *next; 33420cc8ae86Sav 33430cc8ae86Sav while (d != NULL) { 33440cc8ae86Sav next = d->md_next; 33450cc8ae86Sav kmem_free(d, sizeof (mc_dimm_info_t)); 33460cc8ae86Sav d = next; 33470cc8ae86Sav } 33480cc8ae86Sav } 33490cc8ae86Sav 33500cc8ae86Sav /* 33510cc8ae86Sav * mc_get_dimm_list -- get the list of dimms with serial-id info 33520cc8ae86Sav * from the SP. 33530cc8ae86Sav */ 33540cc8ae86Sav mc_dimm_info_t * 33550cc8ae86Sav mc_get_dimm_list(mc_opl_t *mcp) 33560cc8ae86Sav { 33570cc8ae86Sav uint32_t bufsz; 33580cc8ae86Sav uint32_t maxbufsz; 33590cc8ae86Sav int ret; 33600cc8ae86Sav int sexp; 33610cc8ae86Sav board_dimm_info_t *bd_dimmp; 33620cc8ae86Sav mc_dimm_info_t *dimm_list = NULL; 33630cc8ae86Sav 33640cc8ae86Sav maxbufsz = bufsz = sizeof (board_dimm_info_t) + 33650cc8ae86Sav ((MCOPL_MAX_DIMMNAME + MCOPL_MAX_SERIAL + 33660cc8ae86Sav MCOPL_MAX_PARTNUM) * OPL_MAX_DIMMS); 33670cc8ae86Sav 33680cc8ae86Sav bd_dimmp = (board_dimm_info_t *)kmem_alloc(bufsz, KM_SLEEP); 33690cc8ae86Sav ret = scf_get_dimminfo(mcp->mc_board_num, (void *)bd_dimmp, &bufsz); 33700cc8ae86Sav 33710cc8ae86Sav MC_LOG("mc_get_dimm_list: scf_service_getinfo returned=%d\n", ret); 33720cc8ae86Sav if (ret == 0) { 33730cc8ae86Sav sexp = sizeof (board_dimm_info_t) + 33740cc8ae86Sav ((bd_dimmp->bd_dnamesz + bd_dimmp->bd_serialsz + 33750cc8ae86Sav bd_dimmp->bd_partnumsz) * bd_dimmp->bd_numdimms); 33760cc8ae86Sav 33770cc8ae86Sav if ((bd_dimmp->bd_version == OPL_DIMM_INFO_VERSION) && 33780cc8ae86Sav (bd_dimmp->bd_dnamesz <= MCOPL_MAX_DIMMNAME) && 33790cc8ae86Sav (bd_dimmp->bd_serialsz <= MCOPL_MAX_SERIAL) && 33800cc8ae86Sav (bd_dimmp->bd_partnumsz <= MCOPL_MAX_PARTNUM) && 33810cc8ae86Sav (sexp <= bufsz)) { 33820cc8ae86Sav 33830cc8ae86Sav #ifdef DEBUG 33840cc8ae86Sav if (oplmc_debug) 33850cc8ae86Sav mc_dump_dimm_info(bd_dimmp); 33860cc8ae86Sav #endif 33870cc8ae86Sav dimm_list = mc_prepare_dimmlist(bd_dimmp); 33880cc8ae86Sav 33890cc8ae86Sav } else { 33900cc8ae86Sav cmn_err(CE_WARN, "DIMM info version mismatch\n"); 33910cc8ae86Sav } 33920cc8ae86Sav } 33930cc8ae86Sav kmem_free(bd_dimmp, maxbufsz); 33940cc8ae86Sav MC_LOG("mc_get_dimm_list: dimmlist=0x%p\n", dimm_list); 33950cc8ae86Sav return (dimm_list); 33960cc8ae86Sav } 33970cc8ae86Sav 33980cc8ae86Sav /* 33990cc8ae86Sav * mc_prepare_dimmlist - Prepare the dimm list from the infomation 34000cc8ae86Sav * recieved from the SP. 34010cc8ae86Sav */ 34020cc8ae86Sav mc_dimm_info_t * 34030cc8ae86Sav mc_prepare_dimmlist(board_dimm_info_t *bd_dimmp) 34040cc8ae86Sav { 34050cc8ae86Sav char *dimm_name; 34060cc8ae86Sav char *serial; 34070cc8ae86Sav char *part; 34080cc8ae86Sav int dimm; 34090cc8ae86Sav int dnamesz = bd_dimmp->bd_dnamesz; 34100cc8ae86Sav int sersz = bd_dimmp->bd_serialsz; 34110cc8ae86Sav int partsz = bd_dimmp->bd_partnumsz; 34120cc8ae86Sav mc_dimm_info_t *dimm_list = NULL; 34130cc8ae86Sav mc_dimm_info_t *d; 34140cc8ae86Sav 34150cc8ae86Sav dimm_name = (char *)(bd_dimmp + 1); 34160cc8ae86Sav for (dimm = 0; dimm < bd_dimmp->bd_numdimms; dimm++) { 34170cc8ae86Sav 34180cc8ae86Sav d = (mc_dimm_info_t *)kmem_alloc(sizeof (mc_dimm_info_t), 34190cc8ae86Sav KM_SLEEP); 34200cc8ae86Sav snprintf(d->md_dimmname, dnamesz + 1, "%s", dimm_name); 34210cc8ae86Sav serial = dimm_name + dnamesz; 34220cc8ae86Sav snprintf(d->md_serial, sersz + 1, "%s", serial); 34230cc8ae86Sav part = serial + sersz; 34240cc8ae86Sav snprintf(d->md_partnum, partsz + 1, "%s", part); 34250cc8ae86Sav 34260cc8ae86Sav d->md_next = dimm_list; 34270cc8ae86Sav dimm_list = d; 34280cc8ae86Sav dimm_name = part + partsz; 34290cc8ae86Sav } 34300cc8ae86Sav return (dimm_list); 34310cc8ae86Sav } 34320cc8ae86Sav 34330cc8ae86Sav #ifdef DEBUG 34340cc8ae86Sav void 34350cc8ae86Sav mc_dump_dimm(char *buf, int dnamesz, int serialsz, int partnumsz) 34360cc8ae86Sav { 34370cc8ae86Sav char dname[MCOPL_MAX_DIMMNAME + 1]; 34380cc8ae86Sav char serial[MCOPL_MAX_SERIAL + 1]; 34390cc8ae86Sav char part[ MCOPL_MAX_PARTNUM + 1]; 34400cc8ae86Sav char *b; 34410cc8ae86Sav 34420cc8ae86Sav b = buf; 34430cc8ae86Sav snprintf(dname, dnamesz + 1, "%s", b); 34440cc8ae86Sav b += dnamesz; 34450cc8ae86Sav snprintf(serial, serialsz + 1, "%s", b); 34460cc8ae86Sav b += serialsz; 34470cc8ae86Sav snprintf(part, partnumsz + 1, "%s", b); 34480cc8ae86Sav printf("DIMM=%s Serial=%s PartNum=%s\n", dname, serial, part); 34490cc8ae86Sav } 34500cc8ae86Sav 34510cc8ae86Sav void 34520cc8ae86Sav mc_dump_dimm_info(board_dimm_info_t *bd_dimmp) 34530cc8ae86Sav { 34540cc8ae86Sav int dimm; 34550cc8ae86Sav int dnamesz = bd_dimmp->bd_dnamesz; 34560cc8ae86Sav int sersz = bd_dimmp->bd_serialsz; 34570cc8ae86Sav int partsz = bd_dimmp->bd_partnumsz; 34580cc8ae86Sav char *buf; 34590cc8ae86Sav 34600cc8ae86Sav printf("Version=%d Board=%02d DIMMs=%d NameSize=%d " 34610cc8ae86Sav "SerialSize=%d PartnumSize=%d\n", bd_dimmp->bd_version, 34620cc8ae86Sav bd_dimmp->bd_boardnum, bd_dimmp->bd_numdimms, bd_dimmp->bd_dnamesz, 34630cc8ae86Sav bd_dimmp->bd_serialsz, bd_dimmp->bd_partnumsz); 34640cc8ae86Sav printf("======================================================\n"); 34650cc8ae86Sav 34660cc8ae86Sav buf = (char *)(bd_dimmp + 1); 34670cc8ae86Sav for (dimm = 0; dimm < bd_dimmp->bd_numdimms; dimm++) { 34680cc8ae86Sav mc_dump_dimm(buf, dnamesz, sersz, partsz); 34690cc8ae86Sav buf += dnamesz + sersz + partsz; 34700cc8ae86Sav } 34710cc8ae86Sav printf("======================================================\n"); 34720cc8ae86Sav } 34730cc8ae86Sav 34740cc8ae86Sav 34750cc8ae86Sav /* ARGSUSED */ 34760cc8ae86Sav static int 34770cc8ae86Sav mc_ioctl_debug(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 34780cc8ae86Sav int *rvalp) 34790cc8ae86Sav { 34800cc8ae86Sav caddr_t buf; 34810cc8ae86Sav uint64_t pa; 34820cc8ae86Sav int rv = 0; 34830cc8ae86Sav int i; 34840cc8ae86Sav uint32_t flags; 34850cc8ae86Sav static uint32_t offset = 0; 34860cc8ae86Sav 34870cc8ae86Sav 34880cc8ae86Sav flags = (cmd >> 4) & 0xfffffff; 34890cc8ae86Sav 34900cc8ae86Sav cmd &= 0xf; 34910cc8ae86Sav 34920cc8ae86Sav MC_LOG("mc_ioctl(cmd = %x, flags = %x)\n", cmd, flags); 34930cc8ae86Sav 34940cc8ae86Sav if (arg != NULL) { 34950cc8ae86Sav if (ddi_copyin((const void *)arg, (void *)&pa, 34960cc8ae86Sav sizeof (uint64_t), 0) < 0) { 34970cc8ae86Sav rv = EFAULT; 34980cc8ae86Sav return (rv); 34990cc8ae86Sav } 35000cc8ae86Sav buf = NULL; 35010cc8ae86Sav } else { 35020cc8ae86Sav buf = (caddr_t)kmem_alloc(PAGESIZE, KM_SLEEP); 35030cc8ae86Sav 35040cc8ae86Sav pa = va_to_pa(buf); 35050cc8ae86Sav pa += offset; 35060cc8ae86Sav 35070cc8ae86Sav offset += 64; 35080cc8ae86Sav if (offset >= PAGESIZE) 35090cc8ae86Sav offset = 0; 35100cc8ae86Sav } 35110cc8ae86Sav 35120cc8ae86Sav switch (cmd) { 35130cc8ae86Sav case MCI_CE: 35140cc8ae86Sav mc_inject_error(MC_INJECT_INTERMITTENT_CE, pa, 35150cc8ae86Sav flags); 35160cc8ae86Sav break; 35170cc8ae86Sav case MCI_PERM_CE: 35180cc8ae86Sav mc_inject_error(MC_INJECT_PERMANENT_CE, pa, 35190cc8ae86Sav flags); 35200cc8ae86Sav break; 35210cc8ae86Sav case MCI_UE: 35220cc8ae86Sav mc_inject_error(MC_INJECT_UE, pa, 35230cc8ae86Sav flags); 35240cc8ae86Sav break; 35250cc8ae86Sav case MCI_M_CE: 35260cc8ae86Sav mc_inject_error(MC_INJECT_INTERMITTENT_MCE, pa, 35270cc8ae86Sav flags); 35280cc8ae86Sav break; 35290cc8ae86Sav case MCI_M_PCE: 35300cc8ae86Sav mc_inject_error(MC_INJECT_PERMANENT_MCE, pa, 35310cc8ae86Sav flags); 35320cc8ae86Sav break; 35330cc8ae86Sav case MCI_M_UE: 35340cc8ae86Sav mc_inject_error(MC_INJECT_MUE, pa, 35350cc8ae86Sav flags); 35360cc8ae86Sav break; 35370cc8ae86Sav case MCI_CMP: 35380cc8ae86Sav mc_inject_error(MC_INJECT_CMPE, pa, 35390cc8ae86Sav flags); 35400cc8ae86Sav break; 35410cc8ae86Sav case MCI_NOP: 35420cc8ae86Sav mc_inject_error(MC_INJECT_NOP, pa, flags); 35430cc8ae86Sav break; 35440cc8ae86Sav case MCI_SHOW_ALL: 35450cc8ae86Sav mc_debug_show_all = 1; 35460cc8ae86Sav break; 35470cc8ae86Sav case MCI_SHOW_NONE: 35480cc8ae86Sav mc_debug_show_all = 0; 35490cc8ae86Sav break; 35500cc8ae86Sav case MCI_ALLOC: 35510cc8ae86Sav /* 35520cc8ae86Sav * just allocate some kernel memory and never free it 35530cc8ae86Sav * 512 MB seems to be the maximum size supported. 35540cc8ae86Sav */ 35550cc8ae86Sav cmn_err(CE_NOTE, "Allocating kmem %d MB\n", flags * 512); 35560cc8ae86Sav for (i = 0; i < flags; i++) { 35570cc8ae86Sav buf = kmem_alloc(512 * 1024 * 1024, KM_SLEEP); 35580cc8ae86Sav cmn_err(CE_NOTE, "kmem buf %llx PA %llx\n", 35590cc8ae86Sav (u_longlong_t)buf, (u_longlong_t)va_to_pa(buf)); 35600cc8ae86Sav } 35610cc8ae86Sav break; 35620cc8ae86Sav case MCI_SUSPEND: 35630cc8ae86Sav (void) opl_mc_suspend(); 35640cc8ae86Sav break; 35650cc8ae86Sav case MCI_RESUME: 35660cc8ae86Sav (void) opl_mc_resume(); 35670cc8ae86Sav break; 35680cc8ae86Sav default: 35690cc8ae86Sav rv = ENXIO; 35700cc8ae86Sav } 35710cc8ae86Sav return (rv); 35720cc8ae86Sav } 35730cc8ae86Sav 35740cc8ae86Sav #endif /* DEBUG */ 3575