125cf1a30Sjl /* 225cf1a30Sjl * CDDL HEADER START 325cf1a30Sjl * 425cf1a30Sjl * The contents of this file are subject to the terms of the 525cf1a30Sjl * Common Development and Distribution License (the "License"). 625cf1a30Sjl * You may not use this file except in compliance with the License. 725cf1a30Sjl * 825cf1a30Sjl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 925cf1a30Sjl * or http://www.opensolaris.org/os/licensing. 1025cf1a30Sjl * See the License for the specific language governing permissions 1125cf1a30Sjl * and limitations under the License. 1225cf1a30Sjl * 1325cf1a30Sjl * When distributing Covered Code, include this CDDL HEADER in each 1425cf1a30Sjl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1525cf1a30Sjl * If applicable, add the following below this CDDL HEADER, with the 1625cf1a30Sjl * fields enclosed by brackets "[]" replaced with your own identifying 1725cf1a30Sjl * information: Portions Copyright [yyyy] [name of copyright owner] 1825cf1a30Sjl * 1925cf1a30Sjl * CDDL HEADER END 2025cf1a30Sjl */ 21*1e2e7a75Shuah /* 22*1e2e7a75Shuah * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23*1e2e7a75Shuah * Use is subject to license terms. 24*1e2e7a75Shuah */ 2525cf1a30Sjl /* 2625cf1a30Sjl * All Rights Reserved, Copyright (c) FUJITSU LIMITED 2006 2725cf1a30Sjl */ 2825cf1a30Sjl 2925cf1a30Sjl #pragma ident "%Z%%M% %I% %E% SMI" 3025cf1a30Sjl 3125cf1a30Sjl #include <sys/types.h> 3225cf1a30Sjl #include <sys/sysmacros.h> 3325cf1a30Sjl #include <sys/conf.h> 3425cf1a30Sjl #include <sys/modctl.h> 3525cf1a30Sjl #include <sys/stat.h> 3625cf1a30Sjl #include <sys/async.h> 37*1e2e7a75Shuah #include <sys/machcpuvar.h> 3825cf1a30Sjl #include <sys/machsystm.h> 390cc8ae86Sav #include <sys/promif.h> 4025cf1a30Sjl #include <sys/ksynch.h> 4125cf1a30Sjl #include <sys/ddi.h> 4225cf1a30Sjl #include <sys/sunddi.h> 4325cf1a30Sjl #include <sys/ddifm.h> 4425cf1a30Sjl #include <sys/fm/protocol.h> 4525cf1a30Sjl #include <sys/fm/util.h> 4625cf1a30Sjl #include <sys/kmem.h> 4725cf1a30Sjl #include <sys/fm/io/opl_mc_fm.h> 4825cf1a30Sjl #include <sys/memlist.h> 4925cf1a30Sjl #include <sys/param.h> 500cc8ae86Sav #include <sys/disp.h> 5125cf1a30Sjl #include <sys/ontrap.h> 5225cf1a30Sjl #include <vm/page.h> 5325cf1a30Sjl #include <sys/mc-opl.h> 540cc8ae86Sav #include <sys/opl.h> 550cc8ae86Sav #include <sys/opl_dimm.h> 560cc8ae86Sav #include <sys/scfd/scfostoescf.h> 5725cf1a30Sjl 5825cf1a30Sjl /* 5925cf1a30Sjl * Function prototypes 6025cf1a30Sjl */ 6125cf1a30Sjl static int mc_open(dev_t *, int, int, cred_t *); 6225cf1a30Sjl static int mc_close(dev_t, int, int, cred_t *); 6325cf1a30Sjl static int mc_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 6425cf1a30Sjl static int mc_attach(dev_info_t *, ddi_attach_cmd_t); 6525cf1a30Sjl static int mc_detach(dev_info_t *, ddi_detach_cmd_t); 6625cf1a30Sjl 670cc8ae86Sav static int mc_poll_init(void); 680cc8ae86Sav static void mc_poll_fini(void); 6925cf1a30Sjl static int mc_board_add(mc_opl_t *mcp); 7025cf1a30Sjl static int mc_board_del(mc_opl_t *mcp); 7125cf1a30Sjl static int mc_suspend(mc_opl_t *mcp, uint32_t flag); 7225cf1a30Sjl static int mc_resume(mc_opl_t *mcp, uint32_t flag); 730cc8ae86Sav int opl_mc_suspend(void); 740cc8ae86Sav int opl_mc_resume(void); 7525cf1a30Sjl 7625cf1a30Sjl static void insert_mcp(mc_opl_t *mcp); 7725cf1a30Sjl static void delete_mcp(mc_opl_t *mcp); 7825cf1a30Sjl 7925cf1a30Sjl static int pa_to_maddr(mc_opl_t *mcp, uint64_t pa, mc_addr_t *maddr); 8025cf1a30Sjl 8125cf1a30Sjl static int mc_valid_pa(mc_opl_t *mcp, uint64_t pa); 8225cf1a30Sjl 8325cf1a30Sjl int mc_get_mem_unum(int, uint64_t, char *, int, int *); 840cc8ae86Sav int mc_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *paddr); 850cc8ae86Sav int mc_get_mem_offset(uint64_t paddr, uint64_t *offp); 860cc8ae86Sav int mc_get_mem_sid(char *unum, char *buf, int buflen, int *lenp); 870cc8ae86Sav int mc_get_mem_sid_dimm(mc_opl_t *mcp, char *dname, char *buf, 880cc8ae86Sav int buflen, int *lenp); 890cc8ae86Sav mc_dimm_info_t *mc_get_dimm_list(mc_opl_t *mcp); 900cc8ae86Sav mc_dimm_info_t *mc_prepare_dimmlist(board_dimm_info_t *bd_dimmp); 910cc8ae86Sav int mc_set_mem_sid(mc_opl_t *mcp, char *buf, int buflen, int lsb, int bank, 920cc8ae86Sav uint32_t mf_type, uint32_t d_slot); 930cc8ae86Sav static void mc_free_dimm_list(mc_dimm_info_t *d); 9425cf1a30Sjl static void mc_get_mlist(mc_opl_t *); 950cc8ae86Sav static void mc_polling(void); 960cc8ae86Sav static int mc_opl_get_physical_board(int); 970cc8ae86Sav 980cc8ae86Sav #ifdef DEBUG 990cc8ae86Sav static int mc_ioctl_debug(dev_t, int, intptr_t, int, cred_t *, int *); 1000cc8ae86Sav void mc_dump_dimm(char *buf, int dnamesz, int serialsz, int partnumsz); 1010cc8ae86Sav void mc_dump_dimm_info(board_dimm_info_t *bd_dimmp); 1020cc8ae86Sav #endif 10325cf1a30Sjl 10425cf1a30Sjl #pragma weak opl_get_physical_board 10525cf1a30Sjl extern int opl_get_physical_board(int); 1060cc8ae86Sav extern int plat_max_boards(void); 10725cf1a30Sjl 10825cf1a30Sjl /* 10925cf1a30Sjl * Configuration data structures 11025cf1a30Sjl */ 11125cf1a30Sjl static struct cb_ops mc_cb_ops = { 11225cf1a30Sjl mc_open, /* open */ 11325cf1a30Sjl mc_close, /* close */ 11425cf1a30Sjl nulldev, /* strategy */ 11525cf1a30Sjl nulldev, /* print */ 11625cf1a30Sjl nodev, /* dump */ 11725cf1a30Sjl nulldev, /* read */ 11825cf1a30Sjl nulldev, /* write */ 11925cf1a30Sjl mc_ioctl, /* ioctl */ 12025cf1a30Sjl nodev, /* devmap */ 12125cf1a30Sjl nodev, /* mmap */ 12225cf1a30Sjl nodev, /* segmap */ 12325cf1a30Sjl nochpoll, /* poll */ 12425cf1a30Sjl ddi_prop_op, /* cb_prop_op */ 12525cf1a30Sjl 0, /* streamtab */ 12625cf1a30Sjl D_MP | D_NEW | D_HOTPLUG, /* Driver compatibility flag */ 12725cf1a30Sjl CB_REV, /* rev */ 12825cf1a30Sjl nodev, /* cb_aread */ 12925cf1a30Sjl nodev /* cb_awrite */ 13025cf1a30Sjl }; 13125cf1a30Sjl 13225cf1a30Sjl static struct dev_ops mc_ops = { 13325cf1a30Sjl DEVO_REV, /* rev */ 13425cf1a30Sjl 0, /* refcnt */ 13525cf1a30Sjl ddi_getinfo_1to1, /* getinfo */ 13625cf1a30Sjl nulldev, /* identify */ 13725cf1a30Sjl nulldev, /* probe */ 13825cf1a30Sjl mc_attach, /* attach */ 13925cf1a30Sjl mc_detach, /* detach */ 14025cf1a30Sjl nulldev, /* reset */ 14125cf1a30Sjl &mc_cb_ops, /* cb_ops */ 14225cf1a30Sjl (struct bus_ops *)0, /* bus_ops */ 14325cf1a30Sjl nulldev /* power */ 14425cf1a30Sjl }; 14525cf1a30Sjl 14625cf1a30Sjl /* 14725cf1a30Sjl * Driver globals 14825cf1a30Sjl */ 14925cf1a30Sjl 1500cc8ae86Sav static enum { 1510cc8ae86Sav MODEL_FF1 = 0, 1520cc8ae86Sav MODEL_FF2 = 1, 1530cc8ae86Sav MODEL_DC = 2 1540cc8ae86Sav } plat_model = MODEL_DC; /* The default behaviour is DC */ 1550cc8ae86Sav 1560cc8ae86Sav static struct plat_model_names { 1570cc8ae86Sav const char *unit_name; 1580cc8ae86Sav const char *mem_name; 1590cc8ae86Sav } model_names[] = { 1600cc8ae86Sav { "MBU_A", "MEMB" }, 1610cc8ae86Sav { "MBU_B", "MEMB" }, 1620cc8ae86Sav { "CMU", "" } 1630cc8ae86Sav }; 16425cf1a30Sjl 1650cc8ae86Sav /* 1660cc8ae86Sav * The DIMM Names for DC platform. 1670cc8ae86Sav * The index into this table is made up of (bank, dslot), 1680cc8ae86Sav * Where dslot occupies bits 0-1 and bank occupies 2-4. 1690cc8ae86Sav */ 1700cc8ae86Sav static char *mc_dc_dimm_unum_table[OPL_MAX_DIMMS] = { 1710cc8ae86Sav /* --------CMUnn----------- */ 1720cc8ae86Sav /* --CS0-----|--CS1------ */ 1730cc8ae86Sav /* -H-|--L-- | -H- | -L-- */ 1740cc8ae86Sav "03A", "02A", "03B", "02B", /* MAC 0 bank 0 */ 1750cc8ae86Sav "13A", "12A", "13B", "12B", /* MAC 0 bank 1 */ 1760cc8ae86Sav "23A", "22A", "23B", "22B", /* MAC 1 bank 2 */ 1770cc8ae86Sav "33A", "32A", "33B", "32B", /* MAC 1 bank 3 */ 1780cc8ae86Sav "01A", "00A", "01B", "00B", /* MAC 2 bank 4 */ 1790cc8ae86Sav "11A", "10A", "11B", "10B", /* MAC 2 bank 5 */ 1800cc8ae86Sav "21A", "20A", "21B", "20B", /* MAC 3 bank 6 */ 1810cc8ae86Sav "31A", "30A", "31B", "30B" /* MAC 3 bank 7 */ 1820cc8ae86Sav }; 1830cc8ae86Sav 1840cc8ae86Sav /* 1850cc8ae86Sav * The DIMM Names for FF1/FF2 platforms. 1860cc8ae86Sav * The index into this table is made up of (board, bank, dslot), 1870cc8ae86Sav * Where dslot occupies bits 0-1, bank occupies 2-4 and 1880cc8ae86Sav * board occupies the bit 5. 1890cc8ae86Sav */ 1900cc8ae86Sav static char *mc_ff_dimm_unum_table[2 * OPL_MAX_DIMMS] = { 1910cc8ae86Sav /* --------CMU0---------- */ 1920cc8ae86Sav /* --CS0-----|--CS1------ */ 1930cc8ae86Sav /* -H-|--L-- | -H- | -L-- */ 1940cc8ae86Sav "03A", "02A", "03B", "02B", /* MAC 0 bank 0 */ 1950cc8ae86Sav "01A", "00A", "01B", "00B", /* MAC 0 bank 1 */ 1960cc8ae86Sav "13A", "12A", "13B", "12B", /* MAC 1 bank 2 */ 1970cc8ae86Sav "11A", "10A", "11B", "10B", /* MAC 1 bank 3 */ 1980cc8ae86Sav "23A", "20A", "23B", "20B", /* MAC 2 bank 4 */ 1990cc8ae86Sav "21A", "20A", "21B", "20B", /* MAC 2 bank 5 */ 2000cc8ae86Sav "33A", "32A", "33B", "32B", /* MAC 3 bank 6 */ 2010cc8ae86Sav "31A", "30A", "31B", "30B", /* MAC 3 bank 7 */ 2020cc8ae86Sav /* --------CMU1---------- */ 2030cc8ae86Sav /* --CS0-----|--CS1------ */ 2040cc8ae86Sav /* -H-|--L-- | -H- | -L-- */ 2050cc8ae86Sav "43A", "42A", "43B", "42B", /* MAC 0 bank 0 */ 2060cc8ae86Sav "41A", "40A", "41B", "40B", /* MAC 0 bank 1 */ 2070cc8ae86Sav "53A", "52A", "53B", "50B", /* MAC 1 bank 2 */ 2080cc8ae86Sav "51A", "50A", "51B", "50B", /* MAC 1 bank 3 */ 2090cc8ae86Sav "63A", "62A", "63B", "62B", /* MAC 2 bank 4 */ 2100cc8ae86Sav "61A", "60A", "61B", "60B", /* MAC 2 bank 5 */ 2110cc8ae86Sav "73A", "72A", "73B", "72B", /* MAC 3 bank 6 */ 2120cc8ae86Sav "71A", "70A", "71B", "70B" /* MAC 3 bank 7 */ 2130cc8ae86Sav }; 2140cc8ae86Sav 2150cc8ae86Sav #define BD_BK_SLOT_TO_INDEX(bd, bk, s) \ 2160cc8ae86Sav (((bd & 0x01) << 5) | ((bk & 0x07) << 2) | (s & 0x03)) 2170cc8ae86Sav 2180cc8ae86Sav #define INDEX_TO_BANK(i) (((i) & 0x1C) >> 2) 2190cc8ae86Sav #define INDEX_TO_SLOT(i) ((i) & 0x03) 2200cc8ae86Sav 2210cc8ae86Sav /* Isolation unit size is 64 MB */ 2220cc8ae86Sav #define MC_ISOLATION_BSIZE (64 * 1024 * 1024) 2230cc8ae86Sav 2240cc8ae86Sav #define MC_MAX_SPEEDS 7 2250cc8ae86Sav 2260cc8ae86Sav /* make this a structure */ 2270cc8ae86Sav 2280cc8ae86Sav typedef struct { 2290cc8ae86Sav uint32_t mc_speeds; 2300cc8ae86Sav uint32_t mc_period; 2310cc8ae86Sav } mc_scan_speed_t; 2320cc8ae86Sav 2330cc8ae86Sav #define MC_CNTL_SPEED_SHIFT 26 2340cc8ae86Sav 2350cc8ae86Sav static mc_scan_speed_t mc_scan_speeds[MC_MAX_SPEEDS] = { 2360cc8ae86Sav {0x6 << MC_CNTL_SPEED_SHIFT, 0}, 2370cc8ae86Sav {0x5 << MC_CNTL_SPEED_SHIFT, 32}, 2380cc8ae86Sav {0x4 << MC_CNTL_SPEED_SHIFT, 64}, 2390cc8ae86Sav {0x3 << MC_CNTL_SPEED_SHIFT, 128}, 2400cc8ae86Sav {0x2 << MC_CNTL_SPEED_SHIFT, 256}, 2410cc8ae86Sav {0x1 << MC_CNTL_SPEED_SHIFT, 512}, 2420cc8ae86Sav {0x0 << MC_CNTL_SPEED_SHIFT, 1024} 2430cc8ae86Sav }; 2440cc8ae86Sav 2450cc8ae86Sav static uint32_t mc_max_speed = (0x6 << 26); 2460cc8ae86Sav 2470cc8ae86Sav /* we have to measure these delays */ 2480cc8ae86Sav 2490cc8ae86Sav int mc_isolation_bsize = MC_ISOLATION_BSIZE; 2500cc8ae86Sav int mc_patrol_interval_sec = MC_PATROL_INTERVAL_SEC; 2510cc8ae86Sav int mc_max_scf_retry = 16; 2520cc8ae86Sav int mc_max_scf_logs = 64; 2530cc8ae86Sav int mc_max_errlog_processed = BANKNUM_PER_SB*2; 2540cc8ae86Sav int mc_scan_period = 12 * 60 * 60; /* 12 hours period */ 2550cc8ae86Sav int mc_max_rewrite_loop = 100; 2560cc8ae86Sav int mc_rewrite_delay = 10; 2570cc8ae86Sav /* 2580cc8ae86Sav * it takes SCF about 300 m.s. to process a requst. We can bail out 2590cc8ae86Sav * if it is busy. It does not pay to wait for it too long. 2600cc8ae86Sav */ 2610cc8ae86Sav int mc_max_scf_loop = 2; 2620cc8ae86Sav int mc_scf_delay = 100; 2630cc8ae86Sav int mc_pce_dropped = 0; 2640cc8ae86Sav int mc_poll_priority = MINCLSYSPRI; 26525cf1a30Sjl 2660cc8ae86Sav 2670cc8ae86Sav /* 2680cc8ae86Sav * Mutex heierachy in mc-opl 2690cc8ae86Sav * If both mcmutex and mc_lock must be held, 2700cc8ae86Sav * mcmutex must be acquired first, and then mc_lock. 2710cc8ae86Sav */ 2720cc8ae86Sav 2730cc8ae86Sav static kmutex_t mcmutex; 2740cc8ae86Sav mc_opl_t *mc_instances[OPL_MAX_BOARDS]; 2750cc8ae86Sav 2760cc8ae86Sav static kmutex_t mc_polling_lock; 2770cc8ae86Sav static kcondvar_t mc_polling_cv; 2780cc8ae86Sav static kcondvar_t mc_poll_exit_cv; 2790cc8ae86Sav static int mc_poll_cmd = 0; 2800cc8ae86Sav static int mc_pollthr_running = 0; 2810cc8ae86Sav int mc_timeout_period = 0; /* this is in m.s. */ 28225cf1a30Sjl void *mc_statep; 28325cf1a30Sjl 28425cf1a30Sjl #ifdef DEBUG 2852742aa22Shyw int oplmc_debug = 0; 28625cf1a30Sjl #endif 28725cf1a30Sjl 2880cc8ae86Sav static int mc_debug_show_all = 0; 28925cf1a30Sjl 29025cf1a30Sjl extern struct mod_ops mod_driverops; 29125cf1a30Sjl 29225cf1a30Sjl static struct modldrv modldrv = { 29325cf1a30Sjl &mod_driverops, /* module type, this one is a driver */ 2940cc8ae86Sav "OPL Memory-controller %I%", /* module name */ 29525cf1a30Sjl &mc_ops, /* driver ops */ 29625cf1a30Sjl }; 29725cf1a30Sjl 29825cf1a30Sjl static struct modlinkage modlinkage = { 29925cf1a30Sjl MODREV_1, /* rev */ 30025cf1a30Sjl (void *)&modldrv, 30125cf1a30Sjl NULL 30225cf1a30Sjl }; 30325cf1a30Sjl 30425cf1a30Sjl #pragma weak opl_get_mem_unum 3050cc8ae86Sav #pragma weak opl_get_mem_sid 3060cc8ae86Sav #pragma weak opl_get_mem_offset 3070cc8ae86Sav #pragma weak opl_get_mem_addr 3080cc8ae86Sav 30925cf1a30Sjl extern int (*opl_get_mem_unum)(int, uint64_t, char *, int, int *); 3100cc8ae86Sav extern int (*opl_get_mem_sid)(char *unum, char *buf, int buflen, int *lenp); 3110cc8ae86Sav extern int (*opl_get_mem_offset)(uint64_t paddr, uint64_t *offp); 3120cc8ae86Sav extern int (*opl_get_mem_addr)(char *unum, char *sid, uint64_t offset, 3130cc8ae86Sav uint64_t *paddr); 3140cc8ae86Sav 31525cf1a30Sjl 31625cf1a30Sjl /* 31725cf1a30Sjl * pseudo-mc node portid format 31825cf1a30Sjl * 31925cf1a30Sjl * [10] = 0 32025cf1a30Sjl * [9] = 1 32125cf1a30Sjl * [8] = LSB_ID[4] = 0 32225cf1a30Sjl * [7:4] = LSB_ID[3:0] 32325cf1a30Sjl * [3:0] = 0 32425cf1a30Sjl * 32525cf1a30Sjl */ 32625cf1a30Sjl 32725cf1a30Sjl /* 32825cf1a30Sjl * These are the module initialization routines. 32925cf1a30Sjl */ 33025cf1a30Sjl int 33125cf1a30Sjl _init(void) 33225cf1a30Sjl { 3330cc8ae86Sav int error; 3340cc8ae86Sav int plen; 3350cc8ae86Sav char model[20]; 3360cc8ae86Sav pnode_t node; 33725cf1a30Sjl 33825cf1a30Sjl 33925cf1a30Sjl if ((error = ddi_soft_state_init(&mc_statep, 34025cf1a30Sjl sizeof (mc_opl_t), 1)) != 0) 34125cf1a30Sjl return (error); 34225cf1a30Sjl 3430cc8ae86Sav if ((error = mc_poll_init()) != 0) { 3440cc8ae86Sav ddi_soft_state_fini(&mc_statep); 3450cc8ae86Sav return (error); 3460cc8ae86Sav } 3470cc8ae86Sav 34825cf1a30Sjl mutex_init(&mcmutex, NULL, MUTEX_DRIVER, NULL); 34925cf1a30Sjl if (&opl_get_mem_unum) 35025cf1a30Sjl opl_get_mem_unum = mc_get_mem_unum; 3510cc8ae86Sav if (&opl_get_mem_sid) 3520cc8ae86Sav opl_get_mem_sid = mc_get_mem_sid; 3530cc8ae86Sav if (&opl_get_mem_offset) 3540cc8ae86Sav opl_get_mem_offset = mc_get_mem_offset; 3550cc8ae86Sav if (&opl_get_mem_addr) 3560cc8ae86Sav opl_get_mem_addr = mc_get_mem_addr; 3570cc8ae86Sav 3580cc8ae86Sav node = prom_rootnode(); 3590cc8ae86Sav plen = prom_getproplen(node, "model"); 3600cc8ae86Sav 3610cc8ae86Sav if (plen > 0 && plen < sizeof (model)) { 3620cc8ae86Sav (void) prom_getprop(node, "model", model); 3630cc8ae86Sav model[plen] = '\0'; 3640cc8ae86Sav if (strcmp(model, "FF1") == 0) 3650cc8ae86Sav plat_model = MODEL_FF1; 3660cc8ae86Sav else if (strcmp(model, "FF2") == 0) 3670cc8ae86Sav plat_model = MODEL_FF2; 3680cc8ae86Sav else if (strncmp(model, "DC", 2) == 0) 3690cc8ae86Sav plat_model = MODEL_DC; 3700cc8ae86Sav } 37125cf1a30Sjl 37225cf1a30Sjl error = mod_install(&modlinkage); 37325cf1a30Sjl if (error != 0) { 37425cf1a30Sjl if (&opl_get_mem_unum) 37525cf1a30Sjl opl_get_mem_unum = NULL; 3760cc8ae86Sav if (&opl_get_mem_sid) 3770cc8ae86Sav opl_get_mem_sid = NULL; 3780cc8ae86Sav if (&opl_get_mem_offset) 3790cc8ae86Sav opl_get_mem_offset = NULL; 3800cc8ae86Sav if (&opl_get_mem_addr) 3810cc8ae86Sav opl_get_mem_addr = NULL; 38225cf1a30Sjl mutex_destroy(&mcmutex); 3830cc8ae86Sav mc_poll_fini(); 38425cf1a30Sjl ddi_soft_state_fini(&mc_statep); 38525cf1a30Sjl } 38625cf1a30Sjl return (error); 38725cf1a30Sjl } 38825cf1a30Sjl 38925cf1a30Sjl int 39025cf1a30Sjl _fini(void) 39125cf1a30Sjl { 39225cf1a30Sjl int error; 39325cf1a30Sjl 39425cf1a30Sjl if ((error = mod_remove(&modlinkage)) != 0) 39525cf1a30Sjl return (error); 39625cf1a30Sjl 39725cf1a30Sjl if (&opl_get_mem_unum) 39825cf1a30Sjl opl_get_mem_unum = NULL; 3990cc8ae86Sav if (&opl_get_mem_sid) 4000cc8ae86Sav opl_get_mem_sid = NULL; 4010cc8ae86Sav if (&opl_get_mem_offset) 4020cc8ae86Sav opl_get_mem_offset = NULL; 4030cc8ae86Sav if (&opl_get_mem_addr) 4040cc8ae86Sav opl_get_mem_addr = NULL; 40525cf1a30Sjl 4060cc8ae86Sav mutex_destroy(&mcmutex); 4070cc8ae86Sav mc_poll_fini(); 40825cf1a30Sjl ddi_soft_state_fini(&mc_statep); 40925cf1a30Sjl 41025cf1a30Sjl return (0); 41125cf1a30Sjl } 41225cf1a30Sjl 41325cf1a30Sjl int 41425cf1a30Sjl _info(struct modinfo *modinfop) 41525cf1a30Sjl { 41625cf1a30Sjl return (mod_info(&modlinkage, modinfop)); 41725cf1a30Sjl } 41825cf1a30Sjl 4190cc8ae86Sav static void 4200cc8ae86Sav mc_polling_thread() 4210cc8ae86Sav { 4220cc8ae86Sav mutex_enter(&mc_polling_lock); 4230cc8ae86Sav mc_pollthr_running = 1; 4240cc8ae86Sav while (!(mc_poll_cmd & MC_POLL_EXIT)) { 4250cc8ae86Sav mc_polling(); 4260cc8ae86Sav cv_timedwait(&mc_polling_cv, &mc_polling_lock, 4270cc8ae86Sav ddi_get_lbolt() + mc_timeout_period); 4280cc8ae86Sav } 4290cc8ae86Sav mc_pollthr_running = 0; 4300cc8ae86Sav 4310cc8ae86Sav /* 4320cc8ae86Sav * signal if any one is waiting for this thread to exit. 4330cc8ae86Sav */ 4340cc8ae86Sav cv_signal(&mc_poll_exit_cv); 4350cc8ae86Sav mutex_exit(&mc_polling_lock); 4360cc8ae86Sav thread_exit(); 4370cc8ae86Sav /* NOTREACHED */ 4380cc8ae86Sav } 4390cc8ae86Sav 4400cc8ae86Sav static int 4410cc8ae86Sav mc_poll_init() 4420cc8ae86Sav { 4430cc8ae86Sav mutex_init(&mc_polling_lock, NULL, MUTEX_DRIVER, NULL); 4440cc8ae86Sav cv_init(&mc_polling_cv, NULL, CV_DRIVER, NULL); 4450cc8ae86Sav cv_init(&mc_poll_exit_cv, NULL, CV_DRIVER, NULL); 4460cc8ae86Sav return (0); 4470cc8ae86Sav } 4480cc8ae86Sav 4490cc8ae86Sav static void 4500cc8ae86Sav mc_poll_fini() 4510cc8ae86Sav { 4520cc8ae86Sav mutex_enter(&mc_polling_lock); 4530cc8ae86Sav if (mc_pollthr_running) { 4540cc8ae86Sav mc_poll_cmd = MC_POLL_EXIT; 4550cc8ae86Sav cv_signal(&mc_polling_cv); 4560cc8ae86Sav while (mc_pollthr_running) { 4570cc8ae86Sav cv_wait(&mc_poll_exit_cv, &mc_polling_lock); 4580cc8ae86Sav } 4590cc8ae86Sav } 4600cc8ae86Sav mutex_exit(&mc_polling_lock); 4610cc8ae86Sav mutex_destroy(&mc_polling_lock); 4620cc8ae86Sav cv_destroy(&mc_polling_cv); 4630cc8ae86Sav cv_destroy(&mc_poll_exit_cv); 4640cc8ae86Sav } 4650cc8ae86Sav 46625cf1a30Sjl static int 46725cf1a30Sjl mc_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 46825cf1a30Sjl { 46925cf1a30Sjl mc_opl_t *mcp; 47025cf1a30Sjl int instance; 4710cc8ae86Sav int rv; 47225cf1a30Sjl 47325cf1a30Sjl /* get the instance of this devi */ 47425cf1a30Sjl instance = ddi_get_instance(devi); 47525cf1a30Sjl 47625cf1a30Sjl switch (cmd) { 47725cf1a30Sjl case DDI_ATTACH: 47825cf1a30Sjl break; 47925cf1a30Sjl case DDI_RESUME: 48025cf1a30Sjl mcp = ddi_get_soft_state(mc_statep, instance); 4810cc8ae86Sav rv = mc_resume(mcp, MC_DRIVER_SUSPENDED); 4820cc8ae86Sav return (rv); 48325cf1a30Sjl default: 48425cf1a30Sjl return (DDI_FAILURE); 48525cf1a30Sjl } 48625cf1a30Sjl 48725cf1a30Sjl if (ddi_soft_state_zalloc(mc_statep, instance) != DDI_SUCCESS) 48825cf1a30Sjl return (DDI_FAILURE); 48925cf1a30Sjl 49025cf1a30Sjl if ((mcp = ddi_get_soft_state(mc_statep, instance)) == NULL) { 49125cf1a30Sjl goto bad; 49225cf1a30Sjl } 49325cf1a30Sjl 4940cc8ae86Sav if (mc_timeout_period == 0) { 4950cc8ae86Sav mc_patrol_interval_sec = (int)ddi_getprop(DDI_DEV_T_ANY, devi, 4960cc8ae86Sav DDI_PROP_DONTPASS, "mc-timeout-interval-sec", 4970cc8ae86Sav mc_patrol_interval_sec); 4980cc8ae86Sav mc_timeout_period = drv_usectohz( 4990cc8ae86Sav 1000000 * mc_patrol_interval_sec / OPL_MAX_BOARDS); 5000cc8ae86Sav } 5010cc8ae86Sav 50225cf1a30Sjl /* set informations in mc state */ 50325cf1a30Sjl mcp->mc_dip = devi; 50425cf1a30Sjl 50525cf1a30Sjl if (mc_board_add(mcp)) 50625cf1a30Sjl goto bad; 50725cf1a30Sjl 50825cf1a30Sjl insert_mcp(mcp); 5090cc8ae86Sav 5100cc8ae86Sav /* 5110cc8ae86Sav * Start the polling thread if it is not running already. 5120cc8ae86Sav */ 5130cc8ae86Sav mutex_enter(&mc_polling_lock); 5140cc8ae86Sav if (!mc_pollthr_running) { 5150cc8ae86Sav (void) thread_create(NULL, 0, (void (*)())mc_polling_thread, 5160cc8ae86Sav NULL, 0, &p0, TS_RUN, mc_poll_priority); 5170cc8ae86Sav } 5180cc8ae86Sav mutex_exit(&mc_polling_lock); 51925cf1a30Sjl ddi_report_dev(devi); 52025cf1a30Sjl 52125cf1a30Sjl return (DDI_SUCCESS); 52225cf1a30Sjl 52325cf1a30Sjl bad: 52425cf1a30Sjl ddi_soft_state_free(mc_statep, instance); 52525cf1a30Sjl return (DDI_FAILURE); 52625cf1a30Sjl } 52725cf1a30Sjl 52825cf1a30Sjl /* ARGSUSED */ 52925cf1a30Sjl static int 53025cf1a30Sjl mc_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 53125cf1a30Sjl { 5320cc8ae86Sav int rv; 53325cf1a30Sjl int instance; 53425cf1a30Sjl mc_opl_t *mcp; 53525cf1a30Sjl 53625cf1a30Sjl /* get the instance of this devi */ 53725cf1a30Sjl instance = ddi_get_instance(devi); 53825cf1a30Sjl if ((mcp = ddi_get_soft_state(mc_statep, instance)) == NULL) { 53925cf1a30Sjl return (DDI_FAILURE); 54025cf1a30Sjl } 54125cf1a30Sjl 54225cf1a30Sjl switch (cmd) { 54325cf1a30Sjl case DDI_SUSPEND: 5440cc8ae86Sav rv = mc_suspend(mcp, MC_DRIVER_SUSPENDED); 5450cc8ae86Sav return (rv); 54625cf1a30Sjl case DDI_DETACH: 54725cf1a30Sjl break; 54825cf1a30Sjl default: 54925cf1a30Sjl return (DDI_FAILURE); 55025cf1a30Sjl } 55125cf1a30Sjl 5520cc8ae86Sav delete_mcp(mcp); 55325cf1a30Sjl if (mc_board_del(mcp) != DDI_SUCCESS) { 55425cf1a30Sjl return (DDI_FAILURE); 55525cf1a30Sjl } 55625cf1a30Sjl 55725cf1a30Sjl /* free up the soft state */ 55825cf1a30Sjl ddi_soft_state_free(mc_statep, instance); 55925cf1a30Sjl 56025cf1a30Sjl return (DDI_SUCCESS); 56125cf1a30Sjl } 56225cf1a30Sjl 56325cf1a30Sjl /* ARGSUSED */ 56425cf1a30Sjl static int 56525cf1a30Sjl mc_open(dev_t *devp, int flag, int otyp, cred_t *credp) 56625cf1a30Sjl { 56725cf1a30Sjl return (0); 56825cf1a30Sjl } 56925cf1a30Sjl 57025cf1a30Sjl /* ARGSUSED */ 57125cf1a30Sjl static int 57225cf1a30Sjl mc_close(dev_t devp, int flag, int otyp, cred_t *credp) 57325cf1a30Sjl { 57425cf1a30Sjl return (0); 57525cf1a30Sjl } 57625cf1a30Sjl 57725cf1a30Sjl /* ARGSUSED */ 57825cf1a30Sjl static int 57925cf1a30Sjl mc_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 58025cf1a30Sjl int *rvalp) 58125cf1a30Sjl { 5820cc8ae86Sav #ifdef DEBUG 5830cc8ae86Sav return (mc_ioctl_debug(dev, cmd, arg, mode, credp, rvalp)); 5840cc8ae86Sav #else 58525cf1a30Sjl return (ENXIO); 5860cc8ae86Sav #endif 58725cf1a30Sjl } 58825cf1a30Sjl 58925cf1a30Sjl /* 59025cf1a30Sjl * PA validity check: 59125cf1a30Sjl * This function return 1 if the PA is valid, otherwise 59225cf1a30Sjl * return 0. 59325cf1a30Sjl */ 59425cf1a30Sjl 59525cf1a30Sjl /* ARGSUSED */ 59625cf1a30Sjl static int 59725cf1a30Sjl pa_is_valid(mc_opl_t *mcp, uint64_t addr) 59825cf1a30Sjl { 59925cf1a30Sjl /* 60025cf1a30Sjl * Check if the addr is on the board. 60125cf1a30Sjl */ 60225cf1a30Sjl if ((addr < mcp->mc_start_address) || 60325cf1a30Sjl (mcp->mc_start_address + mcp->mc_size <= addr)) 60425cf1a30Sjl return (0); 60525cf1a30Sjl 60625cf1a30Sjl if (mcp->mlist == NULL) 60725cf1a30Sjl mc_get_mlist(mcp); 60825cf1a30Sjl 60925cf1a30Sjl if (mcp->mlist && address_in_memlist(mcp->mlist, addr, 0)) { 61025cf1a30Sjl return (1); 61125cf1a30Sjl } 61225cf1a30Sjl return (0); 61325cf1a30Sjl } 61425cf1a30Sjl 61525cf1a30Sjl /* 61625cf1a30Sjl * mac-pa translation routines. 61725cf1a30Sjl * 61825cf1a30Sjl * Input: mc driver state, (LSB#, Bank#, DIMM address) 61925cf1a30Sjl * Output: physical address 62025cf1a30Sjl * 62125cf1a30Sjl * Valid - return value: 0 62225cf1a30Sjl * Invalid - return value: -1 62325cf1a30Sjl */ 62425cf1a30Sjl static int 62525cf1a30Sjl mcaddr_to_pa(mc_opl_t *mcp, mc_addr_t *maddr, uint64_t *pa) 62625cf1a30Sjl { 62725cf1a30Sjl int i; 62825cf1a30Sjl uint64_t pa_offset = 0; 62925cf1a30Sjl int cs = (maddr->ma_dimm_addr >> CS_SHIFT) & 1; 63025cf1a30Sjl int bank = maddr->ma_bank; 63125cf1a30Sjl mc_addr_t maddr1; 63225cf1a30Sjl int bank0, bank1; 63325cf1a30Sjl 63425cf1a30Sjl MC_LOG("mcaddr /LSB%d/B%d/%x\n", maddr->ma_bd, bank, 63525cf1a30Sjl maddr->ma_dimm_addr); 63625cf1a30Sjl 63725cf1a30Sjl /* loc validity check */ 63825cf1a30Sjl ASSERT(maddr->ma_bd >= 0 && OPL_BOARD_MAX > maddr->ma_bd); 63925cf1a30Sjl ASSERT(bank >= 0 && OPL_BANK_MAX > bank); 64025cf1a30Sjl 64125cf1a30Sjl /* Do translation */ 64225cf1a30Sjl for (i = 0; i < PA_BITS_FOR_MAC; i++) { 64325cf1a30Sjl int pa_bit = 0; 64425cf1a30Sjl int mc_bit = mcp->mc_trans_table[cs][i]; 64525cf1a30Sjl if (mc_bit < MC_ADDRESS_BITS) { 64625cf1a30Sjl pa_bit = (maddr->ma_dimm_addr >> mc_bit) & 1; 64725cf1a30Sjl } else if (mc_bit == MP_NONE) { 64825cf1a30Sjl pa_bit = 0; 64925cf1a30Sjl } else if (mc_bit == MP_BANK_0) { 65025cf1a30Sjl pa_bit = bank & 1; 65125cf1a30Sjl } else if (mc_bit == MP_BANK_1) { 65225cf1a30Sjl pa_bit = (bank >> 1) & 1; 65325cf1a30Sjl } else if (mc_bit == MP_BANK_2) { 65425cf1a30Sjl pa_bit = (bank >> 2) & 1; 65525cf1a30Sjl } 65625cf1a30Sjl pa_offset |= ((uint64_t)pa_bit) << i; 65725cf1a30Sjl } 65825cf1a30Sjl *pa = mcp->mc_start_address + pa_offset; 65925cf1a30Sjl MC_LOG("pa = %lx\n", *pa); 66025cf1a30Sjl 66125cf1a30Sjl if (pa_to_maddr(mcp, *pa, &maddr1) == -1) { 6620cc8ae86Sav cmn_err(CE_WARN, "mcaddr_to_pa: /LSB%d/B%d/%x failed to " 6630cc8ae86Sav "convert PA %lx\n", maddr->ma_bd, bank, 6640cc8ae86Sav maddr->ma_dimm_addr, *pa); 66525cf1a30Sjl return (-1); 66625cf1a30Sjl } 66725cf1a30Sjl 6680cc8ae86Sav /* 6690cc8ae86Sav * In mirror mode, PA is always translated to the even bank. 6700cc8ae86Sav */ 67125cf1a30Sjl if (IS_MIRROR(mcp, maddr->ma_bank)) { 67225cf1a30Sjl bank0 = maddr->ma_bank & ~(1); 67325cf1a30Sjl bank1 = maddr1.ma_bank & ~(1); 67425cf1a30Sjl } else { 67525cf1a30Sjl bank0 = maddr->ma_bank; 67625cf1a30Sjl bank1 = maddr1.ma_bank; 67725cf1a30Sjl } 67825cf1a30Sjl /* 67925cf1a30Sjl * there is no need to check ma_bd because it is generated from 68025cf1a30Sjl * mcp. They are the same. 68125cf1a30Sjl */ 68225cf1a30Sjl if ((bank0 == bank1) && 68325cf1a30Sjl (maddr->ma_dimm_addr == maddr1.ma_dimm_addr)) { 68425cf1a30Sjl return (0); 68525cf1a30Sjl } else { 68625cf1a30Sjl cmn_err(CE_WARN, "Translation error source /LSB%d/B%d/%x, " 68725cf1a30Sjl "PA %lx, target /LSB%d/B%d/%x\n", 68825cf1a30Sjl maddr->ma_bd, bank, maddr->ma_dimm_addr, 68925cf1a30Sjl *pa, maddr1.ma_bd, maddr1.ma_bank, 69025cf1a30Sjl maddr1.ma_dimm_addr); 69125cf1a30Sjl return (-1); 69225cf1a30Sjl } 69325cf1a30Sjl } 69425cf1a30Sjl 69525cf1a30Sjl /* 69625cf1a30Sjl * PA to CS (used by pa_to_maddr). 69725cf1a30Sjl */ 69825cf1a30Sjl static int 69925cf1a30Sjl pa_to_cs(mc_opl_t *mcp, uint64_t pa_offset) 70025cf1a30Sjl { 70125cf1a30Sjl int i; 70225cf1a30Sjl int cs = 0; 70325cf1a30Sjl 70425cf1a30Sjl for (i = 0; i < PA_BITS_FOR_MAC; i++) { 70525cf1a30Sjl /* MAC address bit<29> is arranged on the same PA bit */ 70625cf1a30Sjl /* on both table. So we may use any table. */ 70725cf1a30Sjl if (mcp->mc_trans_table[0][i] == CS_SHIFT) { 70825cf1a30Sjl cs = (pa_offset >> i) & 1; 70925cf1a30Sjl break; 71025cf1a30Sjl } 71125cf1a30Sjl } 71225cf1a30Sjl return (cs); 71325cf1a30Sjl } 71425cf1a30Sjl 71525cf1a30Sjl /* 71625cf1a30Sjl * PA to DIMM (used by pa_to_maddr). 71725cf1a30Sjl */ 71825cf1a30Sjl /* ARGSUSED */ 71925cf1a30Sjl static uint32_t 72025cf1a30Sjl pa_to_dimm(mc_opl_t *mcp, uint64_t pa_offset) 72125cf1a30Sjl { 72225cf1a30Sjl int i; 72325cf1a30Sjl int cs = pa_to_cs(mcp, pa_offset); 72425cf1a30Sjl uint32_t dimm_addr = 0; 72525cf1a30Sjl 72625cf1a30Sjl for (i = 0; i < PA_BITS_FOR_MAC; i++) { 72725cf1a30Sjl int pa_bit_value = (pa_offset >> i) & 1; 72825cf1a30Sjl int mc_bit = mcp->mc_trans_table[cs][i]; 72925cf1a30Sjl if (mc_bit < MC_ADDRESS_BITS) { 73025cf1a30Sjl dimm_addr |= pa_bit_value << mc_bit; 73125cf1a30Sjl } 73225cf1a30Sjl } 73325cf1a30Sjl return (dimm_addr); 73425cf1a30Sjl } 73525cf1a30Sjl 73625cf1a30Sjl /* 73725cf1a30Sjl * PA to Bank (used by pa_to_maddr). 73825cf1a30Sjl */ 73925cf1a30Sjl static int 74025cf1a30Sjl pa_to_bank(mc_opl_t *mcp, uint64_t pa_offset) 74125cf1a30Sjl { 74225cf1a30Sjl int i; 74325cf1a30Sjl int cs = pa_to_cs(mcp, pa_offset); 74425cf1a30Sjl int bankno = mcp->mc_trans_table[cs][INDEX_OF_BANK_SUPPLEMENT_BIT]; 74525cf1a30Sjl 74625cf1a30Sjl 74725cf1a30Sjl for (i = 0; i < PA_BITS_FOR_MAC; i++) { 74825cf1a30Sjl int pa_bit_value = (pa_offset >> i) & 1; 74925cf1a30Sjl int mc_bit = mcp->mc_trans_table[cs][i]; 75025cf1a30Sjl switch (mc_bit) { 75125cf1a30Sjl case MP_BANK_0: 75225cf1a30Sjl bankno |= pa_bit_value; 75325cf1a30Sjl break; 75425cf1a30Sjl case MP_BANK_1: 75525cf1a30Sjl bankno |= pa_bit_value << 1; 75625cf1a30Sjl break; 75725cf1a30Sjl case MP_BANK_2: 75825cf1a30Sjl bankno |= pa_bit_value << 2; 75925cf1a30Sjl break; 76025cf1a30Sjl } 76125cf1a30Sjl } 76225cf1a30Sjl 76325cf1a30Sjl return (bankno); 76425cf1a30Sjl } 76525cf1a30Sjl 76625cf1a30Sjl /* 76725cf1a30Sjl * PA to MAC address translation 76825cf1a30Sjl * 76925cf1a30Sjl * Input: MAC driver state, physicall adress 77025cf1a30Sjl * Output: LSB#, Bank id, mac address 77125cf1a30Sjl * 77225cf1a30Sjl * Valid - return value: 0 77325cf1a30Sjl * Invalid - return value: -1 77425cf1a30Sjl */ 77525cf1a30Sjl 77625cf1a30Sjl int 77725cf1a30Sjl pa_to_maddr(mc_opl_t *mcp, uint64_t pa, mc_addr_t *maddr) 77825cf1a30Sjl { 77925cf1a30Sjl uint64_t pa_offset; 78025cf1a30Sjl 78125cf1a30Sjl /* PA validity check */ 78225cf1a30Sjl if (!pa_is_valid(mcp, pa)) 78325cf1a30Sjl return (-1); 78425cf1a30Sjl 78525cf1a30Sjl 78625cf1a30Sjl /* Do translation */ 78725cf1a30Sjl pa_offset = pa - mcp->mc_start_address; 78825cf1a30Sjl 78925cf1a30Sjl maddr->ma_bd = mcp->mc_board_num; 79025cf1a30Sjl maddr->ma_bank = pa_to_bank(mcp, pa_offset); 79125cf1a30Sjl maddr->ma_dimm_addr = pa_to_dimm(mcp, pa_offset); 79225cf1a30Sjl MC_LOG("pa %lx -> mcaddr /LSB%d/B%d/%x\n", 79325cf1a30Sjl pa_offset, maddr->ma_bd, maddr->ma_bank, maddr->ma_dimm_addr); 79425cf1a30Sjl return (0); 79525cf1a30Sjl } 79625cf1a30Sjl 7970cc8ae86Sav /* 7980cc8ae86Sav * UNUM format for DC is "/CMUnn/MEMxyZ", where 7990cc8ae86Sav * nn = 00..03 for DC1 and 00..07 for DC2 and 00..15 for DC3. 8000cc8ae86Sav * x = MAC 0..3 8010cc8ae86Sav * y = 0..3 (slot info). 8020cc8ae86Sav * Z = 'A' or 'B' 8030cc8ae86Sav * 8040cc8ae86Sav * UNUM format for FF1 is "/MBU_A/MEMBx/MEMyZ", where 8050cc8ae86Sav * x = 0..3 (MEMB number) 8060cc8ae86Sav * y = 0..3 (slot info). 8070cc8ae86Sav * Z = 'A' or 'B' 8080cc8ae86Sav * 8090cc8ae86Sav * UNUM format for FF2 is "/MBU_B/MEMBx/MEMyZ" 8100cc8ae86Sav * x = 0..7 (MEMB number) 8110cc8ae86Sav * y = 0..3 (slot info). 8120cc8ae86Sav * Z = 'A' or 'B' 8130cc8ae86Sav */ 8140cc8ae86Sav int 8150cc8ae86Sav mc_set_mem_unum(char *buf, int buflen, int lsb, int bank, 8160cc8ae86Sav uint32_t mf_type, uint32_t d_slot) 8170cc8ae86Sav { 8180cc8ae86Sav char *dimmnm; 8190cc8ae86Sav char memb_num; 8200cc8ae86Sav int sb; 8210cc8ae86Sav int i; 8220cc8ae86Sav 8230cc8ae86Sav if ((sb = mc_opl_get_physical_board(lsb)) < 0) 8240cc8ae86Sav return (ENODEV); 8250cc8ae86Sav 8260cc8ae86Sav if (plat_model == MODEL_DC) { 8270cc8ae86Sav if (mf_type == FLT_TYPE_PERMANENT_CE) { 8280cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(0, bank, d_slot); 8290cc8ae86Sav dimmnm = mc_dc_dimm_unum_table[i]; 8300cc8ae86Sav snprintf(buf, buflen, "/%s%02d/MEM%s", 8310cc8ae86Sav model_names[plat_model].unit_name, sb, dimmnm); 8320cc8ae86Sav } else { 8330cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(0, bank, 0); 8340cc8ae86Sav snprintf(buf, buflen, "/%s%02d/MEM%s MEM%s MEM%s MEM%s", 8350cc8ae86Sav model_names[plat_model].unit_name, sb, 8360cc8ae86Sav mc_dc_dimm_unum_table[i], 8370cc8ae86Sav mc_dc_dimm_unum_table[i + 1], 8380cc8ae86Sav mc_dc_dimm_unum_table[i + 2], 8390cc8ae86Sav mc_dc_dimm_unum_table[i + 3]); 8400cc8ae86Sav } 8410cc8ae86Sav } else { 8420cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot); 8430cc8ae86Sav if (mf_type == FLT_TYPE_PERMANENT_CE) { 8440cc8ae86Sav dimmnm = mc_ff_dimm_unum_table[i]; 8450cc8ae86Sav memb_num = dimmnm[0]; 8460cc8ae86Sav snprintf(buf, buflen, "/%s/%s%c/MEM%s", 8470cc8ae86Sav model_names[plat_model].unit_name, 8480cc8ae86Sav model_names[plat_model].mem_name, 8490cc8ae86Sav memb_num, &dimmnm[1]); 8500cc8ae86Sav } else { 8510cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(sb, bank, 0); 8520cc8ae86Sav memb_num = mc_ff_dimm_unum_table[i][0], 8530cc8ae86Sav snprintf(buf, buflen, 8540cc8ae86Sav "/%s/%s%c/MEM%s MEM%s MEM%s MEM%s", 8550cc8ae86Sav model_names[plat_model].unit_name, 8560cc8ae86Sav model_names[plat_model].mem_name, memb_num, 8570cc8ae86Sav &mc_ff_dimm_unum_table[i][1], 8580cc8ae86Sav &mc_ff_dimm_unum_table[i + 1][1], 8590cc8ae86Sav &mc_ff_dimm_unum_table[i + 2][1], 8600cc8ae86Sav &mc_ff_dimm_unum_table[i + 3][1]); 8610cc8ae86Sav } 8620cc8ae86Sav } 8630cc8ae86Sav return (0); 8640cc8ae86Sav } 8650cc8ae86Sav 86625cf1a30Sjl static void 86725cf1a30Sjl mc_ereport_post(mc_aflt_t *mc_aflt) 86825cf1a30Sjl { 86925cf1a30Sjl char buf[FM_MAX_CLASS]; 87025cf1a30Sjl char device_path[MAXPATHLEN]; 8710cc8ae86Sav char sid[MAXPATHLEN]; 87225cf1a30Sjl nv_alloc_t *nva = NULL; 87325cf1a30Sjl nvlist_t *ereport, *detector, *resource; 87425cf1a30Sjl errorq_elem_t *eqep; 87525cf1a30Sjl int nflts; 87625cf1a30Sjl mc_flt_stat_t *flt_stat; 8770cc8ae86Sav int i, n; 8780cc8ae86Sav int blen = MAXPATHLEN; 8790cc8ae86Sav char *p, *s = NULL; 88025cf1a30Sjl uint32_t values[2], synd[2], dslot[2]; 8810cc8ae86Sav uint64_t offset = (uint64_t)-1; 8820cc8ae86Sav int ret = -1; 88325cf1a30Sjl 88425cf1a30Sjl if (panicstr) { 88525cf1a30Sjl eqep = errorq_reserve(ereport_errorq); 88625cf1a30Sjl if (eqep == NULL) 88725cf1a30Sjl return; 88825cf1a30Sjl ereport = errorq_elem_nvl(ereport_errorq, eqep); 88925cf1a30Sjl nva = errorq_elem_nva(ereport_errorq, eqep); 89025cf1a30Sjl } else { 89125cf1a30Sjl ereport = fm_nvlist_create(nva); 89225cf1a30Sjl } 89325cf1a30Sjl 89425cf1a30Sjl /* 89525cf1a30Sjl * Create the scheme "dev" FMRI. 89625cf1a30Sjl */ 89725cf1a30Sjl detector = fm_nvlist_create(nva); 89825cf1a30Sjl resource = fm_nvlist_create(nva); 89925cf1a30Sjl 90025cf1a30Sjl nflts = mc_aflt->mflt_nflts; 90125cf1a30Sjl 90225cf1a30Sjl ASSERT(nflts >= 1 && nflts <= 2); 90325cf1a30Sjl 90425cf1a30Sjl flt_stat = mc_aflt->mflt_stat[0]; 90525cf1a30Sjl (void) ddi_pathname(mc_aflt->mflt_mcp->mc_dip, device_path); 90625cf1a30Sjl (void) fm_fmri_dev_set(detector, FM_DEV_SCHEME_VERSION, NULL, 90725cf1a30Sjl device_path, NULL); 90825cf1a30Sjl 90925cf1a30Sjl /* 91025cf1a30Sjl * Encode all the common data into the ereport. 91125cf1a30Sjl */ 91225cf1a30Sjl (void) snprintf(buf, FM_MAX_CLASS, "%s.%s-%s", 91325cf1a30Sjl MC_OPL_ERROR_CLASS, 91425cf1a30Sjl mc_aflt->mflt_is_ptrl ? MC_OPL_PTRL_SUBCLASS : 91525cf1a30Sjl MC_OPL_MI_SUBCLASS, 91625cf1a30Sjl mc_aflt->mflt_erpt_class); 91725cf1a30Sjl 91825cf1a30Sjl MC_LOG("mc_ereport_post: ereport %s\n", buf); 91925cf1a30Sjl 92025cf1a30Sjl 92125cf1a30Sjl fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, 92225cf1a30Sjl fm_ena_generate(mc_aflt->mflt_id, FM_ENA_FMT1), 92325cf1a30Sjl detector, NULL); 92425cf1a30Sjl 92525cf1a30Sjl /* 92625cf1a30Sjl * Set payload. 92725cf1a30Sjl */ 92825cf1a30Sjl fm_payload_set(ereport, MC_OPL_BOARD, DATA_TYPE_UINT32, 92925cf1a30Sjl flt_stat->mf_flt_maddr.ma_bd, NULL); 93025cf1a30Sjl 93125cf1a30Sjl fm_payload_set(ereport, MC_OPL_PA, DATA_TYPE_UINT64, 93225cf1a30Sjl flt_stat->mf_flt_paddr, NULL); 93325cf1a30Sjl 93425cf1a30Sjl if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) { 93525cf1a30Sjl fm_payload_set(ereport, MC_OPL_FLT_TYPE, 93625cf1a30Sjl DATA_TYPE_UINT8, ECC_STICKY, NULL); 93725cf1a30Sjl } 93825cf1a30Sjl 93925cf1a30Sjl for (i = 0; i < nflts; i++) 94025cf1a30Sjl values[i] = mc_aflt->mflt_stat[i]->mf_flt_maddr.ma_bank; 94125cf1a30Sjl 94225cf1a30Sjl fm_payload_set(ereport, MC_OPL_BANK, DATA_TYPE_UINT32_ARRAY, 94325cf1a30Sjl nflts, values, NULL); 94425cf1a30Sjl 94525cf1a30Sjl for (i = 0; i < nflts; i++) 94625cf1a30Sjl values[i] = mc_aflt->mflt_stat[i]->mf_cntl; 94725cf1a30Sjl 94825cf1a30Sjl fm_payload_set(ereport, MC_OPL_STATUS, DATA_TYPE_UINT32_ARRAY, 94925cf1a30Sjl nflts, values, NULL); 95025cf1a30Sjl 95125cf1a30Sjl for (i = 0; i < nflts; i++) 95225cf1a30Sjl values[i] = mc_aflt->mflt_stat[i]->mf_err_add; 95325cf1a30Sjl 9540cc8ae86Sav /* offset is set only for PCE */ 9550cc8ae86Sav if (mc_aflt->mflt_stat[0]->mf_type == FLT_TYPE_PERMANENT_CE) { 9560cc8ae86Sav offset = values[0]; 9570cc8ae86Sav 9580cc8ae86Sav } 95925cf1a30Sjl fm_payload_set(ereport, MC_OPL_ERR_ADD, DATA_TYPE_UINT32_ARRAY, 96025cf1a30Sjl nflts, values, NULL); 96125cf1a30Sjl 96225cf1a30Sjl for (i = 0; i < nflts; i++) 96325cf1a30Sjl values[i] = mc_aflt->mflt_stat[i]->mf_err_log; 96425cf1a30Sjl 96525cf1a30Sjl fm_payload_set(ereport, MC_OPL_ERR_LOG, DATA_TYPE_UINT32_ARRAY, 96625cf1a30Sjl nflts, values, NULL); 96725cf1a30Sjl 96825cf1a30Sjl for (i = 0; i < nflts; i++) { 96925cf1a30Sjl flt_stat = mc_aflt->mflt_stat[i]; 97025cf1a30Sjl if (flt_stat->mf_errlog_valid) { 97125cf1a30Sjl synd[i] = flt_stat->mf_synd; 97225cf1a30Sjl dslot[i] = flt_stat->mf_dimm_slot; 97325cf1a30Sjl values[i] = flt_stat->mf_dram_place; 97425cf1a30Sjl } else { 97525cf1a30Sjl synd[i] = 0; 97625cf1a30Sjl dslot[i] = 0; 97725cf1a30Sjl values[i] = 0; 97825cf1a30Sjl } 97925cf1a30Sjl } 98025cf1a30Sjl 98125cf1a30Sjl fm_payload_set(ereport, MC_OPL_ERR_SYND, 98225cf1a30Sjl DATA_TYPE_UINT32_ARRAY, nflts, synd, NULL); 98325cf1a30Sjl 98425cf1a30Sjl fm_payload_set(ereport, MC_OPL_ERR_DIMMSLOT, 98525cf1a30Sjl DATA_TYPE_UINT32_ARRAY, nflts, dslot, NULL); 98625cf1a30Sjl 98725cf1a30Sjl fm_payload_set(ereport, MC_OPL_ERR_DRAM, 98825cf1a30Sjl DATA_TYPE_UINT32_ARRAY, nflts, values, NULL); 98925cf1a30Sjl 99025cf1a30Sjl device_path[0] = 0; 99125cf1a30Sjl p = &device_path[0]; 9920cc8ae86Sav sid[0] = 0; 9930cc8ae86Sav s = &sid[0]; 9940cc8ae86Sav ret = 0; 99525cf1a30Sjl 99625cf1a30Sjl for (i = 0; i < nflts; i++) { 9970cc8ae86Sav int bank; 99825cf1a30Sjl 99925cf1a30Sjl flt_stat = mc_aflt->mflt_stat[i]; 10000cc8ae86Sav bank = flt_stat->mf_flt_maddr.ma_bank; 10010cc8ae86Sav ret = mc_set_mem_unum(p + strlen(p), blen, 10020cc8ae86Sav flt_stat->mf_flt_maddr.ma_bd, bank, flt_stat->mf_type, 10030cc8ae86Sav flt_stat->mf_dimm_slot); 10040cc8ae86Sav 10050cc8ae86Sav if (ret != 0) { 10060cc8ae86Sav cmn_err(CE_WARN, 10070cc8ae86Sav "mc_ereport_post: Failed to determine the unum " 10080cc8ae86Sav "for board=%d bank=%d type=0x%x slot=0x%x", 10090cc8ae86Sav flt_stat->mf_flt_maddr.ma_bd, bank, 10100cc8ae86Sav flt_stat->mf_type, flt_stat->mf_dimm_slot); 10110cc8ae86Sav continue; 101225cf1a30Sjl } 10130cc8ae86Sav n = strlen(device_path); 101425cf1a30Sjl blen = MAXPATHLEN - n; 101525cf1a30Sjl p = &device_path[n]; 101625cf1a30Sjl if (i < (nflts - 1)) { 101725cf1a30Sjl snprintf(p, blen, " "); 10180cc8ae86Sav blen--; 10190cc8ae86Sav p++; 10200cc8ae86Sav } 10210cc8ae86Sav 10220cc8ae86Sav if (ret == 0) { 10230cc8ae86Sav ret = mc_set_mem_sid(mc_aflt->mflt_mcp, s + strlen(s), 10240cc8ae86Sav blen, flt_stat->mf_flt_maddr.ma_bd, bank, 10250cc8ae86Sav flt_stat->mf_type, flt_stat->mf_dimm_slot); 10260cc8ae86Sav 102725cf1a30Sjl } 102825cf1a30Sjl } 102925cf1a30Sjl 103025cf1a30Sjl (void) fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, 10310cc8ae86Sav NULL, device_path, (ret == 0) ? sid : NULL, 10320cc8ae86Sav (ret == 0) ? offset : (uint64_t)-1); 103325cf1a30Sjl 103425cf1a30Sjl fm_payload_set(ereport, MC_OPL_RESOURCE, DATA_TYPE_NVLIST, 103525cf1a30Sjl resource, NULL); 103625cf1a30Sjl 103725cf1a30Sjl if (panicstr) { 103825cf1a30Sjl errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC); 103925cf1a30Sjl } else { 104025cf1a30Sjl (void) fm_ereport_post(ereport, EVCH_TRYHARD); 104125cf1a30Sjl fm_nvlist_destroy(ereport, FM_NVA_FREE); 104225cf1a30Sjl fm_nvlist_destroy(detector, FM_NVA_FREE); 104325cf1a30Sjl fm_nvlist_destroy(resource, FM_NVA_FREE); 104425cf1a30Sjl } 104525cf1a30Sjl } 104625cf1a30Sjl 10470cc8ae86Sav 104825cf1a30Sjl static void 104925cf1a30Sjl mc_err_drain(mc_aflt_t *mc_aflt) 105025cf1a30Sjl { 105125cf1a30Sjl int rv; 105225cf1a30Sjl page_t *pp; 105325cf1a30Sjl uint64_t errors; 105425cf1a30Sjl uint64_t pa = (uint64_t)(-1); 10550cc8ae86Sav int i; 105625cf1a30Sjl 105725cf1a30Sjl MC_LOG("mc_err_drain: %s\n", 105825cf1a30Sjl mc_aflt->mflt_erpt_class); 105925cf1a30Sjl /* 106025cf1a30Sjl * we come here only when we have: 106125cf1a30Sjl * In mirror mode: CMPE, MUE, SUE 106225cf1a30Sjl * In normal mode: UE, Permanent CE 106325cf1a30Sjl */ 10640cc8ae86Sav for (i = 0; i < mc_aflt->mflt_nflts; i++) { 10650cc8ae86Sav rv = mcaddr_to_pa(mc_aflt->mflt_mcp, 10660cc8ae86Sav &(mc_aflt->mflt_stat[i]->mf_flt_maddr), &pa); 10670cc8ae86Sav if (rv == 0) 10680cc8ae86Sav mc_aflt->mflt_stat[i]->mf_flt_paddr = pa; 10690cc8ae86Sav else 10700cc8ae86Sav mc_aflt->mflt_stat[i]->mf_flt_paddr = (uint64_t)-1; 10710cc8ae86Sav } 10720cc8ae86Sav 10730cc8ae86Sav if (mc_aflt->mflt_stat[0]->mf_type != FLT_TYPE_PERMANENT_CE) { 107425cf1a30Sjl MC_LOG("mc_err_drain:pa = %lx\n", pa); 107525cf1a30Sjl pp = page_numtopp_nolock(pa >> PAGESHIFT); 107625cf1a30Sjl 107725cf1a30Sjl if (pp) { 107825cf1a30Sjl /* 107925cf1a30Sjl * Don't keep retiring and make ereports 108025cf1a30Sjl * on bad pages in PTRL case 108125cf1a30Sjl */ 108225cf1a30Sjl MC_LOG("mc_err_drain:pp = %p\n", pp); 108325cf1a30Sjl if (mc_aflt->mflt_is_ptrl) { 108425cf1a30Sjl errors = 0; 108525cf1a30Sjl if (page_retire_check(pa, &errors) == 0) { 108625cf1a30Sjl MC_LOG("Page retired\n"); 108725cf1a30Sjl return; 108825cf1a30Sjl } 108925cf1a30Sjl if (errors & mc_aflt->mflt_pr) { 109025cf1a30Sjl MC_LOG("errors %lx, mflt_pr %x\n", 109125cf1a30Sjl errors, mc_aflt->mflt_pr); 109225cf1a30Sjl return; 109325cf1a30Sjl } 109425cf1a30Sjl } 109525cf1a30Sjl MC_LOG("offline page %p error %x\n", pp, 109625cf1a30Sjl mc_aflt->mflt_pr); 109725cf1a30Sjl (void) page_retire(pa, mc_aflt->mflt_pr); 109825cf1a30Sjl } 109925cf1a30Sjl } 110025cf1a30Sjl 11010cc8ae86Sav for (i = 0; i < mc_aflt->mflt_nflts; i++) { 11020cc8ae86Sav mc_aflt_t mc_aflt0; 11030cc8ae86Sav if (mc_aflt->mflt_stat[i]->mf_flt_paddr != (uint64_t)-1) { 11040cc8ae86Sav mc_aflt0 = *mc_aflt; 11050cc8ae86Sav mc_aflt0.mflt_nflts = 1; 11060cc8ae86Sav mc_aflt0.mflt_stat[0] = mc_aflt->mflt_stat[i]; 11070cc8ae86Sav mc_ereport_post(&mc_aflt0); 11080cc8ae86Sav } 11090cc8ae86Sav } 11100cc8ae86Sav } 111125cf1a30Sjl 111225cf1a30Sjl /* 111325cf1a30Sjl * The restart address is actually defined in unit of PA[37:6] 111425cf1a30Sjl * the mac patrol will convert that to dimm offset. If the 111525cf1a30Sjl * address is not in the bank, it will continue to search for 111625cf1a30Sjl * the next PA that is within the bank. 111725cf1a30Sjl * 111825cf1a30Sjl * Also the mac patrol scans the dimms based on PA, not 111925cf1a30Sjl * dimm offset. 112025cf1a30Sjl */ 112125cf1a30Sjl static int 112225cf1a30Sjl restart_patrol(mc_opl_t *mcp, int bank, mc_addr_info_t *maddr_info) 112325cf1a30Sjl { 112425cf1a30Sjl page_t *pp; 112525cf1a30Sjl uint64_t pa; 112625cf1a30Sjl int rv; 112725cf1a30Sjl int loop_count = 0; 112825cf1a30Sjl 112925cf1a30Sjl if (maddr_info == NULL || (maddr_info->mi_valid == 0)) { 113025cf1a30Sjl MAC_PTRL_START(mcp, bank); 113125cf1a30Sjl return (0); 113225cf1a30Sjl } 113325cf1a30Sjl 113425cf1a30Sjl rv = mcaddr_to_pa(mcp, &maddr_info->mi_maddr, &pa); 113525cf1a30Sjl if (rv != 0) { 113625cf1a30Sjl MC_LOG("cannot convert mcaddr to pa. use auto restart\n"); 113725cf1a30Sjl MAC_PTRL_START(mcp, bank); 113825cf1a30Sjl return (0); 113925cf1a30Sjl } 114025cf1a30Sjl 114125cf1a30Sjl /* 114225cf1a30Sjl * pa is the last address scanned by the mac patrol 114325cf1a30Sjl * we calculate the next restart address as follows: 114425cf1a30Sjl * first we always advance it by 64 byte. Then begin the loop. 114525cf1a30Sjl * loop { 114625cf1a30Sjl * if it is not in phys_install, we advance to next 64 MB boundary 114725cf1a30Sjl * if it is not backed by a page structure, done 114825cf1a30Sjl * if the page is bad, advance to the next page boundary. 114925cf1a30Sjl * else done 115025cf1a30Sjl * if the new address exceeds the board, wrap around. 115125cf1a30Sjl * } <stop if we come back to the same page> 115225cf1a30Sjl */ 115325cf1a30Sjl 115425cf1a30Sjl if (pa < mcp->mc_start_address || pa >= (mcp->mc_start_address 115525cf1a30Sjl + mcp->mc_size)) { 115625cf1a30Sjl /* pa is not on this board, just retry */ 115725cf1a30Sjl cmn_err(CE_WARN, "restart_patrol: invalid address %lx " 115825cf1a30Sjl "on board %d\n", pa, mcp->mc_board_num); 115925cf1a30Sjl MAC_PTRL_START(mcp, bank); 116025cf1a30Sjl return (0); 116125cf1a30Sjl } 116225cf1a30Sjl 116325cf1a30Sjl MC_LOG("restart_patrol: pa = %lx\n", pa); 116425cf1a30Sjl if (maddr_info->mi_advance) { 116525cf1a30Sjl uint64_t new_pa; 116625cf1a30Sjl 116725cf1a30Sjl if (IS_MIRROR(mcp, bank)) 116825cf1a30Sjl new_pa = pa + 64 * 2; 116925cf1a30Sjl else 117025cf1a30Sjl new_pa = pa + 64; 117125cf1a30Sjl 117225cf1a30Sjl if (!mc_valid_pa(mcp, new_pa)) { 117325cf1a30Sjl MC_LOG("Invalid PA\n"); 11740cc8ae86Sav pa = roundup(new_pa + 1, mc_isolation_bsize); 117525cf1a30Sjl } else { 117625cf1a30Sjl pp = page_numtopp_nolock(new_pa >> PAGESHIFT); 117725cf1a30Sjl if (pp != NULL) { 117825cf1a30Sjl uint64_t errors = 0; 117925cf1a30Sjl if (page_retire_check(new_pa, &errors) && 118025cf1a30Sjl (errors == 0)) { 118125cf1a30Sjl MC_LOG("Page has no error\n"); 11820cc8ae86Sav pa = new_pa; 11830cc8ae86Sav goto done; 118425cf1a30Sjl } 118525cf1a30Sjl /* 118625cf1a30Sjl * skip bad pages 118725cf1a30Sjl * and let the following loop to take care 118825cf1a30Sjl */ 118925cf1a30Sjl pa = roundup(new_pa + 1, PAGESIZE); 119025cf1a30Sjl MC_LOG("Skipping bad page to %lx\n", pa); 119125cf1a30Sjl } else { 119225cf1a30Sjl MC_LOG("Page has no page structure\n"); 11930cc8ae86Sav pa = new_pa; 11940cc8ae86Sav goto done; 119525cf1a30Sjl } 119625cf1a30Sjl } 119725cf1a30Sjl } 119825cf1a30Sjl 119925cf1a30Sjl /* 120025cf1a30Sjl * if we wrap around twice, we just give up and let 120125cf1a30Sjl * mac patrol decide. 120225cf1a30Sjl */ 120325cf1a30Sjl MC_LOG("pa is now %lx\n", pa); 120425cf1a30Sjl while (loop_count <= 1) { 120525cf1a30Sjl if (!mc_valid_pa(mcp, pa)) { 120625cf1a30Sjl MC_LOG("pa is not valid. round up to 64 MB\n"); 120725cf1a30Sjl pa = roundup(pa + 1, 64 * 1024 * 1024); 120825cf1a30Sjl } else { 120925cf1a30Sjl pp = page_numtopp_nolock(pa >> PAGESHIFT); 121025cf1a30Sjl if (pp != NULL) { 121125cf1a30Sjl uint64_t errors = 0; 121225cf1a30Sjl if (page_retire_check(pa, &errors) && 121325cf1a30Sjl (errors == 0)) { 121425cf1a30Sjl MC_LOG("Page has no error\n"); 121525cf1a30Sjl break; 121625cf1a30Sjl } 121725cf1a30Sjl /* skip bad pages */ 121825cf1a30Sjl pa = roundup(pa + 1, PAGESIZE); 121925cf1a30Sjl MC_LOG("Skipping bad page to %lx\n", pa); 122025cf1a30Sjl } else { 122125cf1a30Sjl MC_LOG("Page has no page structure\n"); 122225cf1a30Sjl break; 122325cf1a30Sjl } 122425cf1a30Sjl } 122525cf1a30Sjl if (pa >= (mcp->mc_start_address + mcp->mc_size)) { 122625cf1a30Sjl MC_LOG("Wrap around\n"); 122725cf1a30Sjl pa = mcp->mc_start_address; 122825cf1a30Sjl loop_count++; 122925cf1a30Sjl } 123025cf1a30Sjl } 123125cf1a30Sjl 12320cc8ae86Sav done: 123325cf1a30Sjl /* retstart MAC patrol: PA[37:6] */ 123425cf1a30Sjl MC_LOG("restart at pa = %lx\n", pa); 123525cf1a30Sjl ST_MAC_REG(MAC_RESTART_ADD(mcp, bank), MAC_RESTART_PA(pa)); 123625cf1a30Sjl MAC_PTRL_START_ADD(mcp, bank); 123725cf1a30Sjl 123825cf1a30Sjl return (0); 123925cf1a30Sjl } 124025cf1a30Sjl 124125cf1a30Sjl /* 124225cf1a30Sjl * Rewriting is used for two purposes. 124325cf1a30Sjl * - to correct the error in memory. 124425cf1a30Sjl * - to determine whether the error is permanent or intermittent. 124525cf1a30Sjl * It's done by writing the address in MAC_BANKm_REWRITE_ADD 124625cf1a30Sjl * and issuing REW_REQ command in MAC_BANKm_PTRL_CNRL. After that, 124725cf1a30Sjl * REW_END (and REW_CE/REW_UE if some error detected) is set when 124825cf1a30Sjl * rewrite operation is done. See 4.7.3 and 4.7.11 in Columbus2 PRM. 124925cf1a30Sjl * 125025cf1a30Sjl * Note that rewrite operation doesn't change RAW_UE to Marked UE. 125125cf1a30Sjl * Therefore, we use it only CE case. 125225cf1a30Sjl */ 125325cf1a30Sjl static uint32_t 125425cf1a30Sjl do_rewrite(mc_opl_t *mcp, int bank, uint32_t dimm_addr) 125525cf1a30Sjl { 125625cf1a30Sjl uint32_t cntl; 125725cf1a30Sjl int count = 0; 125825cf1a30Sjl 125925cf1a30Sjl /* first wait to make sure PTRL_STATUS is 0 */ 12600cc8ae86Sav while (count++ < mc_max_rewrite_loop) { 126125cf1a30Sjl cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 126225cf1a30Sjl if (!(cntl & MAC_CNTL_PTRL_STATUS)) 126325cf1a30Sjl break; 12640cc8ae86Sav drv_usecwait(mc_rewrite_delay); 126525cf1a30Sjl } 12660cc8ae86Sav if (count >= mc_max_rewrite_loop) 126725cf1a30Sjl goto bad; 126825cf1a30Sjl 126925cf1a30Sjl count = 0; 127025cf1a30Sjl 127125cf1a30Sjl ST_MAC_REG(MAC_REWRITE_ADD(mcp, bank), dimm_addr); 127225cf1a30Sjl MAC_REW_REQ(mcp, bank); 127325cf1a30Sjl 127425cf1a30Sjl do { 127525cf1a30Sjl cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 12760cc8ae86Sav if (count++ >= mc_max_rewrite_loop) { 127725cf1a30Sjl goto bad; 12780cc8ae86Sav } else { 12790cc8ae86Sav drv_usecwait(mc_rewrite_delay); 12800cc8ae86Sav } 128125cf1a30Sjl /* 128225cf1a30Sjl * If there are other MEMORY or PCI activities, this 128325cf1a30Sjl * will be BUSY, else it should be set immediately 128425cf1a30Sjl */ 128525cf1a30Sjl } while (!(cntl & MAC_CNTL_REW_END)); 128625cf1a30Sjl 128725cf1a30Sjl MAC_CLEAR_ERRS(mcp, bank, MAC_CNTL_REW_ERRS); 128825cf1a30Sjl return (cntl); 128925cf1a30Sjl bad: 129025cf1a30Sjl /* This is bad. Just reset the circuit */ 129125cf1a30Sjl cmn_err(CE_WARN, "mc-opl rewrite timeout on /LSB%d/B%d\n", 129225cf1a30Sjl mcp->mc_board_num, bank); 129325cf1a30Sjl cntl = MAC_CNTL_REW_END; 129425cf1a30Sjl MAC_CMD(mcp, bank, MAC_CNTL_PTRL_RESET); 129525cf1a30Sjl MAC_CLEAR_ERRS(mcp, bank, MAC_CNTL_REW_ERRS); 129625cf1a30Sjl return (cntl); 129725cf1a30Sjl } 129825cf1a30Sjl void 129925cf1a30Sjl mc_process_scf_log(mc_opl_t *mcp) 130025cf1a30Sjl { 13010cc8ae86Sav int count; 13020cc8ae86Sav int n = 0; 130325cf1a30Sjl scf_log_t *p; 130425cf1a30Sjl int bank; 130525cf1a30Sjl 13060cc8ae86Sav for (bank = 0; bank < BANKNUM_PER_SB; bank++) { 13070cc8ae86Sav while ((p = mcp->mc_scf_log[bank]) != NULL && 13080cc8ae86Sav (n < mc_max_errlog_processed)) { 13090cc8ae86Sav ASSERT(bank == p->sl_bank); 13100cc8ae86Sav count = 0; 131125cf1a30Sjl while ((LD_MAC_REG(MAC_STATIC_ERR_ADD(mcp, p->sl_bank)) 131225cf1a30Sjl & MAC_STATIC_ERR_VLD)) { 13130cc8ae86Sav if (count++ >= (mc_max_scf_loop)) { 131425cf1a30Sjl break; 131525cf1a30Sjl } 13160cc8ae86Sav drv_usecwait(mc_scf_delay); 131725cf1a30Sjl } 131825cf1a30Sjl 13190cc8ae86Sav if (count < mc_max_scf_loop) { 132025cf1a30Sjl ST_MAC_REG(MAC_STATIC_ERR_LOG(mcp, p->sl_bank), 132125cf1a30Sjl p->sl_err_log); 132225cf1a30Sjl 132325cf1a30Sjl ST_MAC_REG(MAC_STATIC_ERR_ADD(mcp, p->sl_bank), 132425cf1a30Sjl p->sl_err_add|MAC_STATIC_ERR_VLD); 132525cf1a30Sjl mcp->mc_scf_retry[bank] = 0; 132625cf1a30Sjl } else { 132725cf1a30Sjl /* if we try too many times, just drop the req */ 13280cc8ae86Sav if (mcp->mc_scf_retry[bank]++ <= mc_max_scf_retry) { 132925cf1a30Sjl return; 133025cf1a30Sjl } else { 13310cc8ae86Sav if ((++mc_pce_dropped & 0xff) == 0) { 13320cc8ae86Sav cmn_err(CE_WARN, 13330cc8ae86Sav "Cannot report Permanent CE to SCF\n"); 13340cc8ae86Sav } 133525cf1a30Sjl } 133625cf1a30Sjl } 13370cc8ae86Sav n++; 13380cc8ae86Sav mcp->mc_scf_log[bank] = p->sl_next; 13390cc8ae86Sav mcp->mc_scf_total[bank]--; 13400cc8ae86Sav ASSERT(mcp->mc_scf_total[bank] >= 0); 134125cf1a30Sjl kmem_free(p, sizeof (scf_log_t)); 13420cc8ae86Sav } 134325cf1a30Sjl } 134425cf1a30Sjl } 134525cf1a30Sjl void 134625cf1a30Sjl mc_queue_scf_log(mc_opl_t *mcp, mc_flt_stat_t *flt_stat, int bank) 134725cf1a30Sjl { 134825cf1a30Sjl scf_log_t *p; 134925cf1a30Sjl 13500cc8ae86Sav if (mcp->mc_scf_total[bank] >= mc_max_scf_logs) { 13510cc8ae86Sav if ((++mc_pce_dropped & 0xff) == 0) { 13520cc8ae86Sav cmn_err(CE_WARN, "Too many Permanent CE requests.\n"); 13530cc8ae86Sav } 135425cf1a30Sjl return; 135525cf1a30Sjl } 135625cf1a30Sjl p = kmem_zalloc(sizeof (scf_log_t), KM_SLEEP); 135725cf1a30Sjl p->sl_next = 0; 135825cf1a30Sjl p->sl_err_add = flt_stat->mf_err_add; 135925cf1a30Sjl p->sl_err_log = flt_stat->mf_err_log; 136025cf1a30Sjl p->sl_bank = bank; 136125cf1a30Sjl 13620cc8ae86Sav if (mcp->mc_scf_log[bank] == NULL) { 136325cf1a30Sjl /* 136425cf1a30Sjl * we rely on mc_scf_log to detect NULL queue. 136525cf1a30Sjl * mc_scf_log_tail is irrelevant is such case. 136625cf1a30Sjl */ 13670cc8ae86Sav mcp->mc_scf_log_tail[bank] = mcp->mc_scf_log[bank] = p; 136825cf1a30Sjl } else { 13690cc8ae86Sav mcp->mc_scf_log_tail[bank]->sl_next = p; 13700cc8ae86Sav mcp->mc_scf_log_tail[bank] = p; 137125cf1a30Sjl } 13720cc8ae86Sav mcp->mc_scf_total[bank]++; 137325cf1a30Sjl } 137425cf1a30Sjl /* 137525cf1a30Sjl * This routine determines what kind of CE happens, intermittent 137625cf1a30Sjl * or permanent as follows. (See 4.7.3 in Columbus2 PRM.) 137725cf1a30Sjl * - Do rewrite by issuing REW_REQ command to MAC_PTRL_CNTL register. 137825cf1a30Sjl * - If CE is still detected on the same address even after doing 137925cf1a30Sjl * rewrite operation twice, it is determined as permanent error. 138025cf1a30Sjl * - If error is not detected anymore, it is determined as intermittent 138125cf1a30Sjl * error. 138225cf1a30Sjl * - If UE is detected due to rewrite operation, it should be treated 138325cf1a30Sjl * as UE. 138425cf1a30Sjl */ 138525cf1a30Sjl 138625cf1a30Sjl /* ARGSUSED */ 138725cf1a30Sjl static void 138825cf1a30Sjl mc_scrub_ce(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat, int ptrl_error) 138925cf1a30Sjl { 139025cf1a30Sjl uint32_t cntl; 139125cf1a30Sjl int i; 139225cf1a30Sjl 139325cf1a30Sjl flt_stat->mf_type = FLT_TYPE_PERMANENT_CE; 139425cf1a30Sjl /* 139525cf1a30Sjl * rewrite request 1st time reads and correct error data 139625cf1a30Sjl * and write to DIMM. 2nd rewrite request must be issued 139725cf1a30Sjl * after REW_CE/UE/END is 0. When the 2nd request is completed, 139825cf1a30Sjl * if REW_CE = 1, then it is permanent CE. 139925cf1a30Sjl */ 140025cf1a30Sjl for (i = 0; i < 2; i++) { 140125cf1a30Sjl cntl = do_rewrite(mcp, bank, flt_stat->mf_err_add); 140225cf1a30Sjl /* 140325cf1a30Sjl * If the error becomes UE or CMPE 140425cf1a30Sjl * we return to the caller immediately. 140525cf1a30Sjl */ 140625cf1a30Sjl if (cntl & MAC_CNTL_REW_UE) { 140725cf1a30Sjl if (ptrl_error) 140825cf1a30Sjl flt_stat->mf_cntl |= MAC_CNTL_PTRL_UE; 140925cf1a30Sjl else 141025cf1a30Sjl flt_stat->mf_cntl |= MAC_CNTL_MI_UE; 141125cf1a30Sjl flt_stat->mf_type = FLT_TYPE_UE; 141225cf1a30Sjl return; 141325cf1a30Sjl } 141425cf1a30Sjl if (cntl & MAC_CNTL_REW_CMPE) { 141525cf1a30Sjl if (ptrl_error) 141625cf1a30Sjl flt_stat->mf_cntl |= MAC_CNTL_PTRL_CMPE; 141725cf1a30Sjl else 141825cf1a30Sjl flt_stat->mf_cntl |= MAC_CNTL_MI_CMPE; 141925cf1a30Sjl flt_stat->mf_type = FLT_TYPE_CMPE; 142025cf1a30Sjl return; 142125cf1a30Sjl } 142225cf1a30Sjl } 142325cf1a30Sjl if (!(cntl & MAC_CNTL_REW_CE)) { 142425cf1a30Sjl flt_stat->mf_type = FLT_TYPE_INTERMITTENT_CE; 142525cf1a30Sjl } 142625cf1a30Sjl 142725cf1a30Sjl if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) { 142825cf1a30Sjl /* report PERMANENT_CE to SP via SCF */ 142925cf1a30Sjl if (!(flt_stat->mf_err_log & MAC_ERR_LOG_INVALID)) { 143025cf1a30Sjl mc_queue_scf_log(mcp, flt_stat, bank); 143125cf1a30Sjl } 143225cf1a30Sjl } 143325cf1a30Sjl } 143425cf1a30Sjl 143525cf1a30Sjl #define IS_CMPE(cntl, f) ((cntl) & ((f) ? MAC_CNTL_PTRL_CMPE :\ 143625cf1a30Sjl MAC_CNTL_MI_CMPE)) 143725cf1a30Sjl #define IS_UE(cntl, f) ((cntl) & ((f) ? MAC_CNTL_PTRL_UE : MAC_CNTL_MI_UE)) 143825cf1a30Sjl #define IS_CE(cntl, f) ((cntl) & ((f) ? MAC_CNTL_PTRL_CE : MAC_CNTL_MI_CE)) 143925cf1a30Sjl #define IS_OK(cntl, f) (!((cntl) & ((f) ? MAC_CNTL_PTRL_ERRS : \ 144025cf1a30Sjl MAC_CNTL_MI_ERRS))) 144125cf1a30Sjl 144225cf1a30Sjl 144325cf1a30Sjl static int 144425cf1a30Sjl IS_CE_ONLY(uint32_t cntl, int ptrl_error) 144525cf1a30Sjl { 144625cf1a30Sjl if (ptrl_error) { 144725cf1a30Sjl return ((cntl & MAC_CNTL_PTRL_ERRS) == MAC_CNTL_PTRL_CE); 144825cf1a30Sjl } else { 144925cf1a30Sjl return ((cntl & MAC_CNTL_MI_ERRS) == MAC_CNTL_MI_CE); 145025cf1a30Sjl } 145125cf1a30Sjl } 145225cf1a30Sjl 145325cf1a30Sjl void 145425cf1a30Sjl mc_write_cntl(mc_opl_t *mcp, int bank, uint32_t value) 145525cf1a30Sjl { 14560cc8ae86Sav if (mcp->mc_speedup_period[bank] > 0) 14570cc8ae86Sav value |= mc_max_speed; 14580cc8ae86Sav else 14590cc8ae86Sav value |= mcp->mc_speed; 146025cf1a30Sjl ST_MAC_REG(MAC_PTRL_CNTL(mcp, bank), value); 146125cf1a30Sjl } 146225cf1a30Sjl 146325cf1a30Sjl static void 146425cf1a30Sjl mc_read_ptrl_reg(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat) 146525cf1a30Sjl { 146625cf1a30Sjl flt_stat->mf_cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & 146725cf1a30Sjl MAC_CNTL_PTRL_ERRS; 146825cf1a30Sjl flt_stat->mf_err_add = LD_MAC_REG(MAC_PTRL_ERR_ADD(mcp, bank)); 146925cf1a30Sjl flt_stat->mf_err_log = LD_MAC_REG(MAC_PTRL_ERR_LOG(mcp, bank)); 147025cf1a30Sjl flt_stat->mf_flt_maddr.ma_bd = mcp->mc_board_num; 147125cf1a30Sjl flt_stat->mf_flt_maddr.ma_bank = bank; 147225cf1a30Sjl flt_stat->mf_flt_maddr.ma_dimm_addr = flt_stat->mf_err_add; 147325cf1a30Sjl } 147425cf1a30Sjl 147525cf1a30Sjl static void 147625cf1a30Sjl mc_read_mi_reg(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat) 147725cf1a30Sjl { 147825cf1a30Sjl uint32_t status, old_status; 147925cf1a30Sjl 148025cf1a30Sjl status = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & 148125cf1a30Sjl MAC_CNTL_MI_ERRS; 148225cf1a30Sjl old_status = 0; 148325cf1a30Sjl 148425cf1a30Sjl /* we keep reading until the status is stable */ 148525cf1a30Sjl while (old_status != status) { 148625cf1a30Sjl old_status = status; 148725cf1a30Sjl flt_stat->mf_err_add = 148825cf1a30Sjl LD_MAC_REG(MAC_MI_ERR_ADD(mcp, bank)); 148925cf1a30Sjl flt_stat->mf_err_log = 149025cf1a30Sjl LD_MAC_REG(MAC_MI_ERR_LOG(mcp, bank)); 149125cf1a30Sjl status = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & 149225cf1a30Sjl MAC_CNTL_MI_ERRS; 149325cf1a30Sjl if (status == old_status) { 149425cf1a30Sjl break; 149525cf1a30Sjl } 149625cf1a30Sjl } 149725cf1a30Sjl 149825cf1a30Sjl flt_stat->mf_cntl = status; 149925cf1a30Sjl flt_stat->mf_flt_maddr.ma_bd = mcp->mc_board_num; 150025cf1a30Sjl flt_stat->mf_flt_maddr.ma_bank = bank; 150125cf1a30Sjl flt_stat->mf_flt_maddr.ma_dimm_addr = flt_stat->mf_err_add; 150225cf1a30Sjl } 150325cf1a30Sjl 150425cf1a30Sjl 150525cf1a30Sjl /* 150625cf1a30Sjl * Error philosophy for mirror mode: 150725cf1a30Sjl * 150825cf1a30Sjl * PTRL (The error address for both banks are same, since ptrl stops if it 150925cf1a30Sjl * detects error.) 151025cf1a30Sjl * - Compaire error Report CMPE. 151125cf1a30Sjl * 151225cf1a30Sjl * - UE-UE Report MUE. No rewrite. 151325cf1a30Sjl * 151425cf1a30Sjl * - UE-* UE-(CE/OK). Rewrite to scrub UE. Report SUE. 151525cf1a30Sjl * 151625cf1a30Sjl * - CE-* CE-(CE/OK). Scrub to determine if CE is permanent. 151725cf1a30Sjl * If CE is permanent, inform SCF. Once for each 151825cf1a30Sjl * Dimm. If CE becomes UE or CMPE, go back to above. 151925cf1a30Sjl * 152025cf1a30Sjl * 152125cf1a30Sjl * MI (The error addresses for each bank are the same or different.) 152225cf1a30Sjl * - Compair error If addresses are the same. Just CMPE. 152325cf1a30Sjl * If addresses are different (this could happen 152425cf1a30Sjl * as a result of scrubbing. Report each seperately. 152525cf1a30Sjl * Only report error info on each side. 152625cf1a30Sjl * 152725cf1a30Sjl * - UE-UE Addresses are the same. Report MUE. 152825cf1a30Sjl * Addresses are different. Report SUE on each bank. 152925cf1a30Sjl * Rewrite to clear UE. 153025cf1a30Sjl * 153125cf1a30Sjl * - UE-* UE-(CE/OK) 153225cf1a30Sjl * Rewrite to clear UE. Report SUE for the bank. 153325cf1a30Sjl * 153425cf1a30Sjl * - CE-* CE-(CE/OK). Scrub to determine if CE is permanent. 153525cf1a30Sjl * If CE becomes UE or CMPE, go back to above. 153625cf1a30Sjl * 153725cf1a30Sjl */ 153825cf1a30Sjl 153925cf1a30Sjl static int 154025cf1a30Sjl mc_process_error_mir(mc_opl_t *mcp, mc_aflt_t *mc_aflt, mc_flt_stat_t *flt_stat) 154125cf1a30Sjl { 154225cf1a30Sjl int ptrl_error = mc_aflt->mflt_is_ptrl; 154325cf1a30Sjl int i; 154425cf1a30Sjl int rv = 0; 154525cf1a30Sjl 154625cf1a30Sjl MC_LOG("process mirror errors cntl[0] = %x, cntl[1] = %x\n", 154725cf1a30Sjl flt_stat[0].mf_cntl, flt_stat[1].mf_cntl); 154825cf1a30Sjl 154925cf1a30Sjl if (ptrl_error) { 155025cf1a30Sjl if (((flt_stat[0].mf_cntl | flt_stat[1].mf_cntl) 155125cf1a30Sjl & MAC_CNTL_PTRL_ERRS) == 0) 155225cf1a30Sjl return (0); 155325cf1a30Sjl } else { 155425cf1a30Sjl if (((flt_stat[0].mf_cntl | flt_stat[1].mf_cntl) 155525cf1a30Sjl & MAC_CNTL_MI_ERRS) == 0) 155625cf1a30Sjl return (0); 155725cf1a30Sjl } 155825cf1a30Sjl 155925cf1a30Sjl /* 156025cf1a30Sjl * First we take care of the case of CE 156125cf1a30Sjl * because they can become UE or CMPE 156225cf1a30Sjl */ 156325cf1a30Sjl for (i = 0; i < 2; i++) { 156425cf1a30Sjl if (IS_CE_ONLY(flt_stat[i].mf_cntl, ptrl_error)) { 156525cf1a30Sjl MC_LOG("CE detected on bank %d\n", 156625cf1a30Sjl flt_stat[i].mf_flt_maddr.ma_bank); 156725cf1a30Sjl mc_scrub_ce(mcp, flt_stat[i].mf_flt_maddr.ma_bank, 156825cf1a30Sjl &flt_stat[i], ptrl_error); 156925cf1a30Sjl rv = 1; 157025cf1a30Sjl } 157125cf1a30Sjl } 157225cf1a30Sjl 157325cf1a30Sjl /* The above scrubbing can turn CE into UE or CMPE */ 157425cf1a30Sjl 157525cf1a30Sjl /* 157625cf1a30Sjl * Now we distinguish two cases: same address or not 157725cf1a30Sjl * the same address. It might seem more intuitive to 157825cf1a30Sjl * distinguish PTRL v.s. MI error but it is more 157925cf1a30Sjl * complicated that way. 158025cf1a30Sjl */ 158125cf1a30Sjl 158225cf1a30Sjl if (flt_stat[0].mf_err_add == flt_stat[1].mf_err_add) { 158325cf1a30Sjl 158425cf1a30Sjl if (IS_CMPE(flt_stat[0].mf_cntl, ptrl_error) || 158525cf1a30Sjl IS_CMPE(flt_stat[1].mf_cntl, ptrl_error)) { 158625cf1a30Sjl flt_stat[0].mf_type = FLT_TYPE_CMPE; 158725cf1a30Sjl flt_stat[1].mf_type = FLT_TYPE_CMPE; 158825cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_CMPE; 158925cf1a30Sjl MC_LOG("cmpe error detected\n"); 159025cf1a30Sjl mc_aflt->mflt_nflts = 2; 159125cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[0]; 159225cf1a30Sjl mc_aflt->mflt_stat[1] = &flt_stat[1]; 159325cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 159425cf1a30Sjl mc_err_drain(mc_aflt); 159525cf1a30Sjl return (1); 159625cf1a30Sjl } 159725cf1a30Sjl 159825cf1a30Sjl if (IS_UE(flt_stat[0].mf_cntl, ptrl_error) && 159925cf1a30Sjl IS_UE(flt_stat[1].mf_cntl, ptrl_error)) { 160025cf1a30Sjl /* Both side are UE's */ 160125cf1a30Sjl 160225cf1a30Sjl MAC_SET_ERRLOG_INFO(&flt_stat[0]); 160325cf1a30Sjl MAC_SET_ERRLOG_INFO(&flt_stat[1]); 160425cf1a30Sjl MC_LOG("MUE detected\n"); 16050cc8ae86Sav flt_stat[0].mf_type = FLT_TYPE_MUE; 16060cc8ae86Sav flt_stat[1].mf_type = FLT_TYPE_MUE; 160725cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_MUE; 160825cf1a30Sjl mc_aflt->mflt_nflts = 2; 160925cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[0]; 161025cf1a30Sjl mc_aflt->mflt_stat[1] = &flt_stat[1]; 161125cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 161225cf1a30Sjl mc_err_drain(mc_aflt); 161325cf1a30Sjl return (1); 161425cf1a30Sjl } 161525cf1a30Sjl 161625cf1a30Sjl /* Now the only case is UE/CE, UE/OK, or don't care */ 161725cf1a30Sjl for (i = 0; i < 2; i++) { 161825cf1a30Sjl if (IS_UE(flt_stat[i].mf_cntl, ptrl_error)) { 16190cc8ae86Sav 16200cc8ae86Sav /* rewrite can clear the one side UE error */ 16210cc8ae86Sav 162225cf1a30Sjl if (IS_OK(flt_stat[i^1].mf_cntl, ptrl_error)) { 162325cf1a30Sjl (void) do_rewrite(mcp, 162425cf1a30Sjl flt_stat[i].mf_flt_maddr.ma_bank, 162525cf1a30Sjl flt_stat[i].mf_flt_maddr.ma_dimm_addr); 162625cf1a30Sjl } 162725cf1a30Sjl flt_stat[i].mf_type = FLT_TYPE_UE; 162825cf1a30Sjl MAC_SET_ERRLOG_INFO(&flt_stat[i]); 162925cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_SUE; 163025cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[i]; 163125cf1a30Sjl mc_aflt->mflt_nflts = 1; 163225cf1a30Sjl mc_aflt->mflt_pr = PR_MCE; 163325cf1a30Sjl mc_err_drain(mc_aflt); 163425cf1a30Sjl /* Once we hit a UE/CE or UE/OK case, done */ 163525cf1a30Sjl return (1); 163625cf1a30Sjl } 163725cf1a30Sjl } 163825cf1a30Sjl 163925cf1a30Sjl } else { 164025cf1a30Sjl /* 164125cf1a30Sjl * addresses are different. That means errors 164225cf1a30Sjl * on the 2 banks are not related at all. 164325cf1a30Sjl */ 164425cf1a30Sjl for (i = 0; i < 2; i++) { 164525cf1a30Sjl if (IS_CMPE(flt_stat[i].mf_cntl, ptrl_error)) { 164625cf1a30Sjl flt_stat[i].mf_type = FLT_TYPE_CMPE; 164725cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_CMPE; 164825cf1a30Sjl MC_LOG("cmpe error detected\n"); 164925cf1a30Sjl mc_aflt->mflt_nflts = 1; 165025cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[i]; 165125cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 165225cf1a30Sjl mc_err_drain(mc_aflt); 165325cf1a30Sjl /* no more report on this bank */ 165425cf1a30Sjl flt_stat[i].mf_cntl = 0; 165525cf1a30Sjl rv = 1; 165625cf1a30Sjl } 165725cf1a30Sjl } 165825cf1a30Sjl 16590cc8ae86Sav /* rewrite can clear the one side UE error */ 16600cc8ae86Sav 166125cf1a30Sjl for (i = 0; i < 2; i++) { 166225cf1a30Sjl if (IS_UE(flt_stat[i].mf_cntl, ptrl_error)) { 166325cf1a30Sjl (void) do_rewrite(mcp, 166425cf1a30Sjl flt_stat[i].mf_flt_maddr.ma_bank, 166525cf1a30Sjl flt_stat[i].mf_flt_maddr.ma_dimm_addr); 166625cf1a30Sjl flt_stat[i].mf_type = FLT_TYPE_UE; 166725cf1a30Sjl MAC_SET_ERRLOG_INFO(&flt_stat[i]); 166825cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_SUE; 166925cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[i]; 167025cf1a30Sjl mc_aflt->mflt_nflts = 1; 167125cf1a30Sjl mc_aflt->mflt_pr = PR_MCE; 167225cf1a30Sjl mc_err_drain(mc_aflt); 167325cf1a30Sjl rv = 1; 167425cf1a30Sjl } 167525cf1a30Sjl } 167625cf1a30Sjl } 167725cf1a30Sjl return (rv); 167825cf1a30Sjl } 167925cf1a30Sjl static void 168025cf1a30Sjl mc_error_handler_mir(mc_opl_t *mcp, int bank, mc_addr_info_t *maddr) 168125cf1a30Sjl { 168225cf1a30Sjl mc_aflt_t mc_aflt; 168325cf1a30Sjl mc_flt_stat_t flt_stat[2], mi_flt_stat[2]; 16840cc8ae86Sav int i; 16850cc8ae86Sav int mi_valid; 168625cf1a30Sjl 168725cf1a30Sjl bzero(&mc_aflt, sizeof (mc_aflt_t)); 168825cf1a30Sjl bzero(&flt_stat, 2 * sizeof (mc_flt_stat_t)); 168925cf1a30Sjl bzero(&mi_flt_stat, 2 * sizeof (mc_flt_stat_t)); 169025cf1a30Sjl 169125cf1a30Sjl mc_aflt.mflt_mcp = mcp; 169225cf1a30Sjl mc_aflt.mflt_id = gethrtime(); 169325cf1a30Sjl 169425cf1a30Sjl /* Now read all the registers into flt_stat */ 169525cf1a30Sjl 16960cc8ae86Sav for (i = 0; i < 2; i++) { 16970cc8ae86Sav MC_LOG("Reading registers of bank %d\n", bank); 16980cc8ae86Sav /* patrol registers */ 16990cc8ae86Sav mc_read_ptrl_reg(mcp, bank, &flt_stat[i]); 170025cf1a30Sjl 17010cc8ae86Sav ASSERT(maddr); 17020cc8ae86Sav maddr->mi_maddr = flt_stat[i].mf_flt_maddr; 170325cf1a30Sjl 17040cc8ae86Sav MC_LOG("ptrl registers cntl %x add %x log %x\n", 17050cc8ae86Sav flt_stat[i].mf_cntl, 17060cc8ae86Sav flt_stat[i].mf_err_add, 17070cc8ae86Sav flt_stat[i].mf_err_log); 170825cf1a30Sjl 17090cc8ae86Sav /* MI registers */ 17100cc8ae86Sav mc_read_mi_reg(mcp, bank, &mi_flt_stat[i]); 171125cf1a30Sjl 17120cc8ae86Sav MC_LOG("MI registers cntl %x add %x log %x\n", 17130cc8ae86Sav mi_flt_stat[i].mf_cntl, 17140cc8ae86Sav mi_flt_stat[i].mf_err_add, 17150cc8ae86Sav mi_flt_stat[i].mf_err_log); 171625cf1a30Sjl 17170cc8ae86Sav bank = bank^1; 17180cc8ae86Sav } 171925cf1a30Sjl 172025cf1a30Sjl /* clear errors once we read all the registers */ 17210cc8ae86Sav MAC_CLEAR_ERRS(mcp, bank, 172225cf1a30Sjl (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS)); 172325cf1a30Sjl 17240cc8ae86Sav MAC_CLEAR_ERRS(mcp, bank ^ 1, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS)); 17250cc8ae86Sav 17260cc8ae86Sav /* Process MI errors first */ 172725cf1a30Sjl 17280cc8ae86Sav /* if not error mode, cntl1 is 0 */ 17290cc8ae86Sav if ((mi_flt_stat[0].mf_err_add & MAC_ERR_ADD_INVALID) || 17300cc8ae86Sav (mi_flt_stat[0].mf_err_log & MAC_ERR_LOG_INVALID)) 17310cc8ae86Sav mi_flt_stat[0].mf_cntl = 0; 17320cc8ae86Sav 17330cc8ae86Sav if ((mi_flt_stat[1].mf_err_add & MAC_ERR_ADD_INVALID) || 17340cc8ae86Sav (mi_flt_stat[1].mf_err_log & MAC_ERR_LOG_INVALID)) 17350cc8ae86Sav mi_flt_stat[1].mf_cntl = 0; 173625cf1a30Sjl 17370cc8ae86Sav mc_aflt.mflt_is_ptrl = 0; 17380cc8ae86Sav mi_valid = mc_process_error_mir(mcp, &mc_aflt, &mi_flt_stat[0]); 17390cc8ae86Sav 17400cc8ae86Sav if ((((flt_stat[0].mf_cntl & MAC_CNTL_PTRL_ERRS) >> 17410cc8ae86Sav MAC_CNTL_PTRL_ERR_SHIFT) == 17420cc8ae86Sav ((mi_flt_stat[0].mf_cntl & MAC_CNTL_MI_ERRS) >> 17430cc8ae86Sav MAC_CNTL_MI_ERR_SHIFT)) && 17440cc8ae86Sav (flt_stat[0].mf_err_add == mi_flt_stat[0].mf_err_add) && 17450cc8ae86Sav (((flt_stat[1].mf_cntl & MAC_CNTL_PTRL_ERRS) >> 17460cc8ae86Sav MAC_CNTL_PTRL_ERR_SHIFT) == 17470cc8ae86Sav ((mi_flt_stat[1].mf_cntl & MAC_CNTL_MI_ERRS) >> 17480cc8ae86Sav MAC_CNTL_MI_ERR_SHIFT)) && 17490cc8ae86Sav (flt_stat[1].mf_err_add == mi_flt_stat[1].mf_err_add)) { 17500cc8ae86Sav #ifdef DEBUG 17510cc8ae86Sav MC_LOG("discarding PTRL error because " 17520cc8ae86Sav "it is the same as MI\n"); 17530cc8ae86Sav #endif 17540cc8ae86Sav maddr->mi_valid = mi_valid; 17550cc8ae86Sav return; 17560cc8ae86Sav } 175725cf1a30Sjl /* if not error mode, cntl1 is 0 */ 175825cf1a30Sjl if ((flt_stat[0].mf_err_add & MAC_ERR_ADD_INVALID) || 175925cf1a30Sjl (flt_stat[0].mf_err_log & MAC_ERR_LOG_INVALID)) 176025cf1a30Sjl flt_stat[0].mf_cntl = 0; 176125cf1a30Sjl 176225cf1a30Sjl if ((flt_stat[1].mf_err_add & MAC_ERR_ADD_INVALID) || 176325cf1a30Sjl (flt_stat[1].mf_err_log & MAC_ERR_LOG_INVALID)) 176425cf1a30Sjl flt_stat[1].mf_cntl = 0; 176525cf1a30Sjl 176625cf1a30Sjl mc_aflt.mflt_is_ptrl = 1; 176725cf1a30Sjl maddr->mi_valid = mc_process_error_mir(mcp, &mc_aflt, &flt_stat[0]); 176825cf1a30Sjl } 176925cf1a30Sjl static int 177025cf1a30Sjl mc_process_error(mc_opl_t *mcp, int bank, mc_aflt_t *mc_aflt, 177125cf1a30Sjl mc_flt_stat_t *flt_stat) 177225cf1a30Sjl { 177325cf1a30Sjl int ptrl_error = mc_aflt->mflt_is_ptrl; 177425cf1a30Sjl int rv = 0; 177525cf1a30Sjl 177625cf1a30Sjl mc_aflt->mflt_erpt_class = NULL; 177725cf1a30Sjl if (IS_UE(flt_stat->mf_cntl, ptrl_error)) { 177825cf1a30Sjl MC_LOG("UE deteceted\n"); 177925cf1a30Sjl flt_stat->mf_type = FLT_TYPE_UE; 178025cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_UE; 178125cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 178225cf1a30Sjl MAC_SET_ERRLOG_INFO(flt_stat); 178325cf1a30Sjl rv = 1; 178425cf1a30Sjl } else if (IS_CE(flt_stat->mf_cntl, ptrl_error)) { 178525cf1a30Sjl MC_LOG("CE deteceted\n"); 178625cf1a30Sjl MAC_SET_ERRLOG_INFO(flt_stat); 178725cf1a30Sjl 178825cf1a30Sjl /* Error type can change after scrubing */ 178925cf1a30Sjl mc_scrub_ce(mcp, bank, flt_stat, ptrl_error); 179025cf1a30Sjl 179125cf1a30Sjl if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) { 179225cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_CE; 179325cf1a30Sjl mc_aflt->mflt_pr = PR_MCE; 179425cf1a30Sjl } else if (flt_stat->mf_type == FLT_TYPE_UE) { 179525cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_UE; 179625cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 179725cf1a30Sjl } 179825cf1a30Sjl rv = 1; 179925cf1a30Sjl } 180025cf1a30Sjl MC_LOG("mc_process_error: fault type %x erpt %s\n", 180125cf1a30Sjl flt_stat->mf_type, 180225cf1a30Sjl mc_aflt->mflt_erpt_class); 180325cf1a30Sjl if (mc_aflt->mflt_erpt_class) { 180425cf1a30Sjl mc_aflt->mflt_stat[0] = flt_stat; 180525cf1a30Sjl mc_aflt->mflt_nflts = 1; 180625cf1a30Sjl mc_err_drain(mc_aflt); 180725cf1a30Sjl } 180825cf1a30Sjl return (rv); 180925cf1a30Sjl } 181025cf1a30Sjl 181125cf1a30Sjl static void 181225cf1a30Sjl mc_error_handler(mc_opl_t *mcp, int bank, mc_addr_info_t *maddr) 181325cf1a30Sjl { 181425cf1a30Sjl mc_aflt_t mc_aflt; 181525cf1a30Sjl mc_flt_stat_t flt_stat, mi_flt_stat; 18160cc8ae86Sav int mi_valid; 181725cf1a30Sjl 181825cf1a30Sjl bzero(&mc_aflt, sizeof (mc_aflt_t)); 181925cf1a30Sjl bzero(&flt_stat, sizeof (mc_flt_stat_t)); 182025cf1a30Sjl bzero(&mi_flt_stat, sizeof (mc_flt_stat_t)); 182125cf1a30Sjl 182225cf1a30Sjl mc_aflt.mflt_mcp = mcp; 182325cf1a30Sjl mc_aflt.mflt_id = gethrtime(); 182425cf1a30Sjl 182525cf1a30Sjl /* patrol registers */ 182625cf1a30Sjl mc_read_ptrl_reg(mcp, bank, &flt_stat); 182725cf1a30Sjl 182825cf1a30Sjl ASSERT(maddr); 182925cf1a30Sjl maddr->mi_maddr = flt_stat.mf_flt_maddr; 183025cf1a30Sjl 183125cf1a30Sjl MC_LOG("ptrl registers cntl %x add %x log %x\n", 183225cf1a30Sjl flt_stat.mf_cntl, 183325cf1a30Sjl flt_stat.mf_err_add, 183425cf1a30Sjl flt_stat.mf_err_log); 183525cf1a30Sjl 183625cf1a30Sjl /* MI registers */ 183725cf1a30Sjl mc_read_mi_reg(mcp, bank, &mi_flt_stat); 183825cf1a30Sjl 18390cc8ae86Sav 184025cf1a30Sjl MC_LOG("MI registers cntl %x add %x log %x\n", 184125cf1a30Sjl mi_flt_stat.mf_cntl, 184225cf1a30Sjl mi_flt_stat.mf_err_add, 184325cf1a30Sjl mi_flt_stat.mf_err_log); 184425cf1a30Sjl 184525cf1a30Sjl /* clear errors once we read all the registers */ 184625cf1a30Sjl MAC_CLEAR_ERRS(mcp, bank, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS)); 184725cf1a30Sjl 18480cc8ae86Sav mc_aflt.mflt_is_ptrl = 0; 18490cc8ae86Sav if ((mi_flt_stat.mf_cntl & MAC_CNTL_MI_ERRS) && 18500cc8ae86Sav ((mi_flt_stat.mf_err_add & MAC_ERR_ADD_INVALID) == 0) && 18510cc8ae86Sav ((mi_flt_stat.mf_err_log & MAC_ERR_LOG_INVALID) == 0)) { 18520cc8ae86Sav mi_valid = mc_process_error(mcp, bank, &mc_aflt, &mi_flt_stat); 18530cc8ae86Sav } 18540cc8ae86Sav 18550cc8ae86Sav if ((((flt_stat.mf_cntl & MAC_CNTL_PTRL_ERRS) >> 18560cc8ae86Sav MAC_CNTL_PTRL_ERR_SHIFT) == 18570cc8ae86Sav ((mi_flt_stat.mf_cntl & MAC_CNTL_MI_ERRS) >> 18580cc8ae86Sav MAC_CNTL_MI_ERR_SHIFT)) && 18590cc8ae86Sav (flt_stat.mf_err_add == mi_flt_stat.mf_err_add)) { 18600cc8ae86Sav #ifdef DEBUG 18610cc8ae86Sav MC_LOG("discarding PTRL error because " 18620cc8ae86Sav "it is the same as MI\n"); 18630cc8ae86Sav #endif 18640cc8ae86Sav maddr->mi_valid = mi_valid; 18650cc8ae86Sav return; 18660cc8ae86Sav } 18670cc8ae86Sav 186825cf1a30Sjl mc_aflt.mflt_is_ptrl = 1; 186925cf1a30Sjl if ((flt_stat.mf_cntl & MAC_CNTL_PTRL_ERRS) && 187025cf1a30Sjl ((flt_stat.mf_err_add & MAC_ERR_ADD_INVALID) == 0) && 187125cf1a30Sjl ((flt_stat.mf_err_log & MAC_ERR_LOG_INVALID) == 0)) { 187225cf1a30Sjl maddr->mi_valid = mc_process_error(mcp, bank, 187325cf1a30Sjl &mc_aflt, &flt_stat); 187425cf1a30Sjl } 187525cf1a30Sjl } 187625cf1a30Sjl /* 187725cf1a30Sjl * memory patrol error handling algorithm: 187825cf1a30Sjl * timeout() is used to do periodic polling 187925cf1a30Sjl * This is the flow chart. 188025cf1a30Sjl * timeout -> 188125cf1a30Sjl * mc_check_errors() 188225cf1a30Sjl * if memory bank is installed, read the status register 188325cf1a30Sjl * if any error bit is set, 188425cf1a30Sjl * -> mc_error_handler() 188525cf1a30Sjl * -> read all error regsiters 188625cf1a30Sjl * -> mc_process_error() 188725cf1a30Sjl * determine error type 188825cf1a30Sjl * rewrite to clear error or scrub to determine CE type 188925cf1a30Sjl * inform SCF on permanent CE 189025cf1a30Sjl * -> mc_err_drain 189125cf1a30Sjl * page offline processing 189225cf1a30Sjl * -> mc_ereport_post() 189325cf1a30Sjl */ 189425cf1a30Sjl 189525cf1a30Sjl static void 189625cf1a30Sjl mc_check_errors_func(mc_opl_t *mcp) 189725cf1a30Sjl { 189825cf1a30Sjl mc_addr_info_t maddr_info; 189925cf1a30Sjl int i, error_count = 0; 190025cf1a30Sjl uint32_t stat, cntl; 19010cc8ae86Sav int running; 190225cf1a30Sjl 190325cf1a30Sjl /* 190425cf1a30Sjl * scan errors. 190525cf1a30Sjl */ 19060cc8ae86Sav if (mcp->mc_status & MC_MEMORYLESS) 19070cc8ae86Sav return; 19080cc8ae86Sav 190925cf1a30Sjl for (i = 0; i < BANKNUM_PER_SB; i++) { 191025cf1a30Sjl if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) { 191125cf1a30Sjl stat = ldphysio(MAC_PTRL_STAT(mcp, i)); 191225cf1a30Sjl cntl = ldphysio(MAC_PTRL_CNTL(mcp, i)); 19130cc8ae86Sav running = cntl & MAC_CNTL_PTRL_START; 19140cc8ae86Sav 191525cf1a30Sjl if (cntl & MAC_CNTL_PTRL_ADD_MAX) { 19160cc8ae86Sav mcp->mc_period[i]++; 191725cf1a30Sjl MC_LOG("mc period %ld on " 19180cc8ae86Sav "/LSB%d/B%d\n", mcp->mc_period[i], 191925cf1a30Sjl mcp->mc_board_num, i); 192025cf1a30Sjl MAC_CLEAR_MAX(mcp, i); 19210cc8ae86Sav if (mcp->mc_speedup_period[i] > 0) { 19220cc8ae86Sav /* If patrol is stoppped, we fall through */ 19230cc8ae86Sav if (--mcp->mc_speedup_period[i] == 0 && 19240cc8ae86Sav running) { 19250cc8ae86Sav MAC_CMD(mcp, i, 0); 19260cc8ae86Sav } 19270cc8ae86Sav } 192825cf1a30Sjl } 192925cf1a30Sjl if (mc_debug_show_all) { 193025cf1a30Sjl MC_LOG("/LSB%d/B%d stat %x cntl %x\n", 193125cf1a30Sjl mcp->mc_board_num, i, 193225cf1a30Sjl stat, cntl); 193325cf1a30Sjl } 193425cf1a30Sjl if (stat & (MAC_STAT_PTRL_ERRS|MAC_STAT_MI_ERRS)) { 19350cc8ae86Sav if (running) { 19360cc8ae86Sav MC_LOG("patrol running /LSB%d/B%d\n", 19370cc8ae86Sav mcp->mc_board_num, i); 19380cc8ae86Sav } 19390cc8ae86Sav if (running) { 19400cc8ae86Sav /* speed up the scanning */ 19410cc8ae86Sav mcp->mc_speedup_period[i] = 2; 19420cc8ae86Sav MAC_CMD(mcp, i, 0); 19430cc8ae86Sav } else { 19440cc8ae86Sav mcp->mc_speedup_period[i] = 0; 19450cc8ae86Sav maddr_info.mi_valid = 0; 19460cc8ae86Sav maddr_info.mi_advance = 1; 19470cc8ae86Sav if (IS_MIRROR(mcp, i)) 194825cf1a30Sjl mc_error_handler_mir(mcp, i, 194925cf1a30Sjl &maddr_info); 19500cc8ae86Sav else 195125cf1a30Sjl mc_error_handler(mcp, i, &maddr_info); 195225cf1a30Sjl 19530cc8ae86Sav error_count++; 19540cc8ae86Sav restart_patrol(mcp, i, &maddr_info); 19550cc8ae86Sav } 195625cf1a30Sjl } else { 195725cf1a30Sjl restart_patrol(mcp, i, NULL); 195825cf1a30Sjl } 195925cf1a30Sjl } 196025cf1a30Sjl } 196125cf1a30Sjl if (error_count > 0) 196225cf1a30Sjl mcp->mc_last_error += error_count; 196325cf1a30Sjl else 196425cf1a30Sjl mcp->mc_last_error = 0; 196525cf1a30Sjl } 196625cf1a30Sjl 19670cc8ae86Sav /* 19680cc8ae86Sav * mc_polling -- Check errors for only one instance, 19690cc8ae86Sav * but process errors for all instances to make sure we drain the errors 19700cc8ae86Sav * faster than they can be accumulated. 19710cc8ae86Sav * 19720cc8ae86Sav * Polling on each board should be done only once per each 19730cc8ae86Sav * mc_patrol_interval_sec. This is equivalent to setting mc_tick_left 19740cc8ae86Sav * to OPL_MAX_BOARDS and decrement by 1 on each timeout. 19750cc8ae86Sav * Once mc_tick_left becomes negative, the board becomes a candidate 19760cc8ae86Sav * for polling because it has waited for at least 19770cc8ae86Sav * mc_patrol_interval_sec's long. If mc_timeout_period is calculated 19780cc8ae86Sav * differently, this has to beupdated accordingly. 19790cc8ae86Sav */ 198025cf1a30Sjl 198125cf1a30Sjl static void 19820cc8ae86Sav mc_polling(void) 198325cf1a30Sjl { 19840cc8ae86Sav int i, scan_error; 19850cc8ae86Sav mc_opl_t *mcp; 198625cf1a30Sjl 198725cf1a30Sjl 19880cc8ae86Sav scan_error = 1; 19890cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 19900cc8ae86Sav mutex_enter(&mcmutex); 19910cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) { 19920cc8ae86Sav mutex_exit(&mcmutex); 19930cc8ae86Sav continue; 19940cc8ae86Sav } 19950cc8ae86Sav mutex_enter(&mcp->mc_lock); 19960cc8ae86Sav mutex_exit(&mcmutex); 19970cc8ae86Sav if (scan_error && mcp->mc_tick_left <= 0) { 19980cc8ae86Sav mc_check_errors_func((void *)mcp); 19990cc8ae86Sav mcp->mc_tick_left = OPL_MAX_BOARDS; 20000cc8ae86Sav scan_error = 0; 20010cc8ae86Sav } else { 20020cc8ae86Sav mcp->mc_tick_left--; 20030cc8ae86Sav } 20040cc8ae86Sav mc_process_scf_log(mcp); 20050cc8ae86Sav mutex_exit(&mcp->mc_lock); 200625cf1a30Sjl } 200725cf1a30Sjl } 200825cf1a30Sjl 200925cf1a30Sjl static void 201025cf1a30Sjl get_ptrl_start_address(mc_opl_t *mcp, int bank, mc_addr_t *maddr) 201125cf1a30Sjl { 201225cf1a30Sjl maddr->ma_bd = mcp->mc_board_num; 201325cf1a30Sjl maddr->ma_bank = bank; 201425cf1a30Sjl maddr->ma_dimm_addr = 0; 201525cf1a30Sjl } 201625cf1a30Sjl 201725cf1a30Sjl typedef struct mc_mem_range { 201825cf1a30Sjl uint64_t addr; 201925cf1a30Sjl uint64_t size; 202025cf1a30Sjl } mc_mem_range_t; 202125cf1a30Sjl 202225cf1a30Sjl static int 202325cf1a30Sjl get_base_address(mc_opl_t *mcp) 202425cf1a30Sjl { 202525cf1a30Sjl mc_mem_range_t *mem_range; 202625cf1a30Sjl int len; 202725cf1a30Sjl 202825cf1a30Sjl if (ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS, 202925cf1a30Sjl "sb-mem-ranges", (caddr_t)&mem_range, &len) != DDI_SUCCESS) { 203025cf1a30Sjl return (DDI_FAILURE); 203125cf1a30Sjl } 203225cf1a30Sjl 203325cf1a30Sjl mcp->mc_start_address = mem_range->addr; 203425cf1a30Sjl mcp->mc_size = mem_range->size; 203525cf1a30Sjl 203625cf1a30Sjl kmem_free(mem_range, len); 203725cf1a30Sjl return (DDI_SUCCESS); 203825cf1a30Sjl } 203925cf1a30Sjl 204025cf1a30Sjl struct mc_addr_spec { 204125cf1a30Sjl uint32_t bank; 204225cf1a30Sjl uint32_t phys_hi; 204325cf1a30Sjl uint32_t phys_lo; 204425cf1a30Sjl }; 204525cf1a30Sjl 204625cf1a30Sjl #define REGS_PA(m, i) ((((uint64_t)m[i].phys_hi)<<32) | m[i].phys_lo) 204725cf1a30Sjl 204825cf1a30Sjl static char *mc_tbl_name[] = { 204925cf1a30Sjl "cs0-mc-pa-trans-table", 205025cf1a30Sjl "cs1-mc-pa-trans-table" 205125cf1a30Sjl }; 205225cf1a30Sjl 205325cf1a30Sjl static int 205425cf1a30Sjl mc_valid_pa(mc_opl_t *mcp, uint64_t pa) 205525cf1a30Sjl { 205625cf1a30Sjl struct memlist *ml; 205725cf1a30Sjl 205825cf1a30Sjl if (mcp->mlist == NULL) 205925cf1a30Sjl mc_get_mlist(mcp); 206025cf1a30Sjl 206125cf1a30Sjl for (ml = mcp->mlist; ml; ml = ml->next) { 206225cf1a30Sjl if (ml->address <= pa && pa < (ml->address + ml->size)) 206325cf1a30Sjl return (1); 206425cf1a30Sjl } 206525cf1a30Sjl return (0); 206625cf1a30Sjl } 206725cf1a30Sjl 206825cf1a30Sjl static void 206925cf1a30Sjl mc_memlist_delete(struct memlist *mlist) 207025cf1a30Sjl { 207125cf1a30Sjl struct memlist *ml; 207225cf1a30Sjl 207325cf1a30Sjl for (ml = mlist; ml; ml = mlist) { 207425cf1a30Sjl mlist = ml->next; 207525cf1a30Sjl kmem_free(ml, sizeof (struct memlist)); 207625cf1a30Sjl } 207725cf1a30Sjl } 207825cf1a30Sjl 207925cf1a30Sjl static struct memlist * 208025cf1a30Sjl mc_memlist_dup(struct memlist *mlist) 208125cf1a30Sjl { 208225cf1a30Sjl struct memlist *hl = NULL, *tl, **mlp; 208325cf1a30Sjl 208425cf1a30Sjl if (mlist == NULL) 208525cf1a30Sjl return (NULL); 208625cf1a30Sjl 208725cf1a30Sjl mlp = &hl; 208825cf1a30Sjl tl = *mlp; 208925cf1a30Sjl for (; mlist; mlist = mlist->next) { 209025cf1a30Sjl *mlp = kmem_alloc(sizeof (struct memlist), KM_SLEEP); 209125cf1a30Sjl (*mlp)->address = mlist->address; 209225cf1a30Sjl (*mlp)->size = mlist->size; 209325cf1a30Sjl (*mlp)->prev = tl; 209425cf1a30Sjl tl = *mlp; 209525cf1a30Sjl mlp = &((*mlp)->next); 209625cf1a30Sjl } 209725cf1a30Sjl *mlp = NULL; 209825cf1a30Sjl 209925cf1a30Sjl return (hl); 210025cf1a30Sjl } 210125cf1a30Sjl 210225cf1a30Sjl 210325cf1a30Sjl static struct memlist * 210425cf1a30Sjl mc_memlist_del_span(struct memlist *mlist, uint64_t base, uint64_t len) 210525cf1a30Sjl { 210625cf1a30Sjl uint64_t end; 210725cf1a30Sjl struct memlist *ml, *tl, *nlp; 210825cf1a30Sjl 210925cf1a30Sjl if (mlist == NULL) 211025cf1a30Sjl return (NULL); 211125cf1a30Sjl 211225cf1a30Sjl end = base + len; 211325cf1a30Sjl if ((end <= mlist->address) || (base == end)) 211425cf1a30Sjl return (mlist); 211525cf1a30Sjl 211625cf1a30Sjl for (tl = ml = mlist; ml; tl = ml, ml = nlp) { 211725cf1a30Sjl uint64_t mend; 211825cf1a30Sjl 211925cf1a30Sjl nlp = ml->next; 212025cf1a30Sjl 212125cf1a30Sjl if (end <= ml->address) 212225cf1a30Sjl break; 212325cf1a30Sjl 212425cf1a30Sjl mend = ml->address + ml->size; 212525cf1a30Sjl if (base < mend) { 212625cf1a30Sjl if (base <= ml->address) { 212725cf1a30Sjl ml->address = end; 212825cf1a30Sjl if (end >= mend) 212925cf1a30Sjl ml->size = 0ull; 213025cf1a30Sjl else 213125cf1a30Sjl ml->size = mend - ml->address; 213225cf1a30Sjl } else { 213325cf1a30Sjl ml->size = base - ml->address; 213425cf1a30Sjl if (end < mend) { 213525cf1a30Sjl struct memlist *nl; 213625cf1a30Sjl /* 213725cf1a30Sjl * splitting an memlist entry. 213825cf1a30Sjl */ 213925cf1a30Sjl nl = kmem_alloc(sizeof (struct memlist), 214025cf1a30Sjl KM_SLEEP); 214125cf1a30Sjl nl->address = end; 214225cf1a30Sjl nl->size = mend - nl->address; 214325cf1a30Sjl if ((nl->next = nlp) != NULL) 214425cf1a30Sjl nlp->prev = nl; 214525cf1a30Sjl nl->prev = ml; 214625cf1a30Sjl ml->next = nl; 214725cf1a30Sjl nlp = nl; 214825cf1a30Sjl } 214925cf1a30Sjl } 215025cf1a30Sjl if (ml->size == 0ull) { 215125cf1a30Sjl if (ml == mlist) { 215225cf1a30Sjl if ((mlist = nlp) != NULL) 215325cf1a30Sjl nlp->prev = NULL; 215425cf1a30Sjl kmem_free(ml, sizeof (struct memlist)); 215525cf1a30Sjl if (mlist == NULL) 215625cf1a30Sjl break; 215725cf1a30Sjl ml = nlp; 215825cf1a30Sjl } else { 215925cf1a30Sjl if ((tl->next = nlp) != NULL) 216025cf1a30Sjl nlp->prev = tl; 216125cf1a30Sjl kmem_free(ml, sizeof (struct memlist)); 216225cf1a30Sjl ml = tl; 216325cf1a30Sjl } 216425cf1a30Sjl } 216525cf1a30Sjl } 216625cf1a30Sjl } 216725cf1a30Sjl 216825cf1a30Sjl return (mlist); 216925cf1a30Sjl } 217025cf1a30Sjl 217125cf1a30Sjl static void 217225cf1a30Sjl mc_get_mlist(mc_opl_t *mcp) 217325cf1a30Sjl { 217425cf1a30Sjl struct memlist *mlist; 217525cf1a30Sjl 217625cf1a30Sjl memlist_read_lock(); 217725cf1a30Sjl mlist = mc_memlist_dup(phys_install); 217825cf1a30Sjl memlist_read_unlock(); 217925cf1a30Sjl 218025cf1a30Sjl if (mlist) { 218125cf1a30Sjl mlist = mc_memlist_del_span(mlist, 0ull, mcp->mc_start_address); 218225cf1a30Sjl } 218325cf1a30Sjl 218425cf1a30Sjl if (mlist) { 218525cf1a30Sjl uint64_t startpa, endpa; 218625cf1a30Sjl 218725cf1a30Sjl startpa = mcp->mc_start_address + mcp->mc_size; 218825cf1a30Sjl endpa = ptob(physmax + 1); 218925cf1a30Sjl if (endpa > startpa) { 219025cf1a30Sjl mlist = mc_memlist_del_span(mlist, 219125cf1a30Sjl startpa, endpa - startpa); 219225cf1a30Sjl } 219325cf1a30Sjl } 219425cf1a30Sjl 219525cf1a30Sjl if (mlist) { 219625cf1a30Sjl mcp->mlist = mlist; 219725cf1a30Sjl } 219825cf1a30Sjl } 219925cf1a30Sjl 220025cf1a30Sjl int 220125cf1a30Sjl mc_board_add(mc_opl_t *mcp) 220225cf1a30Sjl { 220325cf1a30Sjl struct mc_addr_spec *macaddr; 22040cc8ae86Sav cs_status_t *cs_status; 22050cc8ae86Sav int len, len1, i, bk, cc; 220625cf1a30Sjl mc_addr_info_t maddr; 220725cf1a30Sjl uint32_t mirr; 22080cc8ae86Sav int nbanks = 0; 22090cc8ae86Sav uint64_t nbytes = 0; 221025cf1a30Sjl 221125cf1a30Sjl /* 221225cf1a30Sjl * Get configurations from "pseudo-mc" node which includes: 221325cf1a30Sjl * board# : LSB number 221425cf1a30Sjl * mac-addr : physical base address of MAC registers 221525cf1a30Sjl * csX-mac-pa-trans-table: translation table from DIMM address 221625cf1a30Sjl * to physical address or vice versa. 221725cf1a30Sjl */ 221825cf1a30Sjl mcp->mc_board_num = (int)ddi_getprop(DDI_DEV_T_ANY, mcp->mc_dip, 221925cf1a30Sjl DDI_PROP_DONTPASS, "board#", -1); 222025cf1a30Sjl 22210cc8ae86Sav if (mcp->mc_board_num == -1) { 22220cc8ae86Sav return (DDI_FAILURE); 22230cc8ae86Sav } 22240cc8ae86Sav 222525cf1a30Sjl /* 222625cf1a30Sjl * Get start address in this CAB. It can be gotten from 222725cf1a30Sjl * "sb-mem-ranges" property. 222825cf1a30Sjl */ 222925cf1a30Sjl 223025cf1a30Sjl if (get_base_address(mcp) == DDI_FAILURE) { 223125cf1a30Sjl return (DDI_FAILURE); 223225cf1a30Sjl } 223325cf1a30Sjl /* get mac-pa trans tables */ 223425cf1a30Sjl for (i = 0; i < MC_TT_CS; i++) { 223525cf1a30Sjl len = MC_TT_ENTRIES; 223625cf1a30Sjl cc = ddi_getlongprop_buf(DDI_DEV_T_ANY, mcp->mc_dip, 223725cf1a30Sjl DDI_PROP_DONTPASS, mc_tbl_name[i], 223825cf1a30Sjl (caddr_t)mcp->mc_trans_table[i], &len); 223925cf1a30Sjl 224025cf1a30Sjl if (cc != DDI_SUCCESS) { 224125cf1a30Sjl bzero(mcp->mc_trans_table[i], MC_TT_ENTRIES); 224225cf1a30Sjl } 224325cf1a30Sjl } 224425cf1a30Sjl mcp->mlist = NULL; 224525cf1a30Sjl 224625cf1a30Sjl mc_get_mlist(mcp); 224725cf1a30Sjl 224825cf1a30Sjl /* initialize bank informations */ 224925cf1a30Sjl cc = ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS, 225025cf1a30Sjl "mc-addr", (caddr_t)&macaddr, &len); 225125cf1a30Sjl if (cc != DDI_SUCCESS) { 225225cf1a30Sjl cmn_err(CE_WARN, "Cannot get mc-addr. err=%d\n", cc); 225325cf1a30Sjl return (DDI_FAILURE); 225425cf1a30Sjl } 225525cf1a30Sjl 22560cc8ae86Sav cc = ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS, 22570cc8ae86Sav "cs-status", (caddr_t)&cs_status, &len1); 225825cf1a30Sjl 22590cc8ae86Sav if (cc != DDI_SUCCESS) { 22600cc8ae86Sav if (len > 0) 22610cc8ae86Sav kmem_free(macaddr, len); 22620cc8ae86Sav cmn_err(CE_WARN, "Cannot get cs-status. err=%d\n", cc); 22630cc8ae86Sav return (DDI_FAILURE); 22640cc8ae86Sav } 226525cf1a30Sjl 22660cc8ae86Sav mutex_init(&mcp->mc_lock, NULL, MUTEX_DRIVER, NULL); 22670cc8ae86Sav 22680cc8ae86Sav for (i = 0; i < len1 / sizeof (cs_status_t); i++) { 22690cc8ae86Sav nbytes += ((uint64_t)cs_status[i].cs_avail_hi << 32) | 22700cc8ae86Sav ((uint64_t)cs_status[i].cs_avail_low); 22710cc8ae86Sav } 22720cc8ae86Sav if (len1 > 0) 22730cc8ae86Sav kmem_free(cs_status, len1); 22740cc8ae86Sav nbanks = len / sizeof (struct mc_addr_spec); 22750cc8ae86Sav 22760cc8ae86Sav if (nbanks > 0) 22770cc8ae86Sav nbytes /= nbanks; 22780cc8ae86Sav else { 22790cc8ae86Sav /* No need to free macaddr because len must be 0 */ 22800cc8ae86Sav mcp->mc_status |= MC_MEMORYLESS; 22810cc8ae86Sav return (DDI_SUCCESS); 22820cc8ae86Sav } 22830cc8ae86Sav 22840cc8ae86Sav for (i = 0; i < BANKNUM_PER_SB; i++) { 22850cc8ae86Sav mcp->mc_scf_retry[i] = 0; 22860cc8ae86Sav mcp->mc_period[i] = 0; 22870cc8ae86Sav mcp->mc_speedup_period[i] = 0; 22880cc8ae86Sav } 22890cc8ae86Sav 22900cc8ae86Sav /* 22910cc8ae86Sav * Get the memory size here. Let it be B (bytes). 22920cc8ae86Sav * Let T be the time in u.s. to scan 64 bytes. 22930cc8ae86Sav * If we want to complete 1 round of scanning in P seconds. 22940cc8ae86Sav * 22950cc8ae86Sav * B * T * 10^(-6) = P 22960cc8ae86Sav * --------------- 22970cc8ae86Sav * 64 22980cc8ae86Sav * 22990cc8ae86Sav * T = P * 64 * 10^6 23000cc8ae86Sav * ------------- 23010cc8ae86Sav * B 23020cc8ae86Sav * 23030cc8ae86Sav * = P * 64 * 10^6 23040cc8ae86Sav * ------------- 23050cc8ae86Sav * B 23060cc8ae86Sav * 23070cc8ae86Sav * The timing bits are set in PTRL_CNTL[28:26] where 23080cc8ae86Sav * 23090cc8ae86Sav * 0 - 1 m.s 23100cc8ae86Sav * 1 - 512 u.s. 23110cc8ae86Sav * 10 - 256 u.s. 23120cc8ae86Sav * 11 - 128 u.s. 23130cc8ae86Sav * 100 - 64 u.s. 23140cc8ae86Sav * 101 - 32 u.s. 23150cc8ae86Sav * 110 - 0 u.s. 23160cc8ae86Sav * 111 - reserved. 23170cc8ae86Sav * 23180cc8ae86Sav * 23190cc8ae86Sav * a[0] = 110, a[1] = 101, ... a[6] = 0 23200cc8ae86Sav * 23210cc8ae86Sav * cs-status property is int x 7 23220cc8ae86Sav * 0 - cs# 23230cc8ae86Sav * 1 - cs-status 23240cc8ae86Sav * 2 - cs-avail.hi 23250cc8ae86Sav * 3 - cs-avail.lo 23260cc8ae86Sav * 4 - dimm-capa.hi 23270cc8ae86Sav * 5 - dimm-capa.lo 23280cc8ae86Sav * 6 - #of dimms 23290cc8ae86Sav */ 23300cc8ae86Sav 23310cc8ae86Sav if (nbytes > 0) { 23320cc8ae86Sav int i; 23330cc8ae86Sav uint64_t ms; 23340cc8ae86Sav ms = ((uint64_t)mc_scan_period * 64 * 1000000)/nbytes; 23350cc8ae86Sav mcp->mc_speed = mc_scan_speeds[MC_MAX_SPEEDS - 1].mc_speeds; 23360cc8ae86Sav for (i = 0; i < MC_MAX_SPEEDS - 1; i++) { 23370cc8ae86Sav if (ms < mc_scan_speeds[i + 1].mc_period) { 23380cc8ae86Sav mcp->mc_speed = mc_scan_speeds[i].mc_speeds; 23390cc8ae86Sav break; 23400cc8ae86Sav } 23410cc8ae86Sav } 23420cc8ae86Sav } else 23430cc8ae86Sav mcp->mc_speed = 0; 23440cc8ae86Sav 23450cc8ae86Sav 23460cc8ae86Sav for (i = 0; i < len / sizeof (struct mc_addr_spec); i++) { 23470cc8ae86Sav struct mc_bank *bankp; 23480cc8ae86Sav uint32_t reg; 23490cc8ae86Sav 23500cc8ae86Sav /* 23510cc8ae86Sav * setup bank 23520cc8ae86Sav */ 23530cc8ae86Sav bk = macaddr[i].bank; 23540cc8ae86Sav bankp = &(mcp->mc_bank[bk]); 23550cc8ae86Sav bankp->mcb_status = BANK_INSTALLED; 23560cc8ae86Sav bankp->mcb_reg_base = REGS_PA(macaddr, i); 23570cc8ae86Sav 23580cc8ae86Sav reg = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bk)); 23590cc8ae86Sav bankp->mcb_ptrl_cntl = (reg & MAC_CNTL_PTRL_PRESERVE_BITS); 236025cf1a30Sjl 236125cf1a30Sjl /* 236225cf1a30Sjl * check if mirror mode 236325cf1a30Sjl */ 236425cf1a30Sjl mirr = LD_MAC_REG(MAC_MIRR(mcp, bk)); 236525cf1a30Sjl 236625cf1a30Sjl if (mirr & MAC_MIRR_MIRROR_MODE) { 236725cf1a30Sjl MC_LOG("Mirror -> /LSB%d/B%d\n", 236825cf1a30Sjl mcp->mc_board_num, bk); 236925cf1a30Sjl bankp->mcb_status |= BANK_MIRROR_MODE; 237025cf1a30Sjl /* 237125cf1a30Sjl * The following bit is only used for 237225cf1a30Sjl * error injection. We should clear it 237325cf1a30Sjl */ 237425cf1a30Sjl if (mirr & MAC_MIRR_BANK_EXCLUSIVE) 237525cf1a30Sjl ST_MAC_REG(MAC_MIRR(mcp, bk), 237625cf1a30Sjl 0); 237725cf1a30Sjl } 237825cf1a30Sjl 237925cf1a30Sjl /* 238025cf1a30Sjl * restart if not mirror mode or the other bank 238125cf1a30Sjl * of the mirror is not running 238225cf1a30Sjl */ 238325cf1a30Sjl if (!(mirr & MAC_MIRR_MIRROR_MODE) || 238425cf1a30Sjl !(mcp->mc_bank[bk^1].mcb_status & 238525cf1a30Sjl BANK_PTRL_RUNNING)) { 238625cf1a30Sjl MC_LOG("Starting up /LSB%d/B%d\n", 238725cf1a30Sjl mcp->mc_board_num, bk); 238825cf1a30Sjl get_ptrl_start_address(mcp, bk, &maddr.mi_maddr); 23890cc8ae86Sav maddr.mi_maddr.ma_bd = mcp->mc_board_num; 23900cc8ae86Sav maddr.mi_maddr.ma_bank = bk; 23910cc8ae86Sav maddr.mi_maddr.ma_dimm_addr = 0; 23920cc8ae86Sav maddr.mi_valid = 0; 239325cf1a30Sjl maddr.mi_advance = 0; 239425cf1a30Sjl restart_patrol(mcp, bk, &maddr); 239525cf1a30Sjl } else { 239625cf1a30Sjl MC_LOG("Not starting up /LSB%d/B%d\n", 239725cf1a30Sjl mcp->mc_board_num, bk); 239825cf1a30Sjl } 239925cf1a30Sjl bankp->mcb_status |= BANK_PTRL_RUNNING; 240025cf1a30Sjl } 24010cc8ae86Sav if (len > 0) 24020cc8ae86Sav kmem_free(macaddr, len); 24030cc8ae86Sav 24040cc8ae86Sav mcp->mc_dimm_list = mc_get_dimm_list(mcp); 240525cf1a30Sjl 240625cf1a30Sjl /* 240725cf1a30Sjl * set interval in HZ. 240825cf1a30Sjl */ 240925cf1a30Sjl mcp->mc_last_error = 0; 241025cf1a30Sjl 241125cf1a30Sjl /* restart memory patrol checking */ 241225cf1a30Sjl mcp->mc_status |= MC_POLL_RUNNING; 241325cf1a30Sjl 241425cf1a30Sjl return (DDI_SUCCESS); 241525cf1a30Sjl } 241625cf1a30Sjl 241725cf1a30Sjl int 241825cf1a30Sjl mc_board_del(mc_opl_t *mcp) 241925cf1a30Sjl { 242025cf1a30Sjl int i; 242125cf1a30Sjl scf_log_t *p; 242225cf1a30Sjl 242325cf1a30Sjl /* 242425cf1a30Sjl * cleanup mac state 242525cf1a30Sjl */ 242625cf1a30Sjl mutex_enter(&mcp->mc_lock); 24270cc8ae86Sav if (mcp->mc_status & MC_MEMORYLESS) { 24280cc8ae86Sav mutex_exit(&mcp->mc_lock); 24290cc8ae86Sav mutex_destroy(&mcp->mc_lock); 24300cc8ae86Sav return (DDI_SUCCESS); 24310cc8ae86Sav } 243225cf1a30Sjl for (i = 0; i < BANKNUM_PER_SB; i++) { 243325cf1a30Sjl if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) { 243425cf1a30Sjl mcp->mc_bank[i].mcb_status &= ~BANK_INSTALLED; 243525cf1a30Sjl } 243625cf1a30Sjl } 243725cf1a30Sjl 243825cf1a30Sjl /* stop memory patrol checking */ 243925cf1a30Sjl if (mcp->mc_status & MC_POLL_RUNNING) { 244025cf1a30Sjl mcp->mc_status &= ~MC_POLL_RUNNING; 244125cf1a30Sjl } 244225cf1a30Sjl 244325cf1a30Sjl /* just throw away all the scf logs */ 24440cc8ae86Sav for (i = 0; i < BANKNUM_PER_SB; i++) { 24450cc8ae86Sav while ((p = mcp->mc_scf_log[i]) != NULL) { 24460cc8ae86Sav mcp->mc_scf_log[i] = p->sl_next; 24470cc8ae86Sav mcp->mc_scf_total[i]--; 244825cf1a30Sjl kmem_free(p, sizeof (scf_log_t)); 24490cc8ae86Sav } 245025cf1a30Sjl } 245125cf1a30Sjl 245225cf1a30Sjl if (mcp->mlist) 245325cf1a30Sjl mc_memlist_delete(mcp->mlist); 245425cf1a30Sjl 24550cc8ae86Sav if (mcp->mc_dimm_list) 24560cc8ae86Sav mc_free_dimm_list(mcp->mc_dimm_list); 24570cc8ae86Sav 245825cf1a30Sjl mutex_exit(&mcp->mc_lock); 245925cf1a30Sjl 246025cf1a30Sjl mutex_destroy(&mcp->mc_lock); 246125cf1a30Sjl return (DDI_SUCCESS); 246225cf1a30Sjl } 246325cf1a30Sjl 246425cf1a30Sjl int 246525cf1a30Sjl mc_suspend(mc_opl_t *mcp, uint32_t flag) 246625cf1a30Sjl { 246725cf1a30Sjl /* stop memory patrol checking */ 246825cf1a30Sjl mutex_enter(&mcp->mc_lock); 24690cc8ae86Sav if (mcp->mc_status & MC_MEMORYLESS) { 24700cc8ae86Sav mutex_exit(&mcp->mc_lock); 24710cc8ae86Sav return (DDI_SUCCESS); 24720cc8ae86Sav } 24730cc8ae86Sav 247425cf1a30Sjl if (mcp->mc_status & MC_POLL_RUNNING) { 247525cf1a30Sjl mcp->mc_status &= ~MC_POLL_RUNNING; 247625cf1a30Sjl } 247725cf1a30Sjl mcp->mc_status |= flag; 247825cf1a30Sjl mutex_exit(&mcp->mc_lock); 247925cf1a30Sjl 248025cf1a30Sjl return (DDI_SUCCESS); 248125cf1a30Sjl } 248225cf1a30Sjl 248325cf1a30Sjl /* caller must clear the SUSPEND bits or this will do nothing */ 248425cf1a30Sjl 248525cf1a30Sjl int 248625cf1a30Sjl mc_resume(mc_opl_t *mcp, uint32_t flag) 248725cf1a30Sjl { 248825cf1a30Sjl int i; 248925cf1a30Sjl uint64_t basepa; 249025cf1a30Sjl 249125cf1a30Sjl mutex_enter(&mcp->mc_lock); 24920cc8ae86Sav if (mcp->mc_status & MC_MEMORYLESS) { 24930cc8ae86Sav mutex_exit(&mcp->mc_lock); 24940cc8ae86Sav return (DDI_SUCCESS); 24950cc8ae86Sav } 249625cf1a30Sjl basepa = mcp->mc_start_address; 249725cf1a30Sjl if (get_base_address(mcp) == DDI_FAILURE) { 249825cf1a30Sjl mutex_exit(&mcp->mc_lock); 249925cf1a30Sjl return (DDI_FAILURE); 250025cf1a30Sjl } 250125cf1a30Sjl 250225cf1a30Sjl if (basepa != mcp->mc_start_address) { 250325cf1a30Sjl if (mcp->mlist) 250425cf1a30Sjl mc_memlist_delete(mcp->mlist); 250525cf1a30Sjl mcp->mlist = NULL; 250625cf1a30Sjl mc_get_mlist(mcp); 250725cf1a30Sjl } 250825cf1a30Sjl 250925cf1a30Sjl mcp->mc_status &= ~flag; 251025cf1a30Sjl 251125cf1a30Sjl if (mcp->mc_status & (MC_SOFT_SUSPENDED | MC_DRIVER_SUSPENDED)) { 251225cf1a30Sjl mutex_exit(&mcp->mc_lock); 251325cf1a30Sjl return (DDI_SUCCESS); 251425cf1a30Sjl } 251525cf1a30Sjl 251625cf1a30Sjl if (!(mcp->mc_status & MC_POLL_RUNNING)) { 251725cf1a30Sjl /* restart memory patrol checking */ 251825cf1a30Sjl mcp->mc_status |= MC_POLL_RUNNING; 251925cf1a30Sjl for (i = 0; i < BANKNUM_PER_SB; i++) { 252025cf1a30Sjl if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) { 252125cf1a30Sjl restart_patrol(mcp, i, NULL); 252225cf1a30Sjl } 252325cf1a30Sjl } 252425cf1a30Sjl } 252525cf1a30Sjl mutex_exit(&mcp->mc_lock); 252625cf1a30Sjl 252725cf1a30Sjl return (DDI_SUCCESS); 252825cf1a30Sjl } 252925cf1a30Sjl 253025cf1a30Sjl static mc_opl_t * 253125cf1a30Sjl mc_pa_to_mcp(uint64_t pa) 253225cf1a30Sjl { 25330cc8ae86Sav mc_opl_t *mcp; 25340cc8ae86Sav int i; 25350cc8ae86Sav 253625cf1a30Sjl ASSERT(MUTEX_HELD(&mcmutex)); 25370cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 25380cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 25390cc8ae86Sav continue; 254025cf1a30Sjl /* if mac patrol is suspended, we cannot rely on it */ 25410cc8ae86Sav if (!(mcp->mc_status & MC_POLL_RUNNING) || 25420cc8ae86Sav (mcp->mc_status & MC_SOFT_SUSPENDED)) 254325cf1a30Sjl continue; 25440cc8ae86Sav if ((mcp->mc_start_address <= pa) && 25450cc8ae86Sav (pa < (mcp->mc_start_address + mcp->mc_size))) { 25460cc8ae86Sav return (mcp); 254725cf1a30Sjl } 254825cf1a30Sjl } 254925cf1a30Sjl return (NULL); 255025cf1a30Sjl } 255125cf1a30Sjl 255225cf1a30Sjl /* 255325cf1a30Sjl * Get Physical Board number from Logical one. 255425cf1a30Sjl */ 255525cf1a30Sjl static int 255625cf1a30Sjl mc_opl_get_physical_board(int sb) 255725cf1a30Sjl { 255825cf1a30Sjl if (&opl_get_physical_board) { 255925cf1a30Sjl return (opl_get_physical_board(sb)); 256025cf1a30Sjl } 256125cf1a30Sjl 256225cf1a30Sjl cmn_err(CE_NOTE, "!opl_get_physical_board() not loaded\n"); 256325cf1a30Sjl return (-1); 256425cf1a30Sjl } 256525cf1a30Sjl 256625cf1a30Sjl /* ARGSUSED */ 256725cf1a30Sjl int 256825cf1a30Sjl mc_get_mem_unum(int synd_code, uint64_t flt_addr, char *buf, int buflen, 256925cf1a30Sjl int *lenp) 257025cf1a30Sjl { 25710cc8ae86Sav int i; 257225cf1a30Sjl int sb; 25730cc8ae86Sav int bank; 25740cc8ae86Sav mc_opl_t *mcp; 25750cc8ae86Sav char memb_num; 257625cf1a30Sjl 257725cf1a30Sjl mutex_enter(&mcmutex); 257825cf1a30Sjl 257925cf1a30Sjl if (((mcp = mc_pa_to_mcp(flt_addr)) == NULL) || 258025cf1a30Sjl (!pa_is_valid(mcp, flt_addr))) { 258125cf1a30Sjl mutex_exit(&mcmutex); 258225cf1a30Sjl if (snprintf(buf, buflen, "UNKNOWN") >= buflen) { 258325cf1a30Sjl return (ENOSPC); 258425cf1a30Sjl } else { 258525cf1a30Sjl if (lenp) 258625cf1a30Sjl *lenp = strlen(buf); 258725cf1a30Sjl } 258825cf1a30Sjl return (0); 258925cf1a30Sjl } 259025cf1a30Sjl 259125cf1a30Sjl bank = pa_to_bank(mcp, flt_addr - mcp->mc_start_address); 259225cf1a30Sjl sb = mc_opl_get_physical_board(mcp->mc_board_num); 259325cf1a30Sjl 259425cf1a30Sjl if (sb == -1) { 259525cf1a30Sjl mutex_exit(&mcmutex); 259625cf1a30Sjl return (ENXIO); 259725cf1a30Sjl } 259825cf1a30Sjl 25990cc8ae86Sav if (plat_model == MODEL_DC) { 26000cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(0, bank, 0); 26010cc8ae86Sav snprintf(buf, buflen, "/%s%02d/MEM%s MEM%s MEM%s MEM%s", 26020cc8ae86Sav model_names[plat_model].unit_name, sb, 26030cc8ae86Sav mc_dc_dimm_unum_table[i], mc_dc_dimm_unum_table[i + 1], 26040cc8ae86Sav mc_dc_dimm_unum_table[i + 2], mc_dc_dimm_unum_table[i + 3]); 260525cf1a30Sjl } else { 26060cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(sb, bank, 0); 26070cc8ae86Sav memb_num = mc_ff_dimm_unum_table[i][0]; 26080cc8ae86Sav snprintf(buf, buflen, "/%s/%s%c/MEM%s MEM%s MEM%s MEM%s", 26090cc8ae86Sav model_names[plat_model].unit_name, 26100cc8ae86Sav model_names[plat_model].mem_name, memb_num, 26110cc8ae86Sav &mc_ff_dimm_unum_table[i][1], 26120cc8ae86Sav 26130cc8ae86Sav &mc_ff_dimm_unum_table[i + 1][1], 26140cc8ae86Sav &mc_ff_dimm_unum_table[i + 2][1], 26150cc8ae86Sav &mc_ff_dimm_unum_table[i + 3][1]); 26160cc8ae86Sav } 26170cc8ae86Sav if (lenp) { 26180cc8ae86Sav *lenp = strlen(buf); 261925cf1a30Sjl } 262025cf1a30Sjl mutex_exit(&mcmutex); 262125cf1a30Sjl return (0); 262225cf1a30Sjl } 262325cf1a30Sjl 262425cf1a30Sjl int 26250cc8ae86Sav opl_mc_suspend(void) 262625cf1a30Sjl { 262725cf1a30Sjl mc_opl_t *mcp; 26280cc8ae86Sav int i; 262925cf1a30Sjl 263025cf1a30Sjl mutex_enter(&mcmutex); 26310cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 26320cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 26330cc8ae86Sav continue; 26340cc8ae86Sav mc_suspend(mcp, MC_SOFT_SUSPENDED); 263525cf1a30Sjl } 263625cf1a30Sjl mutex_exit(&mcmutex); 26370cc8ae86Sav 263825cf1a30Sjl return (0); 263925cf1a30Sjl } 264025cf1a30Sjl 264125cf1a30Sjl int 26420cc8ae86Sav opl_mc_resume(void) 264325cf1a30Sjl { 264425cf1a30Sjl mc_opl_t *mcp; 26450cc8ae86Sav int i; 264625cf1a30Sjl 264725cf1a30Sjl mutex_enter(&mcmutex); 26480cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 26490cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 26500cc8ae86Sav continue; 26510cc8ae86Sav mc_resume(mcp, MC_SOFT_SUSPENDED); 265225cf1a30Sjl } 265325cf1a30Sjl mutex_exit(&mcmutex); 26540cc8ae86Sav 265525cf1a30Sjl return (0); 265625cf1a30Sjl } 265725cf1a30Sjl static void 265825cf1a30Sjl insert_mcp(mc_opl_t *mcp) 265925cf1a30Sjl { 266025cf1a30Sjl mutex_enter(&mcmutex); 26610cc8ae86Sav if (mc_instances[mcp->mc_board_num] != NULL) { 26620cc8ae86Sav MC_LOG("mc-opl instance for board# %d already exists\n", 26630cc8ae86Sav mcp->mc_board_num); 26640cc8ae86Sav } 26650cc8ae86Sav mc_instances[mcp->mc_board_num] = mcp; 266625cf1a30Sjl mutex_exit(&mcmutex); 266725cf1a30Sjl } 266825cf1a30Sjl 266925cf1a30Sjl static void 267025cf1a30Sjl delete_mcp(mc_opl_t *mcp) 267125cf1a30Sjl { 26720cc8ae86Sav mutex_enter(&mcmutex); 26730cc8ae86Sav mc_instances[mcp->mc_board_num] = 0; 26740cc8ae86Sav mutex_exit(&mcmutex); 267525cf1a30Sjl } 267625cf1a30Sjl 267725cf1a30Sjl /* Error injection interface */ 267825cf1a30Sjl 267925cf1a30Sjl /* ARGSUSED */ 268025cf1a30Sjl int 268125cf1a30Sjl mc_inject_error(int error_type, uint64_t pa, uint32_t flags) 268225cf1a30Sjl { 268325cf1a30Sjl mc_opl_t *mcp; 268425cf1a30Sjl int bank; 268525cf1a30Sjl uint32_t dimm_addr; 268625cf1a30Sjl uint32_t cntl; 268725cf1a30Sjl mc_addr_info_t maddr; 268825cf1a30Sjl uint32_t data, stat; 268925cf1a30Sjl int both_sides = 0; 269025cf1a30Sjl uint64_t pa0; 269125cf1a30Sjl on_trap_data_t otd; 269225cf1a30Sjl extern void cpu_flush_ecache(void); 269325cf1a30Sjl 269425cf1a30Sjl MC_LOG("HW mc_inject_error(%x, %lx, %x)\n", error_type, pa, flags); 269525cf1a30Sjl 269625cf1a30Sjl mutex_enter(&mcmutex); 269725cf1a30Sjl if ((mcp = mc_pa_to_mcp(pa)) == NULL) { 269825cf1a30Sjl mutex_exit(&mcmutex); 269925cf1a30Sjl MC_LOG("mc_inject_error: invalid pa\n"); 270025cf1a30Sjl return (ENOTSUP); 270125cf1a30Sjl } 270225cf1a30Sjl 270325cf1a30Sjl mutex_enter(&mcp->mc_lock); 270425cf1a30Sjl mutex_exit(&mcmutex); 270525cf1a30Sjl 270625cf1a30Sjl if (mcp->mc_status & (MC_SOFT_SUSPENDED | MC_DRIVER_SUSPENDED)) { 270725cf1a30Sjl mutex_exit(&mcp->mc_lock); 270825cf1a30Sjl MC_LOG("mc-opl has been suspended. No error injection.\n"); 270925cf1a30Sjl return (EBUSY); 271025cf1a30Sjl } 271125cf1a30Sjl 271225cf1a30Sjl /* convert pa to offset within the board */ 271325cf1a30Sjl MC_LOG("pa %lx, offset %lx\n", pa, pa - mcp->mc_start_address); 271425cf1a30Sjl 271525cf1a30Sjl if (!pa_is_valid(mcp, pa)) { 271625cf1a30Sjl mutex_exit(&mcp->mc_lock); 271725cf1a30Sjl return (EINVAL); 271825cf1a30Sjl } 271925cf1a30Sjl 272025cf1a30Sjl pa0 = pa - mcp->mc_start_address; 272125cf1a30Sjl 272225cf1a30Sjl bank = pa_to_bank(mcp, pa0); 272325cf1a30Sjl 272425cf1a30Sjl if (flags & MC_INJECT_FLAG_OTHER) 272525cf1a30Sjl bank = bank ^ 1; 272625cf1a30Sjl 272725cf1a30Sjl if (MC_INJECT_MIRROR(error_type) && !IS_MIRROR(mcp, bank)) { 272825cf1a30Sjl mutex_exit(&mcp->mc_lock); 272925cf1a30Sjl MC_LOG("Not mirror mode\n"); 273025cf1a30Sjl return (EINVAL); 273125cf1a30Sjl } 273225cf1a30Sjl 273325cf1a30Sjl dimm_addr = pa_to_dimm(mcp, pa0); 273425cf1a30Sjl 273525cf1a30Sjl MC_LOG("injecting error to /LSB%d/B%d/D%x\n", 273625cf1a30Sjl mcp->mc_board_num, bank, dimm_addr); 273725cf1a30Sjl 273825cf1a30Sjl 273925cf1a30Sjl switch (error_type) { 274025cf1a30Sjl case MC_INJECT_INTERMITTENT_MCE: 274125cf1a30Sjl case MC_INJECT_PERMANENT_MCE: 274225cf1a30Sjl case MC_INJECT_MUE: 274325cf1a30Sjl both_sides = 1; 274425cf1a30Sjl } 274525cf1a30Sjl 274625cf1a30Sjl if (flags & MC_INJECT_FLAG_RESET) 274725cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank), 0); 274825cf1a30Sjl 274925cf1a30Sjl ST_MAC_REG(MAC_EG_ADD(mcp, bank), dimm_addr & MAC_EG_ADD_MASK); 275025cf1a30Sjl 275125cf1a30Sjl if (both_sides) { 275225cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), 0); 275325cf1a30Sjl ST_MAC_REG(MAC_EG_ADD(mcp, bank^1), 275425cf1a30Sjl dimm_addr & MAC_EG_ADD_MASK); 275525cf1a30Sjl } 275625cf1a30Sjl 275725cf1a30Sjl switch (error_type) { 275825cf1a30Sjl case MC_INJECT_UE: 275925cf1a30Sjl case MC_INJECT_SUE: 276025cf1a30Sjl case MC_INJECT_MUE: 276125cf1a30Sjl if (flags & MC_INJECT_FLAG_PATH) { 276225cf1a30Sjl cntl = MAC_EG_ADD_FIX 276325cf1a30Sjl |MAC_EG_FORCE_READ00|MAC_EG_FORCE_READ16 27640cc8ae86Sav |MAC_EG_RDERR_ONCE; 276525cf1a30Sjl } else { 276625cf1a30Sjl cntl = MAC_EG_ADD_FIX|MAC_EG_FORCE_DERR00 276725cf1a30Sjl |MAC_EG_FORCE_DERR16|MAC_EG_DERR_ONCE; 276825cf1a30Sjl } 276925cf1a30Sjl flags |= MC_INJECT_FLAG_ST; 277025cf1a30Sjl break; 277125cf1a30Sjl case MC_INJECT_INTERMITTENT_CE: 277225cf1a30Sjl case MC_INJECT_INTERMITTENT_MCE: 277325cf1a30Sjl if (flags & MC_INJECT_FLAG_PATH) { 277425cf1a30Sjl cntl = MAC_EG_ADD_FIX 277525cf1a30Sjl |MAC_EG_FORCE_READ00 27760cc8ae86Sav |MAC_EG_RDERR_ONCE; 277725cf1a30Sjl } else { 277825cf1a30Sjl cntl = MAC_EG_ADD_FIX 277925cf1a30Sjl |MAC_EG_FORCE_DERR16 278025cf1a30Sjl |MAC_EG_DERR_ONCE; 278125cf1a30Sjl } 278225cf1a30Sjl flags |= MC_INJECT_FLAG_ST; 278325cf1a30Sjl break; 278425cf1a30Sjl case MC_INJECT_PERMANENT_CE: 278525cf1a30Sjl case MC_INJECT_PERMANENT_MCE: 278625cf1a30Sjl if (flags & MC_INJECT_FLAG_PATH) { 278725cf1a30Sjl cntl = MAC_EG_ADD_FIX 278825cf1a30Sjl |MAC_EG_FORCE_READ00 27890cc8ae86Sav |MAC_EG_RDERR_ALWAYS; 279025cf1a30Sjl } else { 279125cf1a30Sjl cntl = MAC_EG_ADD_FIX 279225cf1a30Sjl |MAC_EG_FORCE_DERR16 279325cf1a30Sjl |MAC_EG_DERR_ALWAYS; 279425cf1a30Sjl } 279525cf1a30Sjl flags |= MC_INJECT_FLAG_ST; 279625cf1a30Sjl break; 279725cf1a30Sjl case MC_INJECT_CMPE: 279825cf1a30Sjl data = 0xabcdefab; 279925cf1a30Sjl stphys(pa, data); 280025cf1a30Sjl cpu_flush_ecache(); 280125cf1a30Sjl MC_LOG("CMPE: writing data %x to %lx\n", data, pa); 280225cf1a30Sjl ST_MAC_REG(MAC_MIRR(mcp, bank), MAC_MIRR_BANK_EXCLUSIVE); 280325cf1a30Sjl stphys(pa, data ^ 0xffffffff); 280425cf1a30Sjl cpu_flush_ecache(); 280525cf1a30Sjl ST_MAC_REG(MAC_MIRR(mcp, bank), 0); 280625cf1a30Sjl MC_LOG("CMPE: write new data %xto %lx\n", data, pa); 280725cf1a30Sjl cntl = 0; 280825cf1a30Sjl break; 280925cf1a30Sjl case MC_INJECT_NOP: 281025cf1a30Sjl cntl = 0; 281125cf1a30Sjl break; 281225cf1a30Sjl default: 281325cf1a30Sjl MC_LOG("mc_inject_error: invalid option\n"); 281425cf1a30Sjl cntl = 0; 281525cf1a30Sjl } 281625cf1a30Sjl 281725cf1a30Sjl if (cntl) { 281825cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl & MAC_EG_SETUP_MASK); 281925cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl); 282025cf1a30Sjl 282125cf1a30Sjl if (both_sides) { 282225cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl & 282325cf1a30Sjl MAC_EG_SETUP_MASK); 282425cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl); 282525cf1a30Sjl } 282625cf1a30Sjl } 282725cf1a30Sjl 282825cf1a30Sjl /* 282925cf1a30Sjl * For all injection cases except compare error, we 283025cf1a30Sjl * must write to the PA to trigger the error. 283125cf1a30Sjl */ 283225cf1a30Sjl 283325cf1a30Sjl if (flags & MC_INJECT_FLAG_ST) { 283425cf1a30Sjl data = 0xf0e0d0c0; 283525cf1a30Sjl MC_LOG("Writing %x to %lx\n", data, pa); 283625cf1a30Sjl stphys(pa, data); 283725cf1a30Sjl cpu_flush_ecache(); 283825cf1a30Sjl } 283925cf1a30Sjl 284025cf1a30Sjl 284125cf1a30Sjl if (flags & MC_INJECT_FLAG_LD) { 284225cf1a30Sjl if (flags & MC_INJECT_FLAG_NO_TRAP) { 284325cf1a30Sjl if (on_trap(&otd, OT_DATA_EC)) { 284425cf1a30Sjl no_trap(); 284525cf1a30Sjl MC_LOG("Trap occurred\n"); 284625cf1a30Sjl } else { 284725cf1a30Sjl MC_LOG("On-trap Reading from %lx\n", pa); 284825cf1a30Sjl data = ldphys(pa); 284925cf1a30Sjl no_trap(); 285025cf1a30Sjl MC_LOG("data = %x\n", data); 285125cf1a30Sjl } 285225cf1a30Sjl } else { 285325cf1a30Sjl MC_LOG("Reading from %lx\n", pa); 285425cf1a30Sjl data = ldphys(pa); 285525cf1a30Sjl MC_LOG("data = %x\n", data); 285625cf1a30Sjl } 285725cf1a30Sjl } 285825cf1a30Sjl 285925cf1a30Sjl if (flags & MC_INJECT_FLAG_RESTART) { 286025cf1a30Sjl MC_LOG("Restart patrol\n"); 286125cf1a30Sjl maddr.mi_maddr.ma_bd = mcp->mc_board_num; 286225cf1a30Sjl maddr.mi_maddr.ma_bank = bank; 286325cf1a30Sjl maddr.mi_maddr.ma_dimm_addr = dimm_addr; 286425cf1a30Sjl maddr.mi_valid = 1; 286525cf1a30Sjl maddr.mi_advance = 0; 286625cf1a30Sjl restart_patrol(mcp, bank, &maddr); 286725cf1a30Sjl } 286825cf1a30Sjl 286925cf1a30Sjl if (flags & MC_INJECT_FLAG_POLL) { 28700cc8ae86Sav int running; 287125cf1a30Sjl 287225cf1a30Sjl MC_LOG("Poll patrol error\n"); 287325cf1a30Sjl stat = LD_MAC_REG(MAC_PTRL_STAT(mcp, bank)); 287425cf1a30Sjl cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 28750cc8ae86Sav running = cntl & MAC_CNTL_PTRL_START; 287625cf1a30Sjl if (stat & (MAC_STAT_PTRL_ERRS|MAC_STAT_MI_ERRS)) { 28770cc8ae86Sav if (running) { 28780cc8ae86Sav /* speed up the scanning */ 28790cc8ae86Sav mcp->mc_speedup_period[bank] = 2; 28800cc8ae86Sav MAC_CMD(mcp, bank, 0); 28810cc8ae86Sav } else { 28820cc8ae86Sav mcp->mc_speedup_period[bank] = 0; 28830cc8ae86Sav maddr.mi_valid = 0; 28840cc8ae86Sav maddr.mi_advance = 1; 28850cc8ae86Sav if (IS_MIRROR(mcp, bank)) 28860cc8ae86Sav mc_error_handler_mir(mcp, bank, 28870cc8ae86Sav &maddr); 28880cc8ae86Sav else 28890cc8ae86Sav mc_error_handler(mcp, bank, &maddr); 289025cf1a30Sjl 28910cc8ae86Sav restart_patrol(mcp, bank, &maddr); 28920cc8ae86Sav } 289325cf1a30Sjl } else 289425cf1a30Sjl restart_patrol(mcp, bank, NULL); 289525cf1a30Sjl } 289625cf1a30Sjl 289725cf1a30Sjl mutex_exit(&mcp->mc_lock); 289825cf1a30Sjl return (0); 289925cf1a30Sjl } 290025cf1a30Sjl void 290125cf1a30Sjl mc_stphysio(uint64_t pa, uint32_t data) 290225cf1a30Sjl { 29030cc8ae86Sav #ifndef lint 29040cc8ae86Sav uint32_t dummy; 29050cc8ae86Sav #endif 29060cc8ae86Sav 290725cf1a30Sjl MC_LOG("0x%x -> pa(%lx)\n", data, pa); 290825cf1a30Sjl stphysio(pa, data); 29090cc8ae86Sav 29100cc8ae86Sav /* force the above write to be processed by mac patrol */ 29110cc8ae86Sav #ifndef lint 29120cc8ae86Sav dummy = ldphysio(pa); 29130cc8ae86Sav #endif 291425cf1a30Sjl } 291525cf1a30Sjl 291625cf1a30Sjl uint32_t 291725cf1a30Sjl mc_ldphysio(uint64_t pa) 291825cf1a30Sjl { 291925cf1a30Sjl uint32_t rv; 292025cf1a30Sjl 292125cf1a30Sjl rv = ldphysio(pa); 292225cf1a30Sjl MC_LOG("pa(%lx) = 0x%x\n", pa, rv); 292325cf1a30Sjl return (rv); 292425cf1a30Sjl } 29250cc8ae86Sav 29260cc8ae86Sav #define isdigit(ch) ((ch) >= '0' && (ch) <= '9') 29270cc8ae86Sav 29280cc8ae86Sav /* 29290cc8ae86Sav * parse_unum_memory -- extract the board number and the DIMM name from 29300cc8ae86Sav * the unum. 29310cc8ae86Sav * 29320cc8ae86Sav * Return 0 for success and non-zero for a failure. 29330cc8ae86Sav */ 29340cc8ae86Sav int 29350cc8ae86Sav parse_unum_memory(char *unum, int *board, char *dname) 29360cc8ae86Sav { 29370cc8ae86Sav char *c; 29380cc8ae86Sav char x, y, z; 29390cc8ae86Sav 29400cc8ae86Sav if ((c = strstr(unum, "CMU")) != NULL) { 29410cc8ae86Sav /* DC Model */ 29420cc8ae86Sav c += 3; 29430cc8ae86Sav *board = (uint8_t)stoi(&c); 29440cc8ae86Sav if ((c = strstr(c, "MEM")) == NULL) { 29450cc8ae86Sav return (1); 29460cc8ae86Sav } 29470cc8ae86Sav c += 3; 29480cc8ae86Sav if (strlen(c) < 3) { 29490cc8ae86Sav return (2); 29500cc8ae86Sav } 29510cc8ae86Sav if ((!isdigit(c[0])) || (!(isdigit(c[1]))) || 29520cc8ae86Sav ((c[2] != 'A') && (c[2] != 'B'))) { 29530cc8ae86Sav return (3); 29540cc8ae86Sav } 29550cc8ae86Sav x = c[0]; 29560cc8ae86Sav y = c[1]; 29570cc8ae86Sav z = c[2]; 29580cc8ae86Sav } else if ((c = strstr(unum, "MBU_")) != NULL) { 29590cc8ae86Sav /* FF1/FF2 Model */ 29600cc8ae86Sav c += 4; 29610cc8ae86Sav if ((c[0] != 'A') && (c[0] != 'B')) { 29620cc8ae86Sav return (4); 29630cc8ae86Sav } 29640cc8ae86Sav if ((c = strstr(c, "MEMB")) == NULL) { 29650cc8ae86Sav return (5); 29660cc8ae86Sav } 29670cc8ae86Sav c += 4; 29680cc8ae86Sav 29690cc8ae86Sav x = c[0]; 29700cc8ae86Sav *board = ((uint8_t)stoi(&c)) / 4; 29710cc8ae86Sav if ((c = strstr(c, "MEM")) == NULL) { 29720cc8ae86Sav return (6); 29730cc8ae86Sav } 29740cc8ae86Sav c += 3; 29750cc8ae86Sav if (strlen(c) < 2) { 29760cc8ae86Sav return (7); 29770cc8ae86Sav } 29780cc8ae86Sav if ((!isdigit(c[0])) || ((c[1] != 'A') && (c[1] != 'B'))) { 29790cc8ae86Sav return (8); 29800cc8ae86Sav } 29810cc8ae86Sav y = c[0]; 29820cc8ae86Sav z = c[1]; 29830cc8ae86Sav } else { 29840cc8ae86Sav return (9); 29850cc8ae86Sav } 29860cc8ae86Sav if (*board < 0) { 29870cc8ae86Sav return (10); 29880cc8ae86Sav } 29890cc8ae86Sav dname[0] = x; 29900cc8ae86Sav dname[1] = y; 29910cc8ae86Sav dname[2] = z; 29920cc8ae86Sav dname[3] = '\0'; 29930cc8ae86Sav return (0); 29940cc8ae86Sav } 29950cc8ae86Sav 29960cc8ae86Sav /* 29970cc8ae86Sav * mc_get_mem_sid_dimm -- Get the serial-ID for a given board and 29980cc8ae86Sav * the DIMM name. 29990cc8ae86Sav */ 30000cc8ae86Sav int 30010cc8ae86Sav mc_get_mem_sid_dimm(mc_opl_t *mcp, char *dname, char *buf, 30020cc8ae86Sav int buflen, int *lenp) 30030cc8ae86Sav { 30040cc8ae86Sav int ret = ENODEV; 30050cc8ae86Sav mc_dimm_info_t *d = NULL; 30060cc8ae86Sav 30070cc8ae86Sav if ((d = mcp->mc_dimm_list) == NULL) 30080cc8ae86Sav return (ENOTSUP); 30090cc8ae86Sav 30100cc8ae86Sav for (; d != NULL; d = d->md_next) { 30110cc8ae86Sav if (strcmp(d->md_dimmname, dname) == 0) { 30120cc8ae86Sav break; 30130cc8ae86Sav } 30140cc8ae86Sav } 30150cc8ae86Sav if (d != NULL) { 30160cc8ae86Sav *lenp = strlen(d->md_serial) + strlen(d->md_partnum); 30170cc8ae86Sav if (buflen <= *lenp) { 30180cc8ae86Sav cmn_err(CE_WARN, "mc_get_mem_sid_dimm: " 30190cc8ae86Sav "buflen is smaller than %d\n", *lenp); 30200cc8ae86Sav ret = ENOSPC; 30210cc8ae86Sav } else { 30220cc8ae86Sav snprintf(buf, buflen, "%s:%s", 30230cc8ae86Sav d->md_serial, d->md_partnum); 30240cc8ae86Sav ret = 0; 30250cc8ae86Sav } 30260cc8ae86Sav } 30270cc8ae86Sav MC_LOG("mc_get_mem_sid_dimm: Ret=%d Name=%s Serial-ID=%s\n", 30280cc8ae86Sav ret, dname, (ret == 0) ? buf : ""); 30290cc8ae86Sav return (ret); 30300cc8ae86Sav } 30310cc8ae86Sav 30320cc8ae86Sav int 30330cc8ae86Sav mc_set_mem_sid(mc_opl_t *mcp, char *buf, int buflen, int lsb, 30340cc8ae86Sav int bank, uint32_t mf_type, uint32_t d_slot) 30350cc8ae86Sav { 30360cc8ae86Sav int sb; 30370cc8ae86Sav int lenp = buflen; 30380cc8ae86Sav int id; 30390cc8ae86Sav int ret; 30400cc8ae86Sav char *dimmnm; 30410cc8ae86Sav 30420cc8ae86Sav if ((sb = mc_opl_get_physical_board(lsb)) < 0) { 30430cc8ae86Sav return (ENODEV); 30440cc8ae86Sav } 30450cc8ae86Sav 30460cc8ae86Sav if (mf_type == FLT_TYPE_PERMANENT_CE) { 30470cc8ae86Sav if (plat_model == MODEL_DC) { 30480cc8ae86Sav id = BD_BK_SLOT_TO_INDEX(0, bank, d_slot); 30490cc8ae86Sav } else { 30500cc8ae86Sav id = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot); 30510cc8ae86Sav } 30520cc8ae86Sav dimmnm = mc_dc_dimm_unum_table[id]; 30530cc8ae86Sav if ((ret = mc_get_mem_sid_dimm(mcp, dimmnm, buf, buflen, 30540cc8ae86Sav &lenp)) != 0) { 30550cc8ae86Sav return (ret); 30560cc8ae86Sav } 30570cc8ae86Sav } else { 30580cc8ae86Sav return (1); 30590cc8ae86Sav } 30600cc8ae86Sav 30610cc8ae86Sav return (0); 30620cc8ae86Sav } 30630cc8ae86Sav 30640cc8ae86Sav /* 30650cc8ae86Sav * mc_get_mem_sid -- get the DIMM serial-ID corresponding to the unum. 30660cc8ae86Sav */ 30670cc8ae86Sav int 30680cc8ae86Sav mc_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 30690cc8ae86Sav { 30700cc8ae86Sav int i; 30710cc8ae86Sav int ret = ENODEV; 30720cc8ae86Sav int board; 30730cc8ae86Sav char dname[MCOPL_MAX_DIMMNAME + 1]; 30740cc8ae86Sav mc_opl_t *mcp; 30750cc8ae86Sav 30760cc8ae86Sav MC_LOG("mc_get_mem_sid: unum=%s buflen=%d\n", unum, buflen); 30770cc8ae86Sav if ((ret = parse_unum_memory(unum, &board, dname)) != 0) { 30780cc8ae86Sav MC_LOG("mc_get_mem_sid: unum(%s) parsing failed ret=%d\n", 30790cc8ae86Sav unum, ret); 30800cc8ae86Sav return (EINVAL); 30810cc8ae86Sav } 30820cc8ae86Sav 30830cc8ae86Sav if (board < 0) { 30840cc8ae86Sav MC_LOG("mc_get_mem_sid: Invalid board=%d dimm=%s\n", 30850cc8ae86Sav board, dname); 30860cc8ae86Sav return (EINVAL); 30870cc8ae86Sav } 30880cc8ae86Sav 30890cc8ae86Sav mutex_enter(&mcmutex); 30900cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 30910cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 30920cc8ae86Sav continue; 30930cc8ae86Sav mutex_enter(&mcp->mc_lock); 30940cc8ae86Sav if (mcp->mc_board_num == board) { 30950cc8ae86Sav ret = mc_get_mem_sid_dimm(mcp, dname, buf, 30960cc8ae86Sav buflen, lenp); 30970cc8ae86Sav mutex_exit(&mcp->mc_lock); 30980cc8ae86Sav break; 30990cc8ae86Sav } 31000cc8ae86Sav mutex_exit(&mcp->mc_lock); 31010cc8ae86Sav } 31020cc8ae86Sav mutex_exit(&mcmutex); 31030cc8ae86Sav return (ret); 31040cc8ae86Sav } 31050cc8ae86Sav 31060cc8ae86Sav /* 31070cc8ae86Sav * mc_get_mem_offset -- get the offset in a DIMM for a given physical address. 31080cc8ae86Sav */ 31090cc8ae86Sav int 31100cc8ae86Sav mc_get_mem_offset(uint64_t paddr, uint64_t *offp) 31110cc8ae86Sav { 31120cc8ae86Sav int i; 31130cc8ae86Sav int ret = ENODEV; 31140cc8ae86Sav mc_addr_t maddr; 31150cc8ae86Sav mc_opl_t *mcp; 31160cc8ae86Sav 31170cc8ae86Sav mutex_enter(&mcmutex); 31180cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 31190cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 31200cc8ae86Sav continue; 31210cc8ae86Sav mutex_enter(&mcp->mc_lock); 31220cc8ae86Sav if (!pa_is_valid(mcp, paddr)) { 31230cc8ae86Sav mutex_exit(&mcp->mc_lock); 31240cc8ae86Sav continue; 31250cc8ae86Sav } 31260cc8ae86Sav if (pa_to_maddr(mcp, paddr, &maddr) == 0) { 31270cc8ae86Sav *offp = maddr.ma_dimm_addr; 31280cc8ae86Sav ret = 0; 31290cc8ae86Sav } 31300cc8ae86Sav mutex_exit(&mcp->mc_lock); 31310cc8ae86Sav } 31320cc8ae86Sav mutex_exit(&mcmutex); 31330cc8ae86Sav MC_LOG("mc_get_mem_offset: Ret=%d paddr=0x%lx offset=0x%lx\n", 31340cc8ae86Sav ret, paddr, *offp); 31350cc8ae86Sav return (ret); 31360cc8ae86Sav } 31370cc8ae86Sav 31380cc8ae86Sav /* 31390cc8ae86Sav * dname_to_bankslot - Get the bank and slot number from the DIMM name. 31400cc8ae86Sav */ 31410cc8ae86Sav int 31420cc8ae86Sav dname_to_bankslot(char *dname, int *bank, int *slot) 31430cc8ae86Sav { 31440cc8ae86Sav int i; 31450cc8ae86Sav int tsz; 31460cc8ae86Sav char **tbl; 31470cc8ae86Sav 31480cc8ae86Sav if (plat_model == MODEL_DC) { /* DC */ 31490cc8ae86Sav tbl = mc_dc_dimm_unum_table; 31500cc8ae86Sav tsz = OPL_MAX_DIMMS; 31510cc8ae86Sav } else { 31520cc8ae86Sav tbl = mc_ff_dimm_unum_table; 31530cc8ae86Sav tsz = 2 * OPL_MAX_DIMMS; 31540cc8ae86Sav } 31550cc8ae86Sav 31560cc8ae86Sav for (i = 0; i < tsz; i++) { 31570cc8ae86Sav if (strcmp(dname, tbl[i]) == 0) { 31580cc8ae86Sav break; 31590cc8ae86Sav } 31600cc8ae86Sav } 31610cc8ae86Sav if (i == tsz) { 31620cc8ae86Sav return (1); 31630cc8ae86Sav } 31640cc8ae86Sav *bank = INDEX_TO_BANK(i); 31650cc8ae86Sav *slot = INDEX_TO_SLOT(i); 31660cc8ae86Sav return (0); 31670cc8ae86Sav } 31680cc8ae86Sav 31690cc8ae86Sav /* 31700cc8ae86Sav * mc_get_mem_addr -- get the physical address of a DIMM corresponding 31710cc8ae86Sav * to the unum and sid. 31720cc8ae86Sav */ 31730cc8ae86Sav int 31740cc8ae86Sav mc_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *paddr) 31750cc8ae86Sav { 31760cc8ae86Sav int board; 31770cc8ae86Sav int bank; 31780cc8ae86Sav int slot; 31790cc8ae86Sav int i; 31800cc8ae86Sav int ret = ENODEV; 31810cc8ae86Sav char dname[MCOPL_MAX_DIMMNAME + 1]; 31820cc8ae86Sav mc_addr_t maddr; 31830cc8ae86Sav mc_opl_t *mcp; 31840cc8ae86Sav 31850cc8ae86Sav MC_LOG("mc_get_mem_addr: unum=%s sid=%s offset=0x%lx\n", 31860cc8ae86Sav unum, sid, offset); 31870cc8ae86Sav if (parse_unum_memory(unum, &board, dname) != 0) { 31880cc8ae86Sav MC_LOG("mc_get_mem_sid: unum(%s) parsing failed ret=%d\n", 31890cc8ae86Sav unum, ret); 31900cc8ae86Sav return (EINVAL); 31910cc8ae86Sav } 31920cc8ae86Sav 31930cc8ae86Sav if (board < 0) { 31940cc8ae86Sav MC_LOG("mc_get_mem_addr: Invalid board=%d dimm=%s\n", 31950cc8ae86Sav board, dname); 31960cc8ae86Sav return (EINVAL); 31970cc8ae86Sav } 31980cc8ae86Sav 31990cc8ae86Sav mutex_enter(&mcmutex); 32000cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 32010cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 32020cc8ae86Sav continue; 32030cc8ae86Sav mutex_enter(&mcp->mc_lock); 32040cc8ae86Sav if (mcp->mc_board_num != board) { 32050cc8ae86Sav mutex_exit(&mcp->mc_lock); 32060cc8ae86Sav continue; 32070cc8ae86Sav } 32080cc8ae86Sav 32090cc8ae86Sav ret = dname_to_bankslot(dname, &bank, &slot); 32100cc8ae86Sav MC_LOG("mc_get_mem_addr: bank=%d slot=%d\n", bank, slot); 32110cc8ae86Sav if (ret != 0) { 32120cc8ae86Sav MC_LOG("mc_get_mem_addr: dname_to_bankslot failed\n"); 32130cc8ae86Sav ret = ENODEV; 32140cc8ae86Sav } else { 32150cc8ae86Sav maddr.ma_bd = board; 32160cc8ae86Sav maddr.ma_bank = bank; 32170cc8ae86Sav maddr.ma_dimm_addr = offset; 32180cc8ae86Sav ret = mcaddr_to_pa(mcp, &maddr, paddr); 32190cc8ae86Sav if (ret != 0) { 32200cc8ae86Sav MC_LOG("mc_get_mem_addr: " 32210cc8ae86Sav "mcaddr_to_pa failed\n"); 32220cc8ae86Sav ret = ENODEV; 32230cc8ae86Sav } 32240cc8ae86Sav } 32250cc8ae86Sav mutex_exit(&mcp->mc_lock); 32260cc8ae86Sav } 32270cc8ae86Sav mutex_exit(&mcmutex); 32280cc8ae86Sav MC_LOG("mc_get_mem_addr: Ret=%d, Paddr=0x%lx\n", ret, *paddr); 32290cc8ae86Sav return (ret); 32300cc8ae86Sav } 32310cc8ae86Sav 32320cc8ae86Sav static void 32330cc8ae86Sav mc_free_dimm_list(mc_dimm_info_t *d) 32340cc8ae86Sav { 32350cc8ae86Sav mc_dimm_info_t *next; 32360cc8ae86Sav 32370cc8ae86Sav while (d != NULL) { 32380cc8ae86Sav next = d->md_next; 32390cc8ae86Sav kmem_free(d, sizeof (mc_dimm_info_t)); 32400cc8ae86Sav d = next; 32410cc8ae86Sav } 32420cc8ae86Sav } 32430cc8ae86Sav 32440cc8ae86Sav /* 32450cc8ae86Sav * mc_get_dimm_list -- get the list of dimms with serial-id info 32460cc8ae86Sav * from the SP. 32470cc8ae86Sav */ 32480cc8ae86Sav mc_dimm_info_t * 32490cc8ae86Sav mc_get_dimm_list(mc_opl_t *mcp) 32500cc8ae86Sav { 32510cc8ae86Sav uint32_t bufsz; 32520cc8ae86Sav uint32_t maxbufsz; 32530cc8ae86Sav int ret; 32540cc8ae86Sav int sexp; 32550cc8ae86Sav board_dimm_info_t *bd_dimmp; 32560cc8ae86Sav mc_dimm_info_t *dimm_list = NULL; 32570cc8ae86Sav 32580cc8ae86Sav maxbufsz = bufsz = sizeof (board_dimm_info_t) + 32590cc8ae86Sav ((MCOPL_MAX_DIMMNAME + MCOPL_MAX_SERIAL + 32600cc8ae86Sav MCOPL_MAX_PARTNUM) * OPL_MAX_DIMMS); 32610cc8ae86Sav 32620cc8ae86Sav bd_dimmp = (board_dimm_info_t *)kmem_alloc(bufsz, KM_SLEEP); 32630cc8ae86Sav ret = scf_get_dimminfo(mcp->mc_board_num, (void *)bd_dimmp, &bufsz); 32640cc8ae86Sav 32650cc8ae86Sav MC_LOG("mc_get_dimm_list: scf_service_getinfo returned=%d\n", ret); 32660cc8ae86Sav if (ret == 0) { 32670cc8ae86Sav sexp = sizeof (board_dimm_info_t) + 32680cc8ae86Sav ((bd_dimmp->bd_dnamesz + bd_dimmp->bd_serialsz + 32690cc8ae86Sav bd_dimmp->bd_partnumsz) * bd_dimmp->bd_numdimms); 32700cc8ae86Sav 32710cc8ae86Sav if ((bd_dimmp->bd_version == OPL_DIMM_INFO_VERSION) && 32720cc8ae86Sav (bd_dimmp->bd_dnamesz <= MCOPL_MAX_DIMMNAME) && 32730cc8ae86Sav (bd_dimmp->bd_serialsz <= MCOPL_MAX_SERIAL) && 32740cc8ae86Sav (bd_dimmp->bd_partnumsz <= MCOPL_MAX_PARTNUM) && 32750cc8ae86Sav (sexp <= bufsz)) { 32760cc8ae86Sav 32770cc8ae86Sav #ifdef DEBUG 32780cc8ae86Sav if (oplmc_debug) 32790cc8ae86Sav mc_dump_dimm_info(bd_dimmp); 32800cc8ae86Sav #endif 32810cc8ae86Sav dimm_list = mc_prepare_dimmlist(bd_dimmp); 32820cc8ae86Sav 32830cc8ae86Sav } else { 32840cc8ae86Sav cmn_err(CE_WARN, "DIMM info version mismatch\n"); 32850cc8ae86Sav } 32860cc8ae86Sav } 32870cc8ae86Sav kmem_free(bd_dimmp, maxbufsz); 32880cc8ae86Sav MC_LOG("mc_get_dimm_list: dimmlist=0x%p\n", dimm_list); 32890cc8ae86Sav return (dimm_list); 32900cc8ae86Sav } 32910cc8ae86Sav 32920cc8ae86Sav /* 32930cc8ae86Sav * mc_prepare_dimmlist - Prepare the dimm list from the infomation 32940cc8ae86Sav * recieved from the SP. 32950cc8ae86Sav */ 32960cc8ae86Sav mc_dimm_info_t * 32970cc8ae86Sav mc_prepare_dimmlist(board_dimm_info_t *bd_dimmp) 32980cc8ae86Sav { 32990cc8ae86Sav char *dimm_name; 33000cc8ae86Sav char *serial; 33010cc8ae86Sav char *part; 33020cc8ae86Sav int dimm; 33030cc8ae86Sav int dnamesz = bd_dimmp->bd_dnamesz; 33040cc8ae86Sav int sersz = bd_dimmp->bd_serialsz; 33050cc8ae86Sav int partsz = bd_dimmp->bd_partnumsz; 33060cc8ae86Sav mc_dimm_info_t *dimm_list = NULL; 33070cc8ae86Sav mc_dimm_info_t *d; 33080cc8ae86Sav 33090cc8ae86Sav dimm_name = (char *)(bd_dimmp + 1); 33100cc8ae86Sav for (dimm = 0; dimm < bd_dimmp->bd_numdimms; dimm++) { 33110cc8ae86Sav 33120cc8ae86Sav d = (mc_dimm_info_t *)kmem_alloc(sizeof (mc_dimm_info_t), 33130cc8ae86Sav KM_SLEEP); 33140cc8ae86Sav snprintf(d->md_dimmname, dnamesz + 1, "%s", dimm_name); 33150cc8ae86Sav serial = dimm_name + dnamesz; 33160cc8ae86Sav snprintf(d->md_serial, sersz + 1, "%s", serial); 33170cc8ae86Sav part = serial + sersz; 33180cc8ae86Sav snprintf(d->md_partnum, partsz + 1, "%s", part); 33190cc8ae86Sav 33200cc8ae86Sav d->md_next = dimm_list; 33210cc8ae86Sav dimm_list = d; 33220cc8ae86Sav dimm_name = part + partsz; 33230cc8ae86Sav } 33240cc8ae86Sav return (dimm_list); 33250cc8ae86Sav } 33260cc8ae86Sav 33270cc8ae86Sav #ifdef DEBUG 33280cc8ae86Sav void 33290cc8ae86Sav mc_dump_dimm(char *buf, int dnamesz, int serialsz, int partnumsz) 33300cc8ae86Sav { 33310cc8ae86Sav char dname[MCOPL_MAX_DIMMNAME + 1]; 33320cc8ae86Sav char serial[MCOPL_MAX_SERIAL + 1]; 33330cc8ae86Sav char part[ MCOPL_MAX_PARTNUM + 1]; 33340cc8ae86Sav char *b; 33350cc8ae86Sav 33360cc8ae86Sav b = buf; 33370cc8ae86Sav snprintf(dname, dnamesz + 1, "%s", b); 33380cc8ae86Sav b += dnamesz; 33390cc8ae86Sav snprintf(serial, serialsz + 1, "%s", b); 33400cc8ae86Sav b += serialsz; 33410cc8ae86Sav snprintf(part, partnumsz + 1, "%s", b); 33420cc8ae86Sav printf("DIMM=%s Serial=%s PartNum=%s\n", dname, serial, part); 33430cc8ae86Sav } 33440cc8ae86Sav 33450cc8ae86Sav void 33460cc8ae86Sav mc_dump_dimm_info(board_dimm_info_t *bd_dimmp) 33470cc8ae86Sav { 33480cc8ae86Sav int dimm; 33490cc8ae86Sav int dnamesz = bd_dimmp->bd_dnamesz; 33500cc8ae86Sav int sersz = bd_dimmp->bd_serialsz; 33510cc8ae86Sav int partsz = bd_dimmp->bd_partnumsz; 33520cc8ae86Sav char *buf; 33530cc8ae86Sav 33540cc8ae86Sav printf("Version=%d Board=%02d DIMMs=%d NameSize=%d " 33550cc8ae86Sav "SerialSize=%d PartnumSize=%d\n", bd_dimmp->bd_version, 33560cc8ae86Sav bd_dimmp->bd_boardnum, bd_dimmp->bd_numdimms, bd_dimmp->bd_dnamesz, 33570cc8ae86Sav bd_dimmp->bd_serialsz, bd_dimmp->bd_partnumsz); 33580cc8ae86Sav printf("======================================================\n"); 33590cc8ae86Sav 33600cc8ae86Sav buf = (char *)(bd_dimmp + 1); 33610cc8ae86Sav for (dimm = 0; dimm < bd_dimmp->bd_numdimms; dimm++) { 33620cc8ae86Sav mc_dump_dimm(buf, dnamesz, sersz, partsz); 33630cc8ae86Sav buf += dnamesz + sersz + partsz; 33640cc8ae86Sav } 33650cc8ae86Sav printf("======================================================\n"); 33660cc8ae86Sav } 33670cc8ae86Sav 33680cc8ae86Sav 33690cc8ae86Sav /* ARGSUSED */ 33700cc8ae86Sav static int 33710cc8ae86Sav mc_ioctl_debug(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 33720cc8ae86Sav int *rvalp) 33730cc8ae86Sav { 33740cc8ae86Sav caddr_t buf; 33750cc8ae86Sav uint64_t pa; 33760cc8ae86Sav int rv = 0; 33770cc8ae86Sav int i; 33780cc8ae86Sav uint32_t flags; 33790cc8ae86Sav static uint32_t offset = 0; 33800cc8ae86Sav 33810cc8ae86Sav 33820cc8ae86Sav flags = (cmd >> 4) & 0xfffffff; 33830cc8ae86Sav 33840cc8ae86Sav cmd &= 0xf; 33850cc8ae86Sav 33860cc8ae86Sav MC_LOG("mc_ioctl(cmd = %x, flags = %x)\n", cmd, flags); 33870cc8ae86Sav 33880cc8ae86Sav if (arg != NULL) { 33890cc8ae86Sav if (ddi_copyin((const void *)arg, (void *)&pa, 33900cc8ae86Sav sizeof (uint64_t), 0) < 0) { 33910cc8ae86Sav rv = EFAULT; 33920cc8ae86Sav return (rv); 33930cc8ae86Sav } 33940cc8ae86Sav buf = NULL; 33950cc8ae86Sav } else { 33960cc8ae86Sav buf = (caddr_t)kmem_alloc(PAGESIZE, KM_SLEEP); 33970cc8ae86Sav 33980cc8ae86Sav pa = va_to_pa(buf); 33990cc8ae86Sav pa += offset; 34000cc8ae86Sav 34010cc8ae86Sav offset += 64; 34020cc8ae86Sav if (offset >= PAGESIZE) 34030cc8ae86Sav offset = 0; 34040cc8ae86Sav } 34050cc8ae86Sav 34060cc8ae86Sav switch (cmd) { 34070cc8ae86Sav case MCI_CE: 34080cc8ae86Sav mc_inject_error(MC_INJECT_INTERMITTENT_CE, pa, 34090cc8ae86Sav flags); 34100cc8ae86Sav break; 34110cc8ae86Sav case MCI_PERM_CE: 34120cc8ae86Sav mc_inject_error(MC_INJECT_PERMANENT_CE, pa, 34130cc8ae86Sav flags); 34140cc8ae86Sav break; 34150cc8ae86Sav case MCI_UE: 34160cc8ae86Sav mc_inject_error(MC_INJECT_UE, pa, 34170cc8ae86Sav flags); 34180cc8ae86Sav break; 34190cc8ae86Sav case MCI_M_CE: 34200cc8ae86Sav mc_inject_error(MC_INJECT_INTERMITTENT_MCE, pa, 34210cc8ae86Sav flags); 34220cc8ae86Sav break; 34230cc8ae86Sav case MCI_M_PCE: 34240cc8ae86Sav mc_inject_error(MC_INJECT_PERMANENT_MCE, pa, 34250cc8ae86Sav flags); 34260cc8ae86Sav break; 34270cc8ae86Sav case MCI_M_UE: 34280cc8ae86Sav mc_inject_error(MC_INJECT_MUE, pa, 34290cc8ae86Sav flags); 34300cc8ae86Sav break; 34310cc8ae86Sav case MCI_CMP: 34320cc8ae86Sav mc_inject_error(MC_INJECT_CMPE, pa, 34330cc8ae86Sav flags); 34340cc8ae86Sav break; 34350cc8ae86Sav case MCI_NOP: 34360cc8ae86Sav mc_inject_error(MC_INJECT_NOP, pa, flags); 34370cc8ae86Sav break; 34380cc8ae86Sav case MCI_SHOW_ALL: 34390cc8ae86Sav mc_debug_show_all = 1; 34400cc8ae86Sav break; 34410cc8ae86Sav case MCI_SHOW_NONE: 34420cc8ae86Sav mc_debug_show_all = 0; 34430cc8ae86Sav break; 34440cc8ae86Sav case MCI_ALLOC: 34450cc8ae86Sav /* 34460cc8ae86Sav * just allocate some kernel memory and never free it 34470cc8ae86Sav * 512 MB seems to be the maximum size supported. 34480cc8ae86Sav */ 34490cc8ae86Sav cmn_err(CE_NOTE, "Allocating kmem %d MB\n", flags * 512); 34500cc8ae86Sav for (i = 0; i < flags; i++) { 34510cc8ae86Sav buf = kmem_alloc(512 * 1024 * 1024, KM_SLEEP); 34520cc8ae86Sav cmn_err(CE_NOTE, "kmem buf %llx PA %llx\n", 34530cc8ae86Sav (u_longlong_t)buf, (u_longlong_t)va_to_pa(buf)); 34540cc8ae86Sav } 34550cc8ae86Sav break; 34560cc8ae86Sav case MCI_SUSPEND: 34570cc8ae86Sav (void) opl_mc_suspend(); 34580cc8ae86Sav break; 34590cc8ae86Sav case MCI_RESUME: 34600cc8ae86Sav (void) opl_mc_resume(); 34610cc8ae86Sav break; 34620cc8ae86Sav default: 34630cc8ae86Sav rv = ENXIO; 34640cc8ae86Sav } 34650cc8ae86Sav return (rv); 34660cc8ae86Sav } 34670cc8ae86Sav 34680cc8ae86Sav #endif /* DEBUG */ 3469