1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_ERR_IMPL_H 27 #define _SYS_PX_ERR_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Bit Error handling tables: 37 * bit Bit Number 38 * counter Counter for number of errors countered for this bit 39 * err_handler Error Handler Function 40 * erpt_handler Ereport Handler Function 41 * class_name Class Name used for sending ereports for this bit. 42 */ 43 typedef struct px_err_bit_desc { 44 uint_t bit; 45 uint_t counter; 46 int (*err_handler)(); 47 int (*erpt_handler)(); 48 char *class_name; 49 } px_err_bit_desc_t; 50 51 /* 52 * Reg Error handling tables: 53 * 54 * chip_mask mask of chip types supporting this error register 55 * 56 * *intr_mask_p bitmask for enabled interrupts 57 * *log_mask_p bitmask for logged interrupts 58 * *count_mask_p bitmask for counted interrupts 59 * 60 * *err_bit_tbl error bit table 61 * err_bit_keys number of entries in the error bit table. 62 * 63 * reg_bank register bank base 64 * 65 * last_reg last captured register 66 * log_addr interrupt log register offset 67 * enable_addr interrupt enable register offset 68 * status_addr interrupt status register offset 69 * clear_addr interrupt clear register offset 70 * 71 * *msg error messages table 72 */ 73 typedef struct px_err_reg_desc { 74 uint8_t chip_mask; 75 uint64_t *intr_mask_p; 76 uint64_t *log_mask_p; 77 uint64_t *count_mask_p; 78 px_err_bit_desc_t *err_bit_tbl; 79 uint_t err_bit_keys; 80 uint_t reg_bank; 81 uint64_t last_reg; 82 uint32_t log_addr; 83 uint32_t enable_addr; 84 uint32_t status_addr; 85 uint32_t clear_addr; 86 char *msg; 87 } px_err_reg_desc_t; 88 89 /* 90 * Macro to create the error handling forward declaration 91 * 92 * The error handlers examines error, determine the nature of the error 93 * and return error status in terms of PX_FATAL_HW | PX_FATAL_GOS | ... 94 * terminology. 95 */ 96 #define PX_ERR_BIT_HANDLE_DEC(n) int px_err_ ## n ## _handle\ 97 (dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, \ 98 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 99 #define PX_ERR_BIT_HANDLE(n) px_err_ ## n ## _handle 100 101 /* 102 * Macro to create the ereport forward declaration 103 */ 104 #define PX_ERPT_SEND_DEC(n) int px_err_ ## n ## _send_ereport\ 105 (dev_info_t *rpdip, caddr_t csr_base, uint64_t ss_reg, \ 106 ddi_fm_error_t *derr, uint_t bit, char *class_name) 107 #define PX_ERPT_SEND(n) px_err_ ## n ## _send_ereport 108 109 /* 110 * Macro to test for primary vs secondary 111 */ 112 #define PX_ERR_IS_PRI(bit) (bit < 32) 113 114 /* 115 * Predefined error handling functions. 116 */ 117 int px_err_fatal_hw_handle(dev_info_t *rpdip, caddr_t csr_base, 118 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 119 px_err_bit_desc_t *err_bit_descr); 120 int px_err_fatal_gos_handle(dev_info_t *rpdip, caddr_t csr_base, 121 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 122 px_err_bit_desc_t *err_bit_descr); 123 int px_err_fatal_stuck_handle(dev_info_t *rpdip, caddr_t csr_base, 124 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 125 px_err_bit_desc_t *err_bit_descr); 126 int px_err_fatal_sw_handle(dev_info_t *rpdip, caddr_t csr_base, 127 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 128 px_err_bit_desc_t *err_bit_descr); 129 int px_err_non_fatal_handle(dev_info_t *rpdip, caddr_t csr_base, 130 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 131 px_err_bit_desc_t *err_bit_descr); 132 int px_err_ok_handle(dev_info_t *rpdip, caddr_t csr_base, 133 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 134 px_err_bit_desc_t *err_bit_descr); 135 int px_err_unknown_handle(dev_info_t *rpdip, caddr_t csr_base, 136 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 137 px_err_bit_desc_t *err_bit_descr); 138 139 /* 140 * Predefined ereport functions 141 */ 142 PX_ERPT_SEND_DEC(do_not); 143 144 145 /* 146 * JBC/UBC error handling and ereport forward declarations 147 */ 148 149 #define PX_ERR_JBC_CLASS(n) PCIEX_FIRE "." FIRE_JBC_ ## n 150 #define PX_ERR_UBC_CLASS(n) PCIEX_OBERON "." FIRE_UBC_ ## n 151 152 /* 153 * Fire JBC error Handling Forward Declarations 154 * the must-panic type errors such as PX_FATAL_GOS or 155 * post-reset-diagnosed type error such as PX_FATAL_HW 156 * are not furthur diagnosed here because there is no 157 * justification to find out more as immediate error 158 * handling. FMA DE will do the post analysis. 159 */ 160 int px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 161 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 162 px_err_bit_desc_t *err_bit_descr); 163 int px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 164 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 165 px_err_bit_desc_t *err_bit_descr); 166 int px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 167 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 168 px_err_bit_desc_t *err_bit_descr); 169 int px_err_jbc_safe_acc_handle(dev_info_t *rpdip, caddr_t csr_base, 170 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 171 px_err_bit_desc_t *err_bit_descr); 172 int px_err_jbc_csr_handle(dev_info_t *rpdip, caddr_t csr_base, 173 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 174 px_err_bit_desc_t *err_bit_descr); 175 176 /* Fire JBC error ereport Forward Declarations */ 177 PX_ERPT_SEND_DEC(jbc_fatal); 178 PX_ERPT_SEND_DEC(jbc_merge); 179 PX_ERPT_SEND_DEC(jbc_in); 180 PX_ERPT_SEND_DEC(jbc_out); 181 PX_ERPT_SEND_DEC(jbc_odcd); 182 PX_ERPT_SEND_DEC(jbc_idc); 183 PX_ERPT_SEND_DEC(jbc_csr); 184 185 /* Oberon UBC error ereport Forward Declarations */ 186 PX_ERPT_SEND_DEC(ubc_fatal); 187 188 189 /* 190 * DMC error handling and ereport forward declarations 191 */ 192 193 #define PX_ERR_DMC_CLASS(n) PCIEX_FIRE "." FIRE_DMC_ ## n 194 195 /* Fire Bit Error Handling Forward Declarations */ 196 int px_err_imu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 197 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 198 px_err_bit_desc_t *err_bit_descr); 199 int px_err_imu_pme_handle(dev_info_t *rpdip, caddr_t csr_base, 200 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 201 px_err_bit_desc_t *err_bit_descr); 202 int px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 203 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 204 px_err_bit_desc_t *err_bit_descr); 205 int px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 206 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 207 px_err_bit_desc_t *err_bit_descr); 208 int px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 209 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 210 px_err_bit_desc_t *err_bit_descr); 211 int px_err_mmu_tte_cae_handle(dev_info_t *rpdip, caddr_t csr_base, 212 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 213 px_err_bit_desc_t *err_bit_descr); 214 int px_err_mmu_tblwlk_handle(dev_info_t *rpdip, caddr_t csr_base, 215 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 216 px_err_bit_desc_t *err_bit_descr); 217 218 /* Fire Ereport Handling Forward Declarations */ 219 PX_ERPT_SEND_DEC(imu_rds); 220 PX_ERPT_SEND_DEC(imu_scs); 221 PX_ERPT_SEND_DEC(imu); 222 PX_ERPT_SEND_DEC(mmu_tfar_tfsr); 223 PX_ERPT_SEND_DEC(mmu); 224 225 /* 226 * PEC error handling and ereport forward declarations 227 */ 228 229 #define PX_ERR_PEC_CLASS(n) PCIEX_FIRE "." FIRE_PEC_ ## n 230 #define PX_ERR_PEC_OB_CLASS(n) PCIEX_OBERON "." FIRE_PEC_ ## n 231 232 int px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 233 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 234 px_err_bit_desc_t *err_bit_descr); 235 int px_err_tlu_ldn_handle(dev_info_t *rpdip, caddr_t csr_base, 236 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 237 px_err_bit_desc_t *err_bit_descr); 238 239 /* Fire Ereport Handling Forward Declarations */ 240 int px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 241 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 242 px_err_bit_desc_t *err_bit_descr); 243 int px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 244 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 245 px_err_bit_desc_t *err_bit_descr); 246 247 PX_ERPT_SEND_DEC(pec_ilu); 248 PX_ERPT_SEND_DEC(pciex_rx_ue); 249 PX_ERPT_SEND_DEC(pciex_tx_ue); 250 PX_ERPT_SEND_DEC(pciex_rx_tx_ue); 251 PX_ERPT_SEND_DEC(pciex_ue); 252 PX_ERPT_SEND_DEC(pciex_ce); 253 PX_ERPT_SEND_DEC(pciex_rx_oe); 254 PX_ERPT_SEND_DEC(pciex_rx_tx_oe); 255 PX_ERPT_SEND_DEC(pciex_oe); 256 257 #ifdef __cplusplus 258 } 259 #endif 260 261 #endif /* _SYS_PX_ERR_IMPL_H */ 262