1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PX_ERR_IMPL_H 28 #define _SYS_PX_ERR_IMPL_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Bit Error handling tables: 38 * bit Bit Number 39 * counter Counter for number of errors countered for this bit 40 * err_handler Error Handler Function 41 * erpt_handler Ereport Handler Function 42 * class_name Class Name used for sending ereports for this bit. 43 */ 44 typedef struct px_err_bit_desc { 45 uint_t bit; 46 uint_t counter; 47 int (*err_handler)(); 48 int (*erpt_handler)(); 49 char *class_name; 50 } px_err_bit_desc_t; 51 52 /* 53 * Reg Error handling tables: 54 * 55 * enabled enable this register error handler 56 * 57 * *intr_mask_p bitmask for enabled interrupts 58 * *log_mask_p bitmask for logged interrupts 59 * *count_mask_p bitmask for counted interrupts 60 * 61 * *err_bit_tbl error bit table 62 * err_bit_keys number of entries in the error bit table. 63 * 64 * last_reg last captured register 65 * log_addr interrupt log register offset 66 * enable_addr interrupt enable register offset 67 * status_addr interrupt status register offset 68 * clear_addr interrupt clear register offset 69 * 70 * *msg error messages table 71 */ 72 typedef struct px_err_reg_desc { 73 boolean_t enabled; 74 uint64_t *intr_mask_p; 75 uint64_t *log_mask_p; 76 uint64_t *count_mask_p; 77 px_err_bit_desc_t *err_bit_tbl; 78 uint_t err_bit_keys; 79 uint64_t last_reg; 80 uint32_t log_addr; 81 uint32_t enable_addr; 82 uint32_t status_addr; 83 uint32_t clear_addr; 84 char *msg; 85 } px_err_reg_desc_t; 86 87 /* 88 * Macro to create the error handling forward declaration 89 * 90 * The error handlers examines error, determine the nature of the error 91 * and return error status in terms of PX_FATAL_HW | PX_FATAL_GOS | ... 92 * terminology. 93 */ 94 #define PX_ERR_BIT_HANDLE_DEC(n) int px_err_ ## n ## _handle\ 95 (dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, \ 96 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 97 #define PX_ERR_BIT_HANDLE(n) px_err_ ## n ## _handle 98 99 /* 100 * Macro to create the ereport forward declaration 101 */ 102 #define PX_ERPT_SEND_DEC(n) int px_err_ ## n ## _send_ereport\ 103 (dev_info_t *rpdip, caddr_t csr_base, uint64_t ss_reg, \ 104 ddi_fm_error_t *derr, uint_t bit, char *class_name) 105 #define PX_ERPT_SEND(n) px_err_ ## n ## _send_ereport 106 107 /* 108 * Macro to test for primary vs secondary 109 */ 110 #define PX_ERR_IS_PRI(bit) (bit < 32) 111 112 /* 113 * Predefined error handling functions. 114 */ 115 int px_err_fatal_hw_handle(dev_info_t *rpdip, caddr_t csr_base, 116 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 117 px_err_bit_desc_t *err_bit_descr); 118 int px_err_fatal_gos_handle(dev_info_t *rpdip, caddr_t csr_base, 119 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 120 px_err_bit_desc_t *err_bit_descr); 121 int px_err_fatal_stuck_handle(dev_info_t *rpdip, caddr_t csr_base, 122 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 123 px_err_bit_desc_t *err_bit_descr); 124 int px_err_fatal_sw_handle(dev_info_t *rpdip, caddr_t csr_base, 125 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 126 px_err_bit_desc_t *err_bit_descr); 127 int px_err_non_fatal_handle(dev_info_t *rpdip, caddr_t csr_base, 128 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 129 px_err_bit_desc_t *err_bit_descr); 130 int px_err_ok_handle(dev_info_t *rpdip, caddr_t csr_base, 131 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 132 px_err_bit_desc_t *err_bit_descr); 133 int px_err_unknown_handle(dev_info_t *rpdip, caddr_t csr_base, 134 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 135 px_err_bit_desc_t *err_bit_descr); 136 137 /* 138 * Predefined ereport functions 139 */ 140 PX_ERPT_SEND_DEC(do_not); 141 142 143 /* 144 * JBC error handling and ereport forward declarations 145 */ 146 147 #define PX_ERR_JBC_CLASS(n) PCIEX_FIRE "." FIRE_JBC_ ## n 148 149 /* 150 * Fire JBC error Handling Forward Declarations 151 * the must-panic type errors such as PX_FATAL_GOS or 152 * post-reset-diagnosed type error such as PX_FATAL_HW 153 * are not furthur diagnosed here because there is no 154 * justification to find out more as immediate error 155 * handling. FMA DE will do the post analysis. 156 */ 157 int px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 158 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 159 px_err_bit_desc_t *err_bit_descr); 160 int px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 161 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 162 px_err_bit_desc_t *err_bit_descr); 163 int px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 164 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 165 px_err_bit_desc_t *err_bit_descr); 166 int px_err_jbc_csr_handle(dev_info_t *rpdip, caddr_t csr_base, 167 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 168 px_err_bit_desc_t *err_bit_descr); 169 170 /* Fire JBC error ereport Forward Declarations */ 171 PX_ERPT_SEND_DEC(jbc_fatal); 172 PX_ERPT_SEND_DEC(jbc_merge); 173 PX_ERPT_SEND_DEC(jbc_in); 174 PX_ERPT_SEND_DEC(jbc_out); 175 PX_ERPT_SEND_DEC(jbc_odcd); 176 PX_ERPT_SEND_DEC(jbc_idc); 177 PX_ERPT_SEND_DEC(jbc_csr); 178 179 180 /* 181 * DMC error handling and ereport forward declarations 182 */ 183 184 #define PX_ERR_DMC_CLASS(n) PCIEX_FIRE "." FIRE_DMC_ ## n 185 186 /* Fire Bit Error Handling Forward Declarations */ 187 int px_err_imu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 188 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 189 px_err_bit_desc_t *err_bit_descr); 190 int px_err_imu_pme_handle(dev_info_t *rpdip, caddr_t csr_base, 191 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 192 px_err_bit_desc_t *err_bit_descr); 193 int px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 194 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 195 px_err_bit_desc_t *err_bit_descr); 196 int px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 197 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 198 px_err_bit_desc_t *err_bit_descr); 199 int px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 200 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 201 px_err_bit_desc_t *err_bit_descr); 202 int px_err_mmu_tte_cae_handle(dev_info_t *rpdip, caddr_t csr_base, 203 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 204 px_err_bit_desc_t *err_bit_descr); 205 int px_err_mmu_tblwlk_handle(dev_info_t *rpdip, caddr_t csr_base, 206 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 207 px_err_bit_desc_t *err_bit_descr); 208 209 /* Fire Ereport Handling Forward Declarations */ 210 PX_ERPT_SEND_DEC(imu_rds); 211 PX_ERPT_SEND_DEC(imu_scs); 212 PX_ERPT_SEND_DEC(imu); 213 PX_ERPT_SEND_DEC(mmu_tfar_tfsr); 214 PX_ERPT_SEND_DEC(mmu); 215 216 /* 217 * PEC error handling and ereport forward declarations 218 */ 219 220 #define PX_ERR_PEC_CLASS(n) PCIEX_FIRE "." FIRE_PEC_ ## n 221 222 int px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 223 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 224 px_err_bit_desc_t *err_bit_descr); 225 226 /* Fire Ereport Handling Forward Declarations */ 227 int px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 228 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 229 px_err_bit_desc_t *err_bit_descr); 230 int px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 231 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 232 px_err_bit_desc_t *err_bit_descr); 233 234 PX_ERPT_SEND_DEC(pec_ilu); 235 PX_ERPT_SEND_DEC(pciex_rx_ue); 236 PX_ERPT_SEND_DEC(pciex_tx_ue); 237 PX_ERPT_SEND_DEC(pciex_rx_tx_ue); 238 PX_ERPT_SEND_DEC(pciex_ue); 239 PX_ERPT_SEND_DEC(pciex_ce); 240 PX_ERPT_SEND_DEC(pciex_rx_oe); 241 PX_ERPT_SEND_DEC(pciex_rx_tx_oe); 242 PX_ERPT_SEND_DEC(pciex_oe); 243 PX_ERPT_SEND_DEC(pciex_lup); 244 PX_ERPT_SEND_DEC(pciex_ldn); 245 246 #ifdef __cplusplus 247 } 248 #endif 249 250 #endif /* _SYS_PX_ERR_IMPL_H */ 251