1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_ERR_IMPL_H 27 #define _SYS_PX_ERR_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Bit Error handling tables: 37 * bit Bit Number 38 * counter Counter for number of errors countered for this bit 39 * err_handler Error Handler Function 40 * erpt_handler Ereport Handler Function 41 * class_name Class Name used for sending ereports for this bit. 42 */ 43 typedef struct px_err_bit_desc { 44 uint_t bit; 45 uint_t counter; 46 int (*err_handler)(); 47 int (*erpt_handler)(); 48 char *class_name; 49 } px_err_bit_desc_t; 50 51 /* 52 * Reg Error handling tables: 53 * 54 * enabled enable this register error handler 55 * 56 * *intr_mask_p bitmask for enabled interrupts 57 * *log_mask_p bitmask for logged interrupts 58 * *count_mask_p bitmask for counted interrupts 59 * 60 * *err_bit_tbl error bit table 61 * err_bit_keys number of entries in the error bit table. 62 * 63 * last_reg last captured register 64 * log_addr interrupt log register offset 65 * enable_addr interrupt enable register offset 66 * status_addr interrupt status register offset 67 * clear_addr interrupt clear register offset 68 * 69 * *msg error messages table 70 */ 71 typedef struct px_err_reg_desc { 72 boolean_t enabled; 73 uint64_t *intr_mask_p; 74 uint64_t *log_mask_p; 75 uint64_t *count_mask_p; 76 px_err_bit_desc_t *err_bit_tbl; 77 uint_t err_bit_keys; 78 uint64_t last_reg; 79 uint32_t log_addr; 80 uint32_t enable_addr; 81 uint32_t status_addr; 82 uint32_t clear_addr; 83 char *msg; 84 } px_err_reg_desc_t; 85 86 /* 87 * Macro to test for the JBC or UBC error id. 88 */ 89 #define PX_ERR_XBC(id) (((id) == PX_ERR_JBC)||((id) == PX_ERR_UBC)) 90 91 /* 92 * Macro to create the error handling forward declaration 93 * 94 * The error handlers examines error, determine the nature of the error 95 * and return error status in terms of PX_FATAL_HW | PX_FATAL_GOS | ... 96 * terminology. 97 */ 98 #define PX_ERR_BIT_HANDLE_DEC(n) int px_err_ ## n ## _handle\ 99 (dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, \ 100 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 101 #define PX_ERR_BIT_HANDLE(n) px_err_ ## n ## _handle 102 103 /* 104 * Macro to create the ereport forward declaration 105 */ 106 #define PX_ERPT_SEND_DEC(n) int px_err_ ## n ## _send_ereport\ 107 (dev_info_t *rpdip, caddr_t csr_base, uint64_t ss_reg, \ 108 ddi_fm_error_t *derr, uint_t bit, char *class_name) 109 #define PX_ERPT_SEND(n) px_err_ ## n ## _send_ereport 110 111 /* 112 * Macro to test for primary vs secondary 113 */ 114 #define PX_ERR_IS_PRI(bit) (bit < 32) 115 116 /* 117 * Predefined error handling functions. 118 */ 119 int px_err_fatal_hw_handle(dev_info_t *rpdip, caddr_t csr_base, 120 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 121 px_err_bit_desc_t *err_bit_descr); 122 int px_err_fatal_gos_handle(dev_info_t *rpdip, caddr_t csr_base, 123 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 124 px_err_bit_desc_t *err_bit_descr); 125 int px_err_fatal_stuck_handle(dev_info_t *rpdip, caddr_t csr_base, 126 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 127 px_err_bit_desc_t *err_bit_descr); 128 int px_err_fatal_sw_handle(dev_info_t *rpdip, caddr_t csr_base, 129 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 130 px_err_bit_desc_t *err_bit_descr); 131 int px_err_non_fatal_handle(dev_info_t *rpdip, caddr_t csr_base, 132 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 133 px_err_bit_desc_t *err_bit_descr); 134 int px_err_ok_handle(dev_info_t *rpdip, caddr_t csr_base, 135 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 136 px_err_bit_desc_t *err_bit_descr); 137 int px_err_unknown_handle(dev_info_t *rpdip, caddr_t csr_base, 138 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 139 px_err_bit_desc_t *err_bit_descr); 140 141 /* 142 * Predefined ereport functions 143 */ 144 PX_ERPT_SEND_DEC(do_not); 145 146 147 /* 148 * JBC/UBC error handling and ereport forward declarations 149 */ 150 151 #define PX_ERR_JBC_CLASS(n) PCIEX_FIRE "." FIRE_JBC_ ## n 152 #define PX_ERR_UBC_CLASS(n) PCIEX_OBERON "." FIRE_UBC_ ## n 153 154 /* 155 * Fire JBC error Handling Forward Declarations 156 * the must-panic type errors such as PX_FATAL_GOS or 157 * post-reset-diagnosed type error such as PX_FATAL_HW 158 * are not furthur diagnosed here because there is no 159 * justification to find out more as immediate error 160 * handling. FMA DE will do the post analysis. 161 */ 162 int px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 163 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 164 px_err_bit_desc_t *err_bit_descr); 165 int px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 166 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 167 px_err_bit_desc_t *err_bit_descr); 168 int px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 169 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 170 px_err_bit_desc_t *err_bit_descr); 171 int px_err_jbc_csr_handle(dev_info_t *rpdip, caddr_t csr_base, 172 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 173 px_err_bit_desc_t *err_bit_descr); 174 175 /* Fire JBC error ereport Forward Declarations */ 176 PX_ERPT_SEND_DEC(jbc_fatal); 177 PX_ERPT_SEND_DEC(jbc_merge); 178 PX_ERPT_SEND_DEC(jbc_in); 179 PX_ERPT_SEND_DEC(jbc_out); 180 PX_ERPT_SEND_DEC(jbc_odcd); 181 PX_ERPT_SEND_DEC(jbc_idc); 182 PX_ERPT_SEND_DEC(jbc_csr); 183 184 /* Oberon UBC error ereport Forward Declarations */ 185 PX_ERPT_SEND_DEC(ubc_fatal); 186 187 188 /* 189 * DMC error handling and ereport forward declarations 190 */ 191 192 #define PX_ERR_DMC_CLASS(n) PCIEX_FIRE "." FIRE_DMC_ ## n 193 194 /* Fire Bit Error Handling Forward Declarations */ 195 int px_err_imu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 196 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 197 px_err_bit_desc_t *err_bit_descr); 198 int px_err_imu_pme_handle(dev_info_t *rpdip, caddr_t csr_base, 199 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 200 px_err_bit_desc_t *err_bit_descr); 201 int px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 202 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 203 px_err_bit_desc_t *err_bit_descr); 204 int px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 205 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 206 px_err_bit_desc_t *err_bit_descr); 207 int px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 208 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 209 px_err_bit_desc_t *err_bit_descr); 210 int px_err_mmu_tte_cae_handle(dev_info_t *rpdip, caddr_t csr_base, 211 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 212 px_err_bit_desc_t *err_bit_descr); 213 int px_err_mmu_tblwlk_handle(dev_info_t *rpdip, caddr_t csr_base, 214 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 215 px_err_bit_desc_t *err_bit_descr); 216 217 /* Fire Ereport Handling Forward Declarations */ 218 PX_ERPT_SEND_DEC(imu_rds); 219 PX_ERPT_SEND_DEC(imu_scs); 220 PX_ERPT_SEND_DEC(imu); 221 PX_ERPT_SEND_DEC(mmu_tfar_tfsr); 222 PX_ERPT_SEND_DEC(mmu); 223 224 /* 225 * PEC error handling and ereport forward declarations 226 */ 227 228 #define PX_ERR_PEC_CLASS(n) PCIEX_FIRE "." FIRE_PEC_ ## n 229 #define PX_ERR_PEC_OB_CLASS(n) PCIEX_OBERON "." FIRE_PEC_ ## n 230 231 int px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 232 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 233 px_err_bit_desc_t *err_bit_descr); 234 int px_err_tlu_ldn_handle(dev_info_t *rpdip, caddr_t csr_base, 235 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 236 px_err_bit_desc_t *err_bit_descr); 237 238 /* Fire Ereport Handling Forward Declarations */ 239 int px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 240 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 241 px_err_bit_desc_t *err_bit_descr); 242 int px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 243 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 244 px_err_bit_desc_t *err_bit_descr); 245 246 PX_ERPT_SEND_DEC(pec_ilu); 247 PX_ERPT_SEND_DEC(pciex_rx_ue); 248 PX_ERPT_SEND_DEC(pciex_tx_ue); 249 PX_ERPT_SEND_DEC(pciex_rx_tx_ue); 250 PX_ERPT_SEND_DEC(pciex_ue); 251 PX_ERPT_SEND_DEC(pciex_ce); 252 PX_ERPT_SEND_DEC(pciex_rx_oe); 253 PX_ERPT_SEND_DEC(pciex_rx_tx_oe); 254 PX_ERPT_SEND_DEC(pciex_oe); 255 256 #ifdef __cplusplus 257 } 258 #endif 259 260 #endif /* _SYS_PX_ERR_IMPL_H */ 261