1f8d2de6bSjchu /* 2f8d2de6bSjchu * CDDL HEADER START 3f8d2de6bSjchu * 4f8d2de6bSjchu * The contents of this file are subject to the terms of the 525cf1a30Sjl * Common Development and Distribution License (the "License"). 625cf1a30Sjl * You may not use this file except in compliance with the License. 7f8d2de6bSjchu * 8f8d2de6bSjchu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9f8d2de6bSjchu * or http://www.opensolaris.org/os/licensing. 10f8d2de6bSjchu * See the License for the specific language governing permissions 11f8d2de6bSjchu * and limitations under the License. 12f8d2de6bSjchu * 13f8d2de6bSjchu * When distributing Covered Code, include this CDDL HEADER in each 14f8d2de6bSjchu * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15f8d2de6bSjchu * If applicable, add the following below this CDDL HEADER, with the 16f8d2de6bSjchu * fields enclosed by brackets "[]" replaced with your own identifying 17f8d2de6bSjchu * information: Portions Copyright [yyyy] [name of copyright owner] 18f8d2de6bSjchu * 19f8d2de6bSjchu * CDDL HEADER END 20f8d2de6bSjchu */ 21f8d2de6bSjchu /* 2225cf1a30Sjl * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23f8d2de6bSjchu * Use is subject to license terms. 24f8d2de6bSjchu */ 25f8d2de6bSjchu 26f8d2de6bSjchu #ifndef _SYS_PX_ERR_IMPL_H 27f8d2de6bSjchu #define _SYS_PX_ERR_IMPL_H 28f8d2de6bSjchu 29f8d2de6bSjchu #pragma ident "%Z%%M% %I% %E% SMI" 30f8d2de6bSjchu 31f8d2de6bSjchu #ifdef __cplusplus 32f8d2de6bSjchu extern "C" { 33f8d2de6bSjchu #endif 34f8d2de6bSjchu 35f8d2de6bSjchu /* 36f8d2de6bSjchu * Bit Error handling tables: 37f8d2de6bSjchu * bit Bit Number 38f8d2de6bSjchu * counter Counter for number of errors countered for this bit 39f8d2de6bSjchu * err_handler Error Handler Function 40f8d2de6bSjchu * erpt_handler Ereport Handler Function 41f8d2de6bSjchu * class_name Class Name used for sending ereports for this bit. 42f8d2de6bSjchu */ 43f8d2de6bSjchu typedef struct px_err_bit_desc { 44f8d2de6bSjchu uint_t bit; 45f8d2de6bSjchu uint_t counter; 46f8d2de6bSjchu int (*err_handler)(); 47f8d2de6bSjchu int (*erpt_handler)(); 48f8d2de6bSjchu char *class_name; 49f8d2de6bSjchu } px_err_bit_desc_t; 50f8d2de6bSjchu 51f8d2de6bSjchu /* 52f8d2de6bSjchu * Reg Error handling tables: 53f8d2de6bSjchu * 5408a74c0dSschwartz * chip_mask mask of chip types supporting this error register 55f8d2de6bSjchu * 56f8d2de6bSjchu * *intr_mask_p bitmask for enabled interrupts 57f8d2de6bSjchu * *log_mask_p bitmask for logged interrupts 58f8d2de6bSjchu * *count_mask_p bitmask for counted interrupts 59f8d2de6bSjchu * 60f8d2de6bSjchu * *err_bit_tbl error bit table 61f8d2de6bSjchu * err_bit_keys number of entries in the error bit table. 62f8d2de6bSjchu * 6308a74c0dSschwartz * reg_bank register bank base 6408a74c0dSschwartz * 65f8d2de6bSjchu * last_reg last captured register 66f8d2de6bSjchu * log_addr interrupt log register offset 67f8d2de6bSjchu * enable_addr interrupt enable register offset 68f8d2de6bSjchu * status_addr interrupt status register offset 69f8d2de6bSjchu * clear_addr interrupt clear register offset 70f8d2de6bSjchu * 71f8d2de6bSjchu * *msg error messages table 72f8d2de6bSjchu */ 73f8d2de6bSjchu typedef struct px_err_reg_desc { 7408a74c0dSschwartz uint8_t chip_mask; 75f8d2de6bSjchu uint64_t *intr_mask_p; 76f8d2de6bSjchu uint64_t *log_mask_p; 77f8d2de6bSjchu uint64_t *count_mask_p; 78f8d2de6bSjchu px_err_bit_desc_t *err_bit_tbl; 79f8d2de6bSjchu uint_t err_bit_keys; 8008a74c0dSschwartz uint_t reg_bank; 81f8d2de6bSjchu uint64_t last_reg; 82f8d2de6bSjchu uint32_t log_addr; 83f8d2de6bSjchu uint32_t enable_addr; 84f8d2de6bSjchu uint32_t status_addr; 85f8d2de6bSjchu uint32_t clear_addr; 86f8d2de6bSjchu char *msg; 87f8d2de6bSjchu } px_err_reg_desc_t; 88f8d2de6bSjchu 89f8d2de6bSjchu /* 90f8d2de6bSjchu * Macro to create the error handling forward declaration 91f8d2de6bSjchu * 92f8d2de6bSjchu * The error handlers examines error, determine the nature of the error 93*bf8fc234Set * and return error status in terms of PX_HW_RESET | PX_PANIC | ... 94f8d2de6bSjchu * terminology. 95f8d2de6bSjchu */ 96f8d2de6bSjchu #define PX_ERR_BIT_HANDLE_DEC(n) int px_err_ ## n ## _handle\ 97f8d2de6bSjchu (dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, \ 98f8d2de6bSjchu px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 99f8d2de6bSjchu #define PX_ERR_BIT_HANDLE(n) px_err_ ## n ## _handle 100f8d2de6bSjchu 1018bc7d88aSet /* 1028bc7d88aSet * Macro to create the ereport forward declaration 1038bc7d88aSet */ 1048bc7d88aSet #define PX_ERPT_SEND_DEC(n) int px_err_ ## n ## _send_ereport\ 1058bc7d88aSet (dev_info_t *rpdip, caddr_t csr_base, uint64_t ss_reg, \ 1068c334881Sjchu ddi_fm_error_t *derr, uint_t bit, char *class_name) 1078bc7d88aSet #define PX_ERPT_SEND(n) px_err_ ## n ## _send_ereport 1088bc7d88aSet 1098c334881Sjchu /* 1108c334881Sjchu * Macro to test for primary vs secondary 1118c334881Sjchu */ 1128c334881Sjchu #define PX_ERR_IS_PRI(bit) (bit < 32) 1138c334881Sjchu 114f8d2de6bSjchu /* 115f8d2de6bSjchu * Predefined error handling functions. 116f8d2de6bSjchu */ 117*bf8fc234Set void px_err_log_handle(dev_info_t *rpdip, px_err_reg_desc_t *err_reg_descr, 118*bf8fc234Set px_err_bit_desc_t *err_bit_descr, char *msg); 119*bf8fc234Set int px_err_hw_reset_handle(dev_info_t *rpdip, caddr_t csr_base, 120f8d2de6bSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 121f8d2de6bSjchu px_err_bit_desc_t *err_bit_descr); 122*bf8fc234Set int px_err_panic_handle(dev_info_t *rpdip, caddr_t csr_base, 123f8d2de6bSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 124f8d2de6bSjchu px_err_bit_desc_t *err_bit_descr); 125*bf8fc234Set int px_err_protected_handle(dev_info_t *rpdip, caddr_t csr_base, 126f8d2de6bSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 127f8d2de6bSjchu px_err_bit_desc_t *err_bit_descr); 128*bf8fc234Set int px_err_no_panic_handle(dev_info_t *rpdip, caddr_t csr_base, 129f8d2de6bSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 130f8d2de6bSjchu px_err_bit_desc_t *err_bit_descr); 131*bf8fc234Set int px_err_no_error_handle(dev_info_t *rpdip, caddr_t csr_base, 132f8d2de6bSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 133f8d2de6bSjchu px_err_bit_desc_t *err_bit_descr); 134f8d2de6bSjchu 135f8d2de6bSjchu /* 1368bc7d88aSet * Predefined ereport functions 137f8d2de6bSjchu */ 1388bc7d88aSet PX_ERPT_SEND_DEC(do_not); 139f8d2de6bSjchu 140f8d2de6bSjchu 141f8d2de6bSjchu /* 14225cf1a30Sjl * JBC/UBC error handling and ereport forward declarations 143f8d2de6bSjchu */ 144f8d2de6bSjchu 145f8d2de6bSjchu #define PX_ERR_JBC_CLASS(n) PCIEX_FIRE "." FIRE_JBC_ ## n 14625cf1a30Sjl #define PX_ERR_UBC_CLASS(n) PCIEX_OBERON "." FIRE_UBC_ ## n 147f8d2de6bSjchu 148f8d2de6bSjchu /* 149f8d2de6bSjchu * Fire JBC error Handling Forward Declarations 150*bf8fc234Set * the must-panic type errors such as PX_PANIC or 151*bf8fc234Set * post-reset-diagnosed type error such as PX_HW_RESET 152f8d2de6bSjchu * are not furthur diagnosed here because there is no 153f8d2de6bSjchu * justification to find out more as immediate error 154f8d2de6bSjchu * handling. FMA DE will do the post analysis. 155f8d2de6bSjchu */ 156f8d2de6bSjchu int px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 157f8d2de6bSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 158f8d2de6bSjchu px_err_bit_desc_t *err_bit_descr); 159f8d2de6bSjchu int px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 160f8d2de6bSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 161f8d2de6bSjchu px_err_bit_desc_t *err_bit_descr); 162f8d2de6bSjchu int px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 163f8d2de6bSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 164f8d2de6bSjchu px_err_bit_desc_t *err_bit_descr); 165f0a73f04Sschwartz int px_err_jbc_safe_acc_handle(dev_info_t *rpdip, caddr_t csr_base, 166f0a73f04Sschwartz ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 167f0a73f04Sschwartz px_err_bit_desc_t *err_bit_descr); 168f8d2de6bSjchu 169f8d2de6bSjchu /* Fire JBC error ereport Forward Declarations */ 170f8d2de6bSjchu PX_ERPT_SEND_DEC(jbc_fatal); 171f8d2de6bSjchu PX_ERPT_SEND_DEC(jbc_merge); 172f8d2de6bSjchu PX_ERPT_SEND_DEC(jbc_in); 173f8d2de6bSjchu PX_ERPT_SEND_DEC(jbc_out); 174f8d2de6bSjchu PX_ERPT_SEND_DEC(jbc_odcd); 175f8d2de6bSjchu PX_ERPT_SEND_DEC(jbc_idc); 176f8d2de6bSjchu PX_ERPT_SEND_DEC(jbc_csr); 177f8d2de6bSjchu 17825cf1a30Sjl /* Oberon UBC error ereport Forward Declarations */ 17925cf1a30Sjl PX_ERPT_SEND_DEC(ubc_fatal); 18025cf1a30Sjl 181f8d2de6bSjchu 182f8d2de6bSjchu /* 183f8d2de6bSjchu * DMC error handling and ereport forward declarations 184f8d2de6bSjchu */ 185f8d2de6bSjchu 186f8d2de6bSjchu #define PX_ERR_DMC_CLASS(n) PCIEX_FIRE "." FIRE_DMC_ ## n 187f8d2de6bSjchu 188f8d2de6bSjchu /* Fire Bit Error Handling Forward Declarations */ 189f8d2de6bSjchu int px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 190f8d2de6bSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 191f8d2de6bSjchu px_err_bit_desc_t *err_bit_descr); 192f8d2de6bSjchu int px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 193f8d2de6bSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 194f8d2de6bSjchu px_err_bit_desc_t *err_bit_descr); 195f8d2de6bSjchu int px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 196f8d2de6bSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 197f8d2de6bSjchu px_err_bit_desc_t *err_bit_descr); 198*bf8fc234Set int px_err_mmu_parity_handle(dev_info_t *rpdip, caddr_t csr_base, 199f8d2de6bSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 200f8d2de6bSjchu px_err_bit_desc_t *err_bit_descr); 201f8d2de6bSjchu 202f8d2de6bSjchu /* Fire Ereport Handling Forward Declarations */ 203f8d2de6bSjchu PX_ERPT_SEND_DEC(imu_rds); 204f8d2de6bSjchu PX_ERPT_SEND_DEC(imu_scs); 205f8d2de6bSjchu PX_ERPT_SEND_DEC(imu); 206f8d2de6bSjchu PX_ERPT_SEND_DEC(mmu_tfar_tfsr); 207f8d2de6bSjchu PX_ERPT_SEND_DEC(mmu); 208f8d2de6bSjchu 209f8d2de6bSjchu /* 210f8d2de6bSjchu * PEC error handling and ereport forward declarations 211f8d2de6bSjchu */ 212f8d2de6bSjchu 213f8d2de6bSjchu #define PX_ERR_PEC_CLASS(n) PCIEX_FIRE "." FIRE_PEC_ ## n 21425cf1a30Sjl #define PX_ERR_PEC_OB_CLASS(n) PCIEX_OBERON "." FIRE_PEC_ ## n 215f8d2de6bSjchu 216*bf8fc234Set int px_err_wuc_ruc_handle(dev_info_t *rpdip, caddr_t csr_base, 217*bf8fc234Set ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 218*bf8fc234Set px_err_bit_desc_t *err_bit_descr); 2191a887b2eSjchu int px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 2201a887b2eSjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 2211a887b2eSjchu px_err_bit_desc_t *err_bit_descr); 222f9721e07Sjchu int px_err_tlu_ldn_handle(dev_info_t *rpdip, caddr_t csr_base, 223f9721e07Sjchu ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 224f9721e07Sjchu px_err_bit_desc_t *err_bit_descr); 2251a887b2eSjchu 226f8d2de6bSjchu /* Fire Ereport Handling Forward Declarations */ 2278bc7d88aSet int px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 2288bc7d88aSet ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 2298bc7d88aSet px_err_bit_desc_t *err_bit_descr); 2308bc7d88aSet int px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 2318bc7d88aSet ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 2328bc7d88aSet px_err_bit_desc_t *err_bit_descr); 2338bc7d88aSet 234f8d2de6bSjchu PX_ERPT_SEND_DEC(pec_ilu); 235f8d2de6bSjchu PX_ERPT_SEND_DEC(pciex_rx_ue); 236f8d2de6bSjchu PX_ERPT_SEND_DEC(pciex_tx_ue); 237f8d2de6bSjchu PX_ERPT_SEND_DEC(pciex_rx_tx_ue); 238f8d2de6bSjchu PX_ERPT_SEND_DEC(pciex_ue); 239f8d2de6bSjchu PX_ERPT_SEND_DEC(pciex_ce); 240f8d2de6bSjchu PX_ERPT_SEND_DEC(pciex_rx_oe); 241f8d2de6bSjchu PX_ERPT_SEND_DEC(pciex_rx_tx_oe); 242f8d2de6bSjchu PX_ERPT_SEND_DEC(pciex_oe); 243f8d2de6bSjchu 244f8d2de6bSjchu #ifdef __cplusplus 245f8d2de6bSjchu } 246f8d2de6bSjchu #endif 247f8d2de6bSjchu 248f8d2de6bSjchu #endif /* _SYS_PX_ERR_IMPL_H */ 249