1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * sun4u Fire Error Handling 31 */ 32 33 #include <sys/types.h> 34 #include <sys/ddi.h> 35 #include <sys/sunddi.h> 36 #include <sys/fm/protocol.h> 37 #include <sys/fm/util.h> 38 #include <sys/pcie.h> 39 #include <sys/pcie_impl.h> 40 #include "px_obj.h" 41 #include <px_regs.h> 42 #include <px_csr.h> 43 #include <sys/membar.h> 44 #include "pcie_pwr.h" 45 #include "px_lib4u.h" 46 #include "px_err.h" 47 #include "px_err_impl.h" 48 49 /* 50 * JBC error bit table 51 */ 52 #define JBC_BIT_DESC(bit, hdl, erpt) \ 53 JBC_INTERRUPT_STATUS_ ## bit ## _P, \ 54 0, \ 55 PX_ERR_BIT_HANDLE(hdl), \ 56 PX_ERPT_SEND(erpt), \ 57 PX_ERR_JBC_CLASS(bit) 58 px_err_bit_desc_t px_err_cb_tbl[] = { 59 /* JBC FATAL - see io erpt doc, section 1.1 */ 60 { JBC_BIT_DESC(MB_PEA, fatal_hw, jbc_fatal) }, 61 { JBC_BIT_DESC(CPE, fatal_hw, jbc_fatal) }, 62 { JBC_BIT_DESC(APE, fatal_hw, jbc_fatal) }, 63 { JBC_BIT_DESC(PIO_CPE, fatal_hw, jbc_fatal) }, 64 { JBC_BIT_DESC(JTCEEW, fatal_hw, jbc_fatal) }, 65 { JBC_BIT_DESC(JTCEEI, fatal_hw, jbc_fatal) }, 66 { JBC_BIT_DESC(JTCEER, fatal_hw, jbc_fatal) }, 67 68 /* JBC MERGE - see io erpt doc, section 1.2 */ 69 { JBC_BIT_DESC(MB_PER, jbc_merge, jbc_merge) }, 70 { JBC_BIT_DESC(MB_PEW, jbc_merge, jbc_merge) }, 71 72 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 73 { JBC_BIT_DESC(UE_ASYN, fatal_gos, jbc_in) }, 74 { JBC_BIT_DESC(CE_ASYN, jbc_jbusint_in, jbc_in) }, 75 { JBC_BIT_DESC(JTE, fatal_gos, jbc_in) }, 76 { JBC_BIT_DESC(JBE, jbc_jbusint_in, jbc_in) }, 77 { JBC_BIT_DESC(JUE, jbc_jbusint_in, jbc_in) }, 78 { JBC_BIT_DESC(ICISE, fatal_gos, jbc_in) }, 79 { JBC_BIT_DESC(WR_DPE, jbc_jbusint_in, jbc_in) }, 80 { JBC_BIT_DESC(RD_DPE, jbc_jbusint_in, jbc_in) }, 81 { JBC_BIT_DESC(ILL_BMW, jbc_jbusint_in, jbc_in) }, 82 { JBC_BIT_DESC(ILL_BMR, jbc_jbusint_in, jbc_in) }, 83 { JBC_BIT_DESC(BJC, jbc_jbusint_in, jbc_in) }, 84 85 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 86 { JBC_BIT_DESC(IJP, fatal_gos, jbc_out) }, 87 88 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 89 { JBC_BIT_DESC(PIO_UNMAP_RD, jbc_dmcint_odcd, jbc_odcd) }, 90 { JBC_BIT_DESC(ILL_ACC_RD, jbc_dmcint_odcd, jbc_odcd) }, 91 { JBC_BIT_DESC(PIO_UNMAP, jbc_dmcint_odcd, jbc_odcd) }, 92 { JBC_BIT_DESC(PIO_DPE, jbc_dmcint_odcd, jbc_odcd) }, 93 { JBC_BIT_DESC(PIO_CPE, non_fatal, jbc_odcd) }, 94 { JBC_BIT_DESC(ILL_ACC, jbc_dmcint_odcd, jbc_odcd) }, 95 96 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 97 { JBC_BIT_DESC(UNSOL_RD, non_fatal, jbc_idc) }, 98 { JBC_BIT_DESC(UNSOL_INTR, non_fatal, jbc_idc) }, 99 100 /* JBC CSR - see io erpt doc, section 1.7 */ 101 { JBC_BIT_DESC(EBUS_TO, jbc_csr, jbc_csr) } 102 }; 103 104 #define px_err_cb_keys \ 105 (sizeof (px_err_cb_tbl)) / (sizeof (px_err_bit_desc_t)) 106 107 /* 108 * DMC error bit tables 109 */ 110 #define IMU_BIT_DESC(bit, hdl, erpt) \ 111 IMU_INTERRUPT_STATUS_ ## bit ## _P, \ 112 0, \ 113 PX_ERR_BIT_HANDLE(hdl), \ 114 PX_ERPT_SEND(erpt), \ 115 PX_ERR_DMC_CLASS(bit) 116 px_err_bit_desc_t px_err_imu_tbl[] = { 117 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 118 { IMU_BIT_DESC(MSI_MAL_ERR, non_fatal, imu_rds) }, 119 { IMU_BIT_DESC(MSI_PAR_ERR, fatal_stuck, imu_rds) }, 120 { IMU_BIT_DESC(PMEACK_MES_NOT_EN, imu_rbne, imu_rds) }, 121 { IMU_BIT_DESC(PMPME_MES_NOT_EN, imu_pme, imu_rds) }, 122 { IMU_BIT_DESC(FATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 123 { IMU_BIT_DESC(NONFATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 124 { IMU_BIT_DESC(COR_MES_NOT_EN, imu_rbne, imu_rds) }, 125 { IMU_BIT_DESC(MSI_NOT_EN, imu_rbne, imu_rds) }, 126 127 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 128 { IMU_BIT_DESC(EQ_NOT_EN, imu_rbne, imu_rds) }, 129 130 /* DMC IMU - see io erpt doc, section 2.3 */ 131 { IMU_BIT_DESC(EQ_OVER, imu_eq_ovfl, imu) } 132 }; 133 134 #define px_err_imu_keys (sizeof (px_err_imu_tbl)) / (sizeof (px_err_bit_desc_t)) 135 136 /* mmu errors */ 137 #define MMU_BIT_DESC(bit, hdl, erpt) \ 138 MMU_INTERRUPT_STATUS_ ## bit ## _P, \ 139 0, \ 140 PX_ERR_BIT_HANDLE(hdl), \ 141 PX_ERPT_SEND(erpt), \ 142 PX_ERR_DMC_CLASS(bit) 143 px_err_bit_desc_t px_err_mmu_tbl[] = { 144 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 145 { MMU_BIT_DESC(BYP_ERR, mmu_rbne, mmu_tfar_tfsr) }, 146 { MMU_BIT_DESC(BYP_OOR, mmu_tfa, mmu_tfar_tfsr) }, 147 { MMU_BIT_DESC(TRN_ERR, mmu_rbne, mmu_tfar_tfsr) }, 148 { MMU_BIT_DESC(TRN_OOR, mmu_tfa, mmu_tfar_tfsr) }, 149 { MMU_BIT_DESC(TTE_INV, mmu_tfa, mmu_tfar_tfsr) }, 150 { MMU_BIT_DESC(TTE_PRT, mmu_tfa, mmu_tfar_tfsr) }, 151 { MMU_BIT_DESC(TTC_DPE, mmu_tfa, mmu_tfar_tfsr) }, 152 { MMU_BIT_DESC(TBW_DME, mmu_tblwlk, mmu_tfar_tfsr) }, 153 { MMU_BIT_DESC(TBW_UDE, mmu_tblwlk, mmu_tfar_tfsr) }, 154 { MMU_BIT_DESC(TBW_ERR, mmu_tblwlk, mmu_tfar_tfsr) }, 155 { MMU_BIT_DESC(TBW_DPE, mmu_tblwlk, mmu_tfar_tfsr) }, 156 157 /* DMC MMU - see io erpt doc, section 2.5 */ 158 { MMU_BIT_DESC(TTC_CAE, non_fatal, mmu) } 159 }; 160 #define px_err_mmu_keys (sizeof (px_err_mmu_tbl)) / (sizeof (px_err_bit_desc_t)) 161 162 /* 163 * PEC error bit tables 164 */ 165 #define ILU_BIT_DESC(bit, hdl, erpt) \ 166 ILU_INTERRUPT_STATUS_ ## bit ## _P, \ 167 0, \ 168 PX_ERR_BIT_HANDLE(hdl), \ 169 PX_ERPT_SEND(erpt), \ 170 PX_ERR_PEC_CLASS(bit) 171 px_err_bit_desc_t px_err_ilu_tbl[] = { 172 /* PEC ILU none - see io erpt doc, section 3.1 */ 173 { ILU_BIT_DESC(IHB_PE, fatal_gos, pec_ilu) } 174 }; 175 #define px_err_ilu_keys \ 176 (sizeof (px_err_ilu_tbl)) / (sizeof (px_err_bit_desc_t)) 177 178 /* 179 * PEC UE errors implementation is incomplete pending PCIE generic 180 * fabric rules. 181 */ 182 /* pec ue errors */ 183 #define TLU_UC_BIT_DESC(bit, hdl, erpt) \ 184 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 185 0, \ 186 NULL, \ 187 NULL, \ 188 "" 189 px_err_bit_desc_t px_err_tlu_ue_tbl[] = { 190 /* PCI-E Receive Uncorrectable Errors - see io erpt doc, section 3.2 */ 191 { TLU_UC_BIT_DESC(UR, NULL, NULL) }, 192 { TLU_UC_BIT_DESC(ROF, NULL, NULL) }, 193 { TLU_UC_BIT_DESC(UC, NULL, NULL) }, 194 195 /* PCI-E Transmit Uncorrectable Errors - see io erpt doc, section 3.3 */ 196 { TLU_UC_BIT_DESC(CTO, NULL, NULL) }, 197 198 /* PCI-E Rx/Tx Uncorrectable Errors - see io erpt doc, section 3.4 */ 199 { TLU_UC_BIT_DESC(MFP, NULL, NULL) }, 200 { TLU_UC_BIT_DESC(PP, NULL, NULL) }, 201 202 /* Other PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 203 { TLU_UC_BIT_DESC(FCP, NULL, NULL) }, 204 { TLU_UC_BIT_DESC(DLP, NULL, NULL) }, 205 { TLU_UC_BIT_DESC(TE, NULL, NULL) }, 206 { TLU_UC_BIT_DESC(CA, NULL, NULL) } 207 }; 208 #define px_err_tlu_ue_keys \ 209 (sizeof (px_err_tlu_ue_tbl)) / (sizeof (px_err_bit_desc_t)) 210 211 /* 212 * PEC CE errors implementation is incomplete pending PCIE generic 213 * fabric rules. 214 */ 215 /* pec ce errors */ 216 #define TLU_CE_BIT_DESC(bit, hdl, erpt) \ 217 TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 218 0, \ 219 NULL, \ 220 NULL, \ 221 "" 222 px_err_bit_desc_t px_err_tlu_ce_tbl[] = { 223 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 224 { TLU_CE_BIT_DESC(RTO, NULL, NULL) }, 225 { TLU_CE_BIT_DESC(RNR, NULL, NULL) }, 226 { TLU_CE_BIT_DESC(BDP, NULL, NULL) }, 227 { TLU_CE_BIT_DESC(BTP, NULL, NULL) }, 228 { TLU_CE_BIT_DESC(RE, NULL, NULL) } 229 }; 230 #define px_err_tlu_ce_keys \ 231 (sizeof (px_err_tlu_ce_tbl)) / (sizeof (px_err_bit_desc_t)) 232 233 /* pec oe errors */ 234 #define TLU_OE_BIT_DESC(bit, hdl, erpt) \ 235 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 236 0, \ 237 PX_ERR_BIT_HANDLE(hdl), \ 238 PX_ERPT_SEND(erpt), \ 239 PX_ERR_PEC_CLASS(bit) 240 px_err_bit_desc_t px_err_tlu_oe_tbl[] = { 241 /* 242 * TLU Other Event Status (receive only) - see io erpt doc, section 3.7 243 */ 244 { TLU_OE_BIT_DESC(MRC, fatal_hw, pciex_rx_oe) }, 245 246 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 247 { TLU_OE_BIT_DESC(WUC, fatal_stuck, pciex_rx_tx_oe) }, 248 { TLU_OE_BIT_DESC(RUC, fatal_stuck, pciex_rx_tx_oe) }, 249 { TLU_OE_BIT_DESC(CRS, non_fatal, pciex_rx_tx_oe) }, 250 251 /* TLU Other Event - see io erpt doc, section 3.9 */ 252 { TLU_OE_BIT_DESC(IIP, fatal_gos, pciex_oe) }, 253 { TLU_OE_BIT_DESC(EDP, fatal_gos, pciex_oe) }, 254 { TLU_OE_BIT_DESC(EHP, fatal_gos, pciex_oe) }, 255 { TLU_OE_BIT_DESC(LIN, non_fatal, pciex_oe) }, 256 { TLU_OE_BIT_DESC(LRS, non_fatal, pciex_oe) }, 257 { TLU_OE_BIT_DESC(LDN, non_fatal, pciex_ldn) }, 258 { TLU_OE_BIT_DESC(LUP, tlu_lup, pciex_lup) }, 259 { TLU_OE_BIT_DESC(ERU, fatal_gos, pciex_oe) }, 260 { TLU_OE_BIT_DESC(ERO, fatal_gos, pciex_oe) }, 261 { TLU_OE_BIT_DESC(EMP, fatal_gos, pciex_oe) }, 262 { TLU_OE_BIT_DESC(EPE, fatal_gos, pciex_oe) }, 263 { TLU_OE_BIT_DESC(ERP, fatal_gos, pciex_oe) }, 264 { TLU_OE_BIT_DESC(EIP, fatal_gos, pciex_oe) } 265 }; 266 267 #define px_err_tlu_oe_keys \ 268 (sizeof (px_err_tlu_oe_tbl)) / (sizeof (px_err_bit_desc_t)) 269 270 /* 271 * All the following tables below are for LPU Interrupts. These interrupts 272 * are *NOT* error interrupts, but event status interrupts. 273 * 274 * These events are probably of most interest to: 275 * o Hotplug 276 * o Power Management 277 * o etc... 278 * 279 * There are also a few events that would be interresting for FMA. 280 * Again none of the regiseters below state that an error has occured 281 * or that data has been lost. If anything, they give status that an 282 * error is *about* to occur. examples 283 * o INT_SKP_ERR - indicates clock between fire and child is too far 284 * off and is most unlikely able to compensate 285 * o INT_TX_PAR_ERR - A parity error occured in ONE lane. This is 286 * HW recoverable, but will like end up as a future 287 * fabric error as well. 288 * 289 * For now, we don't care about any of these errors and should be ignore, 290 * but cleared. 291 */ 292 293 /* LPU Link Interrupt Table */ 294 #define LPUL_BIT_DESC(bit, hdl, erpt) \ 295 LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 296 0, \ 297 NULL, \ 298 NULL, \ 299 "" 300 px_err_bit_desc_t px_err_lpul_tbl[] = { 301 { LPUL_BIT_DESC(LINK_ERR_ACT, NULL, NULL) } 302 }; 303 #define px_err_lpul_keys \ 304 (sizeof (px_err_lpul_tbl)) / (sizeof (px_err_bit_desc_t)) 305 306 /* LPU Physical Interrupt Table */ 307 #define LPUP_BIT_DESC(bit, hdl, erpt) \ 308 LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 309 0, \ 310 NULL, \ 311 NULL, \ 312 "" 313 px_err_bit_desc_t px_err_lpup_tbl[] = { 314 { LPUP_BIT_DESC(PHY_LAYER_ERR, NULL, NULL) } 315 }; 316 #define px_err_lpup_keys \ 317 (sizeof (px_err_lpup_tbl)) / (sizeof (px_err_bit_desc_t)) 318 319 /* LPU Receive Interrupt Table */ 320 #define LPUR_BIT_DESC(bit, hdl, erpt) \ 321 LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 322 0, \ 323 NULL, \ 324 NULL, \ 325 "" 326 px_err_bit_desc_t px_err_lpur_tbl[] = { 327 { LPUR_BIT_DESC(RCV_PHY, NULL, NULL) } 328 }; 329 #define px_err_lpur_keys \ 330 (sizeof (px_err_lpur_tbl)) / (sizeof (px_err_bit_desc_t)) 331 332 /* LPU Transmit Interrupt Table */ 333 #define LPUX_BIT_DESC(bit, hdl, erpt) \ 334 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 335 0, \ 336 NULL, \ 337 NULL, \ 338 "" 339 px_err_bit_desc_t px_err_lpux_tbl[] = { 340 { LPUX_BIT_DESC(UNMSK, NULL, NULL) } 341 }; 342 #define px_err_lpux_keys \ 343 (sizeof (px_err_lpux_tbl)) / (sizeof (px_err_bit_desc_t)) 344 345 /* LPU LTSSM Interrupt Table */ 346 #define LPUS_BIT_DESC(bit, hdl, erpt) \ 347 LPU_LTSSM_INTERRUPT_AND_STATUS_INT_ ## bit, \ 348 0, \ 349 NULL, \ 350 NULL, \ 351 "" 352 px_err_bit_desc_t px_err_lpus_tbl[] = { 353 { LPUS_BIT_DESC(ANY, NULL, NULL) } 354 }; 355 #define px_err_lpus_keys \ 356 (sizeof (px_err_lpus_tbl)) / (sizeof (px_err_bit_desc_t)) 357 358 /* LPU Gigablaze Glue Interrupt Table */ 359 #define LPUG_BIT_DESC(bit, hdl, erpt) \ 360 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_ ## bit, \ 361 0, \ 362 NULL, \ 363 NULL, \ 364 "" 365 px_err_bit_desc_t px_err_lpug_tbl[] = { 366 { LPUG_BIT_DESC(GLOBL_UNMSK, NULL, NULL) } 367 }; 368 #define px_err_lpug_keys \ 369 (sizeof (px_err_lpug_tbl)) / (sizeof (px_err_bit_desc_t)) 370 371 372 /* Mask and Tables */ 373 #define MnT6(pre) \ 374 B_FALSE, \ 375 &px_ ## pre ## _intr_mask, \ 376 &px_ ## pre ## _log_mask, \ 377 &px_ ## pre ## _count_mask, \ 378 px_err_ ## pre ## _tbl, \ 379 px_err_ ## pre ## _keys, \ 380 0 381 382 /* LPU Registers Addresses */ 383 #define LR4(pre) \ 384 NULL, \ 385 LPU_ ## pre ## _INTERRUPT_MASK, \ 386 LPU_ ## pre ## _INTERRUPT_AND_STATUS, \ 387 LPU_ ## pre ## _INTERRUPT_AND_STATUS 388 389 /* LPU Registers Addresses with Irregularities */ 390 #define LR4_FIXME(pre) \ 391 NULL, \ 392 LPU_ ## pre ## _INTERRUPT_MASK, \ 393 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS, \ 394 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS 395 396 /* TLU Registers Addresses */ 397 #define TR4(pre) \ 398 TLU_ ## pre ## _LOG_ENABLE, \ 399 TLU_ ## pre ## _INTERRUPT_ENABLE, \ 400 TLU_ ## pre ## _INTERRUPT_STATUS, \ 401 TLU_ ## pre ## _STATUS_CLEAR 402 403 /* Registers Addresses for JBC, MMU, IMU and ILU */ 404 #define R4(pre) \ 405 pre ## _ERROR_LOG_ENABLE, \ 406 pre ## _INTERRUPT_ENABLE, \ 407 pre ## _INTERRUPT_STATUS, \ 408 pre ## _ERROR_STATUS_CLEAR 409 410 /* 411 * Register error handling tables. 412 * The ID Field (first field) is identified by an enum px_err_id_t. 413 * It is located in px_err.h 414 */ 415 px_err_reg_desc_t px_err_reg_tbl[] = { 416 { MnT6(cb), R4(JBC), "JBC Error"}, 417 { MnT6(mmu), R4(MMU), "IMU Error"}, 418 { MnT6(imu), R4(IMU), "ILU Error"}, 419 { MnT6(tlu_ue), TR4(UNCORRECTABLE_ERROR), "TLU UE"}, 420 { MnT6(tlu_ce), TR4(CORRECTABLE_ERROR), "TLU CE"}, 421 { MnT6(tlu_oe), TR4(OTHER_EVENT), "TLU OE"}, 422 { MnT6(ilu), R4(ILU), "MMU Error"}, 423 { MnT6(lpul), LR4(LINK_LAYER), "LPU Link Layer"}, 424 { MnT6(lpup), LR4_FIXME(PHY), "LPU Phy Layer"}, 425 { MnT6(lpur), LR4(RECEIVE_PHY), "LPU RX Phy Layer"}, 426 { MnT6(lpux), LR4(TRANSMIT_PHY), "LPU TX Phy Layer"}, 427 { MnT6(lpus), LR4(LTSSM), "LPU LTSSM"}, 428 { MnT6(lpug), LR4(GIGABLAZE_GLUE), "LPU GigaBlaze Glue"} 429 }; 430 #define PX_ERR_REG_KEYS (sizeof (px_err_reg_tbl)) / (sizeof (px_err_reg_tbl[0])) 431 432 typedef struct px_err_ss { 433 uint64_t err_status[PX_ERR_REG_KEYS]; 434 } px_err_ss_t; 435 436 static void px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chkjbc); 437 static int px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, 438 px_err_ss_t *ss); 439 static int px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, 440 int err, int caller); 441 442 /* 443 * px_err_cb_intr: 444 * Interrupt handler for the JBC block. 445 * o lock 446 * o create derr 447 * o px_err_handle(leaf1, with jbc) 448 * o px_err_handle(leaf2, without jbc) 449 * o dispatch (leaf1) 450 * o dispatch (leaf2) 451 * o unlock 452 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 453 */ 454 uint_t 455 px_err_cb_intr(caddr_t arg) 456 { 457 px_fault_t *px_fault_p = (px_fault_t *)arg; 458 dev_info_t *rpdip = px_fault_p->px_fh_dip; 459 dev_info_t *leafdip; 460 px_t *px_p = DIP_TO_STATE(rpdip); 461 px_cb_t *cb_p = px_p->px_cb_p; 462 int err = PX_OK; 463 int ret = DDI_FM_OK; 464 int fatal = 0; 465 int nonfatal = 0; 466 int unknown = 0; 467 int i; 468 boolean_t chkjbc = B_TRUE; 469 ddi_fm_error_t derr; 470 471 /* Create the derr */ 472 bzero(&derr, sizeof (ddi_fm_error_t)); 473 derr.fme_version = DDI_FME_VERSION; 474 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 475 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 476 477 mutex_enter(&cb_p->xbc_fm_mutex); 478 479 /* send ereport/handle/clear for ALL fire leaves */ 480 for (i = 0; i < PX_CB_MAX_LEAF; i++) { 481 if ((px_p = cb_p->xbc_px_list[i]) == NULL) 482 continue; 483 484 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, chkjbc); 485 chkjbc = B_FALSE; 486 } 487 488 /* Check all child devices for errors on ALL fire leaves */ 489 for (i = 0; i < PX_CB_MAX_LEAF; i++) { 490 if ((px_p = cb_p->xbc_px_list[i]) != NULL) { 491 leafdip = px_p->px_dip; 492 ret = ndi_fm_handler_dispatch(leafdip, NULL, &derr); 493 switch (ret) { 494 case DDI_FM_FATAL: 495 fatal++; 496 break; 497 case DDI_FM_NONFATAL: 498 nonfatal++; 499 break; 500 case DDI_FM_UNKNOWN: 501 unknown++; 502 break; 503 default: 504 break; 505 } 506 } 507 } 508 509 /* Set the intr state to idle for the leaf that received the mondo */ 510 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 511 INTR_IDLE_STATE); 512 513 mutex_exit(&cb_p->xbc_fm_mutex); 514 515 /* 516 * PX_FATAL_HW error is diagnosed after system recovered from 517 * HW initiated reset, therefore no furthur handling is required. 518 */ 519 if (fatal || err & (PX_FATAL_GOS | PX_FATAL_SW)) 520 fm_panic("Fatal System Bus Error has occurred\n"); 521 522 return (DDI_INTR_CLAIMED); 523 } 524 525 /* 526 * px_err_dmc_pec_intr: 527 * Interrupt handler for the DMC/PEC block. 528 * o lock 529 * o create derr 530 * o px_err_handle(leaf, with jbc) 531 * o dispatch (leaf) 532 * o unlock 533 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 534 */ 535 uint_t 536 px_err_dmc_pec_intr(caddr_t arg) 537 { 538 px_fault_t *px_fault_p = (px_fault_t *)arg; 539 dev_info_t *rpdip = px_fault_p->px_fh_dip; 540 px_t *px_p = DIP_TO_STATE(rpdip); 541 px_cb_t *cb_p = px_p->px_cb_p; 542 int err = PX_OK; 543 int ret = DDI_FM_OK; 544 ddi_fm_error_t derr; 545 546 /* Create the derr */ 547 bzero(&derr, sizeof (ddi_fm_error_t)); 548 derr.fme_version = DDI_FME_VERSION; 549 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 550 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 551 552 mutex_enter(&cb_p->xbc_fm_mutex); 553 554 /* send ereport/handle/clear fire registers */ 555 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, B_TRUE); 556 557 /* Check all child devices for errors */ 558 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 559 560 /* Set the interrupt state to idle */ 561 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 562 INTR_IDLE_STATE); 563 564 mutex_exit(&cb_p->xbc_fm_mutex); 565 566 /* 567 * PX_FATAL_HW indicates a condition recovered from Fatal-Reset, 568 * therefore it does not cause panic. 569 */ 570 if ((err & (PX_FATAL_GOS | PX_FATAL_SW)) || (ret == DDI_FM_FATAL)) 571 fm_panic("Fatal System Port Error has occurred\n"); 572 573 return (DDI_INTR_CLAIMED); 574 } 575 576 /* 577 * Error register are being handled by px_hlib xxx_init functions. 578 * They are also called again by px_err_add_intr for mondo62 and 63 579 * from px_cb_attach and px_attach 580 */ 581 void 582 px_err_reg_enable(px_t *px_p, px_err_id_t id) 583 { 584 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 585 uint64_t intr_mask = *reg_desc->intr_mask_p; 586 uint64_t log_mask = *reg_desc->log_mask_p; 587 caddr_t csr_base; 588 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 589 590 if (id == PX_ERR_JBC) 591 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 592 else 593 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 594 595 reg_desc->enabled = B_TRUE; 596 597 /* Enable logs if it exists */ 598 if (reg_desc->log_addr != NULL) 599 CSR_XS(csr_base, reg_desc->log_addr, log_mask); 600 601 /* 602 * For readability you in code you set 1 to enable an interrupt. 603 * But in Fire it's backwards. You set 1 to *disable* an intr. 604 * Reverse the user tunable intr mask field. 605 * 606 * Disable All Errors 607 * Clear All Errors 608 * Enable Errors 609 */ 610 CSR_XS(csr_base, reg_desc->enable_addr, 0); 611 CSR_XS(csr_base, reg_desc->clear_addr, -1); 612 CSR_XS(csr_base, reg_desc->enable_addr, intr_mask); 613 DBG(DBG_ATTACH, NULL, "%s Mask: 0x%llx\n", 614 reg_desc->msg, CSR_XR(csr_base, reg_desc->enable_addr)); 615 DBG(DBG_ATTACH, NULL, "%s Status: 0x%llx\n", 616 reg_desc->msg, CSR_XR(csr_base, reg_desc->status_addr)); 617 DBG(DBG_ATTACH, NULL, "%s Clear: 0x%llx\n", 618 reg_desc->msg, CSR_XR(csr_base, reg_desc->clear_addr)); 619 if (reg_desc->log_addr != NULL) { 620 DBG(DBG_ATTACH, NULL, "%s Log: 0x%llx\n", 621 reg_desc->msg, CSR_XR(csr_base, reg_desc->log_addr)); 622 } 623 } 624 625 void 626 px_err_reg_disable(px_t *px_p, px_err_id_t id) 627 { 628 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 629 caddr_t csr_base; 630 631 if (id == PX_ERR_JBC) 632 csr_base = (caddr_t)px_p->px_inos[PX_INTR_XBC]; 633 else 634 csr_base = (caddr_t)px_p->px_inos[PX_INTR_PEC]; 635 636 reg_desc->enabled = B_FALSE; 637 638 switch (id) { 639 case PX_ERR_JBC: 640 case PX_ERR_MMU: 641 case PX_ERR_IMU: 642 case PX_ERR_TLU_UE: 643 case PX_ERR_TLU_CE: 644 case PX_ERR_TLU_OE: 645 case PX_ERR_ILU: 646 if (reg_desc->log_addr != NULL) { 647 CSR_XS(csr_base, reg_desc->log_addr, 0); 648 } 649 CSR_XS(csr_base, reg_desc->enable_addr, 0); 650 break; 651 case PX_ERR_LPU_LINK: 652 case PX_ERR_LPU_PHY: 653 case PX_ERR_LPU_RX: 654 case PX_ERR_LPU_TX: 655 case PX_ERR_LPU_LTSSM: 656 case PX_ERR_LPU_GIGABLZ: 657 if (reg_desc->log_addr != NULL) { 658 CSR_XS(csr_base, reg_desc->log_addr, -1); 659 } 660 CSR_XS(csr_base, reg_desc->enable_addr, -1); 661 break; 662 } 663 } 664 665 /* 666 * px_err_handle: 667 * Common function called by trap, mondo and fabric intr. 668 * o Snap shot current fire registers 669 * o check for safe access 670 * o send ereport and clear snap shot registers 671 * o check severity of snap shot registers 672 * 673 * @param px_p leaf in which to check access 674 * @param derr fm err data structure to be updated 675 * @param caller PX_TRAP_CALL | PX_INTR_CALL 676 * @param chkjbc whether to handle jbc registers 677 * @return err PX_OK | PX_NONFATAL | 678 * PX_FATAL_GOS | PX_FATAL_HW | PX_STUCK_FATAL 679 */ 680 int 681 px_err_handle(px_t *px_p, ddi_fm_error_t *derr, int caller, 682 boolean_t chkjbc) 683 { 684 px_cb_t *cb_p = px_p->px_cb_p; /* for fm_mutex */ 685 px_err_ss_t ss; 686 int err = PX_OK; 687 688 ASSERT(MUTEX_HELD(&cb_p->xbc_fm_mutex)); 689 690 /* snap shot the current fire registers */ 691 px_err_snapshot(px_p, &ss, chkjbc); 692 693 /* check for safe access */ 694 px_err_safeacc_check(px_p, derr); 695 696 /* send ereports/handle/clear registers */ 697 err = px_err_erpt_and_clr(px_p, derr, &ss); 698 699 /* check for error severity */ 700 err = px_err_check_severity(px_p, derr, err, caller); 701 702 /* Mark the On Trap Handle if an error occured */ 703 if (err != PX_OK) { 704 px_pec_t *pec_p = px_p->px_pec_p; 705 on_trap_data_t *otd = pec_p->pec_ontrap_data; 706 707 if ((otd != NULL) && (otd->ot_prot & OT_DATA_ACCESS)) 708 otd->ot_trap |= OT_DATA_ACCESS; 709 } 710 711 return (err); 712 } 713 714 /* 715 * Static function 716 */ 717 718 /* 719 * px_err_snapshot: 720 * Take a current snap shot of all the fire error registers. This includes 721 * JBC, DMC, and PEC, unless chkjbc == false; 722 * 723 * @param px_p leaf in which to take the snap shot. 724 * @param ss pre-allocated memory to store the snap shot. 725 * @param chkjbc boolean on whether to store jbc register. 726 */ 727 static void 728 px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chkjbc) 729 { 730 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 731 caddr_t xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 732 caddr_t pec_csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 733 px_err_reg_desc_t *reg_desc; 734 int reg_id; 735 736 /* snapshot JBC interrupt status */ 737 reg_id = PX_ERR_JBC; 738 if (chkjbc == B_TRUE) { 739 reg_desc = &px_err_reg_tbl[reg_id]; 740 ss->err_status[reg_id] = CSR_XR(xbc_csr_base, 741 reg_desc->status_addr); 742 } else { 743 ss->err_status[reg_id] = 0; 744 } 745 746 /* snapshot DMC/PEC interrupt status */ 747 for (reg_id = 1; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 748 reg_desc = &px_err_reg_tbl[reg_id]; 749 ss->err_status[reg_id] = CSR_XR(pec_csr_base, 750 reg_desc->status_addr); 751 } 752 } 753 754 /* 755 * px_err_erpt_and_clr: 756 * This function does the following thing to all the fire registers based 757 * on an earlier snap shot. 758 * o Send ereport 759 * o Handle the error 760 * o Clear the error 761 * 762 * @param px_p leaf in which to take the snap shot. 763 * @param derr fm err in which the ereport is to be based on 764 * @param ss pre-allocated memory to store the snap shot. 765 */ 766 static int 767 px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, px_err_ss_t *ss) 768 { 769 dev_info_t *rpdip = px_p->px_dip; 770 px_cb_t *cb_p = px_p->px_cb_p; /* for fm_mutex */ 771 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 772 caddr_t csr_base; 773 px_err_reg_desc_t *err_reg_tbl; 774 px_err_bit_desc_t *err_bit_tbl; 775 px_err_bit_desc_t *err_bit_desc; 776 777 uint64_t *log_mask, *count_mask; 778 uint64_t status_addr, clear_addr; 779 uint64_t ss_reg; 780 781 int (*err_handler)(); 782 int (*erpt_handler)(); 783 int reg_id, key; 784 int err = PX_OK; 785 786 ASSERT(MUTEX_HELD(&cb_p->xbc_fm_mutex)); 787 788 /* send erport/handle/clear JBC errors */ 789 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 790 /* Get the correct register description table */ 791 err_reg_tbl = &px_err_reg_tbl[reg_id]; 792 793 /* Get the correct CSR BASE */ 794 if (reg_id == PX_ERR_JBC) { 795 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 796 } else { 797 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 798 } 799 800 /* Get pointers to masks and register addresses */ 801 log_mask = err_reg_tbl->log_mask_p; 802 count_mask = err_reg_tbl->count_mask_p; 803 status_addr = err_reg_tbl->status_addr; 804 clear_addr = err_reg_tbl->clear_addr; 805 ss_reg = ss->err_status[reg_id]; 806 807 /* Get the register BIT description table */ 808 err_bit_tbl = err_reg_tbl->err_bit_tbl; 809 810 /* For each known bit in the register send erpt and handle */ 811 for (key = 0; key < err_reg_tbl->err_bit_keys; key += 1) { 812 /* Get the bit description table for this register */ 813 err_bit_desc = &err_bit_tbl[key]; 814 815 /* 816 * If the ss_reg is set for this bit, 817 * send ereport and handle 818 */ 819 if (BIT_TST(ss_reg, err_bit_desc->bit)) { 820 /* Increment the counter if necessary */ 821 if (BIT_TST(*count_mask, err_bit_desc->bit)) { 822 err_bit_desc->counter++; 823 } 824 825 /* Error Handle for this bit */ 826 err_handler = err_bit_desc->err_handler; 827 if (err_handler) 828 err |= err_handler(rpdip, 829 csr_base, 830 derr, 831 err_reg_tbl, 832 err_bit_desc); 833 834 /* Send the ereport for this bit */ 835 erpt_handler = err_bit_desc->erpt_handler; 836 if (erpt_handler) 837 (void) erpt_handler(rpdip, 838 csr_base, 839 ss_reg, 840 derr, 841 err_bit_desc->class_name); 842 } 843 } 844 /* Log register status */ 845 if ((px_err_log_all) || (ss_reg & *log_mask)) 846 LOG(DBG_ERR_INTR, rpdip, "<%x>=%16llx %s\n", 847 status_addr, ss_reg, err_reg_tbl->msg); 848 849 /* Clear the register and error */ 850 CSR_XS(csr_base, clear_addr, ss_reg); 851 } 852 853 return (err); 854 } 855 856 /* 857 * px_err_check_severity: 858 * Check the severity of the fire error based on an earlier snapshot 859 * 860 * @param px_p leaf in which to take the snap shot. 861 * @param derr fm err in which the ereport is to be based on 862 * @param ss pre-allocated memory to store the snap shot. 863 */ 864 static int 865 px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, int err, int caller) 866 { 867 px_pec_t *pec_p = px_p->px_pec_p; 868 boolean_t is_safeacc = B_FALSE; 869 870 /* nothing to do if called with no error */ 871 if (err == PX_OK) 872 return (err); 873 874 /* Cautious access error handling */ 875 switch (derr->fme_flag) { 876 case DDI_FM_ERR_EXPECTED: 877 if (caller == PX_TRAP_CALL) { 878 /* 879 * for ddi_caut_get treat all events as nonfatal 880 * The trampoline will set err_ena = 0, 881 * err_status = NONFATAL. 882 */ 883 derr->fme_status = DDI_FM_NONFATAL; 884 is_safeacc = B_TRUE; 885 } else { 886 /* 887 * For ddi_caut_put treat all events as nonfatal. Here 888 * we have the handle and can call ndi_fm_acc_err_set(). 889 */ 890 derr->fme_status = DDI_FM_NONFATAL; 891 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 892 is_safeacc = B_TRUE; 893 } 894 break; 895 case DDI_FM_ERR_PEEK: 896 case DDI_FM_ERR_POKE: 897 /* 898 * For ddi_peek/poke treat all events as nonfatal. 899 */ 900 is_safeacc = B_TRUE; 901 break; 902 default: 903 is_safeacc = B_FALSE; 904 } 905 906 /* 907 * The third argument "err" is passed in as error status from checking 908 * Fire register, re-adjust error status from safe access. 909 */ 910 if (is_safeacc && !(err & PX_FATAL_GOS)) 911 return (PX_NONFATAL); 912 913 return (err); 914 } 915 916 /* predefined convenience functions */ 917 /* ARGSUSED */ 918 int 919 px_err_fatal_hw_handle(dev_info_t *rpdip, caddr_t csr_base, 920 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 921 px_err_bit_desc_t *err_bit_descr) 922 { 923 return (PX_FATAL_HW); 924 } 925 926 /* ARGSUSED */ 927 int 928 px_err_fatal_gos_handle(dev_info_t *rpdip, caddr_t csr_base, 929 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 930 px_err_bit_desc_t *err_bit_descr) 931 { 932 return (PX_FATAL_GOS); 933 } 934 935 /* ARGSUSED */ 936 int 937 px_err_fatal_stuck_handle(dev_info_t *rpdip, caddr_t csr_base, 938 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 939 px_err_bit_desc_t *err_bit_descr) 940 { 941 return (PX_STUCK_FATAL); 942 } 943 944 /* ARGSUSED */ 945 int 946 px_err_fatal_sw_handle(dev_info_t *rpdip, caddr_t csr_base, 947 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 948 px_err_bit_desc_t *err_bit_descr) 949 { 950 return (PX_FATAL_SW); 951 } 952 953 /* ARGSUSED */ 954 int 955 px_err_non_fatal_handle(dev_info_t *rpdip, caddr_t csr_base, 956 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 957 px_err_bit_desc_t *err_bit_descr) 958 { 959 return (PX_NONFATAL); 960 } 961 962 /* ARGSUSED */ 963 int 964 px_err_ok_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 965 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 966 { 967 return (PX_OK); 968 } 969 970 /* ARGSUSED */ 971 int 972 px_err_unknown_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 973 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 974 { 975 return (PX_ERR_UNKNOWN); 976 } 977 978 /* JBC FATAL - see io erpt doc, section 1.1 */ 979 PX_ERPT_SEND_DEC(jbc_fatal) 980 { 981 char buf[FM_MAX_CLASS]; 982 983 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 984 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 985 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 986 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 987 FIRE_JBC_ELE, DATA_TYPE_UINT64, 988 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 989 FIRE_JBC_IE, DATA_TYPE_UINT64, 990 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 991 FIRE_JBC_IS, DATA_TYPE_UINT64, 992 ss_reg, 993 FIRE_JBC_ESS, DATA_TYPE_UINT64, 994 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 995 FIRE_JBC_FEL1, DATA_TYPE_UINT64, 996 CSR_XR(csr_base, FATAL_ERROR_LOG_1), 997 FIRE_JBC_FEL2, DATA_TYPE_UINT64, 998 CSR_XR(csr_base, FATAL_ERROR_LOG_2), 999 NULL); 1000 1001 return (PX_OK); 1002 } 1003 1004 /* JBC MERGE - see io erpt doc, section 1.2 */ 1005 PX_ERPT_SEND_DEC(jbc_merge) 1006 { 1007 char buf[FM_MAX_CLASS]; 1008 1009 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1010 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1011 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1012 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1013 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1014 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1015 FIRE_JBC_IE, DATA_TYPE_UINT64, 1016 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1017 FIRE_JBC_IS, DATA_TYPE_UINT64, 1018 ss_reg, 1019 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1020 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1021 FIRE_JBC_MTEL, DATA_TYPE_UINT64, 1022 CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG), 1023 NULL); 1024 1025 return (PX_OK); 1026 } 1027 1028 /* 1029 * JBC Merge buffer nonfatal errors: 1030 * Merge buffer parity error (rd_buf): dma:read:M:nonfatal 1031 * Merge buffer parity error (wr_buf): dma:write:M:nonfatal 1032 */ 1033 /* ARGSUSED */ 1034 int 1035 px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 1036 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1037 px_err_bit_desc_t *err_bit_descr) 1038 { 1039 uint64_t paddr; 1040 int ret; 1041 1042 paddr = CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG); 1043 paddr &= MERGE_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1044 1045 ret = px_handle_lookup( 1046 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1047 1048 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1049 } 1050 1051 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 1052 PX_ERPT_SEND_DEC(jbc_in) 1053 { 1054 char buf[FM_MAX_CLASS]; 1055 1056 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1057 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1058 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1059 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1060 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1061 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1062 FIRE_JBC_IE, DATA_TYPE_UINT64, 1063 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1064 FIRE_JBC_IS, DATA_TYPE_UINT64, 1065 ss_reg, 1066 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1067 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1068 FIRE_JBC_JITEL1, DATA_TYPE_UINT64, 1069 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG), 1070 FIRE_JBC_JITEL2, DATA_TYPE_UINT64, 1071 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG_2), 1072 NULL); 1073 1074 return (PX_OK); 1075 } 1076 1077 /* 1078 * JBC Jbusint IN nonfatal errors: PA logged in Jbusint In Transaction Error 1079 * Log Reg[42:0]. 1080 * CE async fault error: nonfatal 1081 * Jbus bus error: dma::nonfatal 1082 * Jbus unmapped error: pio|dma:rdwr:M:nonfatal 1083 * Write data parity error: pio/write:M:nonfatal 1084 * Read data parity error: pio/read:M:nonfatal 1085 * Illegal NCWR bytemask: pio:write:M:nonfatal 1086 * Illegal NCRD bytemask: pio:write:M:nonfatal 1087 * Invalid jbus transaction: nonfatal 1088 */ 1089 /* ARGSUSED */ 1090 int 1091 px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 1092 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1093 px_err_bit_desc_t *err_bit_descr) 1094 { 1095 uint64_t paddr; 1096 int ret; 1097 1098 paddr = CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG); 1099 paddr &= JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1100 1101 ret = px_handle_lookup( 1102 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1103 1104 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1105 } 1106 1107 1108 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 1109 PX_ERPT_SEND_DEC(jbc_out) 1110 { 1111 char buf[FM_MAX_CLASS]; 1112 1113 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1114 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1115 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1116 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1117 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1118 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1119 FIRE_JBC_IE, DATA_TYPE_UINT64, 1120 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1121 FIRE_JBC_IS, DATA_TYPE_UINT64, 1122 ss_reg, 1123 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1124 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1125 FIRE_JBC_JOTEL1, DATA_TYPE_UINT64, 1126 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG), 1127 FIRE_JBC_JOTEL2, DATA_TYPE_UINT64, 1128 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG_2), 1129 NULL); 1130 1131 return (PX_OK); 1132 } 1133 1134 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 1135 PX_ERPT_SEND_DEC(jbc_odcd) 1136 { 1137 char buf[FM_MAX_CLASS]; 1138 1139 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1140 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1141 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1142 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1143 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1144 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1145 FIRE_JBC_IE, DATA_TYPE_UINT64, 1146 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1147 FIRE_JBC_IS, DATA_TYPE_UINT64, 1148 ss_reg, 1149 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1150 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1151 FIRE_JBC_DMC_ODCD, DATA_TYPE_UINT64, 1152 CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG), 1153 NULL); 1154 1155 return (PX_OK); 1156 } 1157 1158 /* 1159 * JBC Dmcint ODCO nonfatal errer handling - 1160 * Unmapped PIO read error: pio:read:M:nonfatal 1161 * Unmapped PIO write error: pio:write:M:nonfatal 1162 * PIO data parity error: pio:write:M:nonfatal 1163 * Invalid PIO write to PCIe cfg/io, csr, ebus or i2c bus: pio:write:nonfatal 1164 * Invalid PIO read to PCIe cfg/io, csr, ebus or i2c bus: pio:read:nonfatal 1165 */ 1166 /* ARGSUSED */ 1167 int 1168 px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 1169 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1170 px_err_bit_desc_t *err_bit_descr) 1171 { 1172 uint64_t paddr; 1173 int ret; 1174 1175 paddr = CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG); 1176 paddr &= DMCINT_ODCD_ERROR_LOG_ADDRESS_MASK; 1177 1178 ret = px_handle_lookup( 1179 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1180 1181 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1182 } 1183 1184 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1185 PX_ERPT_SEND_DEC(jbc_idc) 1186 { 1187 char buf[FM_MAX_CLASS]; 1188 1189 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1190 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1191 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1192 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1193 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1194 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1195 FIRE_JBC_IE, DATA_TYPE_UINT64, 1196 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1197 FIRE_JBC_IS, DATA_TYPE_UINT64, 1198 ss_reg, 1199 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1200 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1201 FIRE_JBC_DMC_IDC, DATA_TYPE_UINT64, 1202 CSR_XR(csr_base, DMCINT_IDC_ERROR_LOG), 1203 NULL); 1204 1205 return (PX_OK); 1206 } 1207 1208 /* JBC CSR - see io erpt doc, section 1.7 */ 1209 PX_ERPT_SEND_DEC(jbc_csr) 1210 { 1211 char buf[FM_MAX_CLASS]; 1212 1213 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1214 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1215 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1216 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1217 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1218 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1219 FIRE_JBC_IE, DATA_TYPE_UINT64, 1220 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1221 FIRE_JBC_IS, DATA_TYPE_UINT64, 1222 ss_reg, 1223 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1224 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1225 "jbc-error-reg", DATA_TYPE_UINT64, 1226 CSR_XR(csr_base, CSR_ERROR_LOG), 1227 NULL); 1228 1229 return (PX_OK); 1230 } 1231 1232 /* 1233 * JBC CSR errer handling - 1234 * Ebus ready timeout error: pio:rdwr:M:nonfatal 1235 */ 1236 /* ARGSUSED */ 1237 int 1238 px_err_jbc_csr_handle(dev_info_t *rpdip, caddr_t csr_base, 1239 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1240 px_err_bit_desc_t *err_bit_descr) 1241 { 1242 uint64_t paddr; 1243 int ret; 1244 1245 paddr = CSR_XR(csr_base, CSR_ERROR_LOG); 1246 paddr &= CSR_ERROR_LOG_ADDRESS_MASK; 1247 1248 ret = px_handle_lookup( 1249 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1250 1251 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1252 } 1253 1254 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1255 1256 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 1257 PX_ERPT_SEND_DEC(imu_rds) 1258 { 1259 char buf[FM_MAX_CLASS]; 1260 1261 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1262 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1263 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1264 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1265 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1266 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1267 FIRE_IMU_IE, DATA_TYPE_UINT64, 1268 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1269 FIRE_IMU_IS, DATA_TYPE_UINT64, 1270 ss_reg, 1271 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1272 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1273 FIRE_IMU_RDS, DATA_TYPE_UINT64, 1274 CSR_XR(csr_base, IMU_RDS_ERROR_LOG), 1275 NULL); 1276 1277 return (PX_OK); 1278 } 1279 1280 /* imu function to handle all Received but Not Enabled errors */ 1281 /* ARGSUSED */ 1282 int 1283 px_err_imu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1284 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1285 px_err_bit_desc_t *err_bit_descr) 1286 { 1287 uint64_t imu_log_enable, imu_intr_enable; 1288 int mask = BITMASK(err_bit_descr->bit); 1289 int err = PX_NONFATAL; 1290 1291 imu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1292 imu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1293 1294 if (imu_log_enable & imu_intr_enable & mask) { 1295 err = PX_FATAL_SW; 1296 } else { 1297 /* 1298 * S/W bug - this error should always be enabled 1299 */ 1300 1301 /* enable error & intr reporting for this bit */ 1302 CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, imu_log_enable | mask); 1303 CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, imu_intr_enable | mask); 1304 err = PX_NONFATAL; 1305 } 1306 1307 return (err); 1308 } 1309 1310 /* 1311 * No platforms uses PME. Any PME received is simply logged 1312 * for analysis. 1313 */ 1314 /* ARGSUSED */ 1315 int 1316 px_err_imu_pme_handle(dev_info_t *rpdip, caddr_t csr_base, 1317 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1318 px_err_bit_desc_t *err_bit_descr) 1319 { 1320 px_t *px_p = DIP_TO_STATE(rpdip); 1321 1322 px_p->px_pme_ignored++; 1323 return (PX_NONFATAL); 1324 } 1325 1326 /* handle EQ overflow */ 1327 /* ARGSUSED */ 1328 int 1329 px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 1330 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1331 px_err_bit_desc_t *err_bit_descr) 1332 { 1333 px_t *px_p = DIP_TO_STATE(rpdip); 1334 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 1335 msiqid_t eqno; 1336 pci_msiq_state_t msiq_state; 1337 int err = PX_NONFATAL; 1338 int i; 1339 1340 eqno = msiq_state_p->msiq_1st_msiq_id; 1341 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 1342 if (px_lib_msiq_getstate(rpdip, eqno, &msiq_state) == 1343 DDI_SUCCESS) { 1344 if (msiq_state == PCI_MSIQ_STATE_ERROR) { 1345 err = PX_FATAL_SW; 1346 } 1347 } 1348 } 1349 1350 return (err); 1351 } 1352 1353 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 1354 PX_ERPT_SEND_DEC(imu_scs) 1355 { 1356 char buf[FM_MAX_CLASS]; 1357 1358 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1359 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1360 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1361 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1362 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1363 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1364 FIRE_IMU_IE, DATA_TYPE_UINT64, 1365 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1366 FIRE_IMU_IS, DATA_TYPE_UINT64, 1367 ss_reg, 1368 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1369 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1370 FIRE_IMU_SCS, DATA_TYPE_UINT64, 1371 CSR_XR(csr_base, IMU_SCS_ERROR_LOG), 1372 NULL); 1373 1374 return (PX_OK); 1375 } 1376 1377 /* DMC IMU - see io erpt doc, section 2.3 */ 1378 PX_ERPT_SEND_DEC(imu) 1379 { 1380 char buf[FM_MAX_CLASS]; 1381 1382 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1383 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1384 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1385 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1386 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1387 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1388 FIRE_IMU_IE, DATA_TYPE_UINT64, 1389 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1390 FIRE_IMU_IS, DATA_TYPE_UINT64, 1391 ss_reg, 1392 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1393 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1394 NULL); 1395 1396 return (PX_OK); 1397 } 1398 1399 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 1400 PX_ERPT_SEND_DEC(mmu_tfar_tfsr) 1401 { 1402 char buf[FM_MAX_CLASS]; 1403 1404 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1405 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1406 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1407 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1408 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1409 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1410 FIRE_MMU_IE, DATA_TYPE_UINT64, 1411 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1412 FIRE_MMU_IS, DATA_TYPE_UINT64, 1413 ss_reg, 1414 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1415 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1416 FIRE_MMU_TFAR, DATA_TYPE_UINT64, 1417 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS), 1418 FIRE_MMU_TFSR, DATA_TYPE_UINT64, 1419 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS), 1420 NULL); 1421 1422 return (PX_OK); 1423 } 1424 1425 /* DMC MMU - see io erpt doc, section 2.5 */ 1426 PX_ERPT_SEND_DEC(mmu) 1427 { 1428 char buf[FM_MAX_CLASS]; 1429 1430 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1431 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1432 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1433 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1434 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1435 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1436 FIRE_MMU_IE, DATA_TYPE_UINT64, 1437 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1438 FIRE_MMU_IS, DATA_TYPE_UINT64, 1439 ss_reg, 1440 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1441 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1442 NULL); 1443 1444 return (PX_OK); 1445 } 1446 1447 /* imu function to handle all Received but Not Enabled errors */ 1448 int 1449 px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1450 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1451 px_err_bit_desc_t *err_bit_descr) 1452 { 1453 uint64_t mmu_log_enable, mmu_intr_enable; 1454 uint64_t mask = BITMASK(err_bit_descr->bit); 1455 uint64_t mmu_tfa, mmu_ctrl; 1456 uint64_t mmu_enable_bit = 0; 1457 int err = PX_NONFATAL; 1458 int ret; 1459 1460 mmu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1461 mmu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1462 1463 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1464 mmu_ctrl = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1465 1466 switch (err_bit_descr->bit) { 1467 case MMU_INTERRUPT_STATUS_BYP_ERR_P: 1468 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_BE); 1469 break; 1470 case MMU_INTERRUPT_STATUS_TRN_ERR_P: 1471 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_TE); 1472 break; 1473 default: 1474 mmu_enable_bit = 0; 1475 break; 1476 } 1477 1478 /* 1479 * If the interrupts are enabled and Translation/Bypass Enable bit 1480 * was set, then panic. This error should not have occured. 1481 */ 1482 if (mmu_log_enable & mmu_intr_enable & 1483 (mmu_ctrl & mmu_enable_bit)) { 1484 err = PX_FATAL_SW; 1485 } else { 1486 ret = px_handle_lookup( 1487 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1488 err = (ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL; 1489 1490 /* 1491 * S/W bug - this error should always be enabled 1492 */ 1493 1494 /* enable error & intr reporting for this bit */ 1495 CSR_XS(csr_base, MMU_ERROR_LOG_ENABLE, mmu_log_enable | mask); 1496 CSR_XS(csr_base, MMU_INTERRUPT_ENABLE, mmu_intr_enable | mask); 1497 1498 /* enable translation access/bypass enable */ 1499 CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, 1500 mmu_ctrl | mmu_enable_bit); 1501 } 1502 1503 return (err); 1504 } 1505 1506 /* Generic error handling functions that involve MMU Translation Fault Addr */ 1507 /* ARGSUSED */ 1508 int 1509 px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 1510 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1511 px_err_bit_desc_t *err_bit_descr) 1512 { 1513 uint64_t mmu_tfa; 1514 uint_t ret; 1515 1516 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1517 ret = px_handle_lookup( 1518 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1519 1520 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1521 } 1522 1523 /* MMU Table walk errors */ 1524 /* ARGSUSED */ 1525 int 1526 px_err_mmu_tblwlk_handle(dev_info_t *rpdip, caddr_t csr_base, 1527 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1528 px_err_bit_desc_t *err_bit_descr) 1529 { 1530 uint64_t mmu_tfa; 1531 uint_t ret; 1532 1533 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1534 ret = px_handle_lookup( 1535 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1536 1537 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1538 } 1539 1540 /* 1541 * TLU LUP event - power management code is interested in this event. 1542 */ 1543 /* ARGSUSED */ 1544 int 1545 px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 1546 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1547 px_err_bit_desc_t *err_bit_descr) 1548 { 1549 px_t *px_p = DIP_TO_STATE(rpdip); 1550 1551 /* 1552 * Existense of pm info indicates the power management 1553 * is interested in this event. 1554 */ 1555 if (!PCIE_PMINFO(rpdip) || !PCIE_NEXUS_PMINFO(rpdip)) 1556 return (PX_OK); 1557 1558 mutex_enter(&px_p->px_lup_lock); 1559 px_p->px_lupsoft_pending++; 1560 mutex_exit(&px_p->px_lup_lock); 1561 1562 /* 1563 * Post a soft interrupt to wake up threads waiting for this. 1564 */ 1565 ddi_trigger_softintr(px_p->px_lupsoft_id); 1566 1567 return (PX_OK); 1568 } 1569 1570 /* PEC ILU none - see io erpt doc, section 3.1 */ 1571 PX_ERPT_SEND_DEC(pec_ilu) 1572 { 1573 char buf[FM_MAX_CLASS]; 1574 1575 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1576 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1577 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1578 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1579 FIRE_ILU_ELE, DATA_TYPE_UINT64, 1580 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE), 1581 FIRE_ILU_IE, DATA_TYPE_UINT64, 1582 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE), 1583 FIRE_ILU_IS, DATA_TYPE_UINT64, 1584 ss_reg, 1585 FIRE_ILU_ESS, DATA_TYPE_UINT64, 1586 CSR_XR(csr_base, ILU_ERROR_STATUS_SET), 1587 NULL); 1588 1589 return (PX_OK); 1590 } 1591 1592 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 1593 PX_ERPT_SEND_DEC(pciex_ce) 1594 { 1595 char buf[FM_MAX_CLASS]; 1596 1597 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1598 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1599 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1600 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1601 FIRE_TLU_CELE, DATA_TYPE_UINT64, 1602 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE), 1603 FIRE_TLU_CIE, DATA_TYPE_UINT64, 1604 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE), 1605 FIRE_TLU_CIS, DATA_TYPE_UINT64, 1606 ss_reg, 1607 FIRE_TLU_CESS, DATA_TYPE_UINT64, 1608 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_SET), 1609 NULL); 1610 1611 return (PX_OK); 1612 } 1613 1614 /* TLU Other Event Status (receive only) - see io erpt doc, section 3.7 */ 1615 PX_ERPT_SEND_DEC(pciex_rx_oe) 1616 { 1617 char buf[FM_MAX_CLASS]; 1618 1619 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1620 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1621 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1622 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1623 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1624 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1625 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1626 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1627 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1628 ss_reg, 1629 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1630 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1631 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1632 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 1633 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1634 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 1635 NULL); 1636 1637 return (PX_OK); 1638 } 1639 1640 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 1641 PX_ERPT_SEND_DEC(pciex_rx_tx_oe) 1642 { 1643 char buf[FM_MAX_CLASS]; 1644 1645 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1646 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1647 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1648 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1649 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1650 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1651 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1652 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1653 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1654 ss_reg, 1655 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1656 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1657 FIRE_TLU_ROEEH1L, DATA_TYPE_UINT64, 1658 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 1659 FIRE_TLU_ROEEH2L, DATA_TYPE_UINT64, 1660 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 1661 FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, 1662 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG), 1663 FIRE_TLU_TOEEH2L, DATA_TYPE_UINT64, 1664 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG), 1665 NULL); 1666 1667 return (PX_OK); 1668 } 1669 1670 /* TLU Other Event - see io erpt doc, section 3.9 */ 1671 PX_ERPT_SEND_DEC(pciex_oe) 1672 { 1673 char buf[FM_MAX_CLASS]; 1674 1675 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1676 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1677 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1678 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1679 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1680 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1681 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1682 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1683 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1684 ss_reg, 1685 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1686 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1687 NULL); 1688 1689 return (PX_OK); 1690 } 1691 1692 /* TLU Other Event - Link Down see io erpt doc, section 3.9 */ 1693 PX_ERPT_SEND_DEC(pciex_ldn) 1694 { 1695 px_t *px_p = DIP_TO_STATE(rpdip); 1696 1697 /* 1698 * Don't post ereport, if ldn event is due to 1699 * power management. 1700 */ 1701 if (px_p->px_pm_flags & PX_LDN_EXPECTED) { 1702 px_p->px_pm_flags &= ~PX_LDN_EXPECTED; 1703 return (PX_OK); 1704 } 1705 return (PX_ERPT_SEND(pciex_oe)(rpdip, csr_base, ss_reg, derr, 1706 class_name)); 1707 1708 } 1709 1710 /* TLU Other Event - Link Up see io erpt doc, section 3.9 */ 1711 PX_ERPT_SEND_DEC(pciex_lup) 1712 { 1713 px_t *px_p = DIP_TO_STATE(rpdip); 1714 1715 /* 1716 * Don't post ereport, if lup event is due to 1717 * power management. 1718 */ 1719 if (px_p->px_pm_flags & PX_LUP_EXPECTED) { 1720 px_p->px_pm_flags &= ~PX_LUP_EXPECTED; 1721 return (PX_OK); 1722 } 1723 1724 return (PX_ERPT_SEND(pciex_oe)(rpdip, csr_base, ss_reg, derr, 1725 class_name)); 1726 } 1727