xref: /illumos-gate/usr/src/uts/sun4u/io/pci/pci_pci.c (revision 651d856bef3edc901fc0821d2462b7cfd806a735)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 /*
29  *	Sun4u PCI to PCI bus bridge nexus driver
30  */
31 
32 #include <sys/conf.h>
33 #include <sys/kmem.h>
34 #include <sys/debug.h>
35 #include <sys/modctl.h>
36 #include <sys/autoconf.h>
37 #include <sys/ddi_impldefs.h>
38 #include <sys/ddi_subrdefs.h>
39 #include <sys/pcie.h>
40 #include <sys/pcie_impl.h>
41 #include <sys/pci_cap.h>
42 #include <sys/pci/pci_nexus.h>
43 #include <sys/pci/pci_regs.h>
44 #include <sys/ddi.h>
45 #include <sys/sunndi.h>
46 #include <sys/sunddi.h>
47 #include <sys/fm/protocol.h>
48 #include <sys/ddifm.h>
49 #include <sys/pci/pci_pwr.h>
50 #include <sys/pci/pci_debug.h>
51 #include <sys/hotplug/pci/pcihp.h>
52 #include <sys/open.h>
53 #include <sys/stat.h>
54 #include <sys/file.h>
55 
56 #define	NUM_LOGICAL_SLOTS	32
57 
58 #define	PPB_RANGE_LEN 2
59 
60 #define	PPB_32BIT_IO 1
61 #define	PPB_32bit_MEM 1
62 
63 #define	PPB_MEMGRAIN 0x100000
64 #define	PPB_IOGRAIN 0x1000
65 
66 #define	PPB_16bit_IOADDR(addr) ((uint16_t)(((uint8_t)(addr) & 0xF0) << 8))
67 #define	PPB_LADDR(lo, hi) (((uint16_t)(hi) << 16) | (uint16_t)(lo))
68 #define	PPB_32bit_MEMADDR(addr) (PPB_LADDR(0, ((uint16_t)(addr) & 0xFFF0)))
69 
70 typedef struct	slot_table {
71 	uchar_t		bus_id[128];
72 	uchar_t		slot_name[32];
73 	uint8_t		device_no;
74 	uint8_t		phys_slot_num;
75 } slot_table_t;
76 
77 /*
78  * The variable controls the default setting of the command register
79  * for pci devices.  See ppb_initchild() for details.
80  */
81 static ushort_t ppb_command_default = PCI_COMM_SERR_ENABLE |
82 					PCI_COMM_WAIT_CYC_ENAB |
83 					PCI_COMM_PARITY_DETECT |
84 					PCI_COMM_ME |
85 					PCI_COMM_MAE |
86 					PCI_COMM_IO;
87 
88 static int ppb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *,
89 	off_t, off_t, caddr_t *);
90 static int ppb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t,
91 	void *, void *);
92 static int ppb_intr_ops(dev_info_t *dip, dev_info_t *rdip,
93 	ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result);
94 
95 /*
96  * fm_init busop to initialize our children
97  */
98 static int ppb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap,
99 		ddi_iblock_cookie_t *ibc);
100 static void ppb_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle);
101 static void ppb_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle);
102 static int ppb_bus_power(dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op,
103     void *arg, void *result);
104 
105 struct bus_ops ppb_bus_ops = {
106 	BUSO_REV,
107 	ppb_bus_map,
108 	0,
109 	0,
110 	0,
111 	i_ddi_map_fault,
112 	ddi_dma_map,
113 	ddi_dma_allochdl,
114 	ddi_dma_freehdl,
115 	ddi_dma_bindhdl,
116 	ddi_dma_unbindhdl,
117 	ddi_dma_flush,
118 	ddi_dma_win,
119 	ddi_dma_mctl,
120 	ppb_ctlops,
121 	ddi_bus_prop_op,
122 	ndi_busop_get_eventcookie,	/* (*bus_get_eventcookie)();    */
123 	ndi_busop_add_eventcall,	/* (*bus_add_eventcall)();	*/
124 	ndi_busop_remove_eventcall,	/* (*bus_remove_eventcall)();   */
125 	ndi_post_event,			/* (*bus_post_event)();		*/
126 	0,				/* (*bus_intr_ctl)();		*/
127 	0,				/* (*bus_config)(); 		*/
128 	0,				/* (*bus_unconfig)(); 		*/
129 	ppb_fm_init_child,		/* (*bus_fm_init)(); 		*/
130 	NULL,				/* (*bus_fm_fini)(); 		*/
131 	ppb_bus_enter,			/* (*bus_enter)()		*/
132 	ppb_bus_exit,			/* (*bus_exit)()		*/
133 	ppb_bus_power,			/* (*bus_power)()		*/
134 	ppb_intr_ops			/* (*bus_intr_op)(); 		*/
135 };
136 
137 static int ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp);
138 static int ppb_close(dev_t dev, int flags, int otyp, cred_t *credp);
139 static int ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode,
140 						cred_t *credp, int *rvalp);
141 static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
142     int flags, char *name, caddr_t valuep, int *lengthp);
143 
144 static struct cb_ops ppb_cb_ops = {
145 	ppb_open,			/* open */
146 	ppb_close,			/* close */
147 	nulldev,			/* strategy */
148 	nulldev,			/* print */
149 	nulldev,			/* dump */
150 	nulldev,			/* read */
151 	nulldev,			/* write */
152 	ppb_ioctl,			/* ioctl */
153 	nodev,				/* devmap */
154 	nodev,				/* mmap */
155 	nodev,				/* segmap */
156 	nochpoll,			/* poll */
157 	ppb_prop_op,			/* cb_prop_op */
158 	NULL,				/* streamtab */
159 	D_NEW | D_MP | D_HOTPLUG,	/* Driver compatibility flag */
160 	CB_REV,				/* rev */
161 	nodev,				/* int (*cb_aread)() */
162 	nodev				/* int (*cb_awrite)() */
163 };
164 
165 static int ppb_probe(dev_info_t *);
166 static int ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd);
167 static int ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
168 static int ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd,
169     void *arg, void **result);
170 static int ppb_pwr(dev_info_t *dip, int component, int level);
171 
172 struct dev_ops ppb_ops = {
173 	DEVO_REV,		/* devo_rev */
174 	0,			/* refcnt  */
175 	ppb_info,		/* info */
176 	nulldev,		/* identify */
177 	ppb_probe,		/* probe */
178 	ppb_attach,		/* attach */
179 	ppb_detach,		/* detach */
180 	nulldev,		/* reset */
181 	&ppb_cb_ops,		/* driver operations */
182 	&ppb_bus_ops,		/* bus operations */
183 	ppb_pwr
184 };
185 
186 /*
187  * Module linkage information for the kernel.
188  */
189 
190 static struct modldrv modldrv = {
191 	&mod_driverops, /* Type of module */
192 	"Standard PCI to PCI bridge nexus driver %I%",
193 	&ppb_ops,	/* driver ops */
194 };
195 
196 static struct modlinkage modlinkage = {
197 	MODREV_1,
198 	(void *)&modldrv,
199 	NULL
200 };
201 
202 /*
203  * soft state pointer and structure template:
204  */
205 static void *ppb_state;
206 
207 struct ppb_cfg_state {
208 	dev_info_t *dip;
209 	ushort_t command;
210 	uchar_t cache_line_size;
211 	uchar_t latency_timer;
212 	uchar_t header_type;
213 	uchar_t sec_latency_timer;
214 	ushort_t bridge_control;
215 };
216 
217 typedef struct {
218 
219 	dev_info_t *dip;
220 
221 	/*
222 	 * configuration register state for the bus:
223 	 */
224 	uchar_t ppb_cache_line_size;
225 	uchar_t ppb_latency_timer;
226 
227 	/*
228 	 * PM support
229 	 */
230 	ddi_acc_handle_t	ppb_conf_hdl;
231 	uint16_t		ppb_pm_cap_ptr;
232 	pci_pwr_t		*ppb_pwr_p;
233 
234 	/*
235 	 * HP support
236 	 */
237 	boolean_t		hotplug_capable;
238 
239 	kmutex_t ppb_mutex;
240 	uint_t ppb_soft_state;
241 #define	PPB_SOFT_STATE_CLOSED		0x00
242 #define	PPB_SOFT_STATE_OPEN		0x01
243 #define	PPB_SOFT_STATE_OPEN_EXCL	0x02
244 	int fm_cap;
245 	ddi_iblock_cookie_t fm_ibc;
246 
247 	uint8_t parent_bus;
248 } ppb_devstate_t;
249 
250 /*
251  * The following variable enables a workaround for the following obp bug:
252  *
253  *	1234181 - obp should set latency timer registers in pci
254  *		configuration header
255  *
256  * Until this bug gets fixed in the obp, the following workaround should
257  * be enabled.
258  */
259 static uint_t ppb_set_latency_timer_register = 1;
260 
261 /*
262  * The following variable enables a workaround for an obp bug to be
263  * submitted.  A bug requesting a workaround fof this problem has
264  * been filed:
265  *
266  *	1235094 - need workarounds on positron nexus drivers to set cache
267  *		line size registers
268  *
269  * Until this bug gets fixed in the obp, the following workaround should
270  * be enabled.
271  */
272 static uint_t ppb_set_cache_line_size_register = 1;
273 
274 /*
275  * forward function declarations:
276  */
277 
278 /*
279  * FMA error callback
280  * Register error handling callback with our parent. We will just call
281  * our children's error callbacks and return their status.
282  */
283 static int ppb_err_callback(dev_info_t *dip, ddi_fm_error_t *derr,
284 		const void *impl_data);
285 
286 /*
287  * init/fini routines to alloc/dealloc fm structures and
288  * register/unregister our callback.
289  */
290 static void ppb_fm_init(ppb_devstate_t *ppb_p);
291 static void ppb_fm_fini(ppb_devstate_t *ppb_p);
292 
293 static void ppb_removechild(dev_info_t *);
294 static int ppb_initchild(dev_info_t *child);
295 static void ppb_uninitchild(dev_info_t *child);
296 static dev_info_t *get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip);
297 static void ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *dip);
298 static void ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip);
299 static void ppb_init_hotplug(ppb_devstate_t *ppb);
300 static void ppb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t);
301 uint64_t pci_debug_flags = 0;
302 
303 int
304 _init(void)
305 {
306 	int e;
307 	if ((e = ddi_soft_state_init(&ppb_state, sizeof (ppb_devstate_t),
308 	    1)) == 0 && (e = mod_install(&modlinkage)) != 0)
309 		ddi_soft_state_fini(&ppb_state);
310 	return (e);
311 }
312 
313 int
314 _fini(void)
315 {
316 	int e;
317 
318 	if ((e = mod_remove(&modlinkage)) == 0)
319 		ddi_soft_state_fini(&ppb_state);
320 	return (e);
321 }
322 
323 int
324 _info(struct modinfo *modinfop)
325 {
326 	return (mod_info(&modlinkage, modinfop));
327 }
328 
329 /*ARGSUSED*/
330 static int
331 ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
332 {
333 	ppb_devstate_t *ppb_p;	/* per ppb state pointer */
334 	minor_t		minor = getminor((dev_t)arg);
335 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
336 
337 	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
338 	    instance);
339 
340 	switch (infocmd) {
341 	default:
342 		return (DDI_FAILURE);
343 
344 	case DDI_INFO_DEVT2INSTANCE:
345 		*result = (void *)(uintptr_t)instance;
346 		return (DDI_SUCCESS);
347 
348 	case DDI_INFO_DEVT2DEVINFO:
349 		if (ppb_p == NULL)
350 			return (DDI_FAILURE);
351 		*result = (void *)ppb_p->dip;
352 		return (DDI_SUCCESS);
353 	}
354 }
355 
356 /*ARGSUSED*/
357 static int
358 ppb_probe(register dev_info_t *devi)
359 {
360 	return (DDI_PROBE_SUCCESS);
361 }
362 
363 /*ARGSUSED*/
364 static int
365 ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
366 {
367 	int instance;
368 	ppb_devstate_t *ppb;
369 	ddi_acc_handle_t config_handle;
370 
371 	switch (cmd) {
372 	case DDI_ATTACH:
373 
374 		/*
375 		 * Make sure the "device_type" property exists.
376 		 */
377 		(void) ddi_prop_update_string(DDI_DEV_T_NONE, devi,
378 		    "device_type", "pci");
379 
380 		/*
381 		 * Allocate and get soft state structure.
382 		 */
383 		instance = ddi_get_instance(devi);
384 		if (ddi_soft_state_zalloc(ppb_state, instance) != DDI_SUCCESS)
385 			return (DDI_FAILURE);
386 		ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, instance);
387 		ppb->dip = devi;
388 		mutex_init(&ppb->ppb_mutex, NULL, MUTEX_DRIVER, NULL);
389 		ppb->ppb_soft_state = PPB_SOFT_STATE_CLOSED;
390 		if (pci_config_setup(devi, &config_handle) != DDI_SUCCESS) {
391 			mutex_destroy(&ppb->ppb_mutex);
392 			ddi_soft_state_free(ppb_state, instance);
393 			return (DDI_FAILURE);
394 		}
395 		ppb_pwr_setup(ppb, devi);
396 
397 		if (PM_CAPABLE(ppb->ppb_pwr_p)) {
398 			mutex_enter(&ppb->ppb_pwr_p->pwr_mutex);
399 
400 			/*
401 			 * Before reading config registers, make sure power is
402 			 * on, and remains on.
403 			 */
404 			ppb->ppb_pwr_p->pwr_fp++;
405 
406 			pci_pwr_change(ppb->ppb_pwr_p,
407 			    ppb->ppb_pwr_p->current_lvl,
408 			    pci_pwr_new_lvl(ppb->ppb_pwr_p));
409 		}
410 
411 		ppb->ppb_cache_line_size =
412 		    pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ);
413 		ppb->ppb_latency_timer =
414 		    pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER);
415 
416 		/*
417 		 * Check whether the "ranges" property is present.
418 		 * Otherwise create the ranges property by reading
419 		 * the configuration registers
420 		 */
421 		if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS,
422 		    "ranges") == 0) {
423 			ppb_create_ranges_prop(devi, config_handle);
424 		}
425 
426 		pci_config_teardown(&config_handle);
427 
428 		if (PM_CAPABLE(ppb->ppb_pwr_p)) {
429 			ppb->ppb_pwr_p->pwr_fp--;
430 
431 			pci_pwr_change(ppb->ppb_pwr_p,
432 			    ppb->ppb_pwr_p->current_lvl,
433 			    pci_pwr_new_lvl(ppb->ppb_pwr_p));
434 
435 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
436 		}
437 
438 		/*
439 		 * Initialize hotplug support on this bus. At minimum
440 		 * (for non hotplug bus) this would create ":devctl" minor
441 		 * node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls
442 		 * to this bus. This all takes place if this nexus has hot-plug
443 		 * slots and successfully initializes Hot Plug Framework.
444 		 */
445 		ppb->hotplug_capable = B_FALSE;
446 		ppb_init_hotplug(ppb);
447 		if (ppb->hotplug_capable == B_FALSE) {
448 			/*
449 			 * create minor node for devctl interfaces
450 			 */
451 			if (ddi_create_minor_node(devi, "devctl", S_IFCHR,
452 			    PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR),
453 			    DDI_NT_NEXUS, 0) != DDI_SUCCESS) {
454 				if (ppb->ppb_pwr_p != NULL) {
455 					ppb_pwr_teardown(ppb, devi);
456 				}
457 				mutex_destroy(&ppb->ppb_mutex);
458 				ddi_soft_state_free(ppb_state, instance);
459 				return (DDI_FAILURE);
460 			}
461 		}
462 
463 		DEBUG1(DBG_ATTACH, devi,
464 			"ppb_attach(): this nexus %s hotplug slots\n",
465 			ppb->hotplug_capable == B_TRUE ? "has":"has no");
466 
467 		ppb_fm_init(ppb);
468 		ddi_report_dev(devi);
469 
470 		return (DDI_SUCCESS);
471 
472 	case DDI_RESUME:
473 		/*
474 		 * Get the soft state structure for the bridge.
475 		 */
476 		ppb = (ppb_devstate_t *)
477 			ddi_get_soft_state(ppb_state, ddi_get_instance(devi));
478 
479 		pci_pwr_resume(devi, ppb->ppb_pwr_p);
480 
481 		return (DDI_SUCCESS);
482 	}
483 	return (DDI_FAILURE);
484 }
485 
486 /*ARGSUSED*/
487 static int
488 ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
489 {
490 	ppb_devstate_t *ppb;
491 
492 	switch (cmd) {
493 	case DDI_DETACH:
494 		/*
495 		 * And finally free the per-pci soft state after
496 		 * uninitializing hotplug support for this bus.
497 		 */
498 		ppb = (ppb_devstate_t *)
499 		    ddi_get_soft_state(ppb_state, ddi_get_instance(devi));
500 
501 		ppb_fm_fini(ppb);
502 
503 		if (ppb->hotplug_capable == B_TRUE)
504 			if (pcihp_uninit(devi) == DDI_FAILURE)
505 				return (DDI_FAILURE);
506 		else
507 			ddi_remove_minor_node(devi, "devctl");
508 
509 		(void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type");
510 
511 		if (ppb->ppb_pwr_p != NULL) {
512 			ppb_pwr_teardown(ppb, devi);
513 		}
514 		mutex_destroy(&ppb->ppb_mutex);
515 		ddi_soft_state_free(ppb_state, ddi_get_instance(devi));
516 
517 		return (DDI_SUCCESS);
518 
519 	case DDI_SUSPEND:
520 		ppb = (ppb_devstate_t *)
521 			ddi_get_soft_state(ppb_state, ddi_get_instance(devi));
522 
523 		pci_pwr_suspend(devi, ppb->ppb_pwr_p);
524 
525 		return (DDI_SUCCESS);
526 	}
527 	return (DDI_FAILURE);
528 }
529 
530 /*ARGSUSED*/
531 static int
532 ppb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
533 	off_t offset, off_t len, caddr_t *vaddrp)
534 {
535 	register dev_info_t *pdip;
536 
537 	pdip = (dev_info_t *)DEVI(dip)->devi_parent;
538 	return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)
539 	    (pdip, rdip, mp, offset, len, vaddrp));
540 }
541 
542 /*ARGSUSED*/
543 static int
544 ppb_ctlops(dev_info_t *dip, dev_info_t *rdip,
545 	ddi_ctl_enum_t ctlop, void *arg, void *result)
546 {
547 	pci_regspec_t *drv_regp;
548 	int	reglen;
549 	int	rn;
550 	struct	attachspec *as;
551 	struct	detachspec *ds;
552 	int	totreg;
553 	ppb_devstate_t *ppb_p;
554 
555 	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
556 	    ddi_get_instance(dip));
557 
558 	switch (ctlop) {
559 	case DDI_CTLOPS_REPORTDEV:
560 		if (rdip == (dev_info_t *)0)
561 			return (DDI_FAILURE);
562 		cmn_err(CE_CONT, "?PCI-device: %s@%s, %s%d\n",
563 		    ddi_node_name(rdip), ddi_get_name_addr(rdip),
564 		    ddi_driver_name(rdip),
565 		    ddi_get_instance(rdip));
566 		return (DDI_SUCCESS);
567 
568 	case DDI_CTLOPS_INITCHILD:
569 		return (ppb_initchild((dev_info_t *)arg));
570 
571 	case DDI_CTLOPS_UNINITCHILD:
572 		ppb_uninitchild((dev_info_t *)arg);
573 		return (DDI_SUCCESS);
574 
575 	case DDI_CTLOPS_ATTACH:
576 		if (!pcie_is_child(dip, rdip))
577 			return (DDI_SUCCESS);
578 
579 		as = (struct attachspec *)arg;
580 		if ((ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) &&
581 		    (as->when == DDI_POST))
582 			pf_init(rdip, ppb_p->fm_ibc);
583 
584 		return (DDI_SUCCESS);
585 
586 	case DDI_CTLOPS_DETACH:
587 		if (!pcie_is_child(dip, rdip))
588 			return (DDI_SUCCESS);
589 
590 		ds = (struct detachspec *)arg;
591 		if ((ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) &&
592 		    (ds->when == DDI_PRE))
593 			pf_fini(rdip);
594 
595 		return (DDI_SUCCESS);
596 
597 	case DDI_CTLOPS_SIDDEV:
598 		return (DDI_SUCCESS);
599 
600 	case DDI_CTLOPS_REGSIZE:
601 	case DDI_CTLOPS_NREGS:
602 		if (rdip == (dev_info_t *)0)
603 			return (DDI_FAILURE);
604 		break;
605 	default:
606 		return (ddi_ctlops(dip, rdip, ctlop, arg, result));
607 	}
608 
609 	*(int *)result = 0;
610 	if (ddi_getlongprop(DDI_DEV_T_ANY, rdip,
611 		DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg",
612 		(caddr_t)&drv_regp, &reglen) != DDI_SUCCESS)
613 		return (DDI_FAILURE);
614 
615 	totreg = reglen / sizeof (pci_regspec_t);
616 	if (ctlop == DDI_CTLOPS_NREGS)
617 		*(int *)result = totreg;
618 	else if (ctlop == DDI_CTLOPS_REGSIZE) {
619 		rn = *(int *)arg;
620 		if (rn >= totreg) {
621 			kmem_free(drv_regp, reglen);
622 			return (DDI_FAILURE);
623 		}
624 		*(off_t *)result = drv_regp[rn].pci_size_low |
625 			((uint64_t)drv_regp[rn].pci_size_hi << 32);
626 	}
627 
628 	kmem_free(drv_regp, reglen);
629 	return (DDI_SUCCESS);
630 }
631 
632 
633 static dev_info_t *
634 get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip)
635 {
636 	dev_info_t *cdip = rdip;
637 
638 	for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip))
639 		;
640 
641 	return (cdip);
642 }
643 
644 
645 static int
646 ppb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
647     ddi_intr_handle_impl_t *hdlp, void *result)
648 {
649 	dev_info_t	*cdip = rdip;
650 	pci_regspec_t	*pci_rp;
651 	int		reglen, len;
652 	uint32_t	d, intr;
653 
654 	if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
655 		goto done;
656 
657 	/*
658 	 * If the interrupt-map property is defined at this
659 	 * node, it will have performed the interrupt
660 	 * translation as part of the property, so no
661 	 * rotation needs to be done.
662 	 */
663 	if (ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
664 	    "interrupt-map", &len) == DDI_PROP_SUCCESS)
665 		goto done;
666 
667 	cdip = get_my_childs_dip(dip, rdip);
668 
669 	/*
670 	 * Use the devices reg property to determine its
671 	 * PCI bus number and device number.
672 	 */
673 	if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS,
674 	    "reg", (caddr_t)&pci_rp, &reglen) != DDI_SUCCESS)
675 		return (DDI_FAILURE);
676 
677 	intr = hdlp->ih_vector;
678 
679 	/* Spin the interrupt */
680 	d = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi);
681 
682 	if ((intr >= PCI_INTA) && (intr <= PCI_INTD))
683 		hdlp->ih_vector = ((intr - 1 + (d % 4)) % 4 + 1);
684 	else
685 		cmn_err(CE_WARN, "%s%d: %s: PCI intr=%x out of range",
686 		    ddi_driver_name(rdip), ddi_get_instance(rdip),
687 		    ddi_driver_name(dip), intr);
688 
689 	kmem_free(pci_rp, reglen);
690 
691 done:
692 	/* Pass up the request to our parent. */
693 	return (i_ddi_intr_ops(dip, rdip, intr_op, hdlp, result));
694 }
695 
696 static int
697 ppb_bus_power(dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op,
698     void *arg, void *result)
699 {
700 	ppb_devstate_t *ppb;
701 
702 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
703 	    ddi_get_instance(dip));
704 
705 	return (pci_pwr_ops(ppb->ppb_pwr_p, dip, impl_arg, op, arg, result));
706 }
707 
708 
709 /*
710  * name_child
711  *
712  * This function is called from init_child to name a node. It is
713  * also passed as a callback for node merging functions.
714  *
715  * return value: DDI_SUCCESS, DDI_FAILURE
716  */
717 static int
718 ppb_name_child(dev_info_t *child, char *name, int namelen)
719 {
720 	pci_regspec_t *pci_rp;
721 	uint_t slot, func;
722 	char **unit_addr;
723 	uint_t n;
724 
725 	/*
726 	 * Pseudo nodes indicate a prototype node with per-instance
727 	 * properties to be merged into the real h/w device node.
728 	 * The interpretation of the unit-address is DD[,F]
729 	 * where DD is the device id and F is the function.
730 	 */
731 	if (ndi_dev_is_persistent_node(child) == 0) {
732 		if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child,
733 		    DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) !=
734 		    DDI_PROP_SUCCESS) {
735 			cmn_err(CE_WARN, "cannot name node from %s.conf",
736 			    ddi_driver_name(child));
737 			return (DDI_FAILURE);
738 		}
739 		if (n != 1 || *unit_addr == NULL || **unit_addr == 0) {
740 			cmn_err(CE_WARN, "unit-address property in %s.conf"
741 			    " not well-formed", ddi_driver_name(child));
742 			ddi_prop_free(unit_addr);
743 			return (DDI_FAILURE);
744 		}
745 		(void) snprintf(name, namelen, "%s", *unit_addr);
746 		ddi_prop_free(unit_addr);
747 		return (DDI_SUCCESS);
748 	}
749 
750 	/*
751 	 * Get the address portion of the node name based on
752 	 * the function and device number.
753 	 */
754 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
755 	    "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) {
756 		return (DDI_FAILURE);
757 	}
758 
759 	slot = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi);
760 	func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi);
761 
762 	if (func != 0)
763 		(void) snprintf(name, namelen, "%x,%x", slot, func);
764 	else
765 		(void) snprintf(name, namelen, "%x", slot);
766 
767 	ddi_prop_free(pci_rp);
768 	return (DDI_SUCCESS);
769 }
770 
771 static int
772 ppb_initchild(dev_info_t *child)
773 {
774 	char name[MAXNAMELEN];
775 	ddi_acc_handle_t config_handle;
776 	ushort_t command_preserve, command;
777 	uint_t n;
778 	ushort_t bcr;
779 	uchar_t header_type;
780 	uchar_t min_gnt, latency_timer;
781 	ppb_devstate_t *ppb;
782 
783 	/*
784 	 * Name the child
785 	 */
786 	if (ppb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS)
787 		return (DDI_FAILURE);
788 
789 	ddi_set_name_addr(child, name);
790 	ddi_set_parent_data(child, NULL);
791 
792 	/*
793 	 * Pseudo nodes indicate a prototype node with per-instance
794 	 * properties to be merged into the real h/w device node.
795 	 * The interpretation of the unit-address is DD[,F]
796 	 * where DD is the device id and F is the function.
797 	 */
798 	if (ndi_dev_is_persistent_node(child) == 0) {
799 		extern int pci_allow_pseudo_children;
800 
801 		/*
802 		 * Try to merge the properties from this prototype
803 		 * node into real h/w nodes.
804 		 */
805 		if (ndi_merge_node(child, ppb_name_child) == DDI_SUCCESS) {
806 			/*
807 			 * Merged ok - return failure to remove the node.
808 			 */
809 			ppb_removechild(child);
810 			return (DDI_FAILURE);
811 		}
812 
813 		/* workaround for ddivs to run under PCI */
814 		if (pci_allow_pseudo_children)
815 			return (DDI_SUCCESS);
816 
817 		/*
818 		 * The child was not merged into a h/w node,
819 		 * but there's not much we can do with it other
820 		 * than return failure to cause the node to be removed.
821 		 */
822 		cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged",
823 		    ddi_driver_name(child), ddi_get_name_addr(child),
824 		    ddi_driver_name(child));
825 		ppb_removechild(child);
826 		return (DDI_NOT_WELL_FORMED);
827 	}
828 
829 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
830 	    ddi_get_instance(ddi_get_parent(child)));
831 
832 	ddi_set_parent_data(child, NULL);
833 
834 	/*
835 	 * If hardware is PM capable, set up the power info structure.
836 	 * This also ensures the the bus will not be off (0MHz) otherwise
837 	 * system panics during a bus access.
838 	 */
839 	if (PM_CAPABLE(ppb->ppb_pwr_p)) {
840 		/*
841 		 * Create a pwr_info struct for child.  Bus will be
842 		 * at full speed after creating info.
843 		 */
844 		pci_pwr_create_info(ppb->ppb_pwr_p, child);
845 #ifdef DEBUG
846 		ASSERT(ppb->ppb_pwr_p->current_lvl == PM_LEVEL_B0);
847 #endif
848 	}
849 
850 	/*
851 	 * If configuration registers were previously saved by
852 	 * child (before it entered D3), then let the child do the
853 	 * restore to set up the config regs as it'll first need to
854 	 * power the device out of D3.
855 	 */
856 	if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
857 	    "config-regs-saved-by-child") == 1) {
858 		DEBUG2(DBG_PWR, ddi_get_parent(child),
859 			"INITCHILD: config regs to be restored by child"
860 			" for %s@%s\n", ddi_node_name(child),
861 				ddi_get_name_addr(child));
862 
863 		return (DDI_SUCCESS);
864 	}
865 
866 	DEBUG2(DBG_PWR, ddi_get_parent(child),
867 	    "INITCHILD: config regs setup for %s@%s\n",
868 	    ddi_node_name(child), ddi_get_name_addr(child));
869 
870 	if (pci_config_setup(child, &config_handle) != DDI_SUCCESS) {
871 		if (PM_CAPABLE(ppb->ppb_pwr_p)) {
872 			pci_pwr_rm_info(ppb->ppb_pwr_p, child);
873 		}
874 
875 		return (DDI_FAILURE);
876 	}
877 
878 	/*
879 	 * Determine the configuration header type.
880 	 */
881 	header_type = pci_config_get8(config_handle, PCI_CONF_HEADER);
882 
883 	/*
884 	 * Support for the "command-preserve" property.
885 	 */
886 	command_preserve = ddi_prop_get_int(DDI_DEV_T_ANY, child,
887 		DDI_PROP_DONTPASS, "command-preserve", 0);
888 	command = pci_config_get16(config_handle, PCI_CONF_COMM);
889 	command &= (command_preserve | PCI_COMM_BACK2BACK_ENAB);
890 	command |= (ppb_command_default & ~command_preserve);
891 	pci_config_put16(config_handle, PCI_CONF_COMM, command);
892 
893 	/*
894 	 * If the device has a bus control register then program it
895 	 * based on the settings in the command register.
896 	 */
897 	if ((header_type  & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) {
898 		bcr = pci_config_get8(config_handle, PCI_BCNF_BCNTRL);
899 		if (ppb_command_default & PCI_COMM_PARITY_DETECT)
900 			bcr |= PCI_BCNF_BCNTRL_PARITY_ENABLE;
901 		if (ppb_command_default & PCI_COMM_SERR_ENABLE)
902 			bcr |= PCI_BCNF_BCNTRL_SERR_ENABLE;
903 		bcr |= PCI_BCNF_BCNTRL_MAST_AB_MODE;
904 		pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr);
905 	}
906 
907 	/*
908 	 * Initialize cache-line-size configuration register if needed.
909 	 */
910 	if (ppb_set_cache_line_size_register &&
911 	    ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
912 		"cache-line-size", 0) == 0) {
913 		pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ,
914 			ppb->ppb_cache_line_size);
915 		n = pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ);
916 		if (n != 0) {
917 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, child,
918 					"cache-line-size", n);
919 		}
920 	}
921 
922 	/*
923 	 * Initialize latency timer configuration registers if needed.
924 	 */
925 	if (ppb_set_latency_timer_register &&
926 	    ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
927 		"latency-timer", 0) == 0) {
928 
929 		if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) {
930 			latency_timer = ppb->ppb_latency_timer;
931 			pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER,
932 				ppb->ppb_latency_timer);
933 		} else {
934 			min_gnt = pci_config_get8(config_handle,
935 				PCI_CONF_MIN_G);
936 			latency_timer = min_gnt * 8;
937 		}
938 		pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER,
939 			latency_timer);
940 		n = pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER);
941 		if (n != 0) {
942 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, child,
943 					"latency-timer", n);
944 		}
945 	}
946 
947 	/*
948 	 * SPARC PCIe FMA specific
949 	 *
950 	 * Note: parent_data for parent is created only if this is sparc PCI-E
951 	 * platform, for which, SG take a different route to handle device
952 	 * errors.
953 	 */
954 	if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) {
955 		if (pcie_init_ppd(child) == NULL) {
956 			pci_config_teardown(&config_handle);
957 			return (DDI_FAILURE);
958 		}
959 	}
960 
961 	/*
962 	 * Check to see if the XMITS/PCI-X workaround applies.
963 	 */
964 	n = ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_NOTPROM,
965 	    "pcix-update-cmd-reg", -1);
966 
967 	if (n != -1) {
968 		extern void pcix_set_cmd_reg(dev_info_t *child, uint16_t value);
969 		DEBUG1(DBG_INIT_CLD, child, "Turning on XMITS NCPQ "
970 		    "Workaround: value = %x\n", n);
971 		pcix_set_cmd_reg(child, n);
972 	}
973 	pci_config_teardown(&config_handle);
974 	return (DDI_SUCCESS);
975 }
976 
977 static void
978 ppb_uninitchild(dev_info_t *child)
979 {
980 	ppb_devstate_t *ppb;
981 
982 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
983 	    ddi_get_instance(ddi_get_parent(child)));
984 
985 	/*
986 	 * SG OPL FMA specific
987 	 */
988 	if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
989 		pcie_uninit_ppd(child);
990 
991 	ppb_removechild(child);
992 }
993 
994 static void
995 ppb_removechild(dev_info_t *dip)
996 {
997 	ppb_devstate_t *ppb;
998 
999 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1000 	    ddi_get_instance(ddi_get_parent(dip)));
1001 
1002 	if (PM_CAPABLE(ppb->ppb_pwr_p)) {
1003 
1004 		DEBUG2(DBG_PWR, ddi_get_parent(dip),
1005 		    "UNINITCHILD: removing pwr_info for %s@%s\n",
1006 		    ddi_node_name(dip), ddi_get_name_addr(dip));
1007 		pci_pwr_rm_info(ppb->ppb_pwr_p, dip);
1008 	}
1009 
1010 	ddi_set_name_addr(dip, NULL);
1011 
1012 	/*
1013 	 * Strip the node to properly convert it back to prototype form
1014 	 */
1015 	ddi_remove_minor_node(dip, NULL);
1016 
1017 	impl_rem_dev_props(dip);
1018 }
1019 
1020 /*
1021  * If bridge is PM capable, set up PM state for nexus.
1022  */
1023 static void
1024 ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *pdip)
1025 {
1026 	char *comp_array[5];
1027 	int i;
1028 	ddi_acc_handle_t conf_hdl;
1029 	uint8_t pmcsr_bse;
1030 	uint16_t pmcap;
1031 
1032 	/*
1033 	 * Determine if bridge is PM capable.  If not, leave ppb_pwr_p NULL
1034 	 * and return.
1035 	 */
1036 	if (pci_config_setup(pdip, &ppb->ppb_conf_hdl) != DDI_SUCCESS) {
1037 
1038 		return;
1039 	}
1040 
1041 	conf_hdl = ppb->ppb_conf_hdl;
1042 
1043 	/*
1044 	 * Locate and store the power management cap_ptr for future references.
1045 	 */
1046 	if ((PCI_CAP_LOCATE(conf_hdl, PCI_CAP_ID_PM, &ppb->ppb_pm_cap_ptr))
1047 		== DDI_FAILURE) {
1048 		DEBUG0(DBG_PWR, pdip, "bridge does not support PM. PCI"
1049 		    " PM data structure not found in config header\n");
1050 		pci_config_teardown(&conf_hdl);
1051 
1052 		return;
1053 	}
1054 
1055 	/*
1056 	 * Allocate PM state structure for ppb.
1057 	 */
1058 	ppb->ppb_pwr_p = (pci_pwr_t *)
1059 	    kmem_zalloc(sizeof (pci_pwr_t), KM_SLEEP);
1060 	ppb->ppb_pwr_p->pwr_fp = 0;
1061 
1062 	pmcsr_bse = PCI_CAP_GET8(conf_hdl, NULL, ppb->ppb_pm_cap_ptr,
1063 		PCI_PMCSR_BSE);
1064 
1065 	pmcap = PCI_CAP_GET16(conf_hdl, NULL, ppb->ppb_pm_cap_ptr,
1066 		PCI_PMCAP);
1067 
1068 	if (pmcap == PCI_CAP_EINVAL16 || pmcsr_bse == PCI_CAP_EINVAL8) {
1069 		pci_config_teardown(&conf_hdl);
1070 		return;
1071 	}
1072 
1073 	if (pmcap & PCI_PMCAP_D1) {
1074 		DEBUG0(DBG_PWR, pdip, "setup: B1 state supported\n");
1075 		ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B1_CAPABLE;
1076 	} else {
1077 		DEBUG0(DBG_PWR, pdip, "setup: B1 state NOT supported\n");
1078 	}
1079 	if (pmcap & PCI_PMCAP_D2) {
1080 		DEBUG0(DBG_PWR, pdip, "setup: B2 state supported\n");
1081 		ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE;
1082 	} else {
1083 		DEBUG0(DBG_PWR, pdip, "setup: B2 via D2 NOT supported\n");
1084 	}
1085 
1086 	if (pmcsr_bse & PCI_PMCSR_BSE_BPCC_EN) {
1087 		DEBUG0(DBG_PWR, pdip,
1088 		"setup: bridge power/clock control enable\n");
1089 	} else {
1090 		DEBUG0(DBG_PWR, pdip,
1091 		"setup: bridge power/clock control disabled\n");
1092 
1093 		kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t));
1094 		ppb->ppb_pwr_p = NULL;
1095 		pci_config_teardown(&conf_hdl);
1096 
1097 		return;
1098 	}
1099 
1100 	/*
1101 	 * PCI states D0 and D3 always are supported for normal PCI
1102 	 * devices.  D1 and D2 are optional which are checked for above.
1103 	 * Bridge function states D0-D3 correspond to secondary bus states
1104 	 * B0-B3, EXCEPT if PCI_PMCSR_BSE_B2_B3 is set.  In this case, setting
1105 	 * the bridge function to D3 will set the bridge bus to state B2 instead
1106 	 * of B3.  D2 will not correspond to B2 (and in fact, probably
1107 	 * won't be D2 capable).  Implicitly, this means that if
1108 	 * PCI_PMCSR_BSE_B2_B3 is set, the bus will not be B3 capable.
1109 	 */
1110 	if (pmcsr_bse & PCI_PMCSR_BSE_B2_B3) {
1111 		ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE;
1112 		DEBUG0(DBG_PWR, pdip, "B2 supported via D3\n");
1113 	} else {
1114 		ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B3_CAPABLE;
1115 		DEBUG0(DBG_PWR, pdip, "B3 supported via D3\n");
1116 	}
1117 
1118 	ppb->ppb_pwr_p->pwr_dip = pdip;
1119 	mutex_init(&ppb->ppb_pwr_p->pwr_mutex, NULL, MUTEX_DRIVER, NULL);
1120 
1121 	i = 0;
1122 	comp_array[i++] = "NAME=PCI bridge PM";
1123 	if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) {
1124 		comp_array[i++] = "0=Clock/Power Off (B3)";
1125 	}
1126 	if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) {
1127 		comp_array[i++] = "1=Clock Off (B2)";
1128 	}
1129 	if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) {
1130 		comp_array[i++] = "2=Bus Inactive (B1)";
1131 	}
1132 	comp_array[i++] = "3=Full Power (B0)";
1133 
1134 	/*
1135 	 * Create pm-components property. It does not already exist.
1136 	 */
1137 	if (ddi_prop_update_string_array(DDI_DEV_T_NONE, pdip,
1138 	    "pm-components", comp_array, i) != DDI_PROP_SUCCESS) {
1139 		cmn_err(CE_WARN,
1140 		    "%s%d pm-components prop update failed",
1141 		    ddi_driver_name(pdip), ddi_get_instance(pdip));
1142 		pci_config_teardown(&conf_hdl);
1143 		mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex);
1144 		kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t));
1145 		ppb->ppb_pwr_p = NULL;
1146 
1147 		return;
1148 	}
1149 
1150 	if (ddi_prop_create(DDI_DEV_T_NONE, pdip, DDI_PROP_CANSLEEP,
1151 	    "pm-want-child-notification?", NULL, NULL) != DDI_PROP_SUCCESS) {
1152 		cmn_err(CE_WARN,
1153 			"%s%d fail to create pm-want-child-notification? prop",
1154 			ddi_driver_name(pdip), ddi_get_instance(pdip));
1155 
1156 		(void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, "pm-components");
1157 		pci_config_teardown(&conf_hdl);
1158 		mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex);
1159 		kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t));
1160 		ppb->ppb_pwr_p = NULL;
1161 
1162 		return;
1163 	}
1164 
1165 	ppb->ppb_pwr_p->current_lvl =
1166 		pci_pwr_current_lvl(ppb->ppb_pwr_p);
1167 }
1168 
1169 /*
1170  * Remove PM state for nexus.
1171  */
1172 static void
1173 ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip)
1174 {
1175 	int low_lvl;
1176 
1177 	/*
1178 	 * Determine the lowest power level supported.
1179 	 */
1180 	if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) {
1181 		low_lvl = PM_LEVEL_B3;
1182 	} else {
1183 		low_lvl = PM_LEVEL_B2;
1184 	}
1185 
1186 	if (pm_lower_power(dip, PCI_PM_COMP_0, low_lvl) != DDI_SUCCESS) {
1187 		cmn_err(CE_WARN, "%s%d failed to lower power",
1188 		    ddi_driver_name(dip), ddi_get_instance(dip));
1189 	}
1190 
1191 	pci_config_teardown(&ppb->ppb_conf_hdl);
1192 	mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex);
1193 	kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t));
1194 
1195 	if (ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components") !=
1196 		DDI_PROP_SUCCESS) {
1197 		cmn_err(CE_WARN, "%s%d unable to remove prop pm-components",
1198 		    ddi_driver_name(dip), ddi_get_instance(dip));
1199 	}
1200 
1201 	if (ddi_prop_remove(DDI_DEV_T_NONE, dip,
1202 	    "pm-want-child-notification?") != DDI_PROP_SUCCESS) {
1203 		cmn_err(CE_WARN,
1204 		    "%s%d unable to remove prop pm-want_child_notification?",
1205 		    ddi_driver_name(dip), ddi_get_instance(dip));
1206 	}
1207 }
1208 
1209 /*
1210  * Examine the pmcsr register and return the software defined
1211  * state (the difference being whether D3 means B2 or B3).
1212  */
1213 int
1214 pci_pwr_current_lvl(pci_pwr_t *pwr_p)
1215 {
1216 	ppb_devstate_t *ppb;
1217 	uint16_t pmcsr;
1218 
1219 	/*
1220 	 * Find out current power level
1221 	 */
1222 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1223 	    ddi_get_instance(pwr_p->pwr_dip));
1224 
1225 	if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, NULL,
1226 		ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == PCI_CAP_EINVAL16)
1227 		return (DDI_FAILURE);
1228 
1229 	switch (pmcsr & PCI_PMCSR_STATE_MASK) {
1230 	case PCI_PMCSR_D0:
1231 
1232 		return (PM_LEVEL_B0);
1233 	case PCI_PMCSR_D1:
1234 
1235 		return (PM_LEVEL_B1);
1236 	case PCI_PMCSR_D2:
1237 
1238 		return (PM_LEVEL_B2);
1239 	case PCI_PMCSR_D3HOT:
1240 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) {
1241 
1242 			return (PM_LEVEL_B2);
1243 		} else {
1244 
1245 			return (PM_LEVEL_B3);
1246 		}
1247 	}
1248 	/*NOTREACHED*/
1249 	return (PM_LEVEL_B3);
1250 }
1251 
1252 /*
1253  * Power entry point.  Called by the PM framework to change the
1254  * current power state of the bus.  This function must first verify that
1255  * the requested power change is still valid.
1256  */
1257 /*ARGSUSED*/
1258 static int
1259 ppb_pwr(dev_info_t *dip, int component, int lvl)
1260 {
1261 	ppb_devstate_t *ppb;
1262 	uint16_t pmcsr;
1263 	char *str;
1264 	int lowest_lvl;
1265 	int old_lvl;
1266 	int new_lvl;
1267 
1268 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1269 	    ddi_get_instance(dip));
1270 	if (ppb == NULL) {
1271 		cmn_err(CE_WARN, "%s%d ppb_pwr: can't get soft state",
1272 		    ddi_driver_name(dip), ddi_get_instance(dip));
1273 
1274 		return (DDI_FAILURE);
1275 	}
1276 
1277 	DEBUG1(DBG_PWR, dip, "ppb_pwr(): ENTER level = %d\n", lvl);
1278 
1279 	mutex_enter(&ppb->ppb_pwr_p->pwr_mutex);
1280 
1281 	/*
1282 	 * Find out if the power setting is possible.  If it is not,
1283 	 * set component busy and return failure.  If it is possible,
1284 	 * and it is the lowest pwr setting possible, set component
1285 	 * busy so that the framework does not try to lower any further.
1286 	 */
1287 	lowest_lvl = pci_pwr_new_lvl(ppb->ppb_pwr_p);
1288 	if (lowest_lvl > lvl) {
1289 		pci_pwr_component_busy(ppb->ppb_pwr_p);
1290 		DEBUG2(DBG_PWR, dip, "ppb_pwr: failing power request "
1291 			"lowest allowed is %d requested is %d\n",
1292 				lowest_lvl, lvl);
1293 		mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1294 
1295 		return (DDI_FAILURE);
1296 	} else if (lowest_lvl == lvl) {
1297 		pci_pwr_component_busy(ppb->ppb_pwr_p);
1298 	} else {
1299 		pci_pwr_component_idle(ppb->ppb_pwr_p);
1300 	}
1301 
1302 	if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, NULL,
1303 		ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == PCI_CAP_EINVAL16)
1304 		return (DDI_FAILURE);
1305 
1306 	/*
1307 	 * Save the current power level.  This is the actual function level,
1308 	 * not the translated bridge level stored in pwr_p->current_lvl
1309 	 */
1310 	old_lvl = pmcsr & PCI_PMCSR_STATE_MASK;
1311 
1312 	pmcsr &= ~PCI_PMCSR_STATE_MASK;
1313 	switch (lvl) {
1314 	case PM_LEVEL_B0:
1315 		str = "PM_LEVEL_B0 (full speed)";
1316 		pmcsr |= PCI_PMCSR_D0;
1317 		break;
1318 	case PM_LEVEL_B1:
1319 		str = "PM_LEVEL_B1 (light sleep. No bus traffic allowed)";
1320 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) == 0) {
1321 			cmn_err(CE_WARN, "%s%d PCI PM state B1 not supported",
1322 			    ddi_driver_name(dip), ddi_get_instance(dip));
1323 
1324 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1325 			return (DDI_FAILURE);
1326 		}
1327 		pmcsr |= PCI_PMCSR_D1;
1328 		break;
1329 	case PM_LEVEL_B2:
1330 		str = "PM_LEVEL_B2 (clock off)";
1331 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) == 0) {
1332 			cmn_err(CE_WARN, "%s%d PM state B2 not supported...",
1333 			    ddi_driver_name(dip),
1334 			    ddi_get_instance(dip));
1335 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1336 
1337 			return (DDI_FAILURE);
1338 		}
1339 
1340 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) {
1341 			/*
1342 			 * If B3 isn't supported, use D3 for B2 to avoid the
1343 			 * possible case that D2 for B2 isn't supported.
1344 			 * Saves and extra check and state flag..
1345 			 */
1346 			pmcsr |= PCI_PMCSR_D3HOT;
1347 		} else {
1348 			pmcsr |= PCI_PMCSR_D2;
1349 		}
1350 		break;
1351 	case PM_LEVEL_B3:
1352 		str = "PM_LEVEL_B30 (clock and power off)";
1353 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) {
1354 			cmn_err(CE_WARN, "%s%d PM state B3 not supported...",
1355 			    ddi_driver_name(dip),
1356 			    ddi_get_instance(dip));
1357 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1358 
1359 			return (DDI_FAILURE);
1360 		}
1361 		pmcsr |= PCI_PMCSR_D3HOT;
1362 
1363 		break;
1364 
1365 	default:
1366 		cmn_err(CE_WARN, "%s%d Unknown PM state %d",
1367 		    ddi_driver_name(dip), ddi_get_instance(dip), lvl);
1368 		mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1369 
1370 		return (DDI_FAILURE);
1371 	}
1372 
1373 	new_lvl = pmcsr & PCI_PMCSR_STATE_MASK;
1374 
1375 	/*
1376 	 * Save config regs if going into HW state D3 (B2 or B3)
1377 	 */
1378 	if ((old_lvl != PCI_PMCSR_D3HOT) && (new_lvl == PCI_PMCSR_D3HOT)) {
1379 		DEBUG0(DBG_PWR, dip, "ppb_pwr(): SAVING CONFIG REGS\n");
1380 		if (pci_save_config_regs(dip) != DDI_SUCCESS) {
1381 			cmn_err(CE_WARN, "%s%d Save config regs failed",
1382 				ddi_driver_name(dip), ddi_get_instance(dip));
1383 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1384 
1385 			return (DDI_FAILURE);
1386 		}
1387 	}
1388 
1389 	PCI_CAP_PUT16(ppb->ppb_conf_hdl, NULL, ppb->ppb_pm_cap_ptr, PCI_PMCSR,
1390 		pmcsr);
1391 
1392 	/*
1393 	 * No bus transactions should occur without waiting for
1394 	 * settle time specified in PCI PM spec rev 2.1 sec 5.6.1
1395 	 * To make things simple, just use the max time specified for
1396 	 * all state transitions.
1397 	 */
1398 	delay(drv_usectohz(PCI_CLK_SETTLE_TIME));
1399 
1400 	/*
1401 	 * Restore configuration registers if coming out of HW state D3
1402 	 */
1403 	if ((old_lvl == PCI_PMCSR_D3HOT) && (new_lvl != PCI_PMCSR_D3HOT)) {
1404 		DEBUG0(DBG_PWR, dip, "ppb_pwr(): RESTORING CONFIG REGS\n");
1405 		if (pci_restore_config_regs(dip) != DDI_SUCCESS) {
1406 			panic("%s%d restore config regs failed",
1407 			    ddi_driver_name(dip), ddi_get_instance(dip));
1408 		}
1409 		/*NOTREACHED*/
1410 	}
1411 
1412 	ppb->ppb_pwr_p->current_lvl = lvl;
1413 
1414 	mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1415 
1416 	DEBUG1(DBG_PWR, dip, "ppb_set_pwr: set PM state to %s\n\n", str);
1417 
1418 	return (DDI_SUCCESS);
1419 }
1420 
1421 /*
1422  * Initialize hotplug framework if we are hotpluggable.
1423  * Sets flag in the soft state if Hot Plug is supported and initialized
1424  * properly.
1425  */
1426 /*ARGSUSED*/
1427 static void
1428 ppb_init_hotplug(ppb_devstate_t *ppb)
1429 {
1430 	if (ddi_prop_exists(DDI_DEV_T_ANY, ppb->dip, DDI_PROP_DONTPASS,
1431 	    "hotplug-capable")) {
1432 		(void) modload("misc", "pcihp");
1433 
1434 		if (pcihp_init(ppb->dip) != DDI_SUCCESS) {
1435 			cmn_err(CE_WARN,
1436 			    "%s #%d: Failed setting hotplug framework",
1437 			    ddi_driver_name(ppb->dip),
1438 			    ddi_get_instance(ppb->dip));
1439 		} else
1440 			ppb->hotplug_capable = B_TRUE;
1441 	}
1442 
1443 }
1444 
1445 static void
1446 ppb_create_ranges_prop(dev_info_t *dip,
1447 	ddi_acc_handle_t config_handle)
1448 {
1449 	uint32_t base, limit;
1450 	ppb_ranges_t	ranges[PPB_RANGE_LEN];
1451 	uint8_t io_base_lo, io_limit_lo;
1452 	uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit;
1453 	int i = 0, rangelen = sizeof (ppb_ranges_t)/sizeof (int);
1454 
1455 	io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW);
1456 	io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW);
1457 	io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI);
1458 	io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI);
1459 	mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE);
1460 	mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT);
1461 
1462 	/*
1463 	 * Create ranges for IO space
1464 	 */
1465 	ranges[i].size_low = ranges[i].size_high = 0;
1466 	ranges[i].parent_mid = ranges[i].child_mid =
1467 		ranges[i].parent_high = 0;
1468 	ranges[i].child_high = ranges[i].parent_high |=
1469 		(PCI_REG_REL_M | PCI_ADDR_IO);
1470 	base = PPB_16bit_IOADDR(io_base_lo);
1471 	limit = PPB_16bit_IOADDR(io_limit_lo);
1472 
1473 	if ((io_base_lo & 0xf) == PPB_32BIT_IO) {
1474 		base = PPB_LADDR(base, io_base_hi);
1475 	}
1476 	if ((io_limit_lo & 0xf) == PPB_32BIT_IO) {
1477 		limit = PPB_LADDR(limit, io_limit_hi);
1478 	}
1479 
1480 	if ((io_base_lo & PPB_32BIT_IO) && (io_limit_hi > 0)) {
1481 		base = PPB_LADDR(base, io_base_hi);
1482 		limit = PPB_LADDR(limit, io_limit_hi);
1483 	}
1484 
1485 	/*
1486 	 * Create ranges for 32bit memory space
1487 	 */
1488 	base = PPB_32bit_MEMADDR(mem_base);
1489 	limit = PPB_32bit_MEMADDR(mem_limit);
1490 	ranges[i].size_low = ranges[i].size_high = 0;
1491 	ranges[i].parent_mid = ranges[i].child_mid =
1492 		ranges[i].parent_high = 0;
1493 	ranges[i].child_high = ranges[i].parent_high |=
1494 		(PCI_REG_REL_M | PCI_ADDR_MEM32);
1495 	ranges[i].child_low = ranges[i].parent_low = base;
1496 	if (limit >= base) {
1497 		ranges[i].size_low = limit - base + PPB_MEMGRAIN;
1498 		i++;
1499 	}
1500 
1501 	if (i) {
1502 		(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges",
1503 		    (int *)ranges, i * rangelen);
1504 	}
1505 }
1506 
1507 /* ARGSUSED */
1508 static int
1509 ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp)
1510 {
1511 	ppb_devstate_t *ppb_p;
1512 	minor_t		minor = getminor(*devp);
1513 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1514 
1515 	/*
1516 	 * Make sure the open is for the right file type.
1517 	 */
1518 	if (otyp != OTYP_CHR)
1519 		return (EINVAL);
1520 
1521 	/*
1522 	 * Get the soft state structure for the device.
1523 	 */
1524 	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1525 	    instance);
1526 
1527 	if (ppb_p == NULL)
1528 		return (ENXIO);
1529 
1530 	if (ppb_p->hotplug_capable == B_TRUE)
1531 		return ((pcihp_get_cb_ops())->cb_open(devp, flags,
1532 		    otyp, credp));
1533 
1534 	/*
1535 	 * Handle the open by tracking the device state.
1536 	 */
1537 	mutex_enter(&ppb_p->ppb_mutex);
1538 	if (flags & FEXCL) {
1539 		if (ppb_p->ppb_soft_state != PPB_SOFT_STATE_CLOSED) {
1540 			mutex_exit(&ppb_p->ppb_mutex);
1541 			return (EBUSY);
1542 		}
1543 		ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN_EXCL;
1544 	} else {
1545 		if (ppb_p->ppb_soft_state == PPB_SOFT_STATE_OPEN_EXCL) {
1546 			mutex_exit(&ppb_p->ppb_mutex);
1547 			return (EBUSY);
1548 		}
1549 		ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN;
1550 	}
1551 	mutex_exit(&ppb_p->ppb_mutex);
1552 	return (0);
1553 }
1554 
1555 
1556 /* ARGSUSED */
1557 static int
1558 ppb_close(dev_t dev, int flags, int otyp, cred_t *credp)
1559 {
1560 	ppb_devstate_t *ppb_p;
1561 	minor_t		minor = getminor(dev);
1562 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1563 
1564 	if (otyp != OTYP_CHR)
1565 		return (EINVAL);
1566 
1567 	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1568 	    instance);
1569 
1570 	if (ppb_p == NULL)
1571 		return (ENXIO);
1572 
1573 	if (ppb_p->hotplug_capable == B_TRUE)
1574 		return ((pcihp_get_cb_ops())->cb_close(dev, flags,
1575 		    otyp, credp));
1576 
1577 	mutex_enter(&ppb_p->ppb_mutex);
1578 	ppb_p->ppb_soft_state = PPB_SOFT_STATE_CLOSED;
1579 	mutex_exit(&ppb_p->ppb_mutex);
1580 	return (0);
1581 }
1582 
1583 
1584 /*
1585  * ppb_ioctl: devctl hotplug controls
1586  */
1587 /* ARGSUSED */
1588 static int
1589 ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
1590 	int *rvalp)
1591 {
1592 	ppb_devstate_t *ppb_p;
1593 	dev_info_t *self;
1594 	struct devctl_iocdata *dcp;
1595 	uint_t bus_state;
1596 	int rv = 0;
1597 	minor_t		minor = getminor(dev);
1598 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1599 
1600 	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1601 	    instance);
1602 
1603 	if (ppb_p == NULL)
1604 		return (ENXIO);
1605 
1606 	if (ppb_p->hotplug_capable == B_TRUE)
1607 		return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd,
1608 		    arg, mode, credp, rvalp));
1609 
1610 	self = ppb_p->dip;
1611 
1612 	/*
1613 	 * We can use the generic implementation for these ioctls
1614 	 */
1615 	switch (cmd) {
1616 	case DEVCTL_DEVICE_GETSTATE:
1617 	case DEVCTL_DEVICE_ONLINE:
1618 	case DEVCTL_DEVICE_OFFLINE:
1619 	case DEVCTL_BUS_GETSTATE:
1620 		return (ndi_devctl_ioctl(self, cmd, arg, mode, 0));
1621 	}
1622 
1623 	/*
1624 	 * read devctl ioctl data
1625 	 */
1626 	if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS)
1627 		return (EFAULT);
1628 
1629 	switch (cmd) {
1630 
1631 	case DEVCTL_DEVICE_RESET:
1632 		rv = ENOTSUP;
1633 		break;
1634 
1635 	case DEVCTL_BUS_QUIESCE:
1636 		if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS)
1637 			if (bus_state == BUS_QUIESCED)
1638 				break;
1639 		(void) ndi_set_bus_state(self, BUS_QUIESCED);
1640 		break;
1641 
1642 	case DEVCTL_BUS_UNQUIESCE:
1643 		if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS)
1644 			if (bus_state == BUS_ACTIVE)
1645 				break;
1646 		(void) ndi_set_bus_state(self, BUS_ACTIVE);
1647 		break;
1648 
1649 	case DEVCTL_BUS_RESET:
1650 		rv = ENOTSUP;
1651 		break;
1652 
1653 	case DEVCTL_BUS_RESETALL:
1654 		rv = ENOTSUP;
1655 		break;
1656 
1657 	default:
1658 		rv = ENOTTY;
1659 	}
1660 
1661 	ndi_dc_freehdl(dcp);
1662 	return (rv);
1663 }
1664 
1665 static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
1666     int flags, char *name, caddr_t valuep, int *lengthp)
1667 {
1668 	ppb_devstate_t *ppb_p;
1669 	minor_t		minor = getminor(dev);
1670 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1671 
1672 	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1673 	    instance);
1674 
1675 	if (ppb_p == NULL)
1676 		return (ENXIO);
1677 
1678 	if (ppb_p->hotplug_capable == B_TRUE)
1679 		return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op,
1680 		    flags, name, valuep, lengthp));
1681 
1682 	return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp));
1683 }
1684 
1685 /*
1686  * Initialize our FMA resources
1687  */
1688 static void
1689 ppb_fm_init(ppb_devstate_t *ppb_p)
1690 {
1691 	dev_info_t *root = ddi_root_node();
1692 	dev_info_t *pdip;
1693 	char *bus;
1694 
1695 	ppb_p->fm_cap = DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE |
1696 		DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE;
1697 
1698 	/*
1699 	 * Request our capability level and get our parents capability
1700 	 * and ibc.
1701 	 */
1702 	ddi_fm_init(ppb_p->dip, &ppb_p->fm_cap, &ppb_p->fm_ibc);
1703 	ASSERT((ppb_p->fm_cap & DDI_FM_EREPORT_CAPABLE) &&
1704 	    (ppb_p->fm_cap & DDI_FM_ERRCB_CAPABLE));
1705 
1706 	pci_ereport_setup(ppb_p->dip);
1707 
1708 	/*
1709 	 * Register error callback with our parent.
1710 	 */
1711 	ddi_fm_handler_register(ppb_p->dip, ppb_err_callback, NULL);
1712 
1713 	ppb_p->parent_bus = PCIE_PCIECAP_DEV_TYPE_PCI_DEV;
1714 	for (pdip = ddi_get_parent(ppb_p->dip); pdip && (pdip != root) &&
1715 	    (ppb_p->parent_bus != PCIE_PCIECAP_DEV_TYPE_PCIE_DEV);
1716 	    pdip = ddi_get_parent(pdip)) {
1717 		if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip,
1718 		    DDI_PROP_DONTPASS, "device_type", &bus) !=
1719 		    DDI_PROP_SUCCESS)
1720 			break;
1721 
1722 		if (strcmp(bus, "pciex") == 0)
1723 			ppb_p->parent_bus = PCIE_PCIECAP_DEV_TYPE_PCIE_DEV;
1724 
1725 		ddi_prop_free(bus);
1726 	}
1727 }
1728 
1729 /*
1730  * Breakdown our FMA resources
1731  */
1732 static void
1733 ppb_fm_fini(ppb_devstate_t *ppb_p)
1734 {
1735 	/*
1736 	 * Clean up allocated fm structures
1737 	 */
1738 	ddi_fm_handler_unregister(ppb_p->dip);
1739 	pci_ereport_teardown(ppb_p->dip);
1740 	ddi_fm_fini(ppb_p->dip);
1741 }
1742 
1743 /*
1744  * Initialize FMA resources for children devices. Called when
1745  * child calls ddi_fm_init().
1746  */
1747 /*ARGSUSED*/
1748 static int
1749 ppb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap,
1750 		ddi_iblock_cookie_t *ibc)
1751 {
1752 	ppb_devstate_t *ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1753 			ddi_get_instance(dip));
1754 	*ibc = ppb_p->fm_ibc;
1755 	return (ppb_p->fm_cap);
1756 }
1757 
1758 /*
1759  * FMA registered error callback
1760  */
1761 static int
1762 ppb_err_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *impl_data)
1763 {
1764 	ppb_devstate_t *ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1765 			ddi_get_instance(dip));
1766 
1767 	/*
1768 	 * errors handled by SPARC PCI-E framework for PCIe platforms
1769 	 */
1770 	if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
1771 		return (DDI_FM_OK);
1772 
1773 	/*
1774 	 * do the following for SPARC PCI platforms
1775 	 */
1776 	ASSERT(impl_data == NULL);
1777 	pci_ereport_post(dip, derr, NULL);
1778 	return (derr->fme_status);
1779 }
1780 
1781 static void
1782 ppb_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle)
1783 {
1784 	i_ndi_busop_access_enter(dip, handle);
1785 }
1786 
1787 /* ARGSUSED */
1788 static void
1789 ppb_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle)
1790 {
1791 	i_ndi_busop_access_exit(dip, handle);
1792 }
1793