1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26/*
27 * Copyright 2019 Peter Tribble.
28 */
29
30/*
31 * PCI PBM implementation:
32 *	initialization
33 *	Bus error interrupt handler
34 */
35
36#include <sys/types.h>
37#include <sys/kmem.h>
38#include <sys/spl.h>
39#include <sys/sysmacros.h>
40#include <sys/sunddi.h>
41#include <sys/fm/protocol.h>
42#include <sys/fm/util.h>
43#include <sys/machsystm.h>	/* ldphysio() */
44#include <sys/async.h>
45#include <sys/ddi_impldefs.h>
46#include <sys/ontrap.h>
47#include <sys/pci/pci_obj.h>
48#include <sys/membar.h>
49#include <sys/ivintr.h>
50
51/*LINTLIBRARY*/
52
53static uint_t pbm_error_intr(caddr_t a);
54
55/* The nexus interrupt priority values */
56int pci_pil[] = {14, 14, 14, 14, 14, 14};
57void
58pbm_create(pci_t *pci_p)
59{
60	pbm_t *pbm_p;
61	int i, len;
62	int nrange = pci_p->pci_ranges_length / sizeof (pci_ranges_t);
63	dev_info_t *dip = pci_p->pci_dip;
64	pci_ranges_t *rangep = pci_p->pci_ranges;
65	uint64_t base_addr, last_addr;
66
67#ifdef lint
68	dip = dip;
69#endif
70
71	/*
72	 * Allocate a state structure for the PBM and cross-link it
73	 * to its per pci node state structure.
74	 */
75	pbm_p = (pbm_t *)kmem_zalloc(sizeof (pbm_t), KM_SLEEP);
76	pci_p->pci_pbm_p = pbm_p;
77	pbm_p->pbm_pci_p = pci_p;
78
79	len = snprintf(pbm_p->pbm_nameinst_str,
80	    sizeof (pbm_p->pbm_nameinst_str),
81	    "%s%d", NAMEINST(dip));
82	pbm_p->pbm_nameaddr_str = pbm_p->pbm_nameinst_str + ++len;
83	(void) snprintf(pbm_p->pbm_nameaddr_str,
84	    sizeof (pbm_p->pbm_nameinst_str) - len,
85	    "%s@%s", NAMEADDR(dip));
86
87	pci_pbm_setup(pbm_p);
88
89	/*
90	 * Get this pbm's mem32 and mem64 segments to determine whether
91	 * a dma object originates from ths pbm. i.e. dev to dev dma
92	 */
93	/* Init all of our boundaries */
94	base_addr = -1ull;
95	last_addr = 0ull;
96
97	for (i = 0; i < nrange; i++, rangep++) {
98		uint32_t rng_type = rangep->child_high & PCI_ADDR_MASK;
99		if (rng_type == PCI_ADDR_MEM32 || rng_type == PCI_ADDR_MEM64) {
100			uint64_t rng_addr, rng_size;
101
102			rng_addr = (uint64_t)rangep->parent_high << 32;
103			rng_addr |= (uint64_t)rangep->parent_low;
104			rng_size = (uint64_t)rangep->size_high << 32;
105			rng_size |= (uint64_t)rangep->size_low;
106			base_addr = MIN(rng_addr, base_addr);
107			last_addr = MAX(rng_addr + rng_size, last_addr);
108		}
109	}
110	pbm_p->pbm_base_pfn = mmu_btop(base_addr);
111	pbm_p->pbm_last_pfn = mmu_btop(last_addr);
112
113	DEBUG4(DBG_ATTACH, dip,
114	    "pbm_create: ctrl=%x, afsr=%x, afar=%x, diag=%x\n",
115	    pbm_p->pbm_ctrl_reg, pbm_p->pbm_async_flt_status_reg,
116	    pbm_p->pbm_async_flt_addr_reg, pbm_p->pbm_diag_reg);
117	DEBUG1(DBG_ATTACH, dip, "pbm_create: conf=%x\n",
118	    pbm_p->pbm_config_header);
119
120	/*
121	 * Register a function to disable pbm error interrupts during a panic.
122	 */
123	bus_func_register(BF_TYPE_ERRDIS,
124	    (busfunc_t)pbm_disable_pci_errors, pbm_p);
125
126	/*
127	 * create the interrupt-priorities property if it doesn't
128	 * already exist to provide a hint as to the PIL level for
129	 * our interrupt.
130	 */
131	if (ddi_getproplen(DDI_DEV_T_ANY, dip,
132	    DDI_PROP_DONTPASS, "interrupt-priorities",
133	    &len) != DDI_PROP_SUCCESS) {
134				/* Create the interrupt-priorities property. */
135		(void) ddi_prop_create(DDI_DEV_T_NONE, dip,
136		    DDI_PROP_CANSLEEP, "interrupt-priorities",
137		    (caddr_t)pci_pil, sizeof (pci_pil));
138	}
139
140	pbm_configure(pbm_p);
141}
142
143int
144pbm_register_intr(pbm_t *pbm_p)
145{
146	pci_t		*pci_p = pbm_p->pbm_pci_p;
147	uint32_t	mondo;
148	int		r = DDI_SUCCESS;
149
150	ib_nintr_clear(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_PBM]);
151
152	/*
153	 * Install the PCI error interrupt handler.
154	 */
155	mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_PBM]);
156	mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo);
157
158	VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_PBM], (intrfunc)pbm_error_intr,
159	    (caddr_t)pci_p, NULL, NULL) == 0);
160
161	pbm_p->pbm_iblock_cookie = (void *)(uintptr_t)pci_pil[CBNINTR_PBM];
162
163	/*
164	 * Create the pokefault mutex at the PIL below the error interrupt.
165	 */
166	mutex_init(&pbm_p->pbm_pokefault_mutex, NULL, MUTEX_DRIVER,
167	    (void *)(uintptr_t)ipltospl(spltoipl(
168	    (int)(uintptr_t)pbm_p->pbm_iblock_cookie) - 1));
169
170	if (!r)
171		r = pci_pbm_add_intr(pci_p);
172	return (PCI_ATTACH_RETCODE(PCI_PBM_OBJ, PCI_OBJ_INTR_ADD, r));
173}
174
175void
176pbm_destroy(pci_t *pci_p)
177{
178	pbm_t		*pbm_p = pci_p->pci_pbm_p;
179	ib_t		*ib_p = pci_p->pci_ib_p;
180	uint32_t	mondo;
181
182	DEBUG0(DBG_DETACH, pci_p->pci_dip, "pbm_destroy:\n");
183
184	mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_PBM]);
185	mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo);
186
187	/*
188	 * Free the pokefault mutex.
189	 */
190	mutex_destroy(&pbm_p->pbm_pokefault_mutex);
191
192	/*
193	 * Remove the error interrupt and consistent dma sync handler.
194	 */
195	intr_dist_rem(pbm_intr_dist, pbm_p);
196	pci_pbm_rem_intr(pci_p);
197	ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_PBM], IB_INTR_WAIT);
198	VERIFY(rem_ivintr(mondo, pci_pil[CBNINTR_PBM]) == 0);
199
200	/*
201	 * Remove the error disable function.
202	 */
203	bus_func_unregister(BF_TYPE_ERRDIS,
204	    (busfunc_t)pbm_disable_pci_errors, pbm_p);
205
206	pci_pbm_teardown(pbm_p);
207
208	/*
209	 * Free the pbm state structure.
210	 */
211	kmem_free(pbm_p, sizeof (pbm_t));
212	pci_p->pci_pbm_p = NULL;
213}
214
215static uint_t
216pbm_error_intr(caddr_t a)
217{
218	pci_t *pci_p = (pci_t *)a;
219	pbm_t *pbm_p = pci_p->pci_pbm_p;
220	ddi_fm_error_t derr;
221	int err = DDI_FM_OK;
222	on_trap_data_t *otp = pbm_p->pbm_ontrap_data;
223
224	bzero(&derr, sizeof (ddi_fm_error_t));
225	derr.fme_version = DDI_FME_VERSION;
226	mutex_enter(&pci_p->pci_common_p->pci_fm_mutex);
227	if (pbm_p->pbm_excl_handle != NULL) {
228		/*
229		 * cautious write protection, protected from all errors.
230		 */
231		ASSERT(MUTEX_HELD(&pbm_p->pbm_pokefault_mutex));
232		ddi_fm_acc_err_get(pbm_p->pbm_excl_handle, &derr,
233		    DDI_FME_VERSION);
234		ASSERT(derr.fme_flag == DDI_FM_ERR_EXPECTED);
235		derr.fme_acc_handle = pbm_p->pbm_excl_handle;
236		err = pci_pbm_err_handler(pci_p->pci_dip, &derr, (void *)pci_p,
237		    PCI_INTR_CALL);
238	} else if ((otp != NULL) && (otp->ot_prot & OT_DATA_ACCESS)) {
239		/*
240		 * ddi_poke protection, check nexus and children for
241		 * expected errors.
242		 */
243		otp->ot_trap |= OT_DATA_ACCESS;
244		membar_sync();
245		derr.fme_flag = DDI_FM_ERR_POKE;
246		err = pci_pbm_err_handler(pci_p->pci_dip, &derr, (void *)pci_p,
247		    PCI_INTR_CALL);
248	} else if (pci_check_error(pci_p) != 0) {
249		/*
250		 * unprotected error, check for all errors.
251		 */
252		if (pci_errtrig_pa)
253			(void) ldphysio(pci_errtrig_pa);
254		derr.fme_flag = DDI_FM_ERR_UNEXPECTED;
255		err = pci_pbm_err_handler(pci_p->pci_dip, &derr, (void *)pci_p,
256		    PCI_INTR_CALL);
257	}
258
259	if (err == DDI_FM_FATAL) {
260		if (pci_panic_on_fatal_errors) {
261			mutex_exit(&pci_p->pci_common_p->pci_fm_mutex);
262			fm_panic("%s-%d: Fatal PCI bus error(s)\n",
263			    ddi_driver_name(pci_p->pci_dip),
264			    ddi_get_instance(pci_p->pci_dip));
265		}
266	}
267
268	mutex_exit(&pci_p->pci_common_p->pci_fm_mutex);
269	ib_nintr_clear(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_PBM]);
270	return (DDI_INTR_CLAIMED);
271}
272
273void
274pbm_suspend(pbm_t *pbm_p)
275{
276	pci_t *pci_p = pbm_p->pbm_pci_p;
277	ib_ino_t ino = pci_p->pci_inos[CBNINTR_PBM];
278	pbm_p->pbm_imr_save = *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino);
279
280	pci_pbm_suspend(pci_p);
281}
282
283void
284pbm_resume(pbm_t *pbm_p)
285{
286	pci_t *pci_p = pbm_p->pbm_pci_p;
287	ib_ino_t ino = pci_p->pci_inos[CBNINTR_PBM];
288
289	ib_nintr_clear(pci_p->pci_ib_p, ino);
290	*ib_intr_map_reg_addr(pci_p->pci_ib_p, ino) = pbm_p->pbm_imr_save;
291
292	pci_pbm_resume(pci_p);
293}
294
295void
296pbm_intr_dist(void *arg)
297{
298	pbm_t *pbm_p = (pbm_t *)arg;
299	pci_t *pci_p = pbm_p->pbm_pci_p;
300	ib_t *ib_p = pci_p->pci_ib_p;
301	ib_ino_t ino = IB_MONDO_TO_INO(pci_p->pci_inos[CBNINTR_PBM]);
302
303	mutex_enter(&ib_p->ib_intr_lock);
304	ib_intr_dist_nintr(ib_p, ino, ib_intr_map_reg_addr(ib_p, ino));
305	pci_pbm_intr_dist(pbm_p);
306	mutex_exit(&ib_p->ib_intr_lock);
307}
308
309/*
310 * Function used to log PBM AFSR register bits and to lookup and fault
311 * handle associated with PBM AFAR register. Called by pci_pbm_err_handler with
312 * pci_fm_mutex held.
313 */
314int
315pbm_afsr_report(dev_info_t *dip, uint64_t fme_ena, pbm_errstate_t *pbm_err_p)
316{
317	int fatal = 0;
318	int ret = 0;
319	pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
320	pci_common_t *cmn_p = pci_p->pci_common_p;
321
322	ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex));
323
324	pbm_err_p->pbm_pri = PBM_PRIMARY;
325	(void) pci_pbm_classify(pbm_err_p);
326
327	pci_format_addr(dip, &pbm_err_p->pbm_pci.pci_pa, pbm_err_p->pbm_afsr);
328
329	if (pbm_err_p->pbm_log == FM_LOG_PBM)
330		pbm_ereport_post(dip, fme_ena, pbm_err_p);
331
332	/*
333	 * Lookup and fault errant handle
334	 */
335	if (((ret = ndi_fmc_error(dip, NULL, ACC_HANDLE, fme_ena,
336	    (void *)&pbm_err_p->pbm_pci.pci_pa)) == DDI_FM_FATAL) ||
337	    (ret == DDI_FM_UNKNOWN))
338		fatal++;
339
340	/*
341	 * queue target ereport if appropriate
342	 */
343	if (pbm_err_p->pbm_terr_class)
344		pci_target_enqueue(fme_ena, pbm_err_p->pbm_terr_class,
345		    (pbm_err_p->pbm_log == FM_LOG_PCI) ? "pci" :
346		    pbm_err_p->pbm_bridge_type, pbm_err_p->pbm_pci.pci_pa);
347
348	/*
349	 * We are currently not dealing with the multiple error
350	 * case, for any secondary errors we will panic.
351	 */
352	pbm_err_p->pbm_pri = PBM_SECONDARY;
353	if (pci_pbm_classify(pbm_err_p)) {
354		fatal++;
355		if (pbm_err_p->pbm_log == FM_LOG_PBM)
356			pbm_ereport_post(dip, fme_ena, pbm_err_p);
357	}
358
359	if (fatal)
360		return (DDI_FM_FATAL);
361
362	return (DDI_FM_NONFATAL);
363}
364