1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, Version 1.0 only
6 * (the "License"). You may not use this file except in compliance
7 * with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22 /*
23 * Copyright 2000-2002 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/sunddi.h>
30 #include <sys/esunddi.h>
31 #include <sys/ddi.h>
32
33 #include <sys/platform_module.h>
34 #include <sys/errno.h>
35
36 void
startup_platform(void)37 startup_platform(void)
38 {
39 }
40
41 int
set_platform_tsb_spares()42 set_platform_tsb_spares()
43 {
44 return (0);
45 }
46
47 void
set_platform_defaults(void)48 set_platform_defaults(void)
49 {
50 }
51
52
53 /*
54 * Definitions for accessing the pci config space of the isa node
55 * of Southbridge.
56 */
57 #define GROVER_ISA_PATHNAME "/pci@1f,0/isa@7"
58 ddi_acc_handle_t grover_isa_handle; /* handle for isa pci space */
59
60 void
load_platform_drivers(void)61 load_platform_drivers(void)
62 {
63 dev_info_t *dip; /* dip of the isa driver */
64
65
66 if (i_ddi_attach_hw_nodes("power") != DDI_SUCCESS)
67 cmn_err(CE_WARN, "Failed to install \"power\" driver.");
68
69 /*
70 * It is OK to return error because 'us' driver is not available
71 * in all clusters (e.g. missing in Core cluster).
72 */
73 (void) i_ddi_attach_hw_nodes("us");
74
75 if (i_ddi_attach_hw_nodes("grbeep") != DDI_SUCCESS)
76 cmn_err(CE_WARN, "Failed to install \"beep\" driver.");
77
78 /*
79 * Install Isa driver. This is required for the southbridge IDE
80 * workaround - to reset the IDE channel during IDE bus reset.
81 * Panic the system in case ISA driver could not be loaded or
82 * any problem in accessing its pci config space. Since the register
83 * to reset the channel for IDE is in ISA config space!.
84 */
85
86 dip = e_ddi_hold_devi_by_path(GROVER_ISA_PATHNAME, 0);
87 if (dip == NULL) {
88 cmn_err(CE_PANIC, "Could not install the isa driver\n");
89 }
90
91 if (pci_config_setup(dip, &grover_isa_handle) != DDI_SUCCESS) {
92 cmn_err(CE_PANIC, "Could not get the config space of isa\n");
93 }
94 }
95
96 /*
97 * This routine provides a workaround for a bug in the SB chip which
98 * can cause data corruption. Will be invoked from the IDE HBA driver for
99 * Acer SouthBridge at the time of IDE bus reset.
100 */
101 /*ARGSUSED*/
102 int
plat_ide_chipreset(dev_info_t * dip,int chno)103 plat_ide_chipreset(dev_info_t *dip, int chno)
104 {
105 uint8_t val;
106 int ret = DDI_SUCCESS;
107
108 val = pci_config_get8(grover_isa_handle, 0x58);
109 /*
110 * The dip passed as the argument is not used for grover.
111 * This will be needed for platforms which have multiple on-board SB,
112 * The dip passed will be used to match the corresponding ISA node.
113 */
114 switch (chno) {
115 case 0:
116 /*
117 * First disable the primary channel then re-enable it.
118 * As per ALI no wait should be required in between have
119 * given 1ms delay in between to be on safer side.
120 * bit 2 of register 0x58 when 0 disable the channel 0.
121 * bit 2 of register 0x58 when 1 enables the channel 0.
122 */
123 pci_config_put8(grover_isa_handle, 0x58, val & 0xFB);
124 drv_usecwait(1000);
125 pci_config_put8(grover_isa_handle, 0x58, val);
126 break;
127 case 1:
128 /*
129 * bit 3 of register 0x58 when 0 disable the channel 1.
130 * bit 3 of register 0x58 when 1 enables the channel 1.
131 */
132 pci_config_put8(grover_isa_handle, 0x58, val & 0xF7);
133 drv_usecwait(1000);
134 pci_config_put8(grover_isa_handle, 0x58, val);
135 break;
136 default:
137 /*
138 * Unknown channel number passed. Return failure.
139 */
140 ret = DDI_FAILURE;
141 }
142
143 return (ret);
144 }
145
146
147
148 /*ARGSUSED*/
149 int
plat_cpu_poweron(struct cpu * cp)150 plat_cpu_poweron(struct cpu *cp)
151 {
152 return (ENOTSUP); /* not supported on this platform */
153 }
154
155 /*ARGSUSED*/
156 int
plat_cpu_poweroff(struct cpu * cp)157 plat_cpu_poweroff(struct cpu *cp)
158 {
159 return (ENOTSUP); /* not supported on this platform */
160 }
161
162 /*ARGSUSED*/
163 void
plat_freelist_process(int mnode)164 plat_freelist_process(int mnode)
165 {
166 }
167
168 char *platform_module_list[] = {
169 "grppm",
170 (char *)0
171 };
172
173 /*ARGSUSED*/
174 void
plat_tod_fault(enum tod_fault_type tod_bad)175 plat_tod_fault(enum tod_fault_type tod_bad)
176 {
177 }
178