27c478bdstevel@tonic-gate * CDDL HEADER START
37c478bdstevel@tonic-gate *
47c478bdstevel@tonic-gate * The contents of this file are subject to the terms of the
57bafd14jb * Common Development and Distribution License (the "License").
67bafd14jb * You may not use this file except in compliance with the License.
77c478bdstevel@tonic-gate *
87c478bdstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bdstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bdstevel@tonic-gate * See the License for the specific language governing permissions
117c478bdstevel@tonic-gate * and limitations under the License.
127c478bdstevel@tonic-gate *
137c478bdstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bdstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bdstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bdstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bdstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bdstevel@tonic-gate *
197c478bdstevel@tonic-gate * CDDL HEADER END
207c478bdstevel@tonic-gate */
22ae115bcmrj * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
237c478bdstevel@tonic-gate * Use is subject to license terms.
247c478bdstevel@tonic-gate */
277c478bdstevel@tonic-gate * General machine architecture & implementation specific
287c478bdstevel@tonic-gate * assembly language routines.
297c478bdstevel@tonic-gate */
307c478bdstevel@tonic-gate#include "assym.h"
327c478bdstevel@tonic-gate#include <sys/asm_linkage.h>
337c478bdstevel@tonic-gate#include <sys/async.h>
347c478bdstevel@tonic-gate#include <sys/machthread.h>
357bafd14jb#include <sys/vis.h>
367bafd14jb#include <sys/machsig.h>
387c478bdstevel@tonic-gate	ENTRY(set_trap_table)
397c478bdstevel@tonic-gate	set	trap_table, %o1
407c478bdstevel@tonic-gate	rdpr	%tba, %o0
417c478bdstevel@tonic-gate	wrpr	%o1, %tba
427c478bdstevel@tonic-gate	retl
437c478bdstevel@tonic-gate	wrpr	%g0, WSTATE_KERN, %wstate
447c478bdstevel@tonic-gate	SET_SIZE(set_trap_table)
467c478bdstevel@tonic-gate	! Store long word value at physical address
477c478bdstevel@tonic-gate	!
487c478bdstevel@tonic-gate	! void  stdphys(uint64_t physaddr, uint64_t value)
497c478bdstevel@tonic-gate	!
507c478bdstevel@tonic-gate	ENTRY(stdphys)
517c478bdstevel@tonic-gate	/*
527c478bdstevel@tonic-gate	 * disable interrupts, clear Address Mask to access 64 bit physaddr
537c478bdstevel@tonic-gate	 */
547c478bdstevel@tonic-gate	rdpr	%pstate, %o4
557c478bdstevel@tonic-gate	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
567c478bdstevel@tonic-gate	wrpr	%o5, 0, %pstate
577c478bdstevel@tonic-gate	stxa	%o1, [%o0]ASI_MEM
587c478bdstevel@tonic-gate	retl
597c478bdstevel@tonic-gate	wrpr	%g0, %o4, %pstate	! restore earlier pstate register value
607c478bdstevel@tonic-gate	SET_SIZE(stdphys)
637c478bdstevel@tonic-gate	! Store long word value at physical i/o address
647c478bdstevel@tonic-gate	!
657c478bdstevel@tonic-gate	! void  stdphysio(u_longlong_t physaddr, u_longlong_t value)
667c478bdstevel@tonic-gate	!
677c478bdstevel@tonic-gate	ENTRY(stdphysio)
687c478bdstevel@tonic-gate	/*
697c478bdstevel@tonic-gate	 * disable interrupts, clear Address Mask to access 64 bit physaddr
707c478bdstevel@tonic-gate	 */
717c478bdstevel@tonic-gate	rdpr	%pstate, %o4
727c478bdstevel@tonic-gate	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
737c478bdstevel@tonic-gate	wrpr	%o5, 0, %pstate		! clear IE, AM bits
747c478bdstevel@tonic-gate	stxa	%o1, [%o0]ASI_IO
757c478bdstevel@tonic-gate	retl
767c478bdstevel@tonic-gate	wrpr	%g0, %o4, %pstate	! restore earlier pstate register value
777c478bdstevel@tonic-gate	SET_SIZE(stdphysio)
807c478bdstevel@tonic-gate	!
817c478bdstevel@tonic-gate	! Load long word value at physical address
827c478bdstevel@tonic-gate	!
837c478bdstevel@tonic-gate	! uint64_t lddphys(uint64_t physaddr)
847c478bdstevel@tonic-gate	!
857c478bdstevel@tonic-gate	ENTRY(lddphys)
867c478bdstevel@tonic-gate	rdpr	%pstate, %o4
877c478bdstevel@tonic-gate	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
887c478bdstevel@tonic-gate	wrpr	%o5, 0, %pstate
897c478bdstevel@tonic-gate	ldxa	[%o0]ASI_MEM, %o0
907c478bdstevel@tonic-gate	retl
917c478bdstevel@tonic-gate	wrpr	%g0, %o4, %pstate	! restore earlier pstate register value
927c478bdstevel@tonic-gate	SET_SIZE(lddphys)
947c478bdstevel@tonic-gate	!
957c478bdstevel@tonic-gate	! Load long word value at physical i/o address
967c478bdstevel@tonic-gate	!
977c478bdstevel@tonic-gate	! unsigned long long lddphysio(u_longlong_t physaddr)
987c478bdstevel@tonic-gate	!
997c478bdstevel@tonic-gate	ENTRY(lddphysio)
1007c478bdstevel@tonic-gate	rdpr	%pstate, %o4
1017c478bdstevel@tonic-gate	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
1027c478bdstevel@tonic-gate	wrpr	%o5, 0, %pstate	! clear IE, AM bits
1037c478bdstevel@tonic-gate	ldxa	[%o0]ASI_IO, %o0
1047c478bdstevel@tonic-gate	retl
1057c478bdstevel@tonic-gate	wrpr	%g0, %o4, %pstate	! restore earlier pstate register value
1067c478bdstevel@tonic-gate	SET_SIZE(lddphysio)
1087c478bdstevel@tonic-gate	!
1097c478bdstevel@tonic-gate	! Store value at physical address
1107c478bdstevel@tonic-gate	!
1117c478bdstevel@tonic-gate	! void  stphys(uint64_t physaddr, int value)
1127c478bdstevel@tonic-gate	!
1137c478bdstevel@tonic-gate	ENTRY(stphys)
1147c478bdstevel@tonic-gate	rdpr	%pstate, %o4
1157c478bdstevel@tonic-gate	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
1167c478bdstevel@tonic-gate	wrpr	%o5, 0, %pstate
1177c478bdstevel@tonic-gate	sta	%o1, [%o0]ASI_MEM
1187c478bdstevel@tonic-gate	retl
1197c478bdstevel@tonic-gate	wrpr	%g0, %o4, %pstate	! restore earlier pstate register value
1207c478bdstevel@tonic-gate	SET_SIZE(stphys)
1237c478bdstevel@tonic-gate	!
1247c478bdstevel@tonic-gate	! load value at physical address
1257c478bdstevel@tonic-gate	!
1267c478bdstevel@tonic-gate	! int   ldphys(uint64_t physaddr)
1277c478bdstevel@tonic-gate	!
1287c478bdstevel@tonic-gate	ENTRY(ldphys)
1297c478bdstevel@tonic-gate	rdpr	%pstate, %o4
1307c478bdstevel@tonic-gate	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
1317c478bdstevel@tonic-gate	wrpr	%o5, 0, %pstate
1327c478bdstevel@tonic-gate	lda	[%o0]ASI_MEM, %o0
1337c478bdstevel@tonic-gate	srl	%o0, 0, %o0	! clear upper 32 bits
1347c478bdstevel@tonic-gate	retl
1357c478bdstevel@tonic-gate	wrpr	%g0, %o4, %pstate	! restore earlier pstate register value
1367c478bdstevel@tonic-gate	SET_SIZE(ldphys)
1387c478bdstevel@tonic-gate	!
1397c478bdstevel@tonic-gate	! Store value into physical address in I/O space
1407c478bdstevel@tonic-gate	!
1417c478bdstevel@tonic-gate	! void stphysio(u_longlong_t physaddr, uint_t value)
1427c478bdstevel@tonic-gate	!
1437c478bdstevel@tonic-gate	ENTRY_NP(stphysio)
1447c478bdstevel@tonic-gate	rdpr	%pstate, %o4		/* read PSTATE reg */
1457c478bdstevel@tonic-gate	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
1467c478bdstevel@tonic-gate	wrpr	%o5, 0, %pstate
1477c478bdstevel@tonic-gate	stwa	%o1, [%o0]ASI_IO	/* store value via bypass ASI */
1487c478bdstevel@tonic-gate	retl
1497c478bdstevel@tonic-gate	wrpr	%g0, %o4, %pstate	/* restore the PSTATE */
1507c478bdstevel@tonic-gate	SET_SIZE(stphysio)
1527c478bdstevel@tonic-gate	!
1537c478bdstevel@tonic-gate	! Store value into physical address in I/O space
1547c478bdstevel@tonic-gate	!
1557c478bdstevel@tonic-gate	! void sthphysio(u_longlong_t physaddr, ushort_t value)
1567c478bdstevel@tonic-gate	!
1577c478bdstevel@tonic-gate	ENTRY_NP(sthphysio)
1587c478bdstevel@tonic-gate	rdpr	%pstate, %o4		/* read PSTATE reg */
1597c478bdstevel@tonic-gate	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
1607c478bdstevel@tonic-gate	wrpr	%o5, 0, %pstate
1617c478bdstevel@tonic-gate	stha	%o1, [%o0]ASI_IO	/* store value via bypass ASI */
1627c478bdstevel@tonic-gate	retl
1637c478bdstevel@tonic-gate	wrpr	%g0, %o4, %pstate		/* restore the PSTATE */
1647c478bdstevel@tonic-gate	SET_SIZE(sthphysio)
1667c478bdstevel@tonic-gate	!
1677c478bdstevel@tonic-gate	! Store value into one byte physical address in I/O space
1687c478bdstevel@tonic-gate	!
1697c478bdstevel@tonic-gate	! void stbphysio(u_longlong_t physaddr, uchar_t value)
1707c478bdstevel@tonic-gate	!
1717c478bdstevel@tonic-gate	ENTRY_NP(stbphysio)
1727c478bdstevel@tonic-gate	rdpr	%pstate, %o4		/* read PSTATE reg */
1737c478bdstevel@tonic-gate	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
1747c478bdstevel@tonic-gate	wrpr	%o5, 0, %pstate
1757c478bdstevel@tonic-gate	stba	%o1, [%o0]ASI_IO	/* store byte via bypass ASI */
1767c478bdstevel@tonic-gate	retl
1777c478bdstevel@tonic-gate	wrpr	%g0, %o4, %pstate	/* restore the PSTATE */
1787c478bdstevel@tonic-gate	SET_SIZE(stbphysio)
1807c478bdstevel@tonic-gate	!
1817c478bdstevel@tonic-gate	! load value at physical address in I/O space
1827c478bdstevel@tonic-gate	!
1837c478bdstevel@tonic-gate	! uint_t   ldphysio(u_longlong_t physaddr)
1847c478bdstevel@tonic-gate	!
1857c478bdstevel@tonic-gate	ENTRY_NP(ldphysio)
1867c478bdstevel@tonic-gate	rdpr	%pstate, %o4		/* read PSTATE reg */
1877c478bdstevel@tonic-gate	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
1887c478bdstevel@tonic-gate	wrpr	%o5, 0, %pstate
1897c478bdstevel@tonic-gate	lduwa	[%o0]ASI_IO, %o0	/* load value via bypass ASI */
1907c478bdstevel@tonic-gate	retl
1917c478bdstevel@tonic-gate	wrpr	%g0, %o4, %pstate	/* restore pstate */
1927c478bdstevel@tonic-gate	SET_SIZE(ldphysio)
1947c478bdstevel@tonic-gate	!
1957c478bdstevel@tonic-gate	! load value at physical address in I/O space
1967c478bdstevel@tonic-gate	!
1977c478bdstevel@tonic-gate	! ushort_t   ldhphysio(u_longlong_t physaddr)
1987c478bdstevel@tonic-gate	!
1997c478bdstevel@tonic-gate	ENTRY_NP(ldhphysio)
2007c478bdstevel@tonic-gate	rdpr	%pstate, %o4		/* read PSTATE reg */
2017c478bdstevel@tonic-gate	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
2027c478bdstevel@tonic-gate	wrpr	%o5, 0, %pstate
2037c478bdstevel@tonic-gate	lduha	[%o0]ASI_IO, %o0	/* load value via bypass ASI */
2047c478bdstevel@tonic-gate	retl
2057c478bdstevel@tonic-gate	wrpr	%g0, %o4, %pstate	/* restore pstate */
2067c478bdstevel@tonic-gate	SET_SIZE(ldhphysio)
2087c478bdstevel@tonic-gate	!
2097c478bdstevel@tonic-gate	! load byte value at physical address in I/O space
2107c478bdstevel@tonic-gate	!
2117c478bdstevel@tonic-gate	! uchar_t   ldbphysio(u_longlong_t physaddr)
2127c478bdstevel@tonic-gate	!
2137c478bdstevel@tonic-gate	ENTRY_NP(ldbphysio)
2147c478bdstevel@tonic-gate	rdpr	%pstate, %o4		/* read PSTATE reg */
2157c478bdstevel@tonic-gate	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
2167c478bdstevel@tonic-gate	wrpr	%o5, 0, %pstate
2177c478bdstevel@tonic-gate	lduba	[%o0]ASI_IO, %o0	/* load value via bypass ASI */
2187c478bdstevel@tonic-gate	retl
2197c478bdstevel@tonic-gate	wrpr	%g0, %o4, %pstate	/* restore pstate */
2207c478bdstevel@tonic-gate	SET_SIZE(ldbphysio)
2237c478bdstevel@tonic-gate * save_gsr(kfpu_t *fp)
2247c478bdstevel@tonic-gate * Store the graphics status register
2257c478bdstevel@tonic-gate */
2277c478bdstevel@tonic-gate	ENTRY_NP(save_gsr)
2287c478bdstevel@tonic-gate	rd	%gsr, %g2			! save gsr
2297c478bdstevel@tonic-gate	retl
2307c478bdstevel@tonic-gate	stx	%g2, [%o0 + FPU_GSR]
2317c478bdstevel@tonic-gate	SET_SIZE(save_gsr)
2337c478bdstevel@tonic-gate	ENTRY_NP(restore_gsr)
2347c478bdstevel@tonic-gate	ldx	[%o0 + FPU_GSR], %g2
2357c478bdstevel@tonic-gate	wr	%g2, %g0, %gsr
2367c478bdstevel@tonic-gate	retl
2377c478bdstevel@tonic-gate	nop
2387c478bdstevel@tonic-gate	SET_SIZE(restore_gsr)
2417c478bdstevel@tonic-gate * uint64_t
2425892374df * _fp_read_pgsr()
2437c478bdstevel@tonic-gate * Get the graphics status register info from fp and return it
2447c478bdstevel@tonic-gate */
2465892374df	ENTRY_NP(_fp_read_pgsr)
2477c478bdstevel@tonic-gate	retl
2487c478bdstevel@tonic-gate	rd	%gsr, %o0
2495892374df	SET_SIZE(_fp_read_pgsr)
2537c478bdstevel@tonic-gate * uint64_t
2547c478bdstevel@tonic-gate * get_gsr(kfpu_t *fp)
2557c478bdstevel@tonic-gate * Get the graphics status register info from fp and return it
2567c478bdstevel@tonic-gate */
2587c478bdstevel@tonic-gate	ENTRY_NP(get_gsr)
2597c478bdstevel@tonic-gate	retl
2607c478bdstevel@tonic-gate	ldx	[%o0 + FPU_GSR], %o0
2617c478bdstevel@tonic-gate	SET_SIZE(get_gsr)
2645892374df * _fp_write_pgsr(uint64_t *buf, kfpu_t *fp)
2657c478bdstevel@tonic-gate * Set the graphics status register info to fp from buf
2667c478bdstevel@tonic-gate */
2685892374df	ENTRY_NP(_fp_write_pgsr)
2697c478bdstevel@tonic-gate	retl
2707c478bdstevel@tonic-gate	mov	%o0, %gsr
2715892374df	SET_SIZE(_fp_write_pgsr)
2747c478bdstevel@tonic-gate * set_gsr(uint64_t buf, kfpu_t *fp)
2757c478bdstevel@tonic-gate * Set the graphics status register info to fp from buf
2767c478bdstevel@tonic-gate */
2787c478bdstevel@tonic-gate	ENTRY_NP(set_gsr)
2797c478bdstevel@tonic-gate	retl
2807c478bdstevel@tonic-gate	stx	%o0, [%o1 + FPU_GSR]
2817c478bdstevel@tonic-gate	SET_SIZE(set_gsr)
2837c478bdstevel@tonic-gate	ENTRY_NP(kdi_cpu_index)
2847c478bdstevel@tonic-gate	CPU_INDEX(%g1, %g2)
2857c478bdstevel@tonic-gate	jmp	%g7
2867c478bdstevel@tonic-gate	nop
2877c478bdstevel@tonic-gate	SET_SIZE(kdi_cpu_index)
289ae115bcmrj	ENTRY_NP(kmdb_enter)
290ae115bcmrj	t	ST_KMDB_TRAP
291ae115bcmrj	retl
292ae115bcmrj	nop
293ae115bcmrj	SET_SIZE(kmdb_enter)
2967bafd14jb * The Spitfire floating point code has been changed not to use install/
2977bafd14jb * save/restore/fork/freectx() because of the special memcpy library
2987bafd14jb * routines, which will lose too much performance if they have to go
2997bafd14jb * through the fp_disabled trap (which used to call installctx()). So
3007bafd14jb * now fp_save/fp_restore are called from resume, and they don't care
3017bafd14jb * whether floating point was enabled from the user program via the
3027bafd14jb * fp_enabled trap or from the memcpy library, which just turns on floating
3037bafd14jb * point in the fprs register itself. The new routine lwp_freeregs is
3047bafd14jb * called everywhere freectx is called, and code was added to the sun4u-
3057bafd14jb * specific version of lwp_forkregs (which is called everywhere forkctx
3067bafd14jb * is called) to handle forking the floating point registers.
3077bafd14jb *
3087bafd14jb * Note that for the fprs dirty upper/lower bits are not used for now,
3097bafd14jb * because the #instructions to determine if we need to use them is probably
3107bafd14jb * greater than the #insructions just using them. This is a possible future
3117bafd14jb * optimization, only do it with very careful benchmarking!
3127bafd14jb *
3137bafd14jb * The fp_fksave and and fp_load were split into two routines for the
3147bafd14jb * sake of efficiency between the getfpregs/xregs_getfpregs and
3157bafd14jb * setfpregs/xregs_setfpregs. But note that for saving and restoring
3167bafd14jb * context, both *must* happen. For prmachdep, aka access from [k]adb,
3177bafd14jb * it's OK if only one part happens.
3187bafd14jb */
3217bafd14jb * fp_save(kfpu_t *fp)
3227bafd14jb * fp_fksave(kfpu_t *fp)
3237bafd14jb * Store the floating point registers.
3247bafd14jb */
3267bafd14jb	ENTRY_NP(fp_save)
3277bafd14jb	ALTENTRY(fp_fksave)
3287bafd14jb	BSTORE_FPREGS(%o0, %o1)			! store V9 regs
3297bafd14jb	retl
3307bafd14jb	stx	%fsr, [%o0 + FPU_FSR]		! store fsr
3317bafd14jb	SET_SIZE(fp_fksave)
3327bafd14jb	SET_SIZE(fp_save)
3357bafd14jb * fp_v8_fksave(kfpu_t *fp)
3367bafd14jb *
3377bafd14jb * This is like the above routine but only saves the lower half.
3387bafd14jb */
3407bafd14jb	ENTRY_NP(fp_v8_fksave)
3417bafd14jb	BSTORE_V8_FPREGS(%o0, %o1)		! store V8 regs
3427bafd14jb	retl
3437bafd14jb	stx	%fsr, [%o0 + FPU_FSR]		! store fsr
3447bafd14jb	SET_SIZE(fp_v8_fksave)
3477bafd14jb * fp_v8p_fksave(kfpu_t *fp)
3487bafd14jb *
3497bafd14jb * This is like the above routine but only saves the upper half.
3507bafd14jb */
3527bafd14jb	ENTRY_NP(fp_v8p_fksave)
3537bafd14jb	BSTORE_V8P_FPREGS(%o0, %o1)		! store V9 extra regs
3547bafd14jb	retl
3557bafd14jb	stx	%fsr, [%o0 + FPU_FSR]		! store fsr
3567bafd14jb	SET_SIZE(fp_v8p_fksave)
3597bafd14jb * fp_restore(kfpu_t *fp)
3607bafd14jb */
3627bafd14jb	ENTRY_NP(fp_restore)
3637bafd14jb	BLOAD_FPREGS(%o0, %o1)			! load V9 regs
3647bafd14jb	retl
3657bafd14jb	ldx	[%o0 + FPU_FSR], %fsr		! restore fsr
3667bafd14jb	SET_SIZE(fp_restore)
3697bafd14jb * fp_v8_load(kfpu_t *fp)
3707bafd14jb */
3727bafd14jb	ENTRY_NP(fp_v8_load)
3737bafd14jb	BLOAD_V8_FPREGS(%o0, %o1)		! load V8 regs
3747bafd14jb	retl
3757bafd14jb	ldx	[%o0 + FPU_FSR], %fsr		! restore fsr
3767bafd14jb	SET_SIZE(fp_v8_load)
3797bafd14jb * fp_v8p_load(kfpu_t *fp)
3807bafd14jb */
3827bafd14jb	ENTRY_NP(fp_v8p_load)
3837bafd14jb	BLOAD_V8P_FPREGS(%o0, %o1)		! load V9 extra regs
3847bafd14jb	retl
3857bafd14jb	ldx	[%o0 + FPU_FSR], %fsr		! restore fsr
3867bafd14jb	SET_SIZE(fp_v8p_load)