xref: /illumos-gate/usr/src/uts/sun4/io/px/px_pec.c (revision e6b21d58)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
520036fe5Segillett  * Common Development and Distribution License (the "License").
620036fe5Segillett  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
21*e6b21d58SErwin T Tsaur 
227c478bd9Sstevel@tonic-gate /*
23*e6b21d58SErwin T Tsaur  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
247c478bd9Sstevel@tonic-gate  */
257c478bd9Sstevel@tonic-gate 
267c478bd9Sstevel@tonic-gate /*
277c478bd9Sstevel@tonic-gate  * PCI Express PEC implementation:
287c478bd9Sstevel@tonic-gate  *	initialization
297c478bd9Sstevel@tonic-gate  *	Bus error interrupt handler
307c478bd9Sstevel@tonic-gate  */
317c478bd9Sstevel@tonic-gate 
327c478bd9Sstevel@tonic-gate #include <sys/types.h>
337c478bd9Sstevel@tonic-gate #include <sys/kmem.h>
347c478bd9Sstevel@tonic-gate #include <sys/spl.h>
357c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h>
367c478bd9Sstevel@tonic-gate #include <sys/sunddi.h>
377c478bd9Sstevel@tonic-gate #include <sys/machsystm.h>	/* ldphysio() */
387c478bd9Sstevel@tonic-gate #include <sys/async.h>
397c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h>
407c478bd9Sstevel@tonic-gate #include <sys/ontrap.h>
417c478bd9Sstevel@tonic-gate #include <sys/membar.h>
427c478bd9Sstevel@tonic-gate #include "px_obj.h"
437c478bd9Sstevel@tonic-gate 
447c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/
457c478bd9Sstevel@tonic-gate 
467c478bd9Sstevel@tonic-gate extern uint_t px_ranges_phi_mask;
477c478bd9Sstevel@tonic-gate 
48f8d2de6bSjchu static uint_t px_pec_error_intr(caddr_t a);
497c478bd9Sstevel@tonic-gate 
507c478bd9Sstevel@tonic-gate int
px_pec_attach(px_t * px_p)517c478bd9Sstevel@tonic-gate px_pec_attach(px_t *px_p)
527c478bd9Sstevel@tonic-gate {
537c478bd9Sstevel@tonic-gate 	px_pec_t *pec_p;
547c478bd9Sstevel@tonic-gate 	int i, len;
5526947304SEvan Yan 	int nrange = px_p->px_ranges_length / sizeof (pci_ranges_t);
567c478bd9Sstevel@tonic-gate 	dev_info_t *dip = px_p->px_dip;
5726947304SEvan Yan 	pci_ranges_t *rangep = px_p->px_ranges_p;
587c478bd9Sstevel@tonic-gate 
597c478bd9Sstevel@tonic-gate 	/*
607c478bd9Sstevel@tonic-gate 	 * Allocate a state structure for the PEC and cross-link it
617c478bd9Sstevel@tonic-gate 	 * to its per px node state structure.
627c478bd9Sstevel@tonic-gate 	 */
637c478bd9Sstevel@tonic-gate 	pec_p = kmem_zalloc(sizeof (px_pec_t), KM_SLEEP);
647c478bd9Sstevel@tonic-gate 	px_p->px_pec_p = pec_p;
657c478bd9Sstevel@tonic-gate 	pec_p->pec_px_p = px_p;
667c478bd9Sstevel@tonic-gate 
677c478bd9Sstevel@tonic-gate 	len = snprintf(pec_p->pec_nameinst_str,
68d36395bdSrameshc 	    sizeof (pec_p->pec_nameinst_str),
69d36395bdSrameshc 	    "%s%d", NAMEINST(dip));
707c478bd9Sstevel@tonic-gate 	pec_p->pec_nameaddr_str = pec_p->pec_nameinst_str + ++len;
717c478bd9Sstevel@tonic-gate 	(void) snprintf(pec_p->pec_nameaddr_str,
72d36395bdSrameshc 	    sizeof (pec_p->pec_nameinst_str) - len,
73d36395bdSrameshc 	    "%s@%s", NAMEADDR(dip));
747c478bd9Sstevel@tonic-gate 
757c478bd9Sstevel@tonic-gate 	/*
767c478bd9Sstevel@tonic-gate 	 * Get this pec's mem32 and mem64 segments to determine whether
777c478bd9Sstevel@tonic-gate 	 * a dma object originates from ths pec. i.e. dev to dev dma
787c478bd9Sstevel@tonic-gate 	 */
797c478bd9Sstevel@tonic-gate 	for (i = 0; i < nrange; i++, rangep++) {
807c478bd9Sstevel@tonic-gate 		uint64_t rng_addr, rng_size, *pfnbp, *pfnlp;
817c478bd9Sstevel@tonic-gate 		uint32_t rng_type = rangep->child_high & PCI_ADDR_MASK;
827c478bd9Sstevel@tonic-gate 
837c478bd9Sstevel@tonic-gate 		switch (rng_type) {
847c478bd9Sstevel@tonic-gate 			case PCI_ADDR_MEM32:
857c478bd9Sstevel@tonic-gate 				pfnbp = &pec_p->pec_base32_pfn;
867c478bd9Sstevel@tonic-gate 				pfnlp = &pec_p->pec_last32_pfn;
877c478bd9Sstevel@tonic-gate 				break;
887c478bd9Sstevel@tonic-gate 
897c478bd9Sstevel@tonic-gate 			case PCI_ADDR_MEM64:
907c478bd9Sstevel@tonic-gate 				pfnbp = &pec_p->pec_base64_pfn;
917c478bd9Sstevel@tonic-gate 				pfnlp = &pec_p->pec_last64_pfn;
927c478bd9Sstevel@tonic-gate 				break;
937c478bd9Sstevel@tonic-gate 
947c478bd9Sstevel@tonic-gate 			case PCI_ADDR_CONFIG:
957c478bd9Sstevel@tonic-gate 			case PCI_ADDR_IO:
967c478bd9Sstevel@tonic-gate 			default:
977c478bd9Sstevel@tonic-gate 				continue;
987c478bd9Sstevel@tonic-gate 		}
997c478bd9Sstevel@tonic-gate 		rng_addr = (uint64_t)(rangep->parent_high &
100d36395bdSrameshc 		    px_ranges_phi_mask) << 32;
1017c478bd9Sstevel@tonic-gate 		rng_addr |= (uint64_t)rangep->parent_low;
1027c478bd9Sstevel@tonic-gate 		rng_size = (uint64_t)rangep->size_high << 32;
1037c478bd9Sstevel@tonic-gate 		rng_size |= (uint64_t)rangep->size_low;
1047c478bd9Sstevel@tonic-gate 
1057c478bd9Sstevel@tonic-gate 		*pfnbp = mmu_btop(rng_addr);
1067c478bd9Sstevel@tonic-gate 		*pfnlp = mmu_btop(rng_addr + rng_size);
1077c478bd9Sstevel@tonic-gate 	}
1087c478bd9Sstevel@tonic-gate 
109d36395bdSrameshc 	/*
110d36395bdSrameshc 	 * This lock is for serializing safe acc calls. It is not associated
111d36395bdSrameshc 	 * with an iblock cookie.
112d36395bdSrameshc 	 */
113d36395bdSrameshc 	mutex_init(&pec_p->pec_pokefault_mutex, NULL, MUTEX_DRIVER, NULL);
1147c478bd9Sstevel@tonic-gate 
1157c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
1167c478bd9Sstevel@tonic-gate }
1177c478bd9Sstevel@tonic-gate 
1187c478bd9Sstevel@tonic-gate void
px_pec_detach(px_t * px_p)1197c478bd9Sstevel@tonic-gate px_pec_detach(px_t *px_p)
1207c478bd9Sstevel@tonic-gate {
1217c478bd9Sstevel@tonic-gate 	dev_info_t *dip = px_p->px_dip;
1227c478bd9Sstevel@tonic-gate 	px_pec_t *pec_p = px_p->px_pec_p;
1237c478bd9Sstevel@tonic-gate 
1247c478bd9Sstevel@tonic-gate 	/*
1257c478bd9Sstevel@tonic-gate 	 * Free the pokefault mutex.
1267c478bd9Sstevel@tonic-gate 	 */
1277c478bd9Sstevel@tonic-gate 	DBG(DBG_DETACH, dip, "px_pec_detach:\n");
1287c478bd9Sstevel@tonic-gate 	mutex_destroy(&pec_p->pec_pokefault_mutex);
1297c478bd9Sstevel@tonic-gate 
1307c478bd9Sstevel@tonic-gate 	/*
1317c478bd9Sstevel@tonic-gate 	 * Free the pec state structure.
1327c478bd9Sstevel@tonic-gate 	 */
1337c478bd9Sstevel@tonic-gate 	kmem_free(pec_p, sizeof (px_pec_t));
1347c478bd9Sstevel@tonic-gate 	px_p->px_pec_p = NULL;
1357c478bd9Sstevel@tonic-gate }
1367c478bd9Sstevel@tonic-gate 
1377c478bd9Sstevel@tonic-gate /*
1387c478bd9Sstevel@tonic-gate  * pec_msg_add_intr:
1397c478bd9Sstevel@tonic-gate  *
1407c478bd9Sstevel@tonic-gate  * Add interrupt handlers to process correctable/fatal/non fatal
1417c478bd9Sstevel@tonic-gate  * PCIE messages.
1427c478bd9Sstevel@tonic-gate  */
143*e6b21d58SErwin T Tsaur int
px_pec_msg_add_intr(px_t * px_p)1447c478bd9Sstevel@tonic-gate px_pec_msg_add_intr(px_t *px_p)
1457c478bd9Sstevel@tonic-gate {
1467c478bd9Sstevel@tonic-gate 	dev_info_t		*dip = px_p->px_dip;
1477c478bd9Sstevel@tonic-gate 	px_pec_t		*pec_p = px_p->px_pec_p;
1487c478bd9Sstevel@tonic-gate 	ddi_intr_handle_impl_t	hdl;
1497c478bd9Sstevel@tonic-gate 	int			ret = DDI_SUCCESS;
1507c478bd9Sstevel@tonic-gate 
1517c478bd9Sstevel@tonic-gate 	DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_add_intr\n");
1527c478bd9Sstevel@tonic-gate 
15320036fe5Segillett 	/* Initialize handle */
15420036fe5Segillett 	bzero(&hdl, sizeof (ddi_intr_handle_impl_t));
155f8d2de6bSjchu 	hdl.ih_cb_func = (ddi_intr_handler_t *)px_err_fabric_intr;
1567c478bd9Sstevel@tonic-gate 	hdl.ih_ver = DDI_INTR_VERSION;
1577c478bd9Sstevel@tonic-gate 	hdl.ih_state = DDI_IHDL_STATE_ALLOC;
1587c478bd9Sstevel@tonic-gate 	hdl.ih_dip = dip;
1597c478bd9Sstevel@tonic-gate 
1607c478bd9Sstevel@tonic-gate 	/* Add correctable error message handler */
161f8d2de6bSjchu 	hdl.ih_pri = PX_ERR_LOW_PIL;
1627c478bd9Sstevel@tonic-gate 
1637c478bd9Sstevel@tonic-gate 	if ((ret = px_add_msiq_intr(dip, dip, &hdl,
16409b1eac2SEvan Yan 	    MSG_REC, (msgcode_t)PCIE_CORR_MSG, -1,
1657c478bd9Sstevel@tonic-gate 	    &pec_p->pec_corr_msg_msiq_id)) != DDI_SUCCESS) {
1667c478bd9Sstevel@tonic-gate 		DBG(DBG_MSG, px_p->px_dip,
1677c478bd9Sstevel@tonic-gate 		    "PCIE_CORR_MSG registration failed\n");
1687c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
1697c478bd9Sstevel@tonic-gate 	}
1707c478bd9Sstevel@tonic-gate 
1717c478bd9Sstevel@tonic-gate 	px_lib_msg_setmsiq(dip, PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id);
1727c478bd9Sstevel@tonic-gate 	px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_VALID);
1737c478bd9Sstevel@tonic-gate 
174b0fc0e77Sgovinda 	if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
175b0fc0e77Sgovinda 	    px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id),
176b0fc0e77Sgovinda 	    PX_ERR_LOW_PIL, PX_INTR_STATE_ENABLE, MSG_REC,
177b0fc0e77Sgovinda 	    PCIE_CORR_MSG)) != DDI_SUCCESS) {
17836fe4a92Segillett 		DBG(DBG_MSG, px_p->px_dip,
17936fe4a92Segillett 		    "PCIE_CORR_MSG update interrupt state failed\n");
18036fe4a92Segillett 		return (DDI_FAILURE);
18136fe4a92Segillett 	}
18236fe4a92Segillett 
1837c478bd9Sstevel@tonic-gate 	/* Add non-fatal error message handler */
184f8d2de6bSjchu 	hdl.ih_pri = PX_ERR_PIL;
1857c478bd9Sstevel@tonic-gate 
1867c478bd9Sstevel@tonic-gate 	if ((ret = px_add_msiq_intr(dip, dip, &hdl,
18709b1eac2SEvan Yan 	    MSG_REC, (msgcode_t)PCIE_NONFATAL_MSG, -1,
1887c478bd9Sstevel@tonic-gate 	    &pec_p->pec_non_fatal_msg_msiq_id)) != DDI_SUCCESS) {
1897c478bd9Sstevel@tonic-gate 		DBG(DBG_MSG, px_p->px_dip,
1907c478bd9Sstevel@tonic-gate 		    "PCIE_NONFATAL_MSG registration failed\n");
1917c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
1927c478bd9Sstevel@tonic-gate 	}
1937c478bd9Sstevel@tonic-gate 
1947c478bd9Sstevel@tonic-gate 	px_lib_msg_setmsiq(dip, PCIE_NONFATAL_MSG,
1957c478bd9Sstevel@tonic-gate 	    pec_p->pec_non_fatal_msg_msiq_id);
1967c478bd9Sstevel@tonic-gate 	px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG, PCIE_MSG_VALID);
1977c478bd9Sstevel@tonic-gate 
198b0fc0e77Sgovinda 	if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
199b0fc0e77Sgovinda 	    px_msiqid_to_devino(px_p, pec_p->pec_non_fatal_msg_msiq_id),
200b0fc0e77Sgovinda 	    PX_ERR_PIL, PX_INTR_STATE_ENABLE, MSG_REC,
20136fe4a92Segillett 	    PCIE_NONFATAL_MSG)) != DDI_SUCCESS) {
20236fe4a92Segillett 		DBG(DBG_MSG, px_p->px_dip,
20336fe4a92Segillett 		    "PCIE_NONFATAL_MSG update interrupt state failed\n");
20436fe4a92Segillett 		return (DDI_FAILURE);
20536fe4a92Segillett 	}
20636fe4a92Segillett 
2077c478bd9Sstevel@tonic-gate 	/* Add fatal error message handler */
208f8d2de6bSjchu 	hdl.ih_pri = PX_ERR_PIL;
2097c478bd9Sstevel@tonic-gate 
2107c478bd9Sstevel@tonic-gate 	if ((ret = px_add_msiq_intr(dip, dip, &hdl,
21109b1eac2SEvan Yan 	    MSG_REC, (msgcode_t)PCIE_FATAL_MSG, -1,
2127c478bd9Sstevel@tonic-gate 	    &pec_p->pec_fatal_msg_msiq_id)) != DDI_SUCCESS) {
2137c478bd9Sstevel@tonic-gate 		DBG(DBG_MSG, px_p->px_dip,
2147c478bd9Sstevel@tonic-gate 		    "PCIE_FATAL_MSG registration failed\n");
2157c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
2167c478bd9Sstevel@tonic-gate 	}
2177c478bd9Sstevel@tonic-gate 
2187c478bd9Sstevel@tonic-gate 	px_lib_msg_setmsiq(dip, PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id);
2197c478bd9Sstevel@tonic-gate 	px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_VALID);
2207c478bd9Sstevel@tonic-gate 
221b0fc0e77Sgovinda 	if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
222b0fc0e77Sgovinda 	    px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id), PX_ERR_PIL,
223b0fc0e77Sgovinda 	    PX_INTR_STATE_ENABLE, MSG_REC, PCIE_FATAL_MSG)) != DDI_SUCCESS) {
22436fe4a92Segillett 		DBG(DBG_MSG, px_p->px_dip,
22536fe4a92Segillett 		    "PCIE_FATAL_MSG update interrupt state failed\n");
22636fe4a92Segillett 		return (DDI_FAILURE);
22736fe4a92Segillett 	}
22836fe4a92Segillett 
2297c478bd9Sstevel@tonic-gate 	return (ret);
2307c478bd9Sstevel@tonic-gate }
2317c478bd9Sstevel@tonic-gate 
2327c478bd9Sstevel@tonic-gate /*
2337c478bd9Sstevel@tonic-gate  * px_pec_msg_rem_intr:
2347c478bd9Sstevel@tonic-gate  *
2357c478bd9Sstevel@tonic-gate  * Remove interrupt handlers to process correctable/fatal/non fatal
2367c478bd9Sstevel@tonic-gate  * PCIE messages. For now, all these PCIe messages are mapped to
2377c478bd9Sstevel@tonic-gate  * same MSIQ.
2387c478bd9Sstevel@tonic-gate  */
239*e6b21d58SErwin T Tsaur void
px_pec_msg_rem_intr(px_t * px_p)2407c478bd9Sstevel@tonic-gate px_pec_msg_rem_intr(px_t *px_p)
2417c478bd9Sstevel@tonic-gate {
2427c478bd9Sstevel@tonic-gate 	dev_info_t		*dip = px_p->px_dip;
2437c478bd9Sstevel@tonic-gate 	px_pec_t		*pec_p = px_p->px_pec_p;
2447c478bd9Sstevel@tonic-gate 	ddi_intr_handle_impl_t	hdl;
2457c478bd9Sstevel@tonic-gate 
2467c478bd9Sstevel@tonic-gate 	DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_rem_intr: dip 0x%p\n", dip);
2477c478bd9Sstevel@tonic-gate 
24820036fe5Segillett 	/* Initialize handle */
24920036fe5Segillett 	bzero(&hdl, sizeof (ddi_intr_handle_impl_t));
2507c478bd9Sstevel@tonic-gate 	hdl.ih_ver = DDI_INTR_VERSION;
2517c478bd9Sstevel@tonic-gate 	hdl.ih_state = DDI_IHDL_STATE_ALLOC;
2527c478bd9Sstevel@tonic-gate 	hdl.ih_dip = dip;
2537c478bd9Sstevel@tonic-gate 
254665a7fcaSgovinda 	/* Remove correctable error message handler */
2557c478bd9Sstevel@tonic-gate 	if (pec_p->pec_corr_msg_msiq_id >= 0) {
2567c478bd9Sstevel@tonic-gate 		px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_INVALID);
2577c478bd9Sstevel@tonic-gate 
258665a7fcaSgovinda 		hdl.ih_pri = PX_ERR_LOW_PIL;
2597c478bd9Sstevel@tonic-gate 		(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC,
2607c478bd9Sstevel@tonic-gate 		    PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id);
26136fe4a92Segillett 
262b0fc0e77Sgovinda 		(void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
263b0fc0e77Sgovinda 		    px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id),
264b0fc0e77Sgovinda 		    PX_ERR_LOW_PIL, PX_INTR_STATE_DISABLE, MSG_REC,
265b0fc0e77Sgovinda 		    PCIE_CORR_MSG);
26636fe4a92Segillett 
267055d7c80Scarlsonj 		pec_p->pec_corr_msg_msiq_id = (msiqid_t)-1;
2687c478bd9Sstevel@tonic-gate 	}
2697c478bd9Sstevel@tonic-gate 
270665a7fcaSgovinda 	/* Remove non-fatal error message handler */
2717c478bd9Sstevel@tonic-gate 	if (pec_p->pec_non_fatal_msg_msiq_id >= 0) {
2727c478bd9Sstevel@tonic-gate 		px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG,
2737c478bd9Sstevel@tonic-gate 		    PCIE_MSG_INVALID);
2747c478bd9Sstevel@tonic-gate 
275665a7fcaSgovinda 		hdl.ih_pri = PX_ERR_PIL;
2767c478bd9Sstevel@tonic-gate 		(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC,
2777c478bd9Sstevel@tonic-gate 		    PCIE_NONFATAL_MSG, pec_p->pec_non_fatal_msg_msiq_id);
2787c478bd9Sstevel@tonic-gate 
279b0fc0e77Sgovinda 		(void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
280b0fc0e77Sgovinda 		    px_msiqid_to_devino(px_p, pec_p->pec_non_fatal_msg_msiq_id),
281b0fc0e77Sgovinda 		    PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC,
282b0fc0e77Sgovinda 		    PCIE_NONFATAL_MSG);
28336fe4a92Segillett 
284055d7c80Scarlsonj 		pec_p->pec_non_fatal_msg_msiq_id = (msiqid_t)-1;
2857c478bd9Sstevel@tonic-gate 	}
2867c478bd9Sstevel@tonic-gate 
287665a7fcaSgovinda 	/* Remove fatal error message handler */
2887c478bd9Sstevel@tonic-gate 	if (pec_p->pec_fatal_msg_msiq_id >= 0) {
2897c478bd9Sstevel@tonic-gate 		px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_INVALID);
2907c478bd9Sstevel@tonic-gate 
291665a7fcaSgovinda 		hdl.ih_pri = PX_ERR_PIL;
2927c478bd9Sstevel@tonic-gate 		(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC,
2937c478bd9Sstevel@tonic-gate 		    PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id);
2947c478bd9Sstevel@tonic-gate 
295b0fc0e77Sgovinda 		(void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
296b0fc0e77Sgovinda 		    px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id),
297b0fc0e77Sgovinda 		    PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, PCIE_FATAL_MSG);
29836fe4a92Segillett 
299055d7c80Scarlsonj 		pec_p->pec_fatal_msg_msiq_id = (msiqid_t)-1;
3007c478bd9Sstevel@tonic-gate 	}
3017c478bd9Sstevel@tonic-gate }
302