xref: /illumos-gate/usr/src/uts/sun4/io/px/px_fm.h (revision e6b21d58)
1f8d2de6bSjchu /*
2f8d2de6bSjchu  * CDDL HEADER START
3f8d2de6bSjchu  *
4f8d2de6bSjchu  * The contents of this file are subject to the terms of the
5bf8fc234Set  * Common Development and Distribution License (the "License").
6bf8fc234Set  * You may not use this file except in compliance with the License.
7f8d2de6bSjchu  *
8f8d2de6bSjchu  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9f8d2de6bSjchu  * or http://www.opensolaris.org/os/licensing.
10f8d2de6bSjchu  * See the License for the specific language governing permissions
11f8d2de6bSjchu  * and limitations under the License.
12f8d2de6bSjchu  *
13f8d2de6bSjchu  * When distributing Covered Code, include this CDDL HEADER in each
14f8d2de6bSjchu  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15f8d2de6bSjchu  * If applicable, add the following below this CDDL HEADER, with the
16f8d2de6bSjchu  * fields enclosed by brackets "[]" replaced with your own identifying
17f8d2de6bSjchu  * information: Portions Copyright [yyyy] [name of copyright owner]
18f8d2de6bSjchu  *
19f8d2de6bSjchu  * CDDL HEADER END
20f8d2de6bSjchu  */
21f8d2de6bSjchu /*
22d0f40dc6SKrishna Elango  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23f8d2de6bSjchu  */
24f8d2de6bSjchu 
25f8d2de6bSjchu #ifndef _SYS_PX_FM_H
26f8d2de6bSjchu #define	_SYS_PX_FM_H
27f8d2de6bSjchu 
28f8d2de6bSjchu #ifdef	__cplusplus
29f8d2de6bSjchu extern "C" {
30f8d2de6bSjchu #endif
31f8d2de6bSjchu 
32f8d2de6bSjchu #define	PX_ERR_PIL	14
33f8d2de6bSjchu #define	PX_ERR_LOW_PIL  9
34f8d2de6bSjchu 
35f8d2de6bSjchu /*
36f8d2de6bSjchu  * Error handlers maybe called due to trap or interrupts
37f8d2de6bSjchu  * occured.
38f8d2de6bSjchu  */
39f8d2de6bSjchu #define	PX_TRAP_CALL	0
40f8d2de6bSjchu #define	PX_INTR_CALL	1
41f8d2de6bSjchu #define	PX_LIB_CALL	2
42f8d2de6bSjchu 
43f8d2de6bSjchu /*
44f8d2de6bSjchu  * Definition of Fire internal error severity -
45bf8fc234Set  * HW Reset     Errors that cause hardware to automatically reset. Software is
46bf8fc234Set  *              being reset along, sticky status bits need to be cleaned up upon
47bf8fc234Set  *              system initialization.
48bf8fc234Set  * Panic        Errors that definitely result in panic'ing the system.
49bf8fc234Set  * Expected     Expected error, do not panic, plus do not send ereport.
50bf8fc234Set  * Protected    Errors SW to determine panic or not, forgivable for safe access.
51bf8fc234Set  *              Set when SW determines this error is forgivable during safe acc.
52bf8fc234Set  * No-panic     Errors that don't directly result in panic'ing the system.
53bf8fc234Set  * No-Error     When an interrupt occured and no errors were seen
54d0f40dc6SKrishna Elango  * Fabric Scan	Indicates that fabric scan will determine final severity of a
55d0f40dc6SKrishna Elango  *		panicable error.
56f8d2de6bSjchu  */
57d0f40dc6SKrishna Elango #define	PX_FABRIC_SCAN		(0x1 << 6)
58bf8fc234Set #define	PX_HW_RESET		(0x1 << 5)
59bf8fc234Set #define	PX_PANIC		(0x1 << 4)
60bf8fc234Set #define	PX_EXPECTED		(0x1 << 3)
61bf8fc234Set #define	PX_PROTECTED		(0x1 << 2)
62bf8fc234Set #define	PX_NO_PANIC		(0x1 << 1)
63bf8fc234Set #define	PX_NO_ERROR		(0x1 << 0)
64f8d2de6bSjchu 
65bf8fc234Set #define	PX_HB		(0x1 << 2)
66bf8fc234Set #define	PX_RP		(0x1 << 1)
67bf8fc234Set #define	PX_RC		(0x1 << 0)
688bc7d88aSet 
69bf8fc234Set /*
70bf8fc234Set  * Generic PCIe Root Port Error Handling
71bf8fc234Set  * This struct must align with px_pec_err_t in sun4v/io/px/px_err.h
72bf8fc234Set  */
73bf8fc234Set typedef struct px_err_pcie {
74bf8fc234Set 	uint32_t tx_hdr1;	/* sysino */
75bf8fc234Set 	uint32_t tx_hdr2;	/* sysino */
76bf8fc234Set 	uint32_t tx_hdr3;	/* ehdl */
77bf8fc234Set 	uint32_t tx_hdr4;	/* ehdl */
78bf8fc234Set 	uint32_t primary_ue;	/* stick */
79bf8fc234Set 	uint32_t rsvd0;		/* stick */
80bf8fc234Set 	uint32_t rsvd1;		/* pec_desc */
81bf8fc234Set 	uint16_t pci_err_status;
82bf8fc234Set 	uint16_t pcie_err_status;
83bf8fc234Set 	uint32_t ce_reg;
84bf8fc234Set 	uint32_t ue_reg;
85bf8fc234Set 	uint32_t rx_hdr1;	/* hdr[0] */
86bf8fc234Set 	uint32_t rx_hdr2;	/* hdr[0] */
87bf8fc234Set 	uint32_t rx_hdr3;	/* hdr[1] */
88bf8fc234Set 	uint32_t rx_hdr4;	/* hdr[1] */
89bf8fc234Set 	uint32_t rsvd3;		/* err_src_reg */
90bf8fc234Set 	uint32_t rsvd4;		/* root err status */
91bf8fc234Set } px_err_pcie_t;
92bf8fc234Set 
93bf8fc234Set #define	PX_FM_BLOCK_HOST	(0x1 << 0)
94bf8fc234Set #define	PX_FM_BLOCK_PCIE	(0x1 << 1)
95bf8fc234Set #define	PX_FM_BLOCK_ALL		(PX_FM_BLOCK_HOST | PX_FM_BLOCK_PCIE)
968bc7d88aSet 
97f8d2de6bSjchu /*
98f8d2de6bSjchu  * Error handling FMA hook
99f8d2de6bSjchu  */
100f8d2de6bSjchu extern void px_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle);
101f8d2de6bSjchu extern void px_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle);
102f8d2de6bSjchu extern int px_fm_attach(px_t *px_p);
103f8d2de6bSjchu extern void px_fm_detach(px_t *px_p);
104*e6b21d58SErwin T Tsaur extern void px_fm_cb_enable(px_t *px_p);
105*e6b21d58SErwin T Tsaur extern void px_fm_cb_disable(px_t *px_p);
106f8d2de6bSjchu extern int px_fm_init_child(dev_info_t *, dev_info_t *, int,
107f8d2de6bSjchu     ddi_iblock_cookie_t *);
108eae2e508Skrishnae extern void px_fm_acc_setup(ddi_map_req_t *, dev_info_t *, pci_regspec_t *rp);
109f8d2de6bSjchu extern int px_fm_callback(dev_info_t *, ddi_fm_error_t *, const void *);
110bf8fc234Set extern int px_err_cmn_intr(px_t *, ddi_fm_error_t *, int, int);
111f8d2de6bSjchu 
112f8d2de6bSjchu /*
113f8d2de6bSjchu  * Fire interrupt handlers
114f8d2de6bSjchu  */
115f8d2de6bSjchu extern uint_t px_err_cb_intr(caddr_t arg);
116f8d2de6bSjchu extern uint_t px_err_dmc_pec_intr(caddr_t arg);
117f8d2de6bSjchu extern uint_t px_err_fabric_intr(px_t *px_p, msgcode_t msg_code,
118f8d2de6bSjchu     pcie_req_id_t rid);
119f8d2de6bSjchu 
120f8d2de6bSjchu /*
121f8d2de6bSjchu  * Common error handling functions
122f8d2de6bSjchu  */
123eae2e508Skrishnae extern int px_scan_fabric(px_t *px_p, dev_info_t *rdip, ddi_fm_error_t *derr);
124f8d2de6bSjchu extern void px_err_safeacc_check(px_t *px_p, ddi_fm_error_t *derr);
125bf8fc234Set extern int px_err_check_eq(dev_info_t *dip);
126bf8fc234Set extern int px_err_check_pcie(dev_info_t *dip, ddi_fm_error_t *derr,
1275613d828SKrishna Elango     px_err_pcie_t *regs, pf_intr_type_t intr_type);
128eae2e508Skrishnae extern int px_fm_enter(px_t *px_p);
129eae2e508Skrishnae extern void px_fm_exit(px_t *px_p);
130eae2e508Skrishnae extern void px_err_panic(int err, int msg, int fab_err, boolean_t isTest);
131fc256490SJason Beloro extern pf_data_t *px_rp_en_q(px_t *px_p, pcie_req_id_t fault_bdf,
132bf8fc234Set     uint32_t fault_addr, uint16_t s_status);
133fc256490SJason Beloro extern pf_data_t *px_get_pfd(px_t *px_p);
134f8d2de6bSjchu 
135eae2e508Skrishnae /*
136eae2e508Skrishnae  * Sparc specific cfg, pio and dma handle lookup/check functions
137eae2e508Skrishnae  */
138eae2e508Skrishnae extern int px_err_cfg_hdl_check(dev_info_t *dip, const void *handle,
139eae2e508Skrishnae     const void *addr, const void *not_used);
140eae2e508Skrishnae extern int px_err_pio_hdl_check(dev_info_t *dip, const void *handle,
141eae2e508Skrishnae     const void *addr, const void *not_used);
142eae2e508Skrishnae extern int px_err_dma_hdl_check(dev_info_t *dip, const void *handle,
143eae2e508Skrishnae     const void *addr, const void *not_used);
144eae2e508Skrishnae 
145f8d2de6bSjchu #ifdef	__cplusplus
146f8d2de6bSjchu }
147f8d2de6bSjchu #endif
148f8d2de6bSjchu 
149f8d2de6bSjchu #endif	/* _SYS_PX_FM_H */
150