xref: /illumos-gate/usr/src/uts/sparc/sys/machlock.h (revision 7c478bd95313f5f23a4c958a745db2134aa0324)
1*7c478bd9Sstevel@tonic-gate /*
2*7c478bd9Sstevel@tonic-gate  * CDDL HEADER START
3*7c478bd9Sstevel@tonic-gate  *
4*7c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5*7c478bd9Sstevel@tonic-gate  * Common Development and Distribution License, Version 1.0 only
6*7c478bd9Sstevel@tonic-gate  * (the "License").  You may not use this file except in compliance
7*7c478bd9Sstevel@tonic-gate  * with the License.
8*7c478bd9Sstevel@tonic-gate  *
9*7c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*7c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
11*7c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
12*7c478bd9Sstevel@tonic-gate  * and limitations under the License.
13*7c478bd9Sstevel@tonic-gate  *
14*7c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
15*7c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*7c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
17*7c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
18*7c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
19*7c478bd9Sstevel@tonic-gate  *
20*7c478bd9Sstevel@tonic-gate  * CDDL HEADER END
21*7c478bd9Sstevel@tonic-gate  */
22*7c478bd9Sstevel@tonic-gate /*
23*7c478bd9Sstevel@tonic-gate  * Copyright 1990-2003 Sun Microsystems, Inc.  All rights reserved.
24*7c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
25*7c478bd9Sstevel@tonic-gate  */
26*7c478bd9Sstevel@tonic-gate 
27*7c478bd9Sstevel@tonic-gate #ifndef _SYS_MACHLOCK_H
28*7c478bd9Sstevel@tonic-gate #define	_SYS_MACHLOCK_H
29*7c478bd9Sstevel@tonic-gate 
30*7c478bd9Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
31*7c478bd9Sstevel@tonic-gate 
32*7c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
33*7c478bd9Sstevel@tonic-gate extern "C" {
34*7c478bd9Sstevel@tonic-gate #endif
35*7c478bd9Sstevel@tonic-gate 
36*7c478bd9Sstevel@tonic-gate #ifndef	_ASM
37*7c478bd9Sstevel@tonic-gate 
38*7c478bd9Sstevel@tonic-gate #include <sys/types.h>
39*7c478bd9Sstevel@tonic-gate 
40*7c478bd9Sstevel@tonic-gate #ifdef _KERNEL
41*7c478bd9Sstevel@tonic-gate 
42*7c478bd9Sstevel@tonic-gate extern void	lock_set(lock_t *lp);
43*7c478bd9Sstevel@tonic-gate extern int	lock_try(lock_t *lp);
44*7c478bd9Sstevel@tonic-gate extern int	lock_spin_try(lock_t *lp);
45*7c478bd9Sstevel@tonic-gate extern int	ulock_try(lock_t *lp);
46*7c478bd9Sstevel@tonic-gate extern void	ulock_clear(lock_t *lp);
47*7c478bd9Sstevel@tonic-gate extern void	lock_clear(lock_t *lp);
48*7c478bd9Sstevel@tonic-gate extern void	lock_set_spl(lock_t *lp, int new_pil, ushort_t *old_pil);
49*7c478bd9Sstevel@tonic-gate extern void	lock_clear_splx(lock_t *lp, int s);
50*7c478bd9Sstevel@tonic-gate 
51*7c478bd9Sstevel@tonic-gate #endif	/* _KERNEL */
52*7c478bd9Sstevel@tonic-gate 
53*7c478bd9Sstevel@tonic-gate #define	LOCK_HELD_VALUE		0xff
54*7c478bd9Sstevel@tonic-gate #define	LOCK_INIT_CLEAR(lp)	(*(lp) = 0)
55*7c478bd9Sstevel@tonic-gate #define	LOCK_INIT_HELD(lp)	(*(lp) = LOCK_HELD_VALUE)
56*7c478bd9Sstevel@tonic-gate #define	LOCK_HELD(lp)		(*(volatile lock_t *)(lp) != 0)
57*7c478bd9Sstevel@tonic-gate 
58*7c478bd9Sstevel@tonic-gate typedef	lock_t	disp_lock_t;		/* dispatcher lock type */
59*7c478bd9Sstevel@tonic-gate 
60*7c478bd9Sstevel@tonic-gate /*
61*7c478bd9Sstevel@tonic-gate  * SPIN_LOCK() macro indicates whether lock is implemented as a spin lock or
62*7c478bd9Sstevel@tonic-gate  * an adaptive mutex, depending on what interrupt levels use it.
63*7c478bd9Sstevel@tonic-gate  */
64*7c478bd9Sstevel@tonic-gate #define	SPIN_LOCK(pl)	((pl) > ipltospl(LOCK_LEVEL))
65*7c478bd9Sstevel@tonic-gate 
66*7c478bd9Sstevel@tonic-gate /*
67*7c478bd9Sstevel@tonic-gate  * Macro to control loops which spin on a lock and then check state
68*7c478bd9Sstevel@tonic-gate  * periodically.  Its passed an integer, and returns a boolean value
69*7c478bd9Sstevel@tonic-gate  * that if true indicates its a good time to get the scheduler lock and
70*7c478bd9Sstevel@tonic-gate  * check the state of the current owner of the lock.
71*7c478bd9Sstevel@tonic-gate  */
72*7c478bd9Sstevel@tonic-gate #define	LOCK_SAMPLE_INTERVAL(i)	(((i) & 0xff) == 0)
73*7c478bd9Sstevel@tonic-gate 
74*7c478bd9Sstevel@tonic-gate /*
75*7c478bd9Sstevel@tonic-gate  * Extern for CLOCK_LOCK.
76*7c478bd9Sstevel@tonic-gate  */
77*7c478bd9Sstevel@tonic-gate extern	int	hres_lock;
78*7c478bd9Sstevel@tonic-gate 
79*7c478bd9Sstevel@tonic-gate #endif	/* _ASM */
80*7c478bd9Sstevel@tonic-gate 
81*7c478bd9Sstevel@tonic-gate /*
82*7c478bd9Sstevel@tonic-gate  * The definitions of the symbolic interrupt levels:
83*7c478bd9Sstevel@tonic-gate  *
84*7c478bd9Sstevel@tonic-gate  *   CLOCK_LEVEL =>  The level at which one must be to block the clock.
85*7c478bd9Sstevel@tonic-gate  *
86*7c478bd9Sstevel@tonic-gate  *   LOCK_LEVEL  =>  The highest level at which one may block (and thus the
87*7c478bd9Sstevel@tonic-gate  *                   highest level at which one may acquire adaptive locks)
88*7c478bd9Sstevel@tonic-gate  *                   Also the highest level at which one may be preempted.
89*7c478bd9Sstevel@tonic-gate  *
90*7c478bd9Sstevel@tonic-gate  *   DISP_LEVEL  =>  The level at which one must be to perform dispatcher
91*7c478bd9Sstevel@tonic-gate  *                   operations.
92*7c478bd9Sstevel@tonic-gate  *
93*7c478bd9Sstevel@tonic-gate  * The constraints on the platform:
94*7c478bd9Sstevel@tonic-gate  *
95*7c478bd9Sstevel@tonic-gate  *  - CLOCK_LEVEL must be less than or equal to LOCK_LEVEL
96*7c478bd9Sstevel@tonic-gate  *  - LOCK_LEVEL must be less than DISP_LEVEL
97*7c478bd9Sstevel@tonic-gate  *  - DISP_LEVEL should be as close to LOCK_LEVEL as possible
98*7c478bd9Sstevel@tonic-gate  *
99*7c478bd9Sstevel@tonic-gate  * Note that LOCK_LEVEL and CLOCK_LEVEL have historically always been equal;
100*7c478bd9Sstevel@tonic-gate  * changing this relationship is probably possible but not advised.
101*7c478bd9Sstevel@tonic-gate  *
102*7c478bd9Sstevel@tonic-gate  */
103*7c478bd9Sstevel@tonic-gate #define	CLOCK_LEVEL	10
104*7c478bd9Sstevel@tonic-gate #define	LOCK_LEVEL	10
105*7c478bd9Sstevel@tonic-gate #define	DISP_LEVEL	(LOCK_LEVEL + 1)
106*7c478bd9Sstevel@tonic-gate 
107*7c478bd9Sstevel@tonic-gate #define	HIGH_LEVELS	(PIL_MAX - LOCK_LEVEL)
108*7c478bd9Sstevel@tonic-gate 
109*7c478bd9Sstevel@tonic-gate #define	PIL_MAX		15
110*7c478bd9Sstevel@tonic-gate 
111*7c478bd9Sstevel@tonic-gate /*
112*7c478bd9Sstevel@tonic-gate  * The mutex and semaphore code depends on being able to represent a lock
113*7c478bd9Sstevel@tonic-gate  * plus owner in a single 32-bit word.  Thus the owner must contain at most
114*7c478bd9Sstevel@tonic-gate  * 24 significant bits.  At present only threads, mutexes and semaphores
115*7c478bd9Sstevel@tonic-gate  * must be aware of this vile constraint.  Different ISAs may handle this
116*7c478bd9Sstevel@tonic-gate  * differently depending on their capabilities (e.g. compare-and-swap)
117*7c478bd9Sstevel@tonic-gate  * and limitations (e.g. constraints on alignment and/or KERNELBASE).
118*7c478bd9Sstevel@tonic-gate  */
119*7c478bd9Sstevel@tonic-gate #define	PTR24_LSB	5			/* lower bits all zero */
120*7c478bd9Sstevel@tonic-gate #define	PTR24_MSB	(PTR24_LSB + 24)	/* upper bits all one */
121*7c478bd9Sstevel@tonic-gate #define	PTR24_ALIGN	32		/* minimum alignment (1 << lsb) */
122*7c478bd9Sstevel@tonic-gate #define	PTR24_BASE	0xe0000000	/* minimum ptr value (-1 >> (32-msb)) */
123*7c478bd9Sstevel@tonic-gate 
124*7c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
125*7c478bd9Sstevel@tonic-gate }
126*7c478bd9Sstevel@tonic-gate #endif
127*7c478bd9Sstevel@tonic-gate 
128*7c478bd9Sstevel@tonic-gate #endif	/* _SYS_MACHLOCK_H */
129