1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24 * Use is subject to license terms.
25 */
26
27/*	Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T	*/
28/*	  All Rights Reserved	*/
29
30#include <sys/types.h>
31#include <sys/t_lock.h>
32#include <sys/param.h>
33#include <sys/cred.h>
34#include <sys/debug.h>
35#include <sys/inline.h>
36#include <sys/kmem.h>
37#include <sys/proc.h>
38#include <sys/sysmacros.h>
39#include <sys/systm.h>
40#include <sys/vmsystm.h>
41#include <sys/vfs.h>
42#include <sys/vnode.h>
43#include <sys/pcb.h>
44#include <sys/buf.h>
45#include <sys/signal.h>
46#include <sys/user.h>
47#include <sys/cpuvar.h>
48#include <sys/copyops.h>
49#include <sys/watchpoint.h>
50
51#include <sys/fault.h>
52#include <sys/syscall.h>
53#include <sys/procfs.h>
54#include <sys/archsystm.h>
55#include <sys/cmn_err.h>
56#include <sys/stack.h>
57#include <sys/machpcb.h>
58#include <sys/simulate.h>
59#include <sys/fpu/fpusystm.h>
60
61#include <sys/pte.h>
62#include <sys/vmem.h>
63#include <sys/mman.h>
64#include <sys/vmparam.h>
65#include <vm/hat.h>
66#include <vm/as.h>
67#include <vm/seg.h>
68#include <vm/seg_kmem.h>
69#include <vm/seg_kp.h>
70#include <vm/page.h>
71
72#include <fs/proc/prdata.h>
73#include <v9/sys/psr_compat.h>
74
75int	prnwatch = 10000;	/* maximum number of watched areas */
76
77/*
78 * Force a thread into the kernel if it is not already there.
79 * This is a no-op on uniprocessors.
80 */
81/* ARGSUSED */
82void
83prpokethread(kthread_t *t)
84{
85	if (t->t_state == TS_ONPROC && t->t_cpu != CPU)
86		poke_cpu(t->t_cpu->cpu_id);
87}
88
89/*
90 * Return general registers.
91 */
92void
93prgetprregs(klwp_t *lwp, prgregset_t prp)
94{
95	gregset_t gr;
96
97	ASSERT(MUTEX_NOT_HELD(&lwptoproc(lwp)->p_lock));
98
99	getgregs(lwp, gr);
100	bzero(prp, NPRGREG * sizeof (*prp));
101
102	/*
103	 * Can't copy since prgregset_t and gregset_t
104	 * use different defines.
105	 */
106	prp[R_G1] = gr[REG_G1];
107	prp[R_G2] = gr[REG_G2];
108	prp[R_G3] = gr[REG_G3];
109	prp[R_G4] = gr[REG_G4];
110	prp[R_G5] = gr[REG_G5];
111	prp[R_G6] = gr[REG_G6];
112	prp[R_G7] = gr[REG_G7];
113
114	prp[R_O0] = gr[REG_O0];
115	prp[R_O1] = gr[REG_O1];
116	prp[R_O2] = gr[REG_O2];
117	prp[R_O3] = gr[REG_O3];
118	prp[R_O4] = gr[REG_O4];
119	prp[R_O5] = gr[REG_O5];
120	prp[R_O6] = gr[REG_O6];
121	prp[R_O7] = gr[REG_O7];
122
123	if (lwp->lwp_pcb.pcb_xregstat != XREGNONE) {
124		prp[R_L0] = lwp->lwp_pcb.pcb_xregs.rw_local[0];
125		prp[R_L1] = lwp->lwp_pcb.pcb_xregs.rw_local[1];
126		prp[R_L2] = lwp->lwp_pcb.pcb_xregs.rw_local[2];
127		prp[R_L3] = lwp->lwp_pcb.pcb_xregs.rw_local[3];
128		prp[R_L4] = lwp->lwp_pcb.pcb_xregs.rw_local[4];
129		prp[R_L5] = lwp->lwp_pcb.pcb_xregs.rw_local[5];
130		prp[R_L6] = lwp->lwp_pcb.pcb_xregs.rw_local[6];
131		prp[R_L7] = lwp->lwp_pcb.pcb_xregs.rw_local[7];
132
133		prp[R_I0] = lwp->lwp_pcb.pcb_xregs.rw_in[0];
134		prp[R_I1] = lwp->lwp_pcb.pcb_xregs.rw_in[1];
135		prp[R_I2] = lwp->lwp_pcb.pcb_xregs.rw_in[2];
136		prp[R_I3] = lwp->lwp_pcb.pcb_xregs.rw_in[3];
137		prp[R_I4] = lwp->lwp_pcb.pcb_xregs.rw_in[4];
138		prp[R_I5] = lwp->lwp_pcb.pcb_xregs.rw_in[5];
139		prp[R_I6] = lwp->lwp_pcb.pcb_xregs.rw_in[6];
140		prp[R_I7] = lwp->lwp_pcb.pcb_xregs.rw_in[7];
141	}
142
143	prp[R_CCR] = gr[REG_CCR];
144	prp[R_ASI] = gr[REG_ASI];
145	prp[R_FPRS] = gr[REG_FPRS];
146	prp[R_PC]  = gr[REG_PC];
147	prp[R_nPC] = gr[REG_nPC];
148	prp[R_Y]   = gr[REG_Y];
149}
150
151/*
152 * Set general registers.
153 */
154void
155prsetprregs(klwp_t *lwp, prgregset_t prp, int initial)
156{
157	gregset_t gr;
158
159	gr[REG_G1] = prp[R_G1];
160	gr[REG_G2] = prp[R_G2];
161	gr[REG_G3] = prp[R_G3];
162	gr[REG_G4] = prp[R_G4];
163	gr[REG_G5] = prp[R_G5];
164	gr[REG_G6] = prp[R_G6];
165	gr[REG_G7] = prp[R_G7];
166
167	gr[REG_O0] = prp[R_O0];
168	gr[REG_O1] = prp[R_O1];
169	gr[REG_O2] = prp[R_O2];
170	gr[REG_O3] = prp[R_O3];
171	gr[REG_O4] = prp[R_O4];
172	gr[REG_O5] = prp[R_O5];
173	gr[REG_O6] = prp[R_O6];
174	gr[REG_O7] = prp[R_O7];
175
176	lwp->lwp_pcb.pcb_xregs.rw_local[0] = prp[R_L0];
177	lwp->lwp_pcb.pcb_xregs.rw_local[1] = prp[R_L1];
178	lwp->lwp_pcb.pcb_xregs.rw_local[2] = prp[R_L2];
179	lwp->lwp_pcb.pcb_xregs.rw_local[3] = prp[R_L3];
180	lwp->lwp_pcb.pcb_xregs.rw_local[4] = prp[R_L4];
181	lwp->lwp_pcb.pcb_xregs.rw_local[5] = prp[R_L5];
182	lwp->lwp_pcb.pcb_xregs.rw_local[6] = prp[R_L6];
183	lwp->lwp_pcb.pcb_xregs.rw_local[7] = prp[R_L7];
184
185	lwp->lwp_pcb.pcb_xregs.rw_in[0] = prp[R_I0];
186	lwp->lwp_pcb.pcb_xregs.rw_in[1] = prp[R_I1];
187	lwp->lwp_pcb.pcb_xregs.rw_in[2] = prp[R_I2];
188	lwp->lwp_pcb.pcb_xregs.rw_in[3] = prp[R_I3];
189	lwp->lwp_pcb.pcb_xregs.rw_in[4] = prp[R_I4];
190	lwp->lwp_pcb.pcb_xregs.rw_in[5] = prp[R_I5];
191	lwp->lwp_pcb.pcb_xregs.rw_in[6] = prp[R_I6];
192	lwp->lwp_pcb.pcb_xregs.rw_in[7] = prp[R_I7];
193
194	lwp->lwp_pcb.pcb_xregstat = XREGMODIFIED;
195	lwptot(lwp)->t_post_sys = 1;
196
197	/*
198	 * setgregs will only allow the condition codes to be set.
199	 */
200	gr[REG_CCR] = prp[R_CCR];
201	gr[REG_ASI] = prp[R_ASI];
202	gr[REG_FPRS] = prp[R_FPRS];
203	gr[REG_PC]  = prp[R_PC];
204	gr[REG_nPC] = prp[R_nPC];
205	gr[REG_Y]   = prp[R_Y];
206
207	if (initial) {		/* set initial values */
208		if (lwptoproc(lwp)->p_model == DATAMODEL_LP64)
209			lwptoregs(lwp)->r_tstate = TSTATE_USER64|TSTATE_MM_TSO;
210		else
211			lwptoregs(lwp)->r_tstate = TSTATE_USER32|TSTATE_MM_TSO;
212		if (!fpu_exists)
213			lwptoregs(lwp)->r_tstate &= ~TSTATE_PEF;
214	}
215
216	setgregs(lwp, gr);
217}
218
219#ifdef _SYSCALL32_IMPL
220
221/*
222 * modify the lower 32bits of a uint64_t
223 */
224#define	SET_LOWER_32(all, lower)	\
225	(((uint64_t)(all) & 0xffffffff00000000) | (uint32_t)(lower))
226
227/*
228 * Convert prgregset32 to native prgregset.
229 */
230void
231prgregset_32ton(klwp_t *lwp, prgregset32_t src, prgregset_t dest)
232{
233	struct regs *r = lwptoregs(lwp);
234
235	dest[R_G0] = SET_LOWER_32(0, src[R_G0]);
236	dest[R_G1] = SET_LOWER_32(r->r_g1, src[R_G1]);
237	dest[R_G2] = SET_LOWER_32(r->r_g2, src[R_G2]);
238	dest[R_G3] = SET_LOWER_32(r->r_g3, src[R_G3]);
239	dest[R_G4] = SET_LOWER_32(r->r_g4, src[R_G4]);
240	dest[R_G5] = SET_LOWER_32(r->r_g5, src[R_G5]);
241	dest[R_G6] = SET_LOWER_32(r->r_g6, src[R_G6]);
242	dest[R_G7] = SET_LOWER_32(r->r_g7, src[R_G7]);
243
244	dest[R_O0] = SET_LOWER_32(r->r_o0, src[R_O0]);
245	dest[R_O1] = SET_LOWER_32(r->r_o1, src[R_O1]);
246	dest[R_O2] = SET_LOWER_32(r->r_o2, src[R_O2]);
247	dest[R_O3] = SET_LOWER_32(r->r_o3, src[R_O3]);
248	dest[R_O4] = SET_LOWER_32(r->r_o4, src[R_O4]);
249	dest[R_O5] = SET_LOWER_32(r->r_o5, src[R_O5]);
250	dest[R_O6] = SET_LOWER_32(r->r_o6, src[R_O6]);
251	dest[R_O7] = SET_LOWER_32(r->r_o7, src[R_O7]);
252
253	if (lwp->lwp_pcb.pcb_xregstat != XREGNONE) {
254		struct rwindow *rw = &lwp->lwp_pcb.pcb_xregs;
255
256		dest[R_L0] = SET_LOWER_32(rw->rw_local[0], src[R_L0]);
257		dest[R_L1] = SET_LOWER_32(rw->rw_local[1], src[R_L1]);
258		dest[R_L2] = SET_LOWER_32(rw->rw_local[2], src[R_L2]);
259		dest[R_L3] = SET_LOWER_32(rw->rw_local[3], src[R_L3]);
260		dest[R_L4] = SET_LOWER_32(rw->rw_local[4], src[R_L4]);
261		dest[R_L5] = SET_LOWER_32(rw->rw_local[5], src[R_L5]);
262		dest[R_L6] = SET_LOWER_32(rw->rw_local[6], src[R_L6]);
263		dest[R_L7] = SET_LOWER_32(rw->rw_local[7], src[R_L7]);
264
265		dest[R_I0] = SET_LOWER_32(rw->rw_in[0], src[R_I0]);
266		dest[R_I1] = SET_LOWER_32(rw->rw_in[1], src[R_I1]);
267		dest[R_I2] = SET_LOWER_32(rw->rw_in[2], src[R_I2]);
268		dest[R_I3] = SET_LOWER_32(rw->rw_in[3], src[R_I3]);
269		dest[R_I4] = SET_LOWER_32(rw->rw_in[4], src[R_I4]);
270		dest[R_I5] = SET_LOWER_32(rw->rw_in[5], src[R_I5]);
271		dest[R_I6] = SET_LOWER_32(rw->rw_in[6], src[R_I6]);
272		dest[R_I7] = SET_LOWER_32(rw->rw_in[7], src[R_I7]);
273	} else {
274		dest[R_L0] = (uint32_t)src[R_L0];
275		dest[R_L1] = (uint32_t)src[R_L1];
276		dest[R_L2] = (uint32_t)src[R_L2];
277		dest[R_L3] = (uint32_t)src[R_L3];
278		dest[R_L4] = (uint32_t)src[R_L4];
279		dest[R_L5] = (uint32_t)src[R_L5];
280		dest[R_L6] = (uint32_t)src[R_L6];
281		dest[R_L7] = (uint32_t)src[R_L7];
282
283		dest[R_I0] = (uint32_t)src[R_I0];
284		dest[R_I1] = (uint32_t)src[R_I1];
285		dest[R_I2] = (uint32_t)src[R_I2];
286		dest[R_I3] = (uint32_t)src[R_I3];
287		dest[R_I4] = (uint32_t)src[R_I4];
288		dest[R_I5] = (uint32_t)src[R_I5];
289		dest[R_I6] = (uint32_t)src[R_I6];
290		dest[R_I7] = (uint32_t)src[R_I7];
291	}
292
293	dest[R_CCR] = ((r->r_tstate >> TSTATE_CCR_SHIFT) & CCR_XCC) |
294	    ((src[R_PSR] >> (TSTATE_CCR_SHIFT-PSR_TSTATE_CC_SHIFT)) & CCR_ICC);
295
296	dest[R_PC] = SET_LOWER_32(r->r_pc, src[R_PC]);
297	dest[R_nPC] = SET_LOWER_32(r->r_npc, src[R_nPC]);
298	dest[R_Y] = (uint32_t)src[R_Y];
299
300	dest[R_ASI] = (r->r_tstate >> TSTATE_ASI_SHIFT) & TSTATE_ASI_MASK;
301	dest[R_FPRS] = lwptofpu(lwp)->fpu_fprs;
302}
303
304/*
305 * Return 32-bit general registers.
306 */
307
308/* conversion from 64-bit register to 32-bit register */
309#define	R32(r)	(prgreg32_t)(uint32_t)(r)
310
311void
312prgetprregs32(klwp_t *lwp, prgregset32_t prp)
313{
314	gregset32_t gr;
315
316	extern void getgregs32(klwp_t *, gregset32_t);
317
318	ASSERT(MUTEX_NOT_HELD(&lwptoproc(lwp)->p_lock));
319
320	getgregs32(lwp, gr);
321	bzero(prp, NPRGREG * sizeof (*prp));
322
323	/*
324	 * Can't copy since prgregset_t and gregset_t
325	 * use different defines.
326	 */
327	prp[R_G1] = gr[REG_G1];
328	prp[R_G2] = gr[REG_G2];
329	prp[R_G3] = gr[REG_G3];
330	prp[R_G4] = gr[REG_G4];
331	prp[R_G5] = gr[REG_G5];
332	prp[R_G6] = gr[REG_G6];
333	prp[R_G7] = gr[REG_G7];
334
335	prp[R_O0] = gr[REG_O0];
336	prp[R_O1] = gr[REG_O1];
337	prp[R_O2] = gr[REG_O2];
338	prp[R_O3] = gr[REG_O3];
339	prp[R_O4] = gr[REG_O4];
340	prp[R_O5] = gr[REG_O5];
341	prp[R_O6] = gr[REG_O6];
342	prp[R_O7] = gr[REG_O7];
343
344	if (lwp->lwp_pcb.pcb_xregstat != XREGNONE) {
345		prp[R_L0] = R32(lwp->lwp_pcb.pcb_xregs.rw_local[0]);
346		prp[R_L1] = R32(lwp->lwp_pcb.pcb_xregs.rw_local[1]);
347		prp[R_L2] = R32(lwp->lwp_pcb.pcb_xregs.rw_local[2]);
348		prp[R_L3] = R32(lwp->lwp_pcb.pcb_xregs.rw_local[3]);
349		prp[R_L4] = R32(lwp->lwp_pcb.pcb_xregs.rw_local[4]);
350		prp[R_L5] = R32(lwp->lwp_pcb.pcb_xregs.rw_local[5]);
351		prp[R_L6] = R32(lwp->lwp_pcb.pcb_xregs.rw_local[6]);
352		prp[R_L7] = R32(lwp->lwp_pcb.pcb_xregs.rw_local[7]);
353
354		prp[R_I0] = R32(lwp->lwp_pcb.pcb_xregs.rw_in[0]);
355		prp[R_I1] = R32(lwp->lwp_pcb.pcb_xregs.rw_in[1]);
356		prp[R_I2] = R32(lwp->lwp_pcb.pcb_xregs.rw_in[2]);
357		prp[R_I3] = R32(lwp->lwp_pcb.pcb_xregs.rw_in[3]);
358		prp[R_I4] = R32(lwp->lwp_pcb.pcb_xregs.rw_in[4]);
359		prp[R_I5] = R32(lwp->lwp_pcb.pcb_xregs.rw_in[5]);
360		prp[R_I6] = R32(lwp->lwp_pcb.pcb_xregs.rw_in[6]);
361		prp[R_I7] = R32(lwp->lwp_pcb.pcb_xregs.rw_in[7]);
362	}
363
364	prp[R_PSR] = gr[REG_PSR];
365	prp[R_PC]  = gr[REG_PC];
366	prp[R_nPC] = gr[REG_nPC];
367	prp[R_Y]   = gr[REG_Y];
368}
369
370#endif	/* _SYSCALL32_IMPL */
371
372/*
373 * Get the syscall return values for the lwp.
374 */
375int
376prgetrvals(klwp_t *lwp, long *rval1, long *rval2)
377{
378	struct regs *r = lwptoregs(lwp);
379
380	if (r->r_tstate & TSTATE_IC)
381		return ((int)r->r_o0);
382	if (lwp->lwp_eosys == JUSTRETURN) {
383		*rval1 = 0;
384		*rval2 = 0;
385	} else if (lwptoproc(lwp)->p_model == DATAMODEL_ILP32) {
386		*rval1 = r->r_o0 & (uint32_t)0xffffffffU;
387		*rval2 = r->r_o1 & (uint32_t)0xffffffffU;
388	} else {
389		*rval1 = r->r_o0;
390		*rval2 = r->r_o1;
391	}
392	return (0);
393}
394
395/*
396 * Does the system support floating-point, either through hardware
397 * or by trapping and emulating floating-point machine instructions?
398 */
399int
400prhasfp(void)
401{
402	/*
403	 * SunOS5.0 emulates floating-point if FP hardware is not present.
404	 */
405	return (1);
406}
407
408/*
409 * Get floating-point registers.
410 */
411void
412prgetprfpregs(klwp_t *lwp, prfpregset_t *pfp)
413{
414	bzero(pfp, sizeof (*pfp));
415	/*
416	 * This works only because prfpregset_t is intentionally
417	 * constructed to be identical to fpregset_t, with additional
418	 * space for the floating-point queue at the end.
419	 */
420	getfpregs(lwp, (fpregset_t *)pfp);
421	/*
422	 * This is supposed to be a pointer to the floating point queue.
423	 * We can't provide such a thing through the /proc interface.
424	 */
425	pfp->pr_filler = 0;
426	/*
427	 * XXX: to be done: fetch the FP queue if it is non-empty.
428	 */
429}
430
431#ifdef	_SYSCALL32_IMPL
432void
433prgetprfpregs32(klwp_t *lwp, prfpregset32_t *pfp)
434{
435	bzero(pfp, sizeof (*pfp));
436	/*
437	 * This works only because prfpregset32_t is intentionally
438	 * constructed to be identical to fpregset32_t, with additional
439	 * space for the floating-point queue at the end.
440	 */
441	getfpregs32(lwp, (fpregset32_t *)pfp);
442	/*
443	 * This is supposed to be a pointer to the floating point queue.
444	 * We can't provide such a thing through the /proc interface.
445	 */
446	pfp->pr_filler = 0;
447	/*
448	 * XXX: to be done: fetch the FP queue if it is non-empty.
449	 */
450}
451#endif	/* _SYSCALL32_IMPL */
452
453/*
454 * Set floating-point registers.
455 */
456void
457prsetprfpregs(klwp_t *lwp, prfpregset_t *pfp)
458{
459	/*
460	 * XXX: to be done: store the FP queue if it is non-empty.
461	 */
462	pfp->pr_qcnt = 0;
463	/*
464	 * We set fpu_en before calling setfpregs() in order to
465	 * retain the semantics of this operation from older
466	 * versions of the system.  SunOS 5.4 and prior never
467	 * queried fpu_en; they just set the registers.  The
468	 * proper operation if fpu_en is zero is to disable
469	 * floating point in the target process, but this can
470	 * only change after a proper end-of-life period for
471	 * the old semantics.
472	 */
473	pfp->pr_en = 1;
474	/*
475	 * This works only because prfpregset_t is intentionally
476	 * constructed to be identical to fpregset_t, with additional
477	 * space for the floating-point queue at the end.
478	 */
479	setfpregs(lwp, (fpregset_t *)pfp);
480}
481
482#ifdef	_SYSCALL32_IMPL
483void
484prsetprfpregs32(klwp_t *lwp, prfpregset32_t *pfp)
485{
486	/*
487	 * XXX: to be done: store the FP queue if it is non-empty.
488	 */
489	pfp->pr_qcnt = 0;
490	/*
491	 * We set fpu_en before calling setfpregs() in order to
492	 * retain the semantics of this operation from older
493	 * versions of the system.  SunOS 5.4 and prior never
494	 * queried fpu_en; they just set the registers.  The
495	 * proper operation if fpu_en is zero is to disable
496	 * floating point in the target process, but this can
497	 * only change after a proper end-of-life period for
498	 * the old semantics.
499	 */
500	pfp->pr_en = 1;
501	/*
502	 * This works only because prfpregset32_t is intentionally
503	 * constructed to be identical to fpregset32_t, with additional
504	 * space for the floating-point queue at the end.
505	 */
506	setfpregs32(lwp, (fpregset32_t *)pfp);
507}
508#endif	/* _SYSCALL32_IMPL */
509
510/*
511 * Does the system support extra register state?
512 * In a kernel that supports both an _LP64 and an _ILP32 data model,
513 * the answer depends on the data model of the process.
514 * An _LP64 process does not have extra registers.
515 */
516int
517prhasx(proc_t *p)
518{
519	extern int xregs_exists;
520
521	if (p->p_model == DATAMODEL_LP64)
522		return (0);
523	else
524		return (xregs_exists);
525}
526
527/*
528 * Get the size of the extra registers.
529 */
530int
531prgetprxregsize(proc_t *p)
532{
533	return (xregs_getsize(p));
534}
535
536/*
537 * Get extra registers.
538 */
539void
540prgetprxregs(klwp_t *lwp, caddr_t prx)
541{
542	extern void xregs_get(struct _klwp *, caddr_t);
543
544	(void) xregs_get(lwp, prx);
545}
546
547/*
548 * Set extra registers.
549 */
550void
551prsetprxregs(klwp_t *lwp, caddr_t prx)
552{
553	extern void xregs_set(struct _klwp *, caddr_t);
554
555	(void) xregs_set(lwp, prx);
556}
557
558/*
559 * Get the ancillary state registers.
560 */
561void
562prgetasregs(klwp_t *lwp, asrset_t asrset)
563{
564	bzero(asrset, sizeof (asrset_t));
565	getasrs(lwp, asrset);
566	getfpasrs(lwp, asrset);
567}
568
569/*
570 * Set the ancillary state registers.
571 */
572void
573prsetasregs(klwp_t *lwp, asrset_t asrset)
574{
575	setasrs(lwp, asrset);
576	setfpasrs(lwp, asrset);
577}
578
579/*
580 * Return the base (lower limit) of the process stack.
581 */
582caddr_t
583prgetstackbase(proc_t *p)
584{
585	return (p->p_usrstack - p->p_stksize);
586}
587
588/*
589 * Return the "addr" field for pr_addr in prpsinfo_t.
590 * This is a vestige of the past, so whatever we return is OK.
591 */
592caddr_t
593prgetpsaddr(proc_t *p)
594{
595	return ((caddr_t)p);
596}
597
598/*
599 * Arrange to single-step the lwp.
600 */
601void
602prstep(klwp_t *lwp, int watchstep)
603{
604	ASSERT(MUTEX_NOT_HELD(&lwptoproc(lwp)->p_lock));
605
606	lwp->lwp_pcb.pcb_step = STEP_REQUESTED;
607	lwp->lwp_pcb.pcb_tracepc = NULL;
608	if (watchstep)
609		lwp->lwp_pcb.pcb_flags |= WATCH_STEP;
610	else
611		lwp->lwp_pcb.pcb_flags |= NORMAL_STEP;
612}
613
614/*
615 * Undo prstep().
616 */
617void
618prnostep(klwp_t *lwp)
619{
620	ASSERT(ttolwp(curthread) == lwp ||
621	    MUTEX_NOT_HELD(&lwptoproc(lwp)->p_lock));
622
623	lwp->lwp_pcb.pcb_step = STEP_NONE;
624	lwp->lwp_pcb.pcb_tracepc = NULL;
625	lwp->lwp_pcb.pcb_flags &= ~(NORMAL_STEP|WATCH_STEP);
626}
627
628/*
629 * Return non-zero if a single-step is in effect.
630 */
631int
632prisstep(klwp_t *lwp)
633{
634	ASSERT(MUTEX_NOT_HELD(&lwptoproc(lwp)->p_lock));
635
636	return (lwp->lwp_pcb.pcb_step != STEP_NONE);
637}
638
639/*
640 * Set the PC to the specified virtual address.
641 */
642void
643prsvaddr(klwp_t *lwp, caddr_t vaddr)
644{
645	struct regs *r = lwptoregs(lwp);
646
647	ASSERT(MUTEX_NOT_HELD(&lwptoproc(lwp)->p_lock));
648
649	/*
650	 * pc and npc must be word aligned on sparc.
651	 * We silently make it so to avoid a watchdog reset.
652	 */
653	r->r_pc = (uintptr_t)vaddr & ~03L;
654	r->r_npc = r->r_pc + 4;
655}
656
657/*
658 * Map address "addr" in address space "as" into a kernel virtual address.
659 * The memory is guaranteed to be resident and locked down.
660 */
661caddr_t
662prmapin(struct as *as, caddr_t addr, int writing)
663{
664	page_t *pp;
665	caddr_t kaddr;
666	pfn_t pfnum;
667
668	/*
669	 * XXX - Because of past mistakes, we have bits being returned
670	 * by getpfnum that are actually the page type bits of the pte.
671	 * When the object we are trying to map is a memory page with
672	 * a page structure everything is ok and we can use the optimal
673	 * method, ppmapin.  Otherwise, we have to do something special.
674	 */
675	pfnum = hat_getpfnum(as->a_hat, addr);
676	if (pf_is_memory(pfnum)) {
677		pp = page_numtopp_nolock(pfnum);
678		if (pp != NULL) {
679			ASSERT(PAGE_LOCKED(pp));
680			kaddr = ppmapin(pp, writing ?
681			    (PROT_READ | PROT_WRITE) : PROT_READ,
682			    (caddr_t)-1);
683			return (kaddr + ((uintptr_t)addr & PAGEOFFSET));
684		}
685	}
686
687	/*
688	 * Oh well, we didn't have a page struct for the object we were
689	 * trying to map in; ppmapin doesn't handle devices, but allocating a
690	 * heap address allows ppmapout to free virutal space when done.
691	 */
692	kaddr = vmem_alloc(heap_arena, PAGESIZE, VM_SLEEP);
693
694	hat_devload(kas.a_hat, kaddr, PAGESIZE, pfnum,
695	    writing ? (PROT_READ | PROT_WRITE) : PROT_READ, HAT_LOAD_LOCK);
696
697	return (kaddr + ((uintptr_t)addr & PAGEOFFSET));
698}
699
700/*
701 * Unmap address "addr" in address space "as"; inverse of prmapin().
702 */
703/* ARGSUSED */
704void
705prmapout(struct as *as, caddr_t addr, caddr_t vaddr, int writing)
706{
707	extern void ppmapout(caddr_t);
708
709	vaddr = (caddr_t)((uintptr_t)vaddr & PAGEMASK);
710	ppmapout(vaddr);
711}
712
713
714#define	BAMASK22 0xffc00000	/* for masking out disp22 from ba,a */
715#define	BAA	0x30800000	/* ba,a without disp22 */
716#define	FBAA	0x31800000	/* fba,a without disp22 */
717#define	CBAA	0x31c00000	/* cba,a without disp22 */
718
719#define	BAMASK19 0xfff80000	/* for masking out disp19 from ba,a %[ix]cc */
720#define	BAA_icc	0x30480000	/* ba,a %icc without disp19 */
721#define	BAA_xcc	0x30680000	/* ba,a %xcc without disp19 */
722
723
724/*
725 * Prepare to single-step the lwp if requested.
726 * This is called by the lwp itself just before returning to user level.
727 */
728void
729prdostep(void)
730{
731	klwp_t *lwp = ttolwp(curthread);
732	struct regs *r = lwptoregs(lwp);
733	proc_t *p = lwptoproc(lwp);
734	struct as *as = p->p_as;
735	caddr_t pc;
736	caddr_t npc;
737
738	ASSERT(lwp != NULL);
739	ASSERT(r != NULL);
740
741	if (lwp->lwp_pcb.pcb_step == STEP_NONE ||
742	    lwp->lwp_pcb.pcb_step == STEP_ACTIVE)
743		return;
744
745	if (p->p_model == DATAMODEL_ILP32) {
746		pc = (caddr_t)(uintptr_t)(caddr32_t)r->r_pc;
747		npc = (caddr_t)(uintptr_t)(caddr32_t)r->r_npc;
748	} else {
749		pc = (caddr_t)r->r_pc;
750		npc = (caddr_t)r->r_npc;
751	}
752
753	if (lwp->lwp_pcb.pcb_step == STEP_WASACTIVE) {
754		if (npc == (caddr_t)lwp->lwp_pcb.pcb_tracepc)
755			r->r_npc = (greg_t)as->a_userlimit;
756		else {
757			lwp->lwp_pcb.pcb_tracepc = (void *)pc;
758			r->r_pc = (greg_t)as->a_userlimit;
759		}
760	} else {
761		/*
762		 * Single-stepping on sparc is effected by setting nPC
763		 * to an invalid address and expecting FLTBOUNDS to
764		 * occur after the instruction at PC is executed.
765		 * This is not the whole story, however; we must
766		 * deal with branch-always instructions with the
767		 * annul bit set as a special case here.
768		 *
769		 * fuword() returns -1 on error and we can't distinguish
770		 * this from a legitimate instruction of all 1's.
771		 * However 0xffffffff is not one of the branch-always
772		 * instructions we are interested in.  No problem.
773		 */
774		int32_t instr;
775		int32_t i;
776
777		if (fuword32_nowatch((void *)pc, (uint32_t *)&instr) != 0)
778			instr = -1;
779		if ((i = instr & BAMASK22) == BAA || i == FBAA || i == CBAA) {
780			/*
781			 * For ba,a and relatives, compute the
782			 * new PC from the instruction.
783			 */
784			i = (instr << 10) >> 8;
785			lwp->lwp_pcb.pcb_tracepc = (void *)(pc + i);
786			r->r_pc = (greg_t)as->a_userlimit;
787			r->r_npc = r->r_pc + 4;
788		} else if ((i = instr & BAMASK19) == BAA_icc || i == BAA_xcc) {
789			/*
790			 * For ba,a %icc and ba,a %xcc, compute the
791			 * new PC from the instruction.
792			 */
793			i = (instr << 13) >> 11;
794			lwp->lwp_pcb.pcb_tracepc = (void *)(pc + i);
795			r->r_pc = (greg_t)as->a_userlimit;
796			r->r_npc = r->r_pc + 4;
797		} else {
798			lwp->lwp_pcb.pcb_tracepc = (void *)npc;
799			r->r_npc = (greg_t)as->a_userlimit;
800		}
801	}
802
803	lwp->lwp_pcb.pcb_step = STEP_ACTIVE;
804}
805
806/*
807 * Wrap up single stepping of the lwp.
808 * This is called by the lwp itself just after it has taken
809 * the FLTBOUNDS trap.  We fix up the PC and nPC to have their
810 * proper values after the step.  We return 1 to indicate that
811 * this fault really is the one we are expecting, else 0.
812 *
813 * This is also called from syscall() and stop() to reset PC
814 * and nPC to their proper values for debugger visibility.
815 */
816int
817prundostep(void)
818{
819	klwp_t *lwp = ttolwp(curthread);
820	proc_t *p = ttoproc(curthread);
821	struct as *as = p->p_as;
822	int rc = 0;
823	caddr_t pc;
824	caddr_t npc;
825
826	ASSERT(lwp != NULL);
827
828	if (lwp->lwp_pcb.pcb_step == STEP_ACTIVE) {
829		struct regs *r = lwptoregs(lwp);
830
831		ASSERT(r != NULL);
832
833		if (p->p_model == DATAMODEL_ILP32) {
834			pc = (caddr_t)(uintptr_t)(caddr32_t)r->r_pc;
835			npc = (caddr_t)(uintptr_t)(caddr32_t)r->r_npc;
836		} else {
837			pc = (caddr_t)r->r_pc;
838			npc = (caddr_t)r->r_npc;
839		}
840
841		if (pc == (caddr_t)as->a_userlimit ||
842		    pc == (caddr_t)as->a_userlimit + 4) {
843			if (pc == (caddr_t)as->a_userlimit) {
844				r->r_pc = (greg_t)lwp->lwp_pcb.pcb_tracepc;
845				if (npc == (caddr_t)as->a_userlimit + 4)
846					r->r_npc = r->r_pc + 4;
847			} else {
848				r->r_pc = (greg_t)lwp->lwp_pcb.pcb_tracepc + 4;
849				r->r_npc = r->r_pc + 4;
850			}
851			rc = 1;
852		} else {
853			r->r_npc = (greg_t)lwp->lwp_pcb.pcb_tracepc;
854		}
855		lwp->lwp_pcb.pcb_step = STEP_WASACTIVE;
856	}
857
858	return (rc);
859}
860
861/*
862 * Make sure the lwp is in an orderly state
863 * for inspection by a debugger through /proc.
864 *
865 * This needs to be called only once while the current thread remains in the
866 * kernel and needs to be called while holding no resources (mutex locks, etc).
867 *
868 * As a hedge against these conditions, if prstop() is called repeatedly
869 * before prunstop() is called, it does nothing and just returns.
870 *
871 * prunstop() must be called before the thread returns to user level.
872 */
873/* ARGSUSED */
874void
875prstop(int why, int what)
876{
877	klwp_t *lwp = ttolwp(curthread);
878	proc_t *p = lwptoproc(lwp);
879	struct regs *r = lwptoregs(lwp);
880	kfpu_t *pfp = lwptofpu(lwp);
881	caddr_t sp;
882	caddr_t pc;
883	int watched;
884	extern void fp_prsave(kfpu_t *);
885
886	if (lwp->lwp_pcb.pcb_flags & PRSTOP_CALLED)
887		return;
888
889	/*
890	 * Make sure we don't deadlock on a recursive call
891	 * to prstop().  stop() tests the lwp_nostop flag.
892	 */
893	ASSERT(lwp->lwp_nostop == 0);
894	lwp->lwp_nostop = 1;
895	(void) flush_user_windows_to_stack(NULL);
896	if (lwp->lwp_pcb.pcb_step != STEP_NONE)
897		(void) prundostep();
898
899	if (lwp->lwp_pcb.pcb_xregstat == XREGNONE) {
900		/*
901		 * Attempt to fetch the last register window from the stack.
902		 * If that fails, look for it in the pcb.
903		 * If that fails, give up.
904		 */
905		struct machpcb *mpcb = lwptompcb(lwp);
906		struct rwindow32 rwindow32;
907		size_t rw_size;
908		caddr_t rwp;
909		int is64;
910
911		if (mpcb->mpcb_wstate == WSTATE_USER32) {
912			rw_size = sizeof (struct rwindow32);
913			sp = (caddr_t)(uintptr_t)(caddr32_t)r->r_sp;
914			rwp = sp;
915			is64 = 0;
916		} else {
917			rw_size = sizeof (struct rwindow);
918			sp = (caddr_t)r->r_sp;
919			rwp = sp + V9BIAS64;
920			is64 = 1;
921		}
922
923		watched = watch_disable_addr(rwp, rw_size, S_READ);
924		if (is64 &&
925		    copyin(rwp, &lwp->lwp_pcb.pcb_xregs, rw_size) == 0)
926			lwp->lwp_pcb.pcb_xregstat = XREGPRESENT;
927		else if (!is64 &&
928		    copyin(rwp, &rwindow32, rw_size) == 0) {
929			rwindow_32ton(&rwindow32, &lwp->lwp_pcb.pcb_xregs);
930			lwp->lwp_pcb.pcb_xregstat = XREGPRESENT;
931		} else {
932			int i;
933
934			for (i = 0; i < mpcb->mpcb_wbcnt; i++) {
935				if (sp == mpcb->mpcb_spbuf[i]) {
936					if (is64) {
937						bcopy(mpcb->mpcb_wbuf +
938						    (i * rw_size),
939						    &lwp->lwp_pcb.pcb_xregs,
940						    rw_size);
941					} else {
942						struct rwindow32 *rw32 =
943						    (struct rwindow32 *)
944						    (mpcb->mpcb_wbuf +
945						    (i * rw_size));
946						rwindow_32ton(rw32,
947						    &lwp->lwp_pcb.pcb_xregs);
948					}
949					lwp->lwp_pcb.pcb_xregstat = XREGPRESENT;
950					break;
951				}
952			}
953		}
954		if (watched)
955			watch_enable_addr(rwp, rw_size, S_READ);
956	}
957
958	/*
959	 * Make sure the floating point state is saved.
960	 */
961	fp_prsave(pfp);
962
963	if (p->p_model == DATAMODEL_ILP32)
964		pc = (caddr_t)(uintptr_t)(caddr32_t)r->r_pc;
965	else
966		pc = (caddr_t)r->r_pc;
967
968	if (copyin_nowatch(pc, &lwp->lwp_pcb.pcb_instr,
969	    sizeof (lwp->lwp_pcb.pcb_instr)) == 0)
970		lwp->lwp_pcb.pcb_flags |= INSTR_VALID;
971	else {
972		lwp->lwp_pcb.pcb_flags &= ~INSTR_VALID;
973		lwp->lwp_pcb.pcb_instr = 0;
974	}
975
976	(void) save_syscall_args();
977	ASSERT(lwp->lwp_nostop == 1);
978	lwp->lwp_nostop = 0;
979
980	lwp->lwp_pcb.pcb_flags |= PRSTOP_CALLED;
981	aston(curthread);	/* so prunstop() will be called */
982}
983
984/*
985 * Inform prstop() that it should do its work again
986 * the next time it is called.
987 */
988void
989prunstop(void)
990{
991	ttolwp(curthread)->lwp_pcb.pcb_flags &= ~PRSTOP_CALLED;
992}
993
994/*
995 * Fetch the user-level instruction on which the lwp is stopped.
996 * It was saved by the lwp itself, in prstop().
997 * Return non-zero if the instruction is valid.
998 */
999int
1000prfetchinstr(klwp_t *lwp, ulong_t *ip)
1001{
1002	*ip = (ulong_t)(instr_t)lwp->lwp_pcb.pcb_instr;
1003	return (lwp->lwp_pcb.pcb_flags & INSTR_VALID);
1004}
1005
1006int
1007prnwindows(klwp_t *lwp)
1008{
1009	struct machpcb *mpcb = lwptompcb(lwp);
1010
1011	return (mpcb->mpcb_wbcnt);
1012}
1013
1014void
1015prgetwindows(klwp_t *lwp, gwindows_t *gwp)
1016{
1017	getgwins(lwp, gwp);
1018}
1019
1020#ifdef	_SYSCALL32_IMPL
1021void
1022prgetwindows32(klwp_t *lwp, gwindows32_t *gwp)
1023{
1024	getgwins32(lwp, gwp);
1025}
1026#endif	/* _SYSCALL32_IMPL */
1027
1028/*
1029 * Called from trap() when a load or store instruction
1030 * falls in a watched page but is not a watchpoint.
1031 * We emulate the instruction in the kernel.
1032 */
1033int
1034pr_watch_emul(struct regs *rp, caddr_t addr, enum seg_rw rw)
1035{
1036	char *badaddr = (caddr_t)(-1);
1037	int res;
1038	int watched;
1039
1040	/* prevent recursive calls to pr_watch_emul() */
1041	ASSERT(!(curthread->t_flag & T_WATCHPT));
1042	curthread->t_flag |= T_WATCHPT;
1043
1044	watched = watch_disable_addr(addr, 16, rw);
1045	res = do_unaligned(rp, &badaddr);
1046	if (watched)
1047		watch_enable_addr(addr, 16, rw);
1048
1049	curthread->t_flag &= ~T_WATCHPT;
1050	if (res == SIMU_SUCCESS) {
1051		rp->r_pc = rp->r_npc;
1052		rp->r_npc += 4;
1053		return (1);
1054	}
1055	return (0);
1056}
1057