1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26/* Main procedures for sparc FPU simulator. */
27
28#include <sys/fpu/fpu_simulator.h>
29#include <sys/fpu/globals.h>
30#include <sys/fpu/fpusystm.h>
31#include <sys/proc.h>
32#include <sys/signal.h>
33#include <sys/siginfo.h>
34#include <sys/thread.h>
35#include <sys/cpuvar.h>
36#include <sys/cmn_err.h>
37#include <sys/atomic.h>
38#include <sys/regset.h>
39#include <sys/privregs.h>
40#include <sys/vis_simulator.h>
41
42#define	FPUINFO_KSTAT(opcode)	{					\
43	extern void __dtrace_probe___fpuinfo_##opcode(uint64_t *);	\
44	uint64_t *stataddr = &fpuinfo.opcode.value.ui64;		\
45	__dtrace_probe___fpuinfo_##opcode(stataddr);			\
46	atomic_inc_64(&fpuinfo.opcode.value.ui64);			\
47}
48
49#define	FPUINFO_KSTAT_PREC(prec, kstat_s, kstat_d, kstat_q)		\
50	if (prec < 2) {							\
51		FPUINFO_KSTAT(kstat_s);					\
52	} else if (prec == 2) {						\
53		FPUINFO_KSTAT(kstat_d);					\
54	} else {							\
55		FPUINFO_KSTAT(kstat_q);					\
56	}
57
58/*
59 * FPU simulator global kstat data
60 */
61struct fpuinfo_kstat fpuinfo = {
62	{ "fpu_sim_fmovs",		KSTAT_DATA_UINT64},
63	{ "fpu_sim_fmovd",		KSTAT_DATA_UINT64},
64	{ "fpu_sim_fmovq",		KSTAT_DATA_UINT64},
65	{ "fpu_sim_fnegs",		KSTAT_DATA_UINT64},
66	{ "fpu_sim_fnegd",		KSTAT_DATA_UINT64},
67	{ "fpu_sim_fnegq",		KSTAT_DATA_UINT64},
68	{ "fpu_sim_fabss",		KSTAT_DATA_UINT64},
69	{ "fpu_sim_fabsd",		KSTAT_DATA_UINT64},
70	{ "fpu_sim_fabsq",		KSTAT_DATA_UINT64},
71	{ "fpu_sim_fsqrts",		KSTAT_DATA_UINT64},
72	{ "fpu_sim_fsqrtd",		KSTAT_DATA_UINT64},
73	{ "fpu_sim_fsqrtq",		KSTAT_DATA_UINT64},
74	{ "fpu_sim_fadds",		KSTAT_DATA_UINT64},
75	{ "fpu_sim_faddd",		KSTAT_DATA_UINT64},
76	{ "fpu_sim_faddq",		KSTAT_DATA_UINT64},
77	{ "fpu_sim_fsubs",		KSTAT_DATA_UINT64},
78	{ "fpu_sim_fsubd",		KSTAT_DATA_UINT64},
79	{ "fpu_sim_fsubq",		KSTAT_DATA_UINT64},
80	{ "fpu_sim_fmuls",		KSTAT_DATA_UINT64},
81	{ "fpu_sim_fmuld",		KSTAT_DATA_UINT64},
82	{ "fpu_sim_fmulq",		KSTAT_DATA_UINT64},
83	{ "fpu_sim_fdivs",		KSTAT_DATA_UINT64},
84	{ "fpu_sim_fdivd",		KSTAT_DATA_UINT64},
85	{ "fpu_sim_fdivq",		KSTAT_DATA_UINT64},
86	{ "fpu_sim_fcmps",		KSTAT_DATA_UINT64},
87	{ "fpu_sim_fcmpd",		KSTAT_DATA_UINT64},
88	{ "fpu_sim_fcmpq",		KSTAT_DATA_UINT64},
89	{ "fpu_sim_fcmpes",		KSTAT_DATA_UINT64},
90	{ "fpu_sim_fcmped",		KSTAT_DATA_UINT64},
91	{ "fpu_sim_fcmpeq",		KSTAT_DATA_UINT64},
92	{ "fpu_sim_fsmuld",		KSTAT_DATA_UINT64},
93	{ "fpu_sim_fdmulx",		KSTAT_DATA_UINT64},
94	{ "fpu_sim_fstox",		KSTAT_DATA_UINT64},
95	{ "fpu_sim_fdtox",		KSTAT_DATA_UINT64},
96	{ "fpu_sim_fqtox",		KSTAT_DATA_UINT64},
97	{ "fpu_sim_fxtos",		KSTAT_DATA_UINT64},
98	{ "fpu_sim_fxtod",		KSTAT_DATA_UINT64},
99	{ "fpu_sim_fxtoq",		KSTAT_DATA_UINT64},
100	{ "fpu_sim_fitos",		KSTAT_DATA_UINT64},
101	{ "fpu_sim_fitod",		KSTAT_DATA_UINT64},
102	{ "fpu_sim_fitoq",		KSTAT_DATA_UINT64},
103	{ "fpu_sim_fstoi",		KSTAT_DATA_UINT64},
104	{ "fpu_sim_fdtoi",		KSTAT_DATA_UINT64},
105	{ "fpu_sim_fqtoi",		KSTAT_DATA_UINT64},
106	{ "fpu_sim_fmovcc",		KSTAT_DATA_UINT64},
107	{ "fpu_sim_fmovr",		KSTAT_DATA_UINT64},
108	{ "fpu_sim_fmadds",		KSTAT_DATA_UINT64},
109	{ "fpu_sim_fmaddd",		KSTAT_DATA_UINT64},
110	{ "fpu_sim_fmsubs",		KSTAT_DATA_UINT64},
111	{ "fpu_sim_fmsubd",		KSTAT_DATA_UINT64},
112	{ "fpu_sim_fnmadds",		KSTAT_DATA_UINT64},
113	{ "fpu_sim_fnmaddd",		KSTAT_DATA_UINT64},
114	{ "fpu_sim_fnmsubs",		KSTAT_DATA_UINT64},
115	{ "fpu_sim_fnmsubd",		KSTAT_DATA_UINT64},
116	{ "fpu_sim_invalid",		KSTAT_DATA_UINT64},
117};
118
119struct visinfo_kstat visinfo = {
120	{ "vis_edge8",		KSTAT_DATA_UINT64},
121	{ "vis_edge8n",		KSTAT_DATA_UINT64},
122	{ "vis_edge8l",		KSTAT_DATA_UINT64},
123	{ "vis_edge8ln",	KSTAT_DATA_UINT64},
124	{ "vis_edge16",		KSTAT_DATA_UINT64},
125	{ "vis_edge16n",	KSTAT_DATA_UINT64},
126	{ "vis_edge16l",	KSTAT_DATA_UINT64},
127	{ "vis_edge16ln",	KSTAT_DATA_UINT64},
128	{ "vis_edge32",		KSTAT_DATA_UINT64},
129	{ "vis_edge32n",	KSTAT_DATA_UINT64},
130	{ "vis_edge32l",	KSTAT_DATA_UINT64},
131	{ "vis_edge32ln",	KSTAT_DATA_UINT64},
132	{ "vis_array8",		KSTAT_DATA_UINT64},
133	{ "vis_array16",	KSTAT_DATA_UINT64},
134	{ "vis_array32",	KSTAT_DATA_UINT64},
135	{ "vis_bmask",		KSTAT_DATA_UINT64},
136	{ "vis_fcmple16",	KSTAT_DATA_UINT64},
137	{ "vis_fcmpne16",	KSTAT_DATA_UINT64},
138	{ "vis_fcmpgt16",	KSTAT_DATA_UINT64},
139	{ "vis_fcmpeq16",	KSTAT_DATA_UINT64},
140	{ "vis_fcmple32",	KSTAT_DATA_UINT64},
141	{ "vis_fcmpne32",	KSTAT_DATA_UINT64},
142	{ "vis_fcmpgt32",	KSTAT_DATA_UINT64},
143	{ "vis_fcmpeq32",	KSTAT_DATA_UINT64},
144	{ "vis_fmul8x16",	KSTAT_DATA_UINT64},
145	{ "vis_fmul8x16au",	KSTAT_DATA_UINT64},
146	{ "vis_fmul8x16al",	KSTAT_DATA_UINT64},
147	{ "vis_fmul8sux16",	KSTAT_DATA_UINT64},
148	{ "vis_fmul8ulx16",	KSTAT_DATA_UINT64},
149	{ "vis_fmuld8sux16",	KSTAT_DATA_UINT64},
150	{ "vis_fmuld8ulx16",	KSTAT_DATA_UINT64},
151	{ "vis_fpack16",	KSTAT_DATA_UINT64},
152	{ "vis_fpack32",	KSTAT_DATA_UINT64},
153	{ "vis_fpackfix",	KSTAT_DATA_UINT64},
154	{ "vis_fexpand",	KSTAT_DATA_UINT64},
155	{ "vis_fpmerge",	KSTAT_DATA_UINT64},
156	{ "vis_pdist",		KSTAT_DATA_UINT64},
157	{ "vis_pdistn",		KSTAT_DATA_UINT64},
158	{ "vis_bshuffle",	KSTAT_DATA_UINT64},
159
160};
161
162/* PUBLIC FUNCTIONS */
163
164int fp_notp = 1;	/* fp checking not a problem */
165
166/* ARGSUSED */
167static enum ftt_type
168_fp_fpu_simulator(
169	fp_simd_type	*pfpsd,	/* Pointer to fpu simulator data */
170	fp_inst_type	inst,	/* FPU instruction to simulate. */
171	fsr_type	*pfsr,	/* Pointer to image of FSR to read and write. */
172	uint64_t	gsr)	/* Image of GSR to read */
173{
174	unpacked	us1, us2, ud;	/* Unpacked operands and result. */
175	uint32_t	nrs1, nrs2, nrd; /* Register number fields. */
176	uint32_t	usr, andexcep;
177	fsr_type	fsr;
178	enum fcc_type	cc;
179	uint32_t	nfcc;		/* fcc number field. */
180	uint64_t	lusr;
181
182	nrs1 = inst.rs1;
183	nrs2 = inst.rs2;
184	nrd = inst.rd;
185	fsr = *pfsr;
186	pfpsd->fp_current_exceptions = 0;	/* Init current exceptions. */
187	pfpsd->fp_fsrtem    = fsr.tem;		/* Obtain fsr's tem */
188	/*
189	 * Obtain rounding direction and precision
190	 */
191	pfpsd->fp_direction = GSR_IM(gsr) ? GSR_IRND(gsr) : fsr.rnd;
192	pfpsd->fp_precision = fsr.rnp;
193
194	if (inst.op3 == 0x37) { /* IMPDEP2B FMA-fused opcode */
195		fp_fma_inst_type *fma_inst;
196		uint32_t	nrs3;
197		unpacked	us3;
198		unpacked	ust;
199		fma_inst = (fp_fma_inst_type *) &inst;
200		nrs2 = fma_inst->rs2;
201		nrs3 = fma_inst->rs3;
202		switch (fma_inst->var) {
203		case fmadd:
204			_fp_unpack(pfpsd, &us1, nrs1, fma_inst->sz);
205			_fp_unpack(pfpsd, &us2, nrs2, fma_inst->sz);
206			_fp_mul(pfpsd, &us1, &us2, &ust);
207			if ((pfpsd->fp_current_exceptions & fsr.tem) == 0) {
208				_fp_unpack(pfpsd, &us3, nrs3, fma_inst->sz);
209				_fp_add(pfpsd, &ust, &us3, &ud);
210				_fp_pack(pfpsd, &ud, nrd, fma_inst->sz);
211			}
212			FPUINFO_KSTAT_PREC(fma_inst->sz, fpu_sim_fmadds,
213			    fpu_sim_fmaddd, fpu_sim_invalid);
214			break;
215		case fmsub:
216			_fp_unpack(pfpsd, &us1, nrs1, fma_inst->sz);
217			_fp_unpack(pfpsd, &us2, nrs2, fma_inst->sz);
218			_fp_mul(pfpsd, &us1, &us2, &ust);
219			if ((pfpsd->fp_current_exceptions & fsr.tem) == 0) {
220				_fp_unpack(pfpsd, &us3, nrs3, fma_inst->sz);
221				_fp_sub(pfpsd, &ust, &us3, &ud);
222				_fp_pack(pfpsd, &ud, nrd, fma_inst->sz);
223			}
224			FPUINFO_KSTAT_PREC(fma_inst->sz, fpu_sim_fmsubs,
225			    fpu_sim_fmsubd, fpu_sim_invalid);
226			break;
227		case fnmadd:
228			_fp_unpack(pfpsd, &us1, nrs1, fma_inst->sz);
229			_fp_unpack(pfpsd, &us2, nrs2, fma_inst->sz);
230			_fp_mul(pfpsd, &us1, &us2, &ust);
231			if ((pfpsd->fp_current_exceptions & fsr.tem) == 0) {
232				_fp_unpack(pfpsd, &us3, nrs3, fma_inst->sz);
233				if (ust.fpclass != fp_quiet &&
234				    ust.fpclass != fp_signaling)
235					ust.sign ^= 1;
236				_fp_sub(pfpsd, &ust, &us3, &ud);
237				_fp_pack(pfpsd, &ud, nrd, fma_inst->sz);
238			}
239			FPUINFO_KSTAT_PREC(fma_inst->sz, fpu_sim_fnmadds,
240			    fpu_sim_fnmaddd, fpu_sim_invalid);
241			break;
242		case fnmsub:
243			_fp_unpack(pfpsd, &us1, nrs1, fma_inst->sz);
244			_fp_unpack(pfpsd, &us2, nrs2, fma_inst->sz);
245			_fp_mul(pfpsd, &us1, &us2, &ust);
246			if ((pfpsd->fp_current_exceptions & fsr.tem) == 0) {
247				_fp_unpack(pfpsd, &us3, nrs3, fma_inst->sz);
248				if (ust.fpclass != fp_quiet &&
249				    ust.fpclass != fp_signaling)
250					ust.sign ^= 1;
251				_fp_add(pfpsd, &ust, &us3, &ud);
252				_fp_pack(pfpsd, &ud, nrd, fma_inst->sz);
253			}
254			FPUINFO_KSTAT_PREC(fma_inst->sz, fpu_sim_fnmsubs,
255			    fpu_sim_fnmsubd, fpu_sim_invalid);
256		}
257	} else {
258		nfcc = nrd & 0x3;
259		if (inst.op3 == 0x35) {		/* fpop2 */
260			fsr.cexc = 0;
261			*pfsr = fsr;
262			if ((inst.opcode & 0xf) == 0) {
263				if ((fp_notp) && (inst.prec == 0))
264					return (ftt_unimplemented);
265				FPUINFO_KSTAT(fpu_sim_fmovcc);
266				return (fmovcc(pfpsd, inst, pfsr)); /* fmovcc */
267			} else if ((inst.opcode & 0x7) == 1) {
268				if ((fp_notp) && (inst.prec == 0))
269					return (ftt_unimplemented);
270				FPUINFO_KSTAT(fpu_sim_fmovr);
271				return (fmovr(pfpsd, inst));	/* fmovr */
272			}
273		}
274		/* ibit not valid for fpop1 instructions */
275		if ((fp_notp) && (inst.ibit != 0))
276			return (ftt_unimplemented);
277		if ((fp_notp) && (inst.prec == 0)) { /* fxto[sdq], fito[sdq] */
278			if ((inst.opcode != flltos) &&
279			    (inst.opcode != flltod) &&
280			    (inst.opcode != flltox) &&
281			    (inst.opcode != fitos) &&
282			    (inst.opcode != fitod) &&
283			    (inst.opcode != fitox)) {
284				return (ftt_unimplemented);
285			}
286		}
287		switch (inst.opcode) {
288		case fmovs:		/* also covers fmovd, fmovq */
289			if (inst.prec < 2) {	/* fmovs */
290				_fp_unpack_word(pfpsd, &usr, nrs2);
291				_fp_pack_word(pfpsd, &usr, nrd);
292				FPUINFO_KSTAT(fpu_sim_fmovs);
293			} else {		/* fmovd */
294				_fp_unpack_extword(pfpsd, &lusr, nrs2);
295				_fp_pack_extword(pfpsd, &lusr, nrd);
296				if (inst.prec > 2) {		/* fmovq */
297					_fp_unpack_extword(pfpsd, &lusr,
298					    nrs2+2);
299					_fp_pack_extword(pfpsd, &lusr, nrd+2);
300					FPUINFO_KSTAT(fpu_sim_fmovq);
301				} else {
302					FPUINFO_KSTAT(fpu_sim_fmovd);
303				}
304			}
305			break;
306		case fabss:		/* also covers fabsd, fabsq */
307			if (inst.prec < 2) {	/* fabss */
308				_fp_unpack_word(pfpsd, &usr, nrs2);
309				usr &= 0x7fffffff;
310				_fp_pack_word(pfpsd, &usr, nrd);
311				FPUINFO_KSTAT(fpu_sim_fabss);
312			} else {		/* fabsd */
313				_fp_unpack_extword(pfpsd, &lusr, nrs2);
314				lusr &= 0x7fffffffffffffff;
315				_fp_pack_extword(pfpsd, &lusr, nrd);
316				if (inst.prec > 2) {		/* fabsq */
317					_fp_unpack_extword(pfpsd, &lusr,
318					    nrs2+2);
319					_fp_pack_extword(pfpsd, &lusr, nrd+2);
320					FPUINFO_KSTAT(fpu_sim_fabsq);
321				} else {
322					FPUINFO_KSTAT(fpu_sim_fabsd);
323				}
324			}
325			break;
326		case fnegs:		/* also covers fnegd, fnegq */
327			if (inst.prec < 2) {	/* fnegs */
328				_fp_unpack_word(pfpsd, &usr, nrs2);
329				usr ^= 0x80000000;
330				_fp_pack_word(pfpsd, &usr, nrd);
331				FPUINFO_KSTAT(fpu_sim_fnegs);
332			} else {		/* fnegd */
333				_fp_unpack_extword(pfpsd, &lusr, nrs2);
334				lusr ^= 0x8000000000000000;
335				_fp_pack_extword(pfpsd, &lusr, nrd);
336				if (inst.prec > 2) {		/* fnegq */
337					_fp_unpack_extword(pfpsd, &lusr,
338					    nrs2+2);
339					lusr ^= 0x0000000000000000;
340					_fp_pack_extword(pfpsd, &lusr, nrd+2);
341					FPUINFO_KSTAT(fpu_sim_fnegq);
342				} else {
343					FPUINFO_KSTAT(fpu_sim_fnegd);
344				}
345			}
346			break;
347		case fadd:
348			_fp_unpack(pfpsd, &us1, nrs1, inst.prec);
349			_fp_unpack(pfpsd, &us2, nrs2, inst.prec);
350			_fp_add(pfpsd, &us1, &us2, &ud);
351			_fp_pack(pfpsd, &ud, nrd, inst.prec);
352			FPUINFO_KSTAT_PREC(inst.prec, fpu_sim_fadds,
353			    fpu_sim_faddd, fpu_sim_faddq);
354			break;
355		case fsub:
356			_fp_unpack(pfpsd, &us1, nrs1, inst.prec);
357			_fp_unpack(pfpsd, &us2, nrs2, inst.prec);
358			_fp_sub(pfpsd, &us1, &us2, &ud);
359			_fp_pack(pfpsd, &ud, nrd, inst.prec);
360			FPUINFO_KSTAT_PREC(inst.prec, fpu_sim_fsubs,
361			    fpu_sim_fsubd, fpu_sim_fsubq);
362			break;
363		case fmul:
364			_fp_unpack(pfpsd, &us1, nrs1, inst.prec);
365			_fp_unpack(pfpsd, &us2, nrs2, inst.prec);
366			_fp_mul(pfpsd, &us1, &us2, &ud);
367			_fp_pack(pfpsd, &ud, nrd, inst.prec);
368			FPUINFO_KSTAT_PREC(inst.prec, fpu_sim_fmuls,
369			    fpu_sim_fmuld, fpu_sim_fmulq);
370			break;
371		case fsmuld:
372			if ((fp_notp) && (inst.prec != 1))
373				return (ftt_unimplemented);
374			_fp_unpack(pfpsd, &us1, nrs1, inst.prec);
375			_fp_unpack(pfpsd, &us2, nrs2, inst.prec);
376			_fp_mul(pfpsd, &us1, &us2, &ud);
377			_fp_pack(pfpsd, &ud, nrd,
378			    (enum fp_op_type) ((int)inst.prec+1));
379			FPUINFO_KSTAT(fpu_sim_fsmuld);
380			break;
381		case fdmulx:
382			if ((fp_notp) && (inst.prec != 2))
383				return (ftt_unimplemented);
384			_fp_unpack(pfpsd, &us1, nrs1, inst.prec);
385			_fp_unpack(pfpsd, &us2, nrs2, inst.prec);
386			_fp_mul(pfpsd, &us1, &us2, &ud);
387			_fp_pack(pfpsd, &ud, nrd,
388			    (enum fp_op_type) ((int)inst.prec+1));
389			FPUINFO_KSTAT(fpu_sim_fdmulx);
390			break;
391		case fdiv:
392			_fp_unpack(pfpsd, &us1, nrs1, inst.prec);
393			_fp_unpack(pfpsd, &us2, nrs2, inst.prec);
394			_fp_div(pfpsd, &us1, &us2, &ud);
395			_fp_pack(pfpsd, &ud, nrd, inst.prec);
396			FPUINFO_KSTAT_PREC(inst.prec, fpu_sim_fdivs,
397			    fpu_sim_fdivd, fpu_sim_fdivq);
398			break;
399		case fcmp:
400			_fp_unpack(pfpsd, &us1, nrs1, inst.prec);
401			_fp_unpack(pfpsd, &us2, nrs2, inst.prec);
402			cc = _fp_compare(pfpsd, &us1, &us2, 0);
403			if (!(pfpsd->fp_current_exceptions & pfpsd->fp_fsrtem))
404				switch (nfcc) {
405				case fcc_0:
406					fsr.fcc0 = cc;
407					break;
408				case fcc_1:
409					fsr.fcc1 = cc;
410					break;
411				case fcc_2:
412					fsr.fcc2 = cc;
413					break;
414				case fcc_3:
415					fsr.fcc3 = cc;
416					break;
417				}
418			FPUINFO_KSTAT_PREC(inst.prec, fpu_sim_fcmps,
419			    fpu_sim_fcmpd, fpu_sim_fcmpq);
420			break;
421		case fcmpe:
422			_fp_unpack(pfpsd, &us1, nrs1, inst.prec);
423			_fp_unpack(pfpsd, &us2, nrs2, inst.prec);
424			cc = _fp_compare(pfpsd, &us1, &us2, 1);
425			if (!(pfpsd->fp_current_exceptions & pfpsd->fp_fsrtem))
426				switch (nfcc) {
427				case fcc_0:
428					fsr.fcc0 = cc;
429					break;
430				case fcc_1:
431					fsr.fcc1 = cc;
432					break;
433				case fcc_2:
434					fsr.fcc2 = cc;
435					break;
436				case fcc_3:
437					fsr.fcc3 = cc;
438					break;
439				}
440			FPUINFO_KSTAT_PREC(inst.prec, fpu_sim_fcmpes,
441			    fpu_sim_fcmped, fpu_sim_fcmpeq);
442			break;
443		case fsqrt:
444			_fp_unpack(pfpsd, &us1, nrs2, inst.prec);
445			_fp_sqrt(pfpsd, &us1, &ud);
446			_fp_pack(pfpsd, &ud, nrd, inst.prec);
447			FPUINFO_KSTAT_PREC(inst.prec, fpu_sim_fsqrts,
448			    fpu_sim_fsqrtd, fpu_sim_fsqrtq);
449			break;
450		case ftoi:
451			_fp_unpack(pfpsd, &us1, nrs2, inst.prec);
452			pfpsd->fp_direction = fp_tozero;
453			/* Force rounding toward zero. */
454			_fp_pack(pfpsd, &us1, nrd, fp_op_int32);
455			FPUINFO_KSTAT_PREC(inst.prec, fpu_sim_fstoi,
456			    fpu_sim_fdtoi, fpu_sim_fqtoi);
457			break;
458		case ftoll:
459			_fp_unpack(pfpsd, &us1, nrs2, inst.prec);
460			pfpsd->fp_direction = fp_tozero;
461			/* Force rounding toward zero. */
462			_fp_pack(pfpsd, &us1, nrd, fp_op_int64);
463			FPUINFO_KSTAT_PREC(inst.prec, fpu_sim_fstox,
464			    fpu_sim_fdtox, fpu_sim_fqtox);
465			break;
466		case flltos:
467			_fp_unpack(pfpsd, &us1, nrs2, fp_op_int64);
468			_fp_pack(pfpsd, &us1, nrd, fp_op_single);
469			FPUINFO_KSTAT(fpu_sim_fxtos);
470			break;
471		case flltod:
472			_fp_unpack(pfpsd, &us1, nrs2, fp_op_int64);
473			_fp_pack(pfpsd, &us1, nrd, fp_op_double);
474			FPUINFO_KSTAT(fpu_sim_fxtod);
475			break;
476		case flltox:
477			_fp_unpack(pfpsd, &us1, nrs2, fp_op_int64);
478			_fp_pack(pfpsd, &us1, nrd, fp_op_extended);
479			FPUINFO_KSTAT(fpu_sim_fxtoq);
480			break;
481		case fitos:
482			_fp_unpack(pfpsd, &us1, nrs2, inst.prec);
483			_fp_pack(pfpsd, &us1, nrd, fp_op_single);
484			FPUINFO_KSTAT(fpu_sim_fitos);
485			break;
486		case fitod:
487			_fp_unpack(pfpsd, &us1, nrs2, inst.prec);
488			_fp_pack(pfpsd, &us1, nrd, fp_op_double);
489			FPUINFO_KSTAT(fpu_sim_fitod);
490			break;
491		case fitox:
492			_fp_unpack(pfpsd, &us1, nrs2, inst.prec);
493			_fp_pack(pfpsd, &us1, nrd, fp_op_extended);
494			FPUINFO_KSTAT(fpu_sim_fitoq);
495			break;
496		default:
497			return (ftt_unimplemented);
498		}
499	}
500	fsr.cexc = pfpsd->fp_current_exceptions;
501	andexcep = pfpsd->fp_current_exceptions & fsr.tem;
502	if (andexcep != 0) {	/* Signal an IEEE SIGFPE here. */
503		if (andexcep & (1 << fp_invalid)) {
504			pfpsd->fp_trapcode = FPE_FLTINV;
505			fsr.cexc = FSR_CEXC_NV;
506		} else if (andexcep & (1 << fp_overflow)) {
507			pfpsd->fp_trapcode = FPE_FLTOVF;
508			fsr.cexc = FSR_CEXC_OF;
509		} else if (andexcep & (1 << fp_underflow)) {
510			pfpsd->fp_trapcode = FPE_FLTUND;
511			fsr.cexc = FSR_CEXC_UF;
512		} else if (andexcep & (1 << fp_division)) {
513			pfpsd->fp_trapcode = FPE_FLTDIV;
514			fsr.cexc = FSR_CEXC_DZ;
515		} else if (andexcep & (1 << fp_inexact)) {
516			pfpsd->fp_trapcode = FPE_FLTRES;
517			fsr.cexc = FSR_CEXC_NX;
518		} else {
519			pfpsd->fp_trapcode = 0;
520		}
521		*pfsr = fsr;
522		return (ftt_ieee);
523	} else {	/* Just set accrued exception field. */
524		fsr.aexc |= pfpsd->fp_current_exceptions;
525	}
526	*pfsr = fsr;
527	return (ftt_none);
528}
529
530/*
531 * fpu_vis_sim simulates fpu and vis instructions;
532 * It can work with both real and pcb image registers.
533 */
534enum ftt_type
535fpu_vis_sim(
536	fp_simd_type	*pfpsd,	/* Pointer to simulator data */
537	fp_inst_type	*pinst,	/* Address of FPU instruction to simulate */
538	struct regs	*pregs,	/* Pointer to PCB image of registers. */
539	fsr_type	*pfsr,	/* Pointer to image of FSR to read and write */
540	uint64_t	gsr,	/* Image of GSR to read */
541	uint32_t	inst)	/* The FPU instruction to simulate */
542{
543	klwp_id_t lwp = ttolwp(curthread);
544	union {
545		uint32_t	i;
546		fp_inst_type	inst;
547	} fp;
548	kfpu_t *pfp = lwptofpu(lwp);
549	enum ftt_type ftt;
550
551	fp.i = inst;
552	pfpsd->fp_trapaddr = (caddr_t)pinst;
553	if (fpu_exists) {
554		pfpsd->fp_current_read_freg = _fp_read_pfreg;
555		pfpsd->fp_current_write_freg = _fp_write_pfreg;
556		pfpsd->fp_current_read_dreg = _fp_read_pdreg;
557		pfpsd->fp_current_write_dreg = _fp_write_pdreg;
558		pfpsd->fp_current_read_gsr = _fp_read_pgsr;
559		pfpsd->fp_current_write_gsr = _fp_write_pgsr;
560	} else {
561		pfpsd->fp_current_pfregs = pfp;
562		pfpsd->fp_current_read_freg = _fp_read_vfreg;
563		pfpsd->fp_current_write_freg = _fp_write_vfreg;
564		pfpsd->fp_current_read_dreg = _fp_read_vdreg;
565		pfpsd->fp_current_write_dreg = _fp_write_vdreg;
566		pfpsd->fp_current_read_gsr = get_gsr;
567		pfpsd->fp_current_write_gsr = set_gsr;
568	}
569
570	if ((fp.inst.hibits == 2) && (fp.inst.op3 == 0x36)) {
571			ftt = vis_fpu_simulator(pfpsd, fp.inst,
572			    pregs, (ulong_t *)pregs->r_sp, pfp);
573			return (ftt);
574	} else if ((fp.inst.hibits == 2) &&
575	    ((fp.inst.op3 == 0x34) || (fp.inst.op3 == 0x35) ||
576	    (fp.inst.op3 == 0x37))) {
577		ftt =  _fp_fpu_simulator(pfpsd, fp.inst, pfsr, gsr);
578		if (ftt == ftt_none || ftt == ftt_ieee) {
579			pregs->r_pc = pregs->r_npc;
580			pregs->r_npc += 4;
581		}
582		return (ftt);
583	} else {
584		ftt = _fp_iu_simulator(pfpsd, fp.inst, pregs,
585		    (ulong_t *)pregs->r_sp, pfp);
586		return (ftt);
587	}
588}
589
590/*
591 * fpu_simulator simulates FPU instructions only;
592 * reads and writes FPU data registers directly.
593 */
594enum ftt_type
595fpu_simulator(
596	fp_simd_type	*pfpsd,	/* Pointer to simulator data */
597	fp_inst_type	*pinst,	/* Address of FPU instruction to simulate */
598	fsr_type	*pfsr,	/* Pointer to image of FSR to read and write */
599	uint64_t	gsr,	/* Image of GSR to read */
600	uint32_t	inst)	/* The FPU instruction to simulate */
601{
602	union {
603		uint32_t	i;
604		fp_inst_type	inst;
605	} fp;
606
607	fp.i = inst;
608	pfpsd->fp_trapaddr = (caddr_t)pinst;
609	pfpsd->fp_current_read_freg = _fp_read_pfreg;
610	pfpsd->fp_current_write_freg = _fp_write_pfreg;
611	pfpsd->fp_current_read_dreg = _fp_read_pdreg;
612	pfpsd->fp_current_write_dreg = _fp_write_pdreg;
613	pfpsd->fp_current_read_gsr = _fp_read_pgsr;
614	pfpsd->fp_current_write_gsr = _fp_write_pgsr;
615	return (_fp_fpu_simulator(pfpsd, fp.inst, pfsr, gsr));
616}
617
618/*
619 * fp_emulator simulates FPU and CPU-FPU instructions; reads and writes FPU
620 * data registers from image in pfpu.
621 */
622enum ftt_type
623fp_emulator(
624	fp_simd_type	*pfpsd,	/* Pointer to simulator data */
625	fp_inst_type	*pinst,	/* Pointer to FPU instruction to simulate. */
626	struct regs	*pregs,	/* Pointer to PCB image of registers. */
627	void		*prw,	/* Pointer to locals and ins. */
628	kfpu_t		*pfpu)	/* Pointer to FPU register block. */
629{
630	klwp_id_t lwp = ttolwp(curthread);
631	union {
632		uint32_t	i;
633		fp_inst_type	inst;
634	} fp;
635	enum ftt_type	ftt;
636	uint64_t gsr = get_gsr(pfpu);
637	kfpu_t *pfp = lwptofpu(lwp);
638	uint64_t	tfsr;
639
640	tfsr = pfpu->fpu_fsr;
641	pfpsd->fp_current_pfregs = pfpu;
642	pfpsd->fp_current_read_freg = _fp_read_vfreg;
643	pfpsd->fp_current_write_freg = _fp_write_vfreg;
644	pfpsd->fp_current_read_dreg = _fp_read_vdreg;
645	pfpsd->fp_current_write_dreg = _fp_write_vdreg;
646	pfpsd->fp_current_read_gsr = get_gsr;
647	pfpsd->fp_current_write_gsr = set_gsr;
648	pfpsd->fp_trapaddr = (caddr_t)pinst; /* bad inst addr in case we trap */
649	ftt = _fp_read_inst((uint32_t *)pinst, &(fp.i), pfpsd);
650	if (ftt != ftt_none)
651		return (ftt);
652
653	if ((fp.inst.hibits == 2) &&
654	    ((fp.inst.op3 == 0x34) || (fp.inst.op3 == 0x35) ||
655	    (fp.inst.op3 == 0x37))) {
656		ftt = _fp_fpu_simulator(pfpsd, fp.inst, (fsr_type *)&tfsr, gsr);
657		/* Do not retry emulated instruction. */
658		pregs->r_pc = pregs->r_npc;
659		pregs->r_npc += 4;
660		pfpu->fpu_fsr = tfsr;
661		if (ftt != ftt_none) {
662			/*
663			 * Simulation generated an exception of some kind,
664			 * simulate the fp queue for a signal.
665			 */
666			pfpu->fpu_q->FQu.fpq.fpq_addr = (uint32_t *)pinst;
667			pfpu->fpu_q->FQu.fpq.fpq_instr = fp.i;
668			pfpu->fpu_qcnt = 1;
669		}
670	} else if ((fp.inst.hibits == 2) && (fp.inst.op3 == 0x36)) {
671			ftt = vis_fpu_simulator(pfpsd, fp.inst,
672			    pregs, prw, pfp);
673	} else
674		ftt = _fp_iu_simulator(pfpsd, fp.inst, pregs, prw, pfpu);
675
676	if (ftt != ftt_none)
677		return (ftt);
678
679	/*
680	 * If we are single-stepping, don't emulate any more instructions.
681	 */
682	if (lwp->lwp_pcb.pcb_step != STEP_NONE)
683		return (ftt);
684again:
685	/*
686	 * now read next instruction and see if it can be emulated
687	 */
688	pinst = (fp_inst_type *)pregs->r_pc;
689	pfpsd->fp_trapaddr = (caddr_t)pinst; /* bad inst addr in case we trap */
690	ftt = _fp_read_inst((uint32_t *)pinst, &(fp.i), pfpsd);
691	if (ftt != ftt_none)
692		return (ftt);
693	if ((fp.inst.hibits == 2) &&		/* fpops */
694	    ((fp.inst.op3 == 0x34) || (fp.inst.op3 == 0x35) ||
695	    (fp.inst.op3 == 0x37))) {
696		ftt = _fp_fpu_simulator(pfpsd, fp.inst, (fsr_type *)&tfsr, gsr);
697		/* Do not retry emulated instruction. */
698		pfpu->fpu_fsr = tfsr;
699		pregs->r_pc = pregs->r_npc;
700		pregs->r_npc += 4;
701		if (ftt != ftt_none) {
702			/*
703			 * Simulation generated an exception of some kind,
704			 * simulate the fp queue for a signal.
705			 */
706			pfpu->fpu_q->FQu.fpq.fpq_addr = (uint32_t *)pinst;
707			pfpu->fpu_q->FQu.fpq.fpq_instr = fp.i;
708			pfpu->fpu_qcnt = 1;
709		}
710	} else if ((fp.inst.hibits == 2) && (fp.inst.op3 == 0x36)) {
711			ftt = vis_fpu_simulator(pfpsd, fp.inst,
712			    pregs, prw, pfp);
713	} else if (
714						/* rd %gsr */
715	    ((fp.inst.hibits == 2) && ((fp.inst.op3 & 0x3f) == 0x28) &&
716	    (fp.inst.rs1 == 0x13)) ||
717						/* wr %gsr */
718	    ((fp.inst.hibits == 2) && ((fp.inst.op3 & 0x3f) == 0x30) &&
719	    (fp.inst.rd == 0x13)) ||
720						/* movcc */
721	    ((fp.inst.hibits == 2) && ((fp.inst.op3 & 0x3f) == 0x2c) &&
722	    (((fp.i>>18) & 0x1) == 0)) ||
723						/* fbpcc */
724	    ((fp.inst.hibits == 0) && (((fp.i>>22) & 0x7) == 5)) ||
725						/* fldst */
726	    ((fp.inst.hibits == 3) && ((fp.inst.op3 & 0x38) == 0x20)) ||
727						/* fbcc */
728	    ((fp.inst.hibits == 0) && (((fp.i>>22) & 0x7) == 6))) {
729		ftt = _fp_iu_simulator(pfpsd, fp.inst, pregs, prw, pfpu);
730	} else
731		return (ftt);
732
733	if (ftt != ftt_none)
734		return (ftt);
735	else
736		goto again;
737}
738
739/*
740 * FPU simulator global kstat data
741 */
742struct fpustat_kstat fpustat = {
743	{ "fpu_ieee_traps",		KSTAT_DATA_UINT64 },
744	{ "fpu_unfinished_traps",	KSTAT_DATA_UINT64 },
745	{ "fpu_unimplemented",		KSTAT_DATA_UINT64 },
746};
747
748kstat_t *fpu_kstat = NULL;
749kstat_t *fpuinfo_kstat = NULL;
750kstat_t *visinfo_kstat = NULL;
751
752void
753fp_kstat_init(void)
754{
755	const uint_t fpustat_ndata = sizeof (fpustat) / sizeof (kstat_named_t);
756	const uint_t fpuinfo_ndata = sizeof (fpuinfo) / sizeof (kstat_named_t);
757	const uint_t visinfo_ndata = sizeof (visinfo) /sizeof (kstat_named_t);
758
759	ASSERT(fpu_kstat == NULL);
760	if ((fpu_kstat = kstat_create("unix", 0, "fpu_traps", "misc",
761	    KSTAT_TYPE_NAMED, fpustat_ndata, KSTAT_FLAG_VIRTUAL)) == NULL) {
762		cmn_err(CE_WARN, "CPU%d: kstat_create for fpu_traps failed",
763		    CPU->cpu_id);
764	} else {
765		fpu_kstat->ks_data = (void *)&fpustat;
766		kstat_install(fpu_kstat);
767	}
768
769	ASSERT(fpuinfo_kstat == NULL);
770	if ((fpuinfo_kstat = kstat_create("unix", 0, "fpu_info", "misc",
771	    KSTAT_TYPE_NAMED, fpuinfo_ndata, KSTAT_FLAG_VIRTUAL)) == NULL) {
772		cmn_err(CE_WARN, "CPU%d: kstat_create for fpu_info failed",
773		    CPU->cpu_id);
774	} else {
775		fpuinfo_kstat->ks_data = (void *)&fpuinfo;
776		kstat_install(fpuinfo_kstat);
777	}
778	ASSERT(visinfo_kstat == NULL);
779	if ((visinfo_kstat = kstat_create("unix", 0, "vis_info", "misc",
780	    KSTAT_TYPE_NAMED, visinfo_ndata, KSTAT_FLAG_VIRTUAL)) == NULL) {
781		cmn_err(CE_WARN, "CPU%d: kstat_create for vis_info failed",
782		    CPU->cpu_id);
783	} else {
784		visinfo_kstat->ks_data = (void *)&visinfo;
785		kstat_install(visinfo_kstat);
786	}
787}
788
789void
790fp_kstat_update(enum ftt_type ftt)
791{
792	ASSERT((ftt == ftt_ieee) || (ftt == ftt_unfinished) ||
793	    (ftt == ftt_unimplemented));
794	if (ftt == ftt_ieee)
795		atomic_inc_64(&fpustat.fpu_ieee_traps.value.ui64);
796	else if (ftt == ftt_unfinished)
797		atomic_inc_64(&fpustat.fpu_unfinished_traps.value.ui64);
798	else if (ftt == ftt_unimplemented)
799		atomic_inc_64(&fpustat.fpu_unimplemented_traps.value.ui64);
800}
801