1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 /* 25 * Copyright (c) 2010, Intel Corporation. 26 * All rights reserved. 27 */ 28 /* 29 * Copyright (c) 2011, Joyent, Inc. All rights reserved. 30 */ 31 32 #ifndef _SYS_X86_ARCHEXT_H 33 #define _SYS_X86_ARCHEXT_H 34 35 #if !defined(_ASM) 36 #include <sys/regset.h> 37 #include <sys/processor.h> 38 #include <vm/seg_enum.h> 39 #include <vm/page.h> 40 #endif /* _ASM */ 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* 47 * cpuid instruction feature flags in %edx (standard function 1) 48 */ 49 50 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 51 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 52 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 53 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 54 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 55 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 56 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 57 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 58 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 59 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 60 /* 0x400 - reserved */ 61 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 62 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 63 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 64 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 65 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 66 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 67 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 68 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 69 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 70 /* 0x100000 - reserved */ 71 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 72 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 73 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 74 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 75 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 76 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 77 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 78 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 79 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 80 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 81 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 82 83 #define FMT_CPUID_INTC_EDX \ 84 "\20" \ 85 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 86 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 87 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 88 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 89 90 /* 91 * cpuid instruction feature flags in %ecx (standard function 1) 92 */ 93 94 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 95 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 96 /* 0x00000004 - reserved */ 97 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 98 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 99 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 100 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 101 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 102 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 103 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 104 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 105 /* 0x00000800 - reserved */ 106 /* 0x00001000 - reserved */ 107 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 108 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 109 /* 0x00008000 - reserved */ 110 /* 0x00010000 - reserved */ 111 /* 0x00020000 - reserved */ 112 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 113 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 114 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 115 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 116 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 121 122 #define FMT_CPUID_INTC_ECX \ 123 "\20" \ 124 "\35avx\34osxsav\33xsave" \ 125 "\32aes" \ 126 "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \ 127 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 128 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3" 129 130 /* 131 * cpuid instruction feature flags in %edx (extended function 0x80000001) 132 */ 133 134 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 135 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 136 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 137 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 138 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 139 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 140 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 141 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 142 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 143 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 144 /* 0x00000400 - sysc on K6m6 */ 145 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 146 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 147 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 148 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 149 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 150 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 151 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 152 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 153 /* 0x00040000 - reserved */ 154 /* 0x00080000 - reserved */ 155 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 156 /* 0x00200000 - reserved */ 157 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 158 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 159 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 160 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 161 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 162 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 163 /* 0x10000000 - reserved */ 164 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 165 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 166 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 167 168 #define FMT_CPUID_AMD_EDX \ 169 "\20" \ 170 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 171 "\30mmx\27mmxext\25nx\22pse\21pat" \ 172 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 173 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 174 175 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 176 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 177 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 178 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 179 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 180 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 181 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 182 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 183 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 184 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 185 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 186 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ 187 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 188 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 189 190 #define FMT_CPUID_AMD_ECX \ 191 "\20" \ 192 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \ 193 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 194 195 /* 196 * Intel now seems to have claimed part of the "extended" function 197 * space that we previously for non-Intel implementors to use. 198 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 199 * is available in long mode i.e. what AMD indicate using bit 0. 200 * On the other hand, everything else is labelled as reserved. 201 */ 202 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 203 204 205 #define P5_MCHADDR 0x0 206 #define P5_CESR 0x11 207 #define P5_CTR0 0x12 208 #define P5_CTR1 0x13 209 210 #define K5_MCHADDR 0x0 211 #define K5_MCHTYPE 0x01 212 #define K5_TSC 0x10 213 #define K5_TR12 0x12 214 215 #define REG_PAT 0x277 216 217 #define REG_MC0_CTL 0x400 218 #define REG_MC5_MISC 0x417 219 #define REG_PERFCTR0 0xc1 220 #define REG_PERFCTR1 0xc2 221 222 #define REG_PERFEVNT0 0x186 223 #define REG_PERFEVNT1 0x187 224 225 #define REG_TSC 0x10 /* timestamp counter */ 226 #define REG_APIC_BASE_MSR 0x1b 227 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 228 229 #if !defined(__xpv) 230 /* 231 * AMD C1E 232 */ 233 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 234 #define AMD_ACTONCMPHALT_SHIFT 27 235 #define AMD_ACTONCMPHALT_MASK 3 236 #endif 237 238 #define MSR_DEBUGCTL 0x1d9 239 240 #define DEBUGCTL_LBR 0x01 241 #define DEBUGCTL_BTF 0x02 242 243 /* Intel P6, AMD */ 244 #define MSR_LBR_FROM 0x1db 245 #define MSR_LBR_TO 0x1dc 246 #define MSR_LEX_FROM 0x1dd 247 #define MSR_LEX_TO 0x1de 248 249 /* Intel P4 (pre-Prescott, non P4 M) */ 250 #define MSR_P4_LBSTK_TOS 0x1da 251 #define MSR_P4_LBSTK_0 0x1db 252 #define MSR_P4_LBSTK_1 0x1dc 253 #define MSR_P4_LBSTK_2 0x1dd 254 #define MSR_P4_LBSTK_3 0x1de 255 256 /* Intel Pentium M */ 257 #define MSR_P6M_LBSTK_TOS 0x1c9 258 #define MSR_P6M_LBSTK_0 0x040 259 #define MSR_P6M_LBSTK_1 0x041 260 #define MSR_P6M_LBSTK_2 0x042 261 #define MSR_P6M_LBSTK_3 0x043 262 #define MSR_P6M_LBSTK_4 0x044 263 #define MSR_P6M_LBSTK_5 0x045 264 #define MSR_P6M_LBSTK_6 0x046 265 #define MSR_P6M_LBSTK_7 0x047 266 267 /* Intel P4 (Prescott) */ 268 #define MSR_PRP4_LBSTK_TOS 0x1da 269 #define MSR_PRP4_LBSTK_FROM_0 0x680 270 #define MSR_PRP4_LBSTK_FROM_1 0x681 271 #define MSR_PRP4_LBSTK_FROM_2 0x682 272 #define MSR_PRP4_LBSTK_FROM_3 0x683 273 #define MSR_PRP4_LBSTK_FROM_4 0x684 274 #define MSR_PRP4_LBSTK_FROM_5 0x685 275 #define MSR_PRP4_LBSTK_FROM_6 0x686 276 #define MSR_PRP4_LBSTK_FROM_7 0x687 277 #define MSR_PRP4_LBSTK_FROM_8 0x688 278 #define MSR_PRP4_LBSTK_FROM_9 0x689 279 #define MSR_PRP4_LBSTK_FROM_10 0x68a 280 #define MSR_PRP4_LBSTK_FROM_11 0x68b 281 #define MSR_PRP4_LBSTK_FROM_12 0x68c 282 #define MSR_PRP4_LBSTK_FROM_13 0x68d 283 #define MSR_PRP4_LBSTK_FROM_14 0x68e 284 #define MSR_PRP4_LBSTK_FROM_15 0x68f 285 #define MSR_PRP4_LBSTK_TO_0 0x6c0 286 #define MSR_PRP4_LBSTK_TO_1 0x6c1 287 #define MSR_PRP4_LBSTK_TO_2 0x6c2 288 #define MSR_PRP4_LBSTK_TO_3 0x6c3 289 #define MSR_PRP4_LBSTK_TO_4 0x6c4 290 #define MSR_PRP4_LBSTK_TO_5 0x6c5 291 #define MSR_PRP4_LBSTK_TO_6 0x6c6 292 #define MSR_PRP4_LBSTK_TO_7 0x6c7 293 #define MSR_PRP4_LBSTK_TO_8 0x6c8 294 #define MSR_PRP4_LBSTK_TO_9 0x6c9 295 #define MSR_PRP4_LBSTK_TO_10 0x6ca 296 #define MSR_PRP4_LBSTK_TO_11 0x6cb 297 #define MSR_PRP4_LBSTK_TO_12 0x6cc 298 #define MSR_PRP4_LBSTK_TO_13 0x6cd 299 #define MSR_PRP4_LBSTK_TO_14 0x6ce 300 #define MSR_PRP4_LBSTK_TO_15 0x6cf 301 302 #define MCI_CTL_VALUE 0xffffffff 303 304 #define MTRR_TYPE_UC 0 305 #define MTRR_TYPE_WC 1 306 #define MTRR_TYPE_WT 4 307 #define MTRR_TYPE_WP 5 308 #define MTRR_TYPE_WB 6 309 #define MTRR_TYPE_UC_ 7 310 311 /* 312 * For Solaris we set up the page attritubute table in the following way: 313 * PAT0 Write-Back 314 * PAT1 Write-Through 315 * PAT2 Unchacheable- 316 * PAT3 Uncacheable 317 * PAT4 Write-Back 318 * PAT5 Write-Through 319 * PAT6 Write-Combine 320 * PAT7 Uncacheable 321 * The only difference from h/w default is entry 6. 322 */ 323 #define PAT_DEFAULT_ATTRIBUTE \ 324 ((uint64_t)MTRR_TYPE_WB | \ 325 ((uint64_t)MTRR_TYPE_WT << 8) | \ 326 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 327 ((uint64_t)MTRR_TYPE_UC << 24) | \ 328 ((uint64_t)MTRR_TYPE_WB << 32) | \ 329 ((uint64_t)MTRR_TYPE_WT << 40) | \ 330 ((uint64_t)MTRR_TYPE_WC << 48) | \ 331 ((uint64_t)MTRR_TYPE_UC << 56)) 332 333 #define X86FSET_LARGEPAGE 0 334 #define X86FSET_TSC 1 335 #define X86FSET_MSR 2 336 #define X86FSET_MTRR 3 337 #define X86FSET_PGE 4 338 #define X86FSET_DE 5 339 #define X86FSET_CMOV 6 340 #define X86FSET_MMX 7 341 #define X86FSET_MCA 8 342 #define X86FSET_PAE 9 343 #define X86FSET_CX8 10 344 #define X86FSET_PAT 11 345 #define X86FSET_SEP 12 346 #define X86FSET_SSE 13 347 #define X86FSET_SSE2 14 348 #define X86FSET_HTT 15 349 #define X86FSET_ASYSC 16 350 #define X86FSET_NX 17 351 #define X86FSET_SSE3 18 352 #define X86FSET_CX16 19 353 #define X86FSET_CMP 20 354 #define X86FSET_TSCP 21 355 #define X86FSET_MWAIT 22 356 #define X86FSET_SSE4A 23 357 #define X86FSET_CPUID 24 358 #define X86FSET_SSSE3 25 359 #define X86FSET_SSE4_1 26 360 #define X86FSET_SSE4_2 27 361 #define X86FSET_1GPG 28 362 #define X86FSET_CLFSH 29 363 #define X86FSET_64 30 364 #define X86FSET_AES 31 365 #define X86FSET_PCLMULQDQ 32 366 #define X86FSET_XSAVE 33 367 #define X86FSET_AVX 34 368 #define X86FSET_VMX 35 369 #define X86FSET_SVM 36 370 371 /* 372 * flags to patch tsc_read routine. 373 */ 374 #define X86_NO_TSC 0x0 375 #define X86_HAVE_TSCP 0x1 376 #define X86_TSC_MFENCE 0x2 377 #define X86_TSC_LFENCE 0x4 378 379 /* 380 * Intel Deep C-State invariant TSC in leaf 0x80000007. 381 */ 382 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 383 384 /* 385 * Intel Deep C-state always-running local APIC timer 386 */ 387 #define CPUID_CSTATE_ARAT (0x4) 388 389 /* 390 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 391 */ 392 #define CPUID_EPB_SUPPORT (1 << 3) 393 394 /* 395 * Intel TSC deadline timer 396 */ 397 #define CPUID_DEADLINE_TSC (1 << 24) 398 399 /* 400 * x86_type is a legacy concept; this is supplanted 401 * for most purposes by x86_featureset; modern CPUs 402 * should be X86_TYPE_OTHER 403 */ 404 #define X86_TYPE_OTHER 0 405 #define X86_TYPE_486 1 406 #define X86_TYPE_P5 2 407 #define X86_TYPE_P6 3 408 #define X86_TYPE_CYRIX_486 4 409 #define X86_TYPE_CYRIX_6x86L 5 410 #define X86_TYPE_CYRIX_6x86 6 411 #define X86_TYPE_CYRIX_GXm 7 412 #define X86_TYPE_CYRIX_6x86MX 8 413 #define X86_TYPE_CYRIX_MediaGX 9 414 #define X86_TYPE_CYRIX_MII 10 415 #define X86_TYPE_VIA_CYRIX_III 11 416 #define X86_TYPE_P4 12 417 418 /* 419 * x86_vendor allows us to select between 420 * implementation features and helps guide 421 * the interpretation of the cpuid instruction. 422 */ 423 #define X86_VENDOR_Intel 0 424 #define X86_VENDORSTR_Intel "GenuineIntel" 425 426 #define X86_VENDOR_IntelClone 1 427 428 #define X86_VENDOR_AMD 2 429 #define X86_VENDORSTR_AMD "AuthenticAMD" 430 431 #define X86_VENDOR_Cyrix 3 432 #define X86_VENDORSTR_CYRIX "CyrixInstead" 433 434 #define X86_VENDOR_UMC 4 435 #define X86_VENDORSTR_UMC "UMC UMC UMC " 436 437 #define X86_VENDOR_NexGen 5 438 #define X86_VENDORSTR_NexGen "NexGenDriven" 439 440 #define X86_VENDOR_Centaur 6 441 #define X86_VENDORSTR_Centaur "CentaurHauls" 442 443 #define X86_VENDOR_Rise 7 444 #define X86_VENDORSTR_Rise "RiseRiseRise" 445 446 #define X86_VENDOR_SiS 8 447 #define X86_VENDORSTR_SiS "SiS SiS SiS " 448 449 #define X86_VENDOR_TM 9 450 #define X86_VENDORSTR_TM "GenuineTMx86" 451 452 #define X86_VENDOR_NSC 10 453 #define X86_VENDORSTR_NSC "Geode by NSC" 454 455 /* 456 * Vendor string max len + \0 457 */ 458 #define X86_VENDOR_STRLEN 13 459 460 /* 461 * Some vendor/family/model/stepping ranges are commonly grouped under 462 * a single identifying banner by the vendor. The following encode 463 * that "revision" in a uint32_t with the 8 most significant bits 464 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 465 * family, and the remaining 16 typically forming a bitmask of revisions 466 * within that family with more significant bits indicating "later" revisions. 467 */ 468 469 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 470 #define _X86_CHIPREV_VENDOR_SHIFT 24 471 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 472 #define _X86_CHIPREV_FAMILY_SHIFT 16 473 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 474 475 #define _X86_CHIPREV_VENDOR(x) \ 476 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 477 #define _X86_CHIPREV_FAMILY(x) \ 478 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 479 #define _X86_CHIPREV_REV(x) \ 480 ((x) & _X86_CHIPREV_REV_MASK) 481 482 /* True if x matches in vendor and family and if x matches the given rev mask */ 483 #define X86_CHIPREV_MATCH(x, mask) \ 484 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 485 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 486 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 487 488 /* True if x matches in vendor and family, and rev is at least minx */ 489 #define X86_CHIPREV_ATLEAST(x, minx) \ 490 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 491 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 492 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 493 494 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 495 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 496 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 497 498 /* True if x matches in vendor, and family is at least minx */ 499 #define X86_CHIPFAM_ATLEAST(x, minx) \ 500 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 501 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 502 503 /* Revision default */ 504 #define X86_CHIPREV_UNKNOWN 0x0 505 506 /* 507 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 508 * sufficiently different that we will distinguish them; in all other 509 * case we will identify the major revision. 510 */ 511 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 512 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 513 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 514 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 515 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 516 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 517 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 518 519 /* 520 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 521 */ 522 #define X86_CHIPREV_AMD_10_REV_A \ 523 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 524 #define X86_CHIPREV_AMD_10_REV_B \ 525 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 526 #define X86_CHIPREV_AMD_10_REV_C \ 527 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 528 #define X86_CHIPREV_AMD_10_REV_D \ 529 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 530 531 /* 532 * Definitions for AMD Family 0x11. 533 */ 534 #define X86_CHIPREV_AMD_11 \ 535 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0001) 536 537 538 /* 539 * Various socket/package types, extended as the need to distinguish 540 * a new type arises. The top 8 byte identfies the vendor and the 541 * remaining 24 bits describe 24 socket types. 542 */ 543 544 #define _X86_SOCKET_VENDOR_SHIFT 24 545 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 546 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 547 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 548 549 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 550 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 551 552 #define X86_SOCKET_MATCH(s, mask) \ 553 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 554 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 555 556 #define X86_SOCKET_UNKNOWN 0x0 557 /* 558 * AMD socket types 559 */ 560 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 561 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 562 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 563 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 564 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 565 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 566 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 567 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 568 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 569 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 570 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 571 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 572 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 573 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 574 575 /* 576 * xgetbv/xsetbv support 577 */ 578 579 #define XFEATURE_ENABLED_MASK 0x0 580 /* 581 * XFEATURE_ENABLED_MASK values (eax) 582 */ 583 #define XFEATURE_LEGACY_FP 0x1 584 #define XFEATURE_SSE 0x2 585 #define XFEATURE_AVX 0x4 586 #define XFEATURE_MAX XFEATURE_AVX 587 #define XFEATURE_FP_ALL (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX) 588 589 #if !defined(_ASM) 590 591 #if defined(_KERNEL) || defined(_KMEMUSER) 592 593 #define NUM_X86_FEATURES 37 594 extern uchar_t x86_featureset[]; 595 596 extern void free_x86_featureset(void *featureset); 597 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 598 extern void add_x86_feature(void *featureset, uint_t feature); 599 extern void remove_x86_feature(void *featureset, uint_t feature); 600 extern boolean_t compare_x86_featureset(void *setA, void *setB); 601 extern void print_x86_featureset(void *featureset); 602 603 604 extern uint_t x86_type; 605 extern uint_t x86_vendor; 606 extern uint_t x86_clflush_size; 607 608 extern uint_t pentiumpro_bug4046376; 609 extern uint_t pentiumpro_bug4064495; 610 611 extern uint_t enable486; 612 613 extern const char CyrixInstead[]; 614 615 #endif 616 617 #if defined(_KERNEL) 618 619 /* 620 * This structure is used to pass arguments and get return values back 621 * from the CPUID instruction in __cpuid_insn() routine. 622 */ 623 struct cpuid_regs { 624 uint32_t cp_eax; 625 uint32_t cp_ebx; 626 uint32_t cp_ecx; 627 uint32_t cp_edx; 628 }; 629 630 /* 631 * Utility functions to get/set extended control registers (XCR) 632 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 633 */ 634 extern uint64_t get_xcr(uint_t); 635 extern void set_xcr(uint_t, uint64_t); 636 637 extern uint64_t rdmsr(uint_t); 638 extern void wrmsr(uint_t, const uint64_t); 639 extern uint64_t xrdmsr(uint_t); 640 extern void xwrmsr(uint_t, const uint64_t); 641 extern int checked_rdmsr(uint_t, uint64_t *); 642 extern int checked_wrmsr(uint_t, uint64_t); 643 644 extern void invalidate_cache(void); 645 extern ulong_t getcr4(void); 646 extern void setcr4(ulong_t); 647 648 extern void mtrr_sync(void); 649 650 extern void cpu_fast_syscall_enable(void *); 651 extern void cpu_fast_syscall_disable(void *); 652 653 struct cpu; 654 655 extern int cpuid_checkpass(struct cpu *, int); 656 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 657 extern uint32_t __cpuid_insn(struct cpuid_regs *); 658 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 659 extern int cpuid_getidstr(struct cpu *, char *, size_t); 660 extern const char *cpuid_getvendorstr(struct cpu *); 661 extern uint_t cpuid_getvendor(struct cpu *); 662 extern uint_t cpuid_getfamily(struct cpu *); 663 extern uint_t cpuid_getmodel(struct cpu *); 664 extern uint_t cpuid_getstep(struct cpu *); 665 extern uint_t cpuid_getsig(struct cpu *); 666 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 667 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 668 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 669 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 670 extern int cpuid_get_chipid(struct cpu *); 671 extern id_t cpuid_get_coreid(struct cpu *); 672 extern int cpuid_get_pkgcoreid(struct cpu *); 673 extern int cpuid_get_clogid(struct cpu *); 674 extern int cpuid_get_cacheid(struct cpu *); 675 extern uint32_t cpuid_get_apicid(struct cpu *); 676 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 677 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 678 extern int cpuid_is_cmt(struct cpu *); 679 extern int cpuid_syscall32_insn(struct cpu *); 680 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 681 682 extern uint32_t cpuid_getchiprev(struct cpu *); 683 extern const char *cpuid_getchiprevstr(struct cpu *); 684 extern uint32_t cpuid_getsockettype(struct cpu *); 685 extern const char *cpuid_getsocketstr(struct cpu *); 686 687 extern int cpuid_have_cr8access(struct cpu *); 688 689 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 690 691 struct cpuid_info; 692 693 extern void setx86isalist(void); 694 extern void cpuid_alloc_space(struct cpu *); 695 extern void cpuid_free_space(struct cpu *); 696 extern void cpuid_pass1(struct cpu *, uchar_t *); 697 extern void cpuid_pass2(struct cpu *); 698 extern void cpuid_pass3(struct cpu *); 699 extern uint_t cpuid_pass4(struct cpu *); 700 extern void cpuid_set_cpu_properties(void *, processorid_t, 701 struct cpuid_info *); 702 703 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 704 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 705 706 #if !defined(__xpv) 707 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 708 extern void cpuid_mwait_free(struct cpu *); 709 extern int cpuid_deep_cstates_supported(void); 710 extern int cpuid_arat_supported(void); 711 extern int cpuid_iepb_supported(struct cpu *); 712 extern int cpuid_deadline_tsc_supported(void); 713 extern int vmware_platform(void); 714 #endif 715 716 struct cpu_ucode_info; 717 718 extern void ucode_alloc_space(struct cpu *); 719 extern void ucode_free_space(struct cpu *); 720 extern void ucode_check(struct cpu *); 721 extern void ucode_cleanup(); 722 723 #if !defined(__xpv) 724 extern char _tsc_mfence_start; 725 extern char _tsc_mfence_end; 726 extern char _tscp_start; 727 extern char _tscp_end; 728 extern char _no_rdtsc_start; 729 extern char _no_rdtsc_end; 730 extern char _tsc_lfence_start; 731 extern char _tsc_lfence_end; 732 #endif 733 734 #if !defined(__xpv) 735 extern char bcopy_patch_start; 736 extern char bcopy_patch_end; 737 extern char bcopy_ck_size; 738 #endif 739 740 extern void post_startup_cpu_fixups(void); 741 742 extern uint_t workaround_errata(struct cpu *); 743 744 #if defined(OPTERON_ERRATUM_93) 745 extern int opteron_erratum_93; 746 #endif 747 748 #if defined(OPTERON_ERRATUM_91) 749 extern int opteron_erratum_91; 750 #endif 751 752 #if defined(OPTERON_ERRATUM_100) 753 extern int opteron_erratum_100; 754 #endif 755 756 #if defined(OPTERON_ERRATUM_121) 757 extern int opteron_erratum_121; 758 #endif 759 760 #if defined(OPTERON_WORKAROUND_6323525) 761 extern int opteron_workaround_6323525; 762 extern void patch_workaround_6323525(void); 763 #endif 764 765 extern int get_hwenv(void); 766 extern int is_controldom(void); 767 768 extern void xsave_setup_msr(struct cpu *); 769 770 /* 771 * Defined hardware environments 772 */ 773 #define HW_NATIVE 0x00 /* Running on bare metal */ 774 #define HW_XEN_PV 0x01 /* Running on Xen Hypervisor paravirutualized */ 775 #define HW_XEN_HVM 0x02 /* Running on Xen hypervisor HVM */ 776 #define HW_VMWARE 0x03 /* Running on VMware hypervisor */ 777 778 #endif /* _KERNEL */ 779 780 #endif 781 782 #ifdef __cplusplus 783 } 784 #endif 785 786 #endif /* _SYS_X86_ARCHEXT_H */ 787