xref: /illumos-gate/usr/src/uts/intel/sys/x86_archext.h (revision f21ed392afb2ea96924762977a86c2b1c42373f8)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 /*
26  * Copyright (c) 2009, Intel Corporation.
27  * All rights reserved.
28  */
29 
30 #ifndef _SYS_X86_ARCHEXT_H
31 #define	_SYS_X86_ARCHEXT_H
32 
33 #if !defined(_ASM)
34 #include <sys/regset.h>
35 #include <sys/processor.h>
36 #include <vm/seg_enum.h>
37 #include <vm/page.h>
38 #endif	/* _ASM */
39 
40 #ifdef	__cplusplus
41 extern "C" {
42 #endif
43 
44 /*
45  * cpuid instruction feature flags in %edx (standard function 1)
46  */
47 
48 #define	CPUID_INTC_EDX_FPU	0x00000001	/* x87 fpu present */
49 #define	CPUID_INTC_EDX_VME	0x00000002	/* virtual-8086 extension */
50 #define	CPUID_INTC_EDX_DE	0x00000004	/* debugging extensions */
51 #define	CPUID_INTC_EDX_PSE	0x00000008	/* page size extension */
52 #define	CPUID_INTC_EDX_TSC	0x00000010	/* time stamp counter */
53 #define	CPUID_INTC_EDX_MSR	0x00000020	/* rdmsr and wrmsr */
54 #define	CPUID_INTC_EDX_PAE	0x00000040	/* physical addr extension */
55 #define	CPUID_INTC_EDX_MCE	0x00000080	/* machine check exception */
56 #define	CPUID_INTC_EDX_CX8	0x00000100	/* cmpxchg8b instruction */
57 #define	CPUID_INTC_EDX_APIC	0x00000200	/* local APIC */
58 						/* 0x400 - reserved */
59 #define	CPUID_INTC_EDX_SEP	0x00000800	/* sysenter and sysexit */
60 #define	CPUID_INTC_EDX_MTRR	0x00001000	/* memory type range reg */
61 #define	CPUID_INTC_EDX_PGE	0x00002000	/* page global enable */
62 #define	CPUID_INTC_EDX_MCA	0x00004000	/* machine check arch */
63 #define	CPUID_INTC_EDX_CMOV	0x00008000	/* conditional move insns */
64 #define	CPUID_INTC_EDX_PAT	0x00010000	/* page attribute table */
65 #define	CPUID_INTC_EDX_PSE36	0x00020000	/* 36-bit pagesize extension */
66 #define	CPUID_INTC_EDX_PSN	0x00040000	/* processor serial number */
67 #define	CPUID_INTC_EDX_CLFSH	0x00080000	/* clflush instruction */
68 						/* 0x100000 - reserved */
69 #define	CPUID_INTC_EDX_DS	0x00200000	/* debug store exists */
70 #define	CPUID_INTC_EDX_ACPI	0x00400000	/* monitoring + clock ctrl */
71 #define	CPUID_INTC_EDX_MMX	0x00800000	/* MMX instructions */
72 #define	CPUID_INTC_EDX_FXSR	0x01000000	/* fxsave and fxrstor */
73 #define	CPUID_INTC_EDX_SSE	0x02000000	/* streaming SIMD extensions */
74 #define	CPUID_INTC_EDX_SSE2	0x04000000	/* SSE extensions */
75 #define	CPUID_INTC_EDX_SS	0x08000000	/* self-snoop */
76 #define	CPUID_INTC_EDX_HTT	0x10000000	/* Hyper Thread Technology */
77 #define	CPUID_INTC_EDX_TM	0x20000000	/* thermal monitoring */
78 #define	CPUID_INTC_EDX_IA64	0x40000000	/* Itanium emulating IA32 */
79 #define	CPUID_INTC_EDX_PBE	0x80000000	/* Pending Break Enable */
80 
81 #define	FMT_CPUID_INTC_EDX					\
82 	"\20"							\
83 	"\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr"	\
84 	"\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat"	\
85 	"\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8"		\
86 	"\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
87 
88 /*
89  * cpuid instruction feature flags in %ecx (standard function 1)
90  */
91 
92 #define	CPUID_INTC_ECX_SSE3	0x00000001	/* Yet more SSE extensions */
93 #define	CPUID_INTC_ECX_PCLMULQDQ 0x00000002 	/* PCLMULQDQ insn */
94 						/* 0x00000004 - reserved */
95 #define	CPUID_INTC_ECX_MON	0x00000008	/* MONITOR/MWAIT */
96 #define	CPUID_INTC_ECX_DSCPL	0x00000010	/* CPL-qualified debug store */
97 #define	CPUID_INTC_ECX_VMX	0x00000020	/* Hardware VM extensions */
98 #define	CPUID_INTC_ECX_SMX	0x00000040	/* Secure mode extensions */
99 #define	CPUID_INTC_ECX_EST	0x00000080	/* enhanced SpeedStep */
100 #define	CPUID_INTC_ECX_TM2	0x00000100	/* thermal monitoring */
101 #define	CPUID_INTC_ECX_SSSE3	0x00000200	/* Supplemental SSE3 insns */
102 #define	CPUID_INTC_ECX_CID	0x00000400	/* L1 context ID */
103 						/* 0x00000800 - reserved */
104 						/* 0x00001000 - reserved */
105 #define	CPUID_INTC_ECX_CX16	0x00002000	/* cmpxchg16 */
106 #define	CPUID_INTC_ECX_ETPRD	0x00004000	/* extended task pri messages */
107 						/* 0x00008000 - reserved */
108 						/* 0x00010000 - reserved */
109 						/* 0x00020000 - reserved */
110 #define	CPUID_INTC_ECX_DCA	0x00040000	/* direct cache access */
111 #define	CPUID_INTC_ECX_SSE4_1	0x00080000	/* SSE4.1 insns */
112 #define	CPUID_INTC_ECX_SSE4_2	0x00100000	/* SSE4.2 insns */
113 #define	CPUID_INTC_ECX_MOVBE	0x00400000	/* MOVBE insn */
114 #define	CPUID_INTC_ECX_POPCNT	0x00800000	/* POPCNT insn */
115 #define	CPUID_INTC_ECX_AES	0x02000000	/* AES insns */
116 
117 #define	FMT_CPUID_INTC_ECX					\
118 	"\20"							\
119 	"\32aes"						\
120 	"\30popcnt\27movbe\25sse4.2\24sse4.1\23dca"		\
121 	"\20\17etprd\16cx16\13cid\12ssse3\11tm2"		\
122 	"\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
123 
124 /*
125  * cpuid instruction feature flags in %edx (extended function 0x80000001)
126  */
127 
128 #define	CPUID_AMD_EDX_FPU	0x00000001	/* x87 fpu present */
129 #define	CPUID_AMD_EDX_VME	0x00000002	/* virtual-8086 extension */
130 #define	CPUID_AMD_EDX_DE	0x00000004	/* debugging extensions */
131 #define	CPUID_AMD_EDX_PSE	0x00000008	/* page size extensions */
132 #define	CPUID_AMD_EDX_TSC	0x00000010	/* time stamp counter */
133 #define	CPUID_AMD_EDX_MSR	0x00000020	/* rdmsr and wrmsr */
134 #define	CPUID_AMD_EDX_PAE	0x00000040	/* physical addr extension */
135 #define	CPUID_AMD_EDX_MCE	0x00000080	/* machine check exception */
136 #define	CPUID_AMD_EDX_CX8	0x00000100	/* cmpxchg8b instruction */
137 #define	CPUID_AMD_EDX_APIC	0x00000200	/* local APIC */
138 						/* 0x00000400 - sysc on K6m6 */
139 #define	CPUID_AMD_EDX_SYSC	0x00000800	/* AMD: syscall and sysret */
140 #define	CPUID_AMD_EDX_MTRR	0x00001000	/* memory type and range reg */
141 #define	CPUID_AMD_EDX_PGE	0x00002000	/* page global enable */
142 #define	CPUID_AMD_EDX_MCA	0x00004000	/* machine check arch */
143 #define	CPUID_AMD_EDX_CMOV	0x00008000	/* conditional move insns */
144 #define	CPUID_AMD_EDX_PAT	0x00010000	/* K7: page attribute table */
145 #define	CPUID_AMD_EDX_FCMOV	0x00010000	/* FCMOVcc etc. */
146 #define	CPUID_AMD_EDX_PSE36	0x00020000	/* 36-bit pagesize extension */
147 				/* 0x00040000 - reserved */
148 				/* 0x00080000 - reserved */
149 #define	CPUID_AMD_EDX_NX	0x00100000	/* AMD: no-execute page prot */
150 				/* 0x00200000 - reserved */
151 #define	CPUID_AMD_EDX_MMXamd	0x00400000	/* AMD: MMX extensions */
152 #define	CPUID_AMD_EDX_MMX	0x00800000	/* MMX instructions */
153 #define	CPUID_AMD_EDX_FXSR	0x01000000	/* fxsave and fxrstor */
154 #define	CPUID_AMD_EDX_FFXSR	0x02000000	/* fast fxsave/fxrstor */
155 #define	CPUID_AMD_EDX_1GPG	0x04000000	/* 1GB page */
156 #define	CPUID_AMD_EDX_TSCP	0x08000000	/* rdtscp instruction */
157 				/* 0x10000000 - reserved */
158 #define	CPUID_AMD_EDX_LM	0x20000000	/* AMD: long mode */
159 #define	CPUID_AMD_EDX_3DNowx	0x40000000	/* AMD: extensions to 3DNow! */
160 #define	CPUID_AMD_EDX_3DNow	0x80000000	/* AMD: 3DNow! instructions */
161 
162 #define	FMT_CPUID_AMD_EDX					\
163 	"\20"							\
164 	"\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr"		\
165 	"\30mmx\27mmxext\25nx\22pse\21pat"			\
166 	"\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8"	\
167 	"\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
168 
169 #define	CPUID_AMD_ECX_AHF64	0x00000001	/* LAHF and SAHF in long mode */
170 #define	CPUID_AMD_ECX_CMP_LGCY	0x00000002	/* AMD: multicore chip */
171 #define	CPUID_AMD_ECX_SVM	0x00000004	/* AMD: secure VM */
172 #define	CPUID_AMD_ECX_EAS	0x00000008	/* extended apic space */
173 #define	CPUID_AMD_ECX_CR8D	0x00000010	/* AMD: 32-bit mov %cr8 */
174 #define	CPUID_AMD_ECX_LZCNT	0x00000020	/* AMD: LZCNT insn */
175 #define	CPUID_AMD_ECX_SSE4A	0x00000040	/* AMD: SSE4A insns */
176 #define	CPUID_AMD_ECX_MAS	0x00000080	/* AMD: MisAlignSse mnode */
177 #define	CPUID_AMD_ECX_3DNP	0x00000100	/* AMD: 3DNowPrefectch */
178 #define	CPUID_AMD_ECX_OSVW	0x00000200	/* AMD: OSVW */
179 #define	CPUID_AMD_ECX_IBS	0x00000400	/* AMD: IBS */
180 #define	CPUID_AMD_ECX_SSE5	0x00000800	/* AMD: SSE5 */
181 #define	CPUID_AMD_ECX_SKINIT	0x00001000	/* AMD: SKINIT */
182 #define	CPUID_AMD_ECX_WDT	0x00002000	/* AMD: WDT */
183 
184 #define	FMT_CPUID_AMD_ECX					\
185 	"\20"							\
186 	"\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas"	\
187 	"\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
188 
189 /*
190  * Intel now seems to have claimed part of the "extended" function
191  * space that we previously for non-Intel implementors to use.
192  * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
193  * is available in long mode i.e. what AMD indicate using bit 0.
194  * On the other hand, everything else is labelled as reserved.
195  */
196 #define	CPUID_INTC_ECX_AHF64	0x00100000	/* LAHF and SAHF in long mode */
197 
198 
199 #define	P5_MCHADDR	0x0
200 #define	P5_CESR		0x11
201 #define	P5_CTR0		0x12
202 #define	P5_CTR1		0x13
203 
204 #define	K5_MCHADDR	0x0
205 #define	K5_MCHTYPE	0x01
206 #define	K5_TSC		0x10
207 #define	K5_TR12		0x12
208 
209 #define	REG_PAT		0x277
210 
211 #define	REG_MC0_CTL		0x400
212 #define	REG_MC5_MISC		0x417
213 #define	REG_PERFCTR0		0xc1
214 #define	REG_PERFCTR1		0xc2
215 
216 #define	REG_PERFEVNT0		0x186
217 #define	REG_PERFEVNT1		0x187
218 
219 #define	REG_TSC			0x10	/* timestamp counter */
220 #define	REG_APIC_BASE_MSR	0x1b
221 #define	REG_X2APIC_BASE_MSR	0x800	/* The MSR address offset of x2APIC */
222 
223 #if !defined(__xpv)
224 /*
225  * AMD C1E
226  */
227 #define	MSR_AMD_INT_PENDING_CMP_HALT	0xC0010055
228 #define	AMD_ACTONCMPHALT_SHIFT	27
229 #define	AMD_ACTONCMPHALT_MASK	3
230 #endif
231 
232 #define	MSR_DEBUGCTL		0x1d9
233 
234 #define	DEBUGCTL_LBR		0x01
235 #define	DEBUGCTL_BTF		0x02
236 
237 /* Intel P6, AMD */
238 #define	MSR_LBR_FROM		0x1db
239 #define	MSR_LBR_TO		0x1dc
240 #define	MSR_LEX_FROM		0x1dd
241 #define	MSR_LEX_TO		0x1de
242 
243 /* Intel P4 (pre-Prescott, non P4 M) */
244 #define	MSR_P4_LBSTK_TOS	0x1da
245 #define	MSR_P4_LBSTK_0		0x1db
246 #define	MSR_P4_LBSTK_1		0x1dc
247 #define	MSR_P4_LBSTK_2		0x1dd
248 #define	MSR_P4_LBSTK_3		0x1de
249 
250 /* Intel Pentium M */
251 #define	MSR_P6M_LBSTK_TOS	0x1c9
252 #define	MSR_P6M_LBSTK_0		0x040
253 #define	MSR_P6M_LBSTK_1		0x041
254 #define	MSR_P6M_LBSTK_2		0x042
255 #define	MSR_P6M_LBSTK_3		0x043
256 #define	MSR_P6M_LBSTK_4		0x044
257 #define	MSR_P6M_LBSTK_5		0x045
258 #define	MSR_P6M_LBSTK_6		0x046
259 #define	MSR_P6M_LBSTK_7		0x047
260 
261 /* Intel P4 (Prescott) */
262 #define	MSR_PRP4_LBSTK_TOS	0x1da
263 #define	MSR_PRP4_LBSTK_FROM_0	0x680
264 #define	MSR_PRP4_LBSTK_FROM_1	0x681
265 #define	MSR_PRP4_LBSTK_FROM_2	0x682
266 #define	MSR_PRP4_LBSTK_FROM_3	0x683
267 #define	MSR_PRP4_LBSTK_FROM_4	0x684
268 #define	MSR_PRP4_LBSTK_FROM_5	0x685
269 #define	MSR_PRP4_LBSTK_FROM_6	0x686
270 #define	MSR_PRP4_LBSTK_FROM_7	0x687
271 #define	MSR_PRP4_LBSTK_FROM_8 	0x688
272 #define	MSR_PRP4_LBSTK_FROM_9	0x689
273 #define	MSR_PRP4_LBSTK_FROM_10	0x68a
274 #define	MSR_PRP4_LBSTK_FROM_11 	0x68b
275 #define	MSR_PRP4_LBSTK_FROM_12	0x68c
276 #define	MSR_PRP4_LBSTK_FROM_13	0x68d
277 #define	MSR_PRP4_LBSTK_FROM_14	0x68e
278 #define	MSR_PRP4_LBSTK_FROM_15	0x68f
279 #define	MSR_PRP4_LBSTK_TO_0	0x6c0
280 #define	MSR_PRP4_LBSTK_TO_1	0x6c1
281 #define	MSR_PRP4_LBSTK_TO_2	0x6c2
282 #define	MSR_PRP4_LBSTK_TO_3	0x6c3
283 #define	MSR_PRP4_LBSTK_TO_4	0x6c4
284 #define	MSR_PRP4_LBSTK_TO_5	0x6c5
285 #define	MSR_PRP4_LBSTK_TO_6	0x6c6
286 #define	MSR_PRP4_LBSTK_TO_7	0x6c7
287 #define	MSR_PRP4_LBSTK_TO_8	0x6c8
288 #define	MSR_PRP4_LBSTK_TO_9 	0x6c9
289 #define	MSR_PRP4_LBSTK_TO_10	0x6ca
290 #define	MSR_PRP4_LBSTK_TO_11	0x6cb
291 #define	MSR_PRP4_LBSTK_TO_12	0x6cc
292 #define	MSR_PRP4_LBSTK_TO_13	0x6cd
293 #define	MSR_PRP4_LBSTK_TO_14	0x6ce
294 #define	MSR_PRP4_LBSTK_TO_15	0x6cf
295 
296 #define	MCI_CTL_VALUE		0xffffffff
297 
298 #define	MTRR_TYPE_UC		0
299 #define	MTRR_TYPE_WC		1
300 #define	MTRR_TYPE_WT		4
301 #define	MTRR_TYPE_WP		5
302 #define	MTRR_TYPE_WB		6
303 #define	MTRR_TYPE_UC_		7
304 
305 /*
306  * For Solaris we set up the page attritubute table in the following way:
307  * PAT0	Write-Back
308  * PAT1	Write-Through
309  * PAT2	Unchacheable-
310  * PAT3	Uncacheable
311  * PAT4 Write-Back
312  * PAT5	Write-Through
313  * PAT6	Write-Combine
314  * PAT7 Uncacheable
315  * The only difference from h/w default is entry 6.
316  */
317 #define	PAT_DEFAULT_ATTRIBUTE			\
318 	((uint64_t)MTRR_TYPE_WB |		\
319 	((uint64_t)MTRR_TYPE_WT << 8) |		\
320 	((uint64_t)MTRR_TYPE_UC_ << 16) |	\
321 	((uint64_t)MTRR_TYPE_UC << 24) |	\
322 	((uint64_t)MTRR_TYPE_WB << 32) |	\
323 	((uint64_t)MTRR_TYPE_WT << 40) |	\
324 	((uint64_t)MTRR_TYPE_WC << 48) |	\
325 	((uint64_t)MTRR_TYPE_UC << 56))
326 
327 #define	X86_LARGEPAGE	0x00000001
328 #define	X86_TSC		0x00000002
329 #define	X86_MSR		0x00000004
330 #define	X86_MTRR	0x00000008
331 #define	X86_PGE		0x00000010
332 #define	X86_DE		0x00000020
333 #define	X86_CMOV	0x00000040
334 #define	X86_MMX 	0x00000080
335 #define	X86_MCA		0x00000100
336 #define	X86_PAE		0x00000200
337 #define	X86_CX8		0x00000400
338 #define	X86_PAT		0x00000800
339 #define	X86_SEP		0x00001000
340 #define	X86_SSE		0x00002000
341 #define	X86_SSE2	0x00004000
342 #define	X86_HTT		0x00008000
343 #define	X86_ASYSC	0x00010000
344 #define	X86_NX		0x00020000
345 #define	X86_SSE3	0x00040000
346 #define	X86_CX16	0x00080000
347 #define	X86_CMP		0x00100000
348 #define	X86_TSCP	0x00200000
349 #define	X86_MWAIT	0x00400000
350 #define	X86_SSE4A	0x00800000
351 #define	X86_CPUID	0x01000000
352 #define	X86_SSSE3	0x02000000
353 #define	X86_SSE4_1	0x04000000
354 #define	X86_SSE4_2	0x08000000
355 #define	X86_1GPG	0x10000000
356 #define	X86_CLFSH	0x20000000
357 #define	X86_64		0x40000000
358 #define	X86_AES		0x80000000
359 
360 #define	FMT_X86_FEATURE						\
361 	"\20"							\
362 	"\40aes\34sse4_2\33sse4_1\32ssse3\31cpuid"		\
363 	"\30sse4a\27mwait\26tscp\25cmp\24cx16\23sse3\22nx\21asysc"\
364 	"\20htt\17sse2\16sse\15sep\14pat\13cx8\12pae\11mca"	\
365 	"\10mmx\7cmov\6de\5pge\4mtrr\3msr\2tsc\1lgpg"
366 
367 /*
368  * flags to patch tsc_read routine.
369  */
370 #define	X86_NO_TSC		0x0
371 #define	X86_HAVE_TSCP		0x1
372 #define	X86_TSC_MFENCE		0x2
373 #define	X86_TSC_LFENCE		0x4
374 
375 /*
376  * Intel Deep C-State invariant TSC in leaf 0x80000007.
377  */
378 #define	CPUID_TSC_CSTATE_INVARIANCE	(0x100)
379 
380 /*
381  * Intel Deep C-state always-running local APIC timer
382  */
383 #define	CPUID_CSTATE_ARAT	(0x4)
384 
385 /*
386  * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
387  */
388 #define	CPUID_EPB_SUPPORT	(1 << 3)
389 
390 /*
391  * x86_type is a legacy concept; this is supplanted
392  * for most purposes by x86_feature; modern CPUs
393  * should be X86_TYPE_OTHER
394  */
395 #define	X86_TYPE_OTHER		0
396 #define	X86_TYPE_486		1
397 #define	X86_TYPE_P5		2
398 #define	X86_TYPE_P6		3
399 #define	X86_TYPE_CYRIX_486	4
400 #define	X86_TYPE_CYRIX_6x86L	5
401 #define	X86_TYPE_CYRIX_6x86	6
402 #define	X86_TYPE_CYRIX_GXm	7
403 #define	X86_TYPE_CYRIX_6x86MX	8
404 #define	X86_TYPE_CYRIX_MediaGX	9
405 #define	X86_TYPE_CYRIX_MII	10
406 #define	X86_TYPE_VIA_CYRIX_III	11
407 #define	X86_TYPE_P4		12
408 
409 /*
410  * x86_vendor allows us to select between
411  * implementation features and helps guide
412  * the interpretation of the cpuid instruction.
413  */
414 #define	X86_VENDOR_Intel	0
415 #define	X86_VENDORSTR_Intel	"GenuineIntel"
416 
417 #define	X86_VENDOR_IntelClone	1
418 
419 #define	X86_VENDOR_AMD		2
420 #define	X86_VENDORSTR_AMD	"AuthenticAMD"
421 
422 #define	X86_VENDOR_Cyrix	3
423 #define	X86_VENDORSTR_CYRIX	"CyrixInstead"
424 
425 #define	X86_VENDOR_UMC		4
426 #define	X86_VENDORSTR_UMC	"UMC UMC UMC "
427 
428 #define	X86_VENDOR_NexGen	5
429 #define	X86_VENDORSTR_NexGen	"NexGenDriven"
430 
431 #define	X86_VENDOR_Centaur	6
432 #define	X86_VENDORSTR_Centaur	"CentaurHauls"
433 
434 #define	X86_VENDOR_Rise		7
435 #define	X86_VENDORSTR_Rise	"RiseRiseRise"
436 
437 #define	X86_VENDOR_SiS		8
438 #define	X86_VENDORSTR_SiS	"SiS SiS SiS "
439 
440 #define	X86_VENDOR_TM		9
441 #define	X86_VENDORSTR_TM	"GenuineTMx86"
442 
443 #define	X86_VENDOR_NSC		10
444 #define	X86_VENDORSTR_NSC	"Geode by NSC"
445 
446 /*
447  * Vendor string max len + \0
448  */
449 #define	X86_VENDOR_STRLEN	13
450 
451 /*
452  * Some vendor/family/model/stepping ranges are commonly grouped under
453  * a single identifying banner by the vendor.  The following encode
454  * that "revision" in a uint32_t with the 8 most significant bits
455  * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
456  * family, and the remaining 16 typically forming a bitmask of revisions
457  * within that family with more significant bits indicating "later" revisions.
458  */
459 
460 #define	_X86_CHIPREV_VENDOR_MASK	0xff000000u
461 #define	_X86_CHIPREV_VENDOR_SHIFT	24
462 #define	_X86_CHIPREV_FAMILY_MASK	0x00ff0000u
463 #define	_X86_CHIPREV_FAMILY_SHIFT	16
464 #define	_X86_CHIPREV_REV_MASK		0x0000ffffu
465 
466 #define	_X86_CHIPREV_VENDOR(x) \
467 	(((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
468 #define	_X86_CHIPREV_FAMILY(x) \
469 	(((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
470 #define	_X86_CHIPREV_REV(x) \
471 	((x) & _X86_CHIPREV_REV_MASK)
472 
473 /* True if x matches in vendor and family and if x matches the given rev mask */
474 #define	X86_CHIPREV_MATCH(x, mask) \
475 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
476 	_X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
477 	((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
478 
479 /* True if x matches in vendor and family and rev is at least minx */
480 #define	X86_CHIPREV_ATLEAST(x, minx) \
481 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
482 	_X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
483 	_X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
484 
485 #define	_X86_CHIPREV_MKREV(vendor, family, rev) \
486 	((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
487 	(family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
488 
489 /* Revision default */
490 #define	X86_CHIPREV_UNKNOWN	0x0
491 
492 /*
493  * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
494  * sufficiently different that we will distinguish them; in all other
495  * case we will identify the major revision.
496  */
497 #define	X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
498 #define	X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
499 #define	X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
500 #define	X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
501 #define	X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
502 #define	X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
503 #define	X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
504 
505 /*
506  * Definitions for AMD Family 0x10.  Rev A was Engineering Samples only.
507  */
508 #define	X86_CHIPREV_AMD_10_REV_A \
509 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
510 #define	X86_CHIPREV_AMD_10_REV_B \
511 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
512 #define	X86_CHIPREV_AMD_10_REV_C \
513 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
514 #define	X86_CHIPREV_AMD_10_REV_D \
515 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
516 
517 /*
518  * Definitions for AMD Family 0x11.
519  */
520 #define	X86_CHIPREV_AMD_11 \
521 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0001)
522 
523 
524 /*
525  * Various socket/package types, extended as the need to distinguish
526  * a new type arises.  The top 8 byte identfies the vendor and the
527  * remaining 24 bits describe 24 socket types.
528  */
529 
530 #define	_X86_SOCKET_VENDOR_SHIFT	24
531 #define	_X86_SOCKET_VENDOR(x)	((x) >> _X86_SOCKET_VENDOR_SHIFT)
532 #define	_X86_SOCKET_TYPE_MASK	0x00ffffff
533 #define	_X86_SOCKET_TYPE(x)		((x) & _X86_SOCKET_TYPE_MASK)
534 
535 #define	_X86_SOCKET_MKVAL(vendor, bitval) \
536 	((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
537 
538 #define	X86_SOCKET_MATCH(s, mask) \
539 	(_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
540 	(_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
541 
542 #define	X86_SOCKET_UNKNOWN 0x0
543 	/*
544 	 * AMD socket types
545 	 */
546 #define	X86_SOCKET_754		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
547 #define	X86_SOCKET_939		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
548 #define	X86_SOCKET_940		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
549 #define	X86_SOCKET_S1g1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
550 #define	X86_SOCKET_AM2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
551 #define	X86_SOCKET_F1207	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
552 #define	X86_SOCKET_S1g2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
553 #define	X86_SOCKET_S1g3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
554 #define	X86_SOCKET_AM		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
555 #define	X86_SOCKET_AM2R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
556 #define	X86_SOCKET_AM3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
557 #define	X86_SOCKET_G34		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
558 #define	X86_SOCKET_ASB2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
559 #define	X86_SOCKET_C32		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
560 
561 #if !defined(_ASM)
562 
563 #if defined(_KERNEL) || defined(_KMEMUSER)
564 
565 extern uint_t x86_feature;
566 extern uint_t x86_type;
567 extern uint_t x86_vendor;
568 extern uint_t x86_clflush_size;
569 
570 extern uint_t pentiumpro_bug4046376;
571 extern uint_t pentiumpro_bug4064495;
572 
573 extern uint_t enable486;
574 
575 extern const char CyrixInstead[];
576 
577 #endif
578 
579 #if defined(_KERNEL)
580 
581 /*
582  * This structure is used to pass arguments and get return values back
583  * from the CPUID instruction in __cpuid_insn() routine.
584  */
585 struct cpuid_regs {
586 	uint32_t	cp_eax;
587 	uint32_t	cp_ebx;
588 	uint32_t	cp_ecx;
589 	uint32_t	cp_edx;
590 };
591 
592 extern uint64_t rdmsr(uint_t);
593 extern void wrmsr(uint_t, const uint64_t);
594 extern uint64_t xrdmsr(uint_t);
595 extern void xwrmsr(uint_t, const uint64_t);
596 extern int checked_rdmsr(uint_t, uint64_t *);
597 extern int checked_wrmsr(uint_t, uint64_t);
598 
599 extern void invalidate_cache(void);
600 extern ulong_t getcr4(void);
601 extern void setcr4(ulong_t);
602 
603 extern void mtrr_sync(void);
604 
605 extern void cpu_fast_syscall_enable(void *);
606 extern void cpu_fast_syscall_disable(void *);
607 
608 struct cpu;
609 
610 extern int cpuid_checkpass(struct cpu *, int);
611 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
612 extern uint32_t __cpuid_insn(struct cpuid_regs *);
613 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
614 extern int cpuid_getidstr(struct cpu *, char *, size_t);
615 extern const char *cpuid_getvendorstr(struct cpu *);
616 extern uint_t cpuid_getvendor(struct cpu *);
617 extern uint_t cpuid_getfamily(struct cpu *);
618 extern uint_t cpuid_getmodel(struct cpu *);
619 extern uint_t cpuid_getstep(struct cpu *);
620 extern uint_t cpuid_getsig(struct cpu *);
621 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
622 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
623 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
624 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
625 extern int cpuid_get_chipid(struct cpu *);
626 extern id_t cpuid_get_coreid(struct cpu *);
627 extern int cpuid_get_pkgcoreid(struct cpu *);
628 extern int cpuid_get_clogid(struct cpu *);
629 extern uint32_t cpuid_get_apicid(struct cpu *);
630 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
631 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
632 extern int cpuid_is_cmt(struct cpu *);
633 extern int cpuid_syscall32_insn(struct cpu *);
634 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
635 
636 extern uint32_t cpuid_getchiprev(struct cpu *);
637 extern const char *cpuid_getchiprevstr(struct cpu *);
638 extern uint32_t cpuid_getsockettype(struct cpu *);
639 extern const char *cpuid_getsocketstr(struct cpu *);
640 
641 extern int cpuid_have_cr8access(struct cpu *);
642 
643 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
644 
645 struct cpuid_info;
646 
647 extern void setx86isalist(void);
648 extern void cpuid_alloc_space(struct cpu *);
649 extern void cpuid_free_space(struct cpu *);
650 extern uint_t cpuid_pass1(struct cpu *);
651 extern void cpuid_pass2(struct cpu *);
652 extern void cpuid_pass3(struct cpu *);
653 extern uint_t cpuid_pass4(struct cpu *);
654 extern void cpuid_set_cpu_properties(void *, processorid_t,
655     struct cpuid_info *);
656 
657 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
658 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
659 
660 #if !defined(__xpv)
661 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
662 extern void cpuid_mwait_free(struct cpu *);
663 extern int cpuid_deep_cstates_supported(void);
664 extern int cpuid_arat_supported(void);
665 extern int cpuid_iepb_supported(struct cpu *);
666 extern int vmware_platform(void);
667 #endif
668 
669 struct cpu_ucode_info;
670 
671 extern void ucode_alloc_space(struct cpu *);
672 extern void ucode_free_space(struct cpu *);
673 extern void ucode_check(struct cpu *);
674 extern void ucode_cleanup();
675 
676 #if !defined(__xpv)
677 extern	char _tsc_mfence_start;
678 extern	char _tsc_mfence_end;
679 extern	char _tscp_start;
680 extern	char _tscp_end;
681 extern	char _no_rdtsc_start;
682 extern	char _no_rdtsc_end;
683 extern	char _tsc_lfence_start;
684 extern	char _tsc_lfence_end;
685 #endif
686 
687 #if !defined(__xpv)
688 extern	char bcopy_patch_start;
689 extern	char bcopy_patch_end;
690 extern	char bcopy_ck_size;
691 #endif
692 
693 extern void post_startup_cpu_fixups(void);
694 
695 extern uint_t workaround_errata(struct cpu *);
696 
697 #if defined(OPTERON_ERRATUM_93)
698 extern int opteron_erratum_93;
699 #endif
700 
701 #if defined(OPTERON_ERRATUM_91)
702 extern int opteron_erratum_91;
703 #endif
704 
705 #if defined(OPTERON_ERRATUM_100)
706 extern int opteron_erratum_100;
707 #endif
708 
709 #if defined(OPTERON_ERRATUM_121)
710 extern int opteron_erratum_121;
711 #endif
712 
713 #if defined(OPTERON_WORKAROUND_6323525)
714 extern int opteron_workaround_6323525;
715 extern void patch_workaround_6323525(void);
716 #endif
717 
718 extern int get_hwenv(void);
719 extern int is_controldom(void);
720 
721 /*
722  * Defined hardware environments
723  */
724 #define	HW_NATIVE	0x00	/* Running on bare metal */
725 #define	HW_XEN_PV	0x01	/* Running on Xen Hypervisor paravirutualized */
726 #define	HW_XEN_HVM	0x02	/* Running on Xen hypervisor HVM */
727 #define	HW_VMWARE	0x03	/* Running on VMware hypervisor */
728 
729 #endif	/* _KERNEL */
730 
731 #endif
732 
733 #ifdef	__cplusplus
734 }
735 #endif
736 
737 #endif	/* _SYS_X86_ARCHEXT_H */
738