1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright (c) 2019, Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 */ 36 37 #ifndef _SYS_X86_ARCHEXT_H 38 #define _SYS_X86_ARCHEXT_H 39 40 #if !defined(_ASM) 41 #include <sys/regset.h> 42 #include <sys/processor.h> 43 #include <vm/seg_enum.h> 44 #include <vm/page.h> 45 #endif /* _ASM */ 46 47 #ifdef __cplusplus 48 extern "C" { 49 #endif 50 51 /* 52 * cpuid instruction feature flags in %edx (standard function 1) 53 */ 54 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 65 /* 0x400 - reserved */ 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 75 /* 0x100000 - reserved */ 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 87 88 /* 89 * cpuid instruction feature flags in %ecx (standard function 1) 90 */ 91 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 103 /* 0x00000800 - reserved */ 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 108 /* 0x00010000 - reserved */ 109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 124 125 /* 126 * cpuid instruction feature flags in %edx (extended function 0x80000001) 127 */ 128 129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 139 /* 0x00000400 - sysc on K6m6 */ 140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 148 /* 0x00040000 - reserved */ 149 /* 0x00080000 - reserved */ 150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 151 /* 0x00200000 - reserved */ 152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 158 /* 0x10000000 - reserved */ 159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 162 163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 174 #define CPUID_AMD_ECX_XOP 0x00000800 /* AMD: Extended Operation */ 175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 177 /* 0x00004000 - reserved */ 178 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 179 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 180 /* 0x00020000 - reserved */ 181 /* 0x00040000 - reserved */ 182 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 183 /* 0x00100000 - reserved */ 184 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 186 #define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */ 187 #define CUPID_AMD_ECX_PCENB 0x01000000 /* AMD: NB ext perf counter */ 188 /* 0x02000000 - reserved */ 189 #define CPUID_AMD_ECX_DBKP 0x40000000 /* AMD: Data breakpoint */ 190 #define CPUID_AMD_ECX_PERFTSC 0x08000000 /* AMD: TSC Perf Counter */ 191 #define CPUID_AMD_ECX_PERFL3 0x10000000 /* AMD: L3 Perf Counter */ 192 #define CPUID_AMD_ECX_MONITORX 0x20000000 /* AMD: clzero */ 193 /* 0x40000000 - reserved */ 194 /* 0x80000000 - reserved */ 195 196 /* 197 * AMD uses %ebx for some of their features (extended function 0x80000008). 198 */ 199 #define CPUID_AMD_EBX_CLZERO 0x000000001 /* AMD: CLZERO instr */ 200 #define CPUID_AMD_EBX_IRCMSR 0x000000002 /* AMD: Ret. instrs MSR */ 201 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 202 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 203 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 204 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 205 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 206 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 207 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 208 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 209 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 210 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 211 212 /* 213 * Intel now seems to have claimed part of the "extended" function 214 * space that we previously for non-Intel implementors to use. 215 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 216 * is available in long mode i.e. what AMD indicate using bit 0. 217 * On the other hand, everything else is labelled as reserved. 218 */ 219 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 220 221 /* 222 * Intel also uses cpuid leaf 7 to have additional instructions and features. 223 * Like some other leaves, but unlike the current ones we care about, it 224 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 225 * with the potential use of additional sub-leaves in the future, we now 226 * specifically label the EBX features with their leaf and sub-leaf. 227 */ 228 #define CPUID_INTC_EBX_7_0_FSGSBASE 0x00000001 /* FSGSBASE */ 229 #define CPUID_INTC_EBX_7_0_TSC_ADJ 0x00000002 /* TSC adjust MSR */ 230 #define CPUID_INTC_EBX_7_0_SGX 0x00000004 /* SGX */ 231 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 232 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 233 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 234 /* Bit 6 is reserved */ 235 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 236 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 237 #define CPUID_INTC_EBX_7_0_ENH_REP_MOV 0x00000200 /* Enhanced REP MOVSB */ 238 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 239 #define CPUID_INTC_EBX_7_0_RTM 0x00000800 /* RTM instrs */ 240 #define CPUID_INTC_EBX_7_0_PQM 0x00001000 /* QoS Monitoring */ 241 #define CPUID_INTC_EBX_7_0_DEP_CSDS 0x00002000 /* Deprecates CS/DS */ 242 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 243 #define CPUID_INTC_EBX_7_0_PQE 0x00080000 /* QoS Enforcement */ 244 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 245 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 246 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 247 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 248 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 249 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 250 /* Bit 22 is reserved */ 251 #define CPUID_INTC_EBX_7_0_CLFLUSHOPT 0x00800000 /* CLFLUSOPT */ 252 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 253 #define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */ 254 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 255 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 256 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 257 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 258 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 259 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 260 261 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 262 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 263 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 264 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 265 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 266 267 #define CPUID_INTC_ECX_7_0_PREFETCHWT1 0x00000001 /* PREFETCHWT1 */ 268 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 269 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 270 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 271 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 272 #define CPUID_INTC_ECX_7_0_WAITPKG 0x00000020 /* WAITPKG */ 273 #define CPUID_INTC_ECX_7_0_AVX512VBMI2 0x00000040 /* AVX512 VBMI2 */ 274 /* bit 7 is reserved */ 275 #define CPUID_INTC_ECX_7_0_GFNI 0x00000100 /* GFNI */ 276 #define CPUID_INTC_ECX_7_0_VAES 0x00000200 /* VAES */ 277 #define CPUID_INTC_ECX_7_0_VPCLMULQDQ 0x00000400 /* VPCLMULQDQ */ 278 #define CPUID_INTC_ECX_7_0_AVX512VNNI 0x00000800 /* AVX512 VNNI */ 279 #define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000 /* AVX512 BITALG */ 280 /* bit 13 is reserved */ 281 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 282 /* bits 15-16 are reserved */ 283 /* bits 17-21 are the value of MAWAU */ 284 #define CPUID_INTC_ECX_7_0_RDPID 0x00400000 /* RPID, IA32_TSC_AUX */ 285 /* bits 23-24 are reserved */ 286 #define CPUID_INTC_ECX_7_0_CLDEMOTE 0x02000000 /* Cache line demote */ 287 /* bit 26 is resrved */ 288 #define CPUID_INTC_ECX_7_0_MOVDIRI 0x08000000 /* MOVDIRI insn */ 289 #define CPUID_INTC_ECX_7_0_MOVDIR64B 0x10000000 /* MOVDIR64B insn */ 290 /* bit 29 is reserved */ 291 #define CPUID_INTC_ECX_7_0_SGXLC 0x40000000 /* SGX Launch config */ 292 /* bit 31 is reserved */ 293 294 /* 295 * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and 296 * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still 297 * valid when AVX512 is not. However, the following flags all are only valid 298 * when AVX512 is present. 299 */ 300 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 301 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \ 302 CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 303 304 /* bits 0-1 are reserved */ 305 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 306 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 307 #define CPUID_INTC_EDX_7_0_FSREPMOV 0x00000010 /* fast short rep mov */ 308 /* bits 5-17 are resreved */ 309 #define CPUID_INTC_EDX_7_0_PCONFIG 0x00040000 /* PCONFIG */ 310 /* bits 19-26 are reserved */ 311 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 312 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 313 #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */ 314 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 315 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 316 317 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 318 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS) 319 320 /* 321 * Intel also uses cpuid leaf 0xd to report additional instructions and features 322 * when the sub-leaf in %ecx == 1. We label these using the same convention as 323 * with leaf 7. 324 */ 325 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 326 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 327 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 328 329 #define REG_PAT 0x277 330 #define REG_TSC 0x10 /* timestamp counter */ 331 #define REG_APIC_BASE_MSR 0x1b 332 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 333 334 #if !defined(__xpv) 335 /* 336 * AMD C1E 337 */ 338 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 339 #define AMD_ACTONCMPHALT_SHIFT 27 340 #define AMD_ACTONCMPHALT_MASK 3 341 #endif 342 343 #define MSR_DEBUGCTL 0x1d9 344 345 #define DEBUGCTL_LBR 0x01 346 #define DEBUGCTL_BTF 0x02 347 348 /* Intel P6, AMD */ 349 #define MSR_LBR_FROM 0x1db 350 #define MSR_LBR_TO 0x1dc 351 #define MSR_LEX_FROM 0x1dd 352 #define MSR_LEX_TO 0x1de 353 354 /* Intel P4 (pre-Prescott, non P4 M) */ 355 #define MSR_P4_LBSTK_TOS 0x1da 356 #define MSR_P4_LBSTK_0 0x1db 357 #define MSR_P4_LBSTK_1 0x1dc 358 #define MSR_P4_LBSTK_2 0x1dd 359 #define MSR_P4_LBSTK_3 0x1de 360 361 /* Intel Pentium M */ 362 #define MSR_P6M_LBSTK_TOS 0x1c9 363 #define MSR_P6M_LBSTK_0 0x040 364 #define MSR_P6M_LBSTK_1 0x041 365 #define MSR_P6M_LBSTK_2 0x042 366 #define MSR_P6M_LBSTK_3 0x043 367 #define MSR_P6M_LBSTK_4 0x044 368 #define MSR_P6M_LBSTK_5 0x045 369 #define MSR_P6M_LBSTK_6 0x046 370 #define MSR_P6M_LBSTK_7 0x047 371 372 /* Intel P4 (Prescott) */ 373 #define MSR_PRP4_LBSTK_TOS 0x1da 374 #define MSR_PRP4_LBSTK_FROM_0 0x680 375 #define MSR_PRP4_LBSTK_FROM_1 0x681 376 #define MSR_PRP4_LBSTK_FROM_2 0x682 377 #define MSR_PRP4_LBSTK_FROM_3 0x683 378 #define MSR_PRP4_LBSTK_FROM_4 0x684 379 #define MSR_PRP4_LBSTK_FROM_5 0x685 380 #define MSR_PRP4_LBSTK_FROM_6 0x686 381 #define MSR_PRP4_LBSTK_FROM_7 0x687 382 #define MSR_PRP4_LBSTK_FROM_8 0x688 383 #define MSR_PRP4_LBSTK_FROM_9 0x689 384 #define MSR_PRP4_LBSTK_FROM_10 0x68a 385 #define MSR_PRP4_LBSTK_FROM_11 0x68b 386 #define MSR_PRP4_LBSTK_FROM_12 0x68c 387 #define MSR_PRP4_LBSTK_FROM_13 0x68d 388 #define MSR_PRP4_LBSTK_FROM_14 0x68e 389 #define MSR_PRP4_LBSTK_FROM_15 0x68f 390 #define MSR_PRP4_LBSTK_TO_0 0x6c0 391 #define MSR_PRP4_LBSTK_TO_1 0x6c1 392 #define MSR_PRP4_LBSTK_TO_2 0x6c2 393 #define MSR_PRP4_LBSTK_TO_3 0x6c3 394 #define MSR_PRP4_LBSTK_TO_4 0x6c4 395 #define MSR_PRP4_LBSTK_TO_5 0x6c5 396 #define MSR_PRP4_LBSTK_TO_6 0x6c6 397 #define MSR_PRP4_LBSTK_TO_7 0x6c7 398 #define MSR_PRP4_LBSTK_TO_8 0x6c8 399 #define MSR_PRP4_LBSTK_TO_9 0x6c9 400 #define MSR_PRP4_LBSTK_TO_10 0x6ca 401 #define MSR_PRP4_LBSTK_TO_11 0x6cb 402 #define MSR_PRP4_LBSTK_TO_12 0x6cc 403 #define MSR_PRP4_LBSTK_TO_13 0x6cd 404 #define MSR_PRP4_LBSTK_TO_14 0x6ce 405 #define MSR_PRP4_LBSTK_TO_15 0x6cf 406 407 /* 408 * General Xeon based MSRs 409 */ 410 #define MSR_PPIN_CTL 0x04e 411 #define MSR_PPIN 0x04f 412 #define MSR_PLATFORM_INFO 0x0ce 413 414 #define MSR_PLATFORM_INFO_PPIN (1 << 23) 415 #define MSR_PPIN_CTL_MASK 0x03 416 #define MSR_PPIN_CTL_LOCKED 0x01 417 #define MSR_PPIN_CTL_ENABLED 0x02 418 419 /* 420 * Intel IA32_ARCH_CAPABILITIES MSR. 421 */ 422 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 423 #define IA32_ARCH_CAP_RDCL_NO 0x0001 424 #define IA32_ARCH_CAP_IBRS_ALL 0x0002 425 #define IA32_ARCH_CAP_RSBA 0x0004 426 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008 427 #define IA32_ARCH_CAP_SSB_NO 0x0010 428 429 /* 430 * Intel Speculation related MSRs 431 */ 432 #define MSR_IA32_SPEC_CTRL 0x48 433 #define IA32_SPEC_CTRL_IBRS 0x01 434 #define IA32_SPEC_CTRL_STIBP 0x02 435 #define IA32_SPEC_CTRL_SSBD 0x04 436 437 #define MSR_IA32_PRED_CMD 0x49 438 #define IA32_PRED_CMD_IBPB 0x01 439 440 #define MSR_IA32_FLUSH_CMD 0x10b 441 #define IA32_FLUSH_CMD_L1D 0x01 442 443 #define MCI_CTL_VALUE 0xffffffff 444 445 #define MTRR_TYPE_UC 0 446 #define MTRR_TYPE_WC 1 447 #define MTRR_TYPE_WT 4 448 #define MTRR_TYPE_WP 5 449 #define MTRR_TYPE_WB 6 450 #define MTRR_TYPE_UC_ 7 451 452 /* 453 * For Solaris we set up the page attritubute table in the following way: 454 * PAT0 Write-Back 455 * PAT1 Write-Through 456 * PAT2 Unchacheable- 457 * PAT3 Uncacheable 458 * PAT4 Write-Back 459 * PAT5 Write-Through 460 * PAT6 Write-Combine 461 * PAT7 Uncacheable 462 * The only difference from h/w default is entry 6. 463 */ 464 #define PAT_DEFAULT_ATTRIBUTE \ 465 ((uint64_t)MTRR_TYPE_WB | \ 466 ((uint64_t)MTRR_TYPE_WT << 8) | \ 467 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 468 ((uint64_t)MTRR_TYPE_UC << 24) | \ 469 ((uint64_t)MTRR_TYPE_WB << 32) | \ 470 ((uint64_t)MTRR_TYPE_WT << 40) | \ 471 ((uint64_t)MTRR_TYPE_WC << 48) | \ 472 ((uint64_t)MTRR_TYPE_UC << 56)) 473 474 #define X86FSET_LARGEPAGE 0 475 #define X86FSET_TSC 1 476 #define X86FSET_MSR 2 477 #define X86FSET_MTRR 3 478 #define X86FSET_PGE 4 479 #define X86FSET_DE 5 480 #define X86FSET_CMOV 6 481 #define X86FSET_MMX 7 482 #define X86FSET_MCA 8 483 #define X86FSET_PAE 9 484 #define X86FSET_CX8 10 485 #define X86FSET_PAT 11 486 #define X86FSET_SEP 12 487 #define X86FSET_SSE 13 488 #define X86FSET_SSE2 14 489 #define X86FSET_HTT 15 490 #define X86FSET_ASYSC 16 491 #define X86FSET_NX 17 492 #define X86FSET_SSE3 18 493 #define X86FSET_CX16 19 494 #define X86FSET_CMP 20 495 #define X86FSET_TSCP 21 496 #define X86FSET_MWAIT 22 497 #define X86FSET_SSE4A 23 498 #define X86FSET_CPUID 24 499 #define X86FSET_SSSE3 25 500 #define X86FSET_SSE4_1 26 501 #define X86FSET_SSE4_2 27 502 #define X86FSET_1GPG 28 503 #define X86FSET_CLFSH 29 504 #define X86FSET_64 30 505 #define X86FSET_AES 31 506 #define X86FSET_PCLMULQDQ 32 507 #define X86FSET_XSAVE 33 508 #define X86FSET_AVX 34 509 #define X86FSET_VMX 35 510 #define X86FSET_SVM 36 511 #define X86FSET_TOPOEXT 37 512 #define X86FSET_F16C 38 513 #define X86FSET_RDRAND 39 514 #define X86FSET_X2APIC 40 515 #define X86FSET_AVX2 41 516 #define X86FSET_BMI1 42 517 #define X86FSET_BMI2 43 518 #define X86FSET_FMA 44 519 #define X86FSET_SMEP 45 520 #define X86FSET_SMAP 46 521 #define X86FSET_ADX 47 522 #define X86FSET_RDSEED 48 523 #define X86FSET_MPX 49 524 #define X86FSET_AVX512F 50 525 #define X86FSET_AVX512DQ 51 526 #define X86FSET_AVX512PF 52 527 #define X86FSET_AVX512ER 53 528 #define X86FSET_AVX512CD 54 529 #define X86FSET_AVX512BW 55 530 #define X86FSET_AVX512VL 56 531 #define X86FSET_AVX512FMA 57 532 #define X86FSET_AVX512VBMI 58 533 #define X86FSET_AVX512VPOPCDQ 59 534 #define X86FSET_AVX512NNIW 60 535 #define X86FSET_AVX512FMAPS 61 536 #define X86FSET_XSAVEOPT 62 537 #define X86FSET_XSAVEC 63 538 #define X86FSET_XSAVES 64 539 #define X86FSET_SHA 65 540 #define X86FSET_UMIP 66 541 #define X86FSET_PKU 67 542 #define X86FSET_OSPKE 68 543 #define X86FSET_PCID 69 544 #define X86FSET_INVPCID 70 545 #define X86FSET_IBRS 71 546 #define X86FSET_IBPB 72 547 #define X86FSET_STIBP 73 548 #define X86FSET_SSBD 74 549 #define X86FSET_SSBD_VIRT 75 550 #define X86FSET_RDCL_NO 76 551 #define X86FSET_IBRS_ALL 77 552 #define X86FSET_RSBA 78 553 #define X86FSET_SSB_NO 79 554 #define X86FSET_STIBP_ALL 80 555 #define X86FSET_FLUSH_CMD 81 556 #define X86FSET_L1D_VM_NO 82 557 #define X86FSET_FSGSBASE 83 558 #define X86FSET_CLFLUSHOPT 84 559 #define X86FSET_CLWB 85 560 #define X86FSET_MONITORX 86 561 #define X86FSET_CLZERO 87 562 #define X86FSET_XOP 88 563 #define X86FSET_FMA4 89 564 #define X86FSET_TBM 90 565 566 /* 567 * Intel Deep C-State invariant TSC in leaf 0x80000007. 568 */ 569 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 570 571 /* 572 * Intel Deep C-state always-running local APIC timer 573 */ 574 #define CPUID_CSTATE_ARAT (0x4) 575 576 /* 577 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 578 */ 579 #define CPUID_EPB_SUPPORT (1 << 3) 580 581 /* 582 * Intel TSC deadline timer 583 */ 584 #define CPUID_DEADLINE_TSC (1 << 24) 585 586 /* 587 * x86_type is a legacy concept; this is supplanted 588 * for most purposes by x86_featureset; modern CPUs 589 * should be X86_TYPE_OTHER 590 */ 591 #define X86_TYPE_OTHER 0 592 #define X86_TYPE_486 1 593 #define X86_TYPE_P5 2 594 #define X86_TYPE_P6 3 595 #define X86_TYPE_CYRIX_486 4 596 #define X86_TYPE_CYRIX_6x86L 5 597 #define X86_TYPE_CYRIX_6x86 6 598 #define X86_TYPE_CYRIX_GXm 7 599 #define X86_TYPE_CYRIX_6x86MX 8 600 #define X86_TYPE_CYRIX_MediaGX 9 601 #define X86_TYPE_CYRIX_MII 10 602 #define X86_TYPE_VIA_CYRIX_III 11 603 #define X86_TYPE_P4 12 604 605 /* 606 * x86_vendor allows us to select between 607 * implementation features and helps guide 608 * the interpretation of the cpuid instruction. 609 */ 610 #define X86_VENDOR_Intel 0 611 #define X86_VENDORSTR_Intel "GenuineIntel" 612 613 #define X86_VENDOR_IntelClone 1 614 615 #define X86_VENDOR_AMD 2 616 #define X86_VENDORSTR_AMD "AuthenticAMD" 617 618 #define X86_VENDOR_Cyrix 3 619 #define X86_VENDORSTR_CYRIX "CyrixInstead" 620 621 #define X86_VENDOR_UMC 4 622 #define X86_VENDORSTR_UMC "UMC UMC UMC " 623 624 #define X86_VENDOR_NexGen 5 625 #define X86_VENDORSTR_NexGen "NexGenDriven" 626 627 #define X86_VENDOR_Centaur 6 628 #define X86_VENDORSTR_Centaur "CentaurHauls" 629 630 #define X86_VENDOR_Rise 7 631 #define X86_VENDORSTR_Rise "RiseRiseRise" 632 633 #define X86_VENDOR_SiS 8 634 #define X86_VENDORSTR_SiS "SiS SiS SiS " 635 636 #define X86_VENDOR_TM 9 637 #define X86_VENDORSTR_TM "GenuineTMx86" 638 639 #define X86_VENDOR_NSC 10 640 #define X86_VENDORSTR_NSC "Geode by NSC" 641 642 /* 643 * Vendor string max len + \0 644 */ 645 #define X86_VENDOR_STRLEN 13 646 647 /* 648 * Some vendor/family/model/stepping ranges are commonly grouped under 649 * a single identifying banner by the vendor. The following encode 650 * that "revision" in a uint32_t with the 8 most significant bits 651 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 652 * family, and the remaining 16 typically forming a bitmask of revisions 653 * within that family with more significant bits indicating "later" revisions. 654 */ 655 656 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 657 #define _X86_CHIPREV_VENDOR_SHIFT 24 658 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 659 #define _X86_CHIPREV_FAMILY_SHIFT 16 660 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 661 662 #define _X86_CHIPREV_VENDOR(x) \ 663 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 664 #define _X86_CHIPREV_FAMILY(x) \ 665 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 666 #define _X86_CHIPREV_REV(x) \ 667 ((x) & _X86_CHIPREV_REV_MASK) 668 669 /* True if x matches in vendor and family and if x matches the given rev mask */ 670 #define X86_CHIPREV_MATCH(x, mask) \ 671 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 672 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 673 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 674 675 /* True if x matches in vendor and family, and rev is at least minx */ 676 #define X86_CHIPREV_ATLEAST(x, minx) \ 677 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 678 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 679 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 680 681 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 682 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 683 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 684 685 /* True if x matches in vendor, and family is at least minx */ 686 #define X86_CHIPFAM_ATLEAST(x, minx) \ 687 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 688 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 689 690 /* Revision default */ 691 #define X86_CHIPREV_UNKNOWN 0x0 692 693 /* 694 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 695 * sufficiently different that we will distinguish them; in all other 696 * case we will identify the major revision. 697 */ 698 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 699 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 700 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 701 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 702 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 703 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 704 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 705 706 /* 707 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 708 */ 709 #define X86_CHIPREV_AMD_10_REV_A \ 710 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 711 #define X86_CHIPREV_AMD_10_REV_B \ 712 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 713 #define X86_CHIPREV_AMD_10_REV_C2 \ 714 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 715 #define X86_CHIPREV_AMD_10_REV_C3 \ 716 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 717 #define X86_CHIPREV_AMD_10_REV_D0 \ 718 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 719 #define X86_CHIPREV_AMD_10_REV_D1 \ 720 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 721 #define X86_CHIPREV_AMD_10_REV_E \ 722 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 723 724 /* 725 * Definitions for AMD Family 0x11. 726 */ 727 #define X86_CHIPREV_AMD_11_REV_B \ 728 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 729 730 /* 731 * Definitions for AMD Family 0x12. 732 */ 733 #define X86_CHIPREV_AMD_12_REV_B \ 734 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 735 736 /* 737 * Definitions for AMD Family 0x14. 738 */ 739 #define X86_CHIPREV_AMD_14_REV_B \ 740 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 741 #define X86_CHIPREV_AMD_14_REV_C \ 742 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 743 744 /* 745 * Definitions for AMD Family 0x15 746 */ 747 #define X86_CHIPREV_AMD_15OR_REV_B2 \ 748 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 749 750 #define X86_CHIPREV_AMD_15TN_REV_A1 \ 751 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 752 753 /* 754 * Various socket/package types, extended as the need to distinguish 755 * a new type arises. The top 8 byte identfies the vendor and the 756 * remaining 24 bits describe 24 socket types. 757 */ 758 759 #define _X86_SOCKET_VENDOR_SHIFT 24 760 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 761 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 762 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 763 764 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 765 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 766 767 #define X86_SOCKET_MATCH(s, mask) \ 768 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 769 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 770 771 #define X86_SOCKET_UNKNOWN 0x0 772 /* 773 * AMD socket types 774 */ 775 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 776 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 777 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 778 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 779 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 780 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 781 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 782 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 783 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 784 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 785 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 786 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 787 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 788 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 789 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 790 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 791 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 792 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 793 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 794 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 795 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 796 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 797 798 799 /* 800 * Definitions for Intel processor models. Note, these model values can overlap 801 * in a given family. Processor models are added here on an as needed basis. The 802 * Xeon extension here is to refer to what has been called the EP/EX lines or 803 * E5/E7, generally multi-socket capable processors. 804 */ 805 #define INTC_MODEL_IVYBRIDGE_XEON 0x3E 806 #define INTC_MODEL_HASWELL_XEON 0x3F 807 #define INTC_MODEL_BROADWELL_XEON 0x4F 808 #define INTC_MODEL_BROADWELL_XEON_D 0x56 809 #define INTC_MODEL_SKYLAKE_XEON 0x55 810 811 /* 812 * xgetbv/xsetbv support 813 * See section 13.3 in vol. 1 of the Intel devlopers manual. 814 */ 815 816 #define XFEATURE_ENABLED_MASK 0x0 817 /* 818 * XFEATURE_ENABLED_MASK values (eax) 819 * See setup_xfem(). 820 */ 821 #define XFEATURE_LEGACY_FP 0x1 822 #define XFEATURE_SSE 0x2 823 #define XFEATURE_AVX 0x4 824 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ 825 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ 826 /* bit 8 unused */ 827 #define XFEATURE_PKRU 0x200 828 #define XFEATURE_FP_ALL \ 829 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 830 XFEATURE_AVX512 | XFEATURE_PKRU) 831 832 /* 833 * Define the set of xfeature flags that should be considered valid in the xsave 834 * state vector when we initialize an lwp. This is distinct from the full set so 835 * that all of the processor's normal logic and tracking of the xsave state is 836 * usable. This should correspond to the state that's been initialized by the 837 * ABI to hold meaningful values. Adding additional bits here can have serious 838 * performance implications and cause performance degradations when using the 839 * FPU vector (xmm) registers. 840 */ 841 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 842 843 #if !defined(_ASM) 844 845 #if defined(_KERNEL) || defined(_KMEMUSER) 846 847 #define NUM_X86_FEATURES 91 848 extern uchar_t x86_featureset[]; 849 850 extern void free_x86_featureset(void *featureset); 851 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 852 extern void add_x86_feature(void *featureset, uint_t feature); 853 extern void remove_x86_feature(void *featureset, uint_t feature); 854 extern boolean_t compare_x86_featureset(void *setA, void *setB); 855 extern void print_x86_featureset(void *featureset); 856 857 858 extern uint_t x86_type; 859 extern uint_t x86_vendor; 860 extern uint_t x86_clflush_size; 861 862 extern uint_t pentiumpro_bug4046376; 863 864 extern const char CyrixInstead[]; 865 866 #endif 867 868 #if defined(_KERNEL) 869 870 /* 871 * This structure is used to pass arguments and get return values back 872 * from the CPUID instruction in __cpuid_insn() routine. 873 */ 874 struct cpuid_regs { 875 uint32_t cp_eax; 876 uint32_t cp_ebx; 877 uint32_t cp_ecx; 878 uint32_t cp_edx; 879 }; 880 881 extern int x86_use_pcid; 882 extern int x86_use_invpcid; 883 884 /* 885 * Utility functions to get/set extended control registers (XCR) 886 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 887 */ 888 extern uint64_t get_xcr(uint_t); 889 extern void set_xcr(uint_t, uint64_t); 890 891 extern uint64_t rdmsr(uint_t); 892 extern void wrmsr(uint_t, const uint64_t); 893 extern uint64_t xrdmsr(uint_t); 894 extern void xwrmsr(uint_t, const uint64_t); 895 extern int checked_rdmsr(uint_t, uint64_t *); 896 extern int checked_wrmsr(uint_t, uint64_t); 897 898 extern void invalidate_cache(void); 899 extern ulong_t getcr4(void); 900 extern void setcr4(ulong_t); 901 902 extern void mtrr_sync(void); 903 904 extern void cpu_fast_syscall_enable(void); 905 extern void cpu_fast_syscall_disable(void); 906 907 struct cpu; 908 909 extern int cpuid_checkpass(struct cpu *, int); 910 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 911 extern uint32_t __cpuid_insn(struct cpuid_regs *); 912 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 913 extern int cpuid_getidstr(struct cpu *, char *, size_t); 914 extern const char *cpuid_getvendorstr(struct cpu *); 915 extern uint_t cpuid_getvendor(struct cpu *); 916 extern uint_t cpuid_getfamily(struct cpu *); 917 extern uint_t cpuid_getmodel(struct cpu *); 918 extern uint_t cpuid_getstep(struct cpu *); 919 extern uint_t cpuid_getsig(struct cpu *); 920 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 921 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 922 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 923 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 924 extern int cpuid_get_chipid(struct cpu *); 925 extern id_t cpuid_get_coreid(struct cpu *); 926 extern int cpuid_get_pkgcoreid(struct cpu *); 927 extern int cpuid_get_clogid(struct cpu *); 928 extern int cpuid_get_cacheid(struct cpu *); 929 extern uint32_t cpuid_get_apicid(struct cpu *); 930 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 931 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 932 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 933 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 934 extern size_t cpuid_get_xsave_size(); 935 extern boolean_t cpuid_need_fp_excp_handling(); 936 extern int cpuid_is_cmt(struct cpu *); 937 extern int cpuid_syscall32_insn(struct cpu *); 938 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 939 940 extern uint32_t cpuid_getchiprev(struct cpu *); 941 extern const char *cpuid_getchiprevstr(struct cpu *); 942 extern uint32_t cpuid_getsockettype(struct cpu *); 943 extern const char *cpuid_getsocketstr(struct cpu *); 944 945 extern int cpuid_have_cr8access(struct cpu *); 946 947 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 948 949 struct cpuid_info; 950 951 extern void setx86isalist(void); 952 extern void cpuid_alloc_space(struct cpu *); 953 extern void cpuid_free_space(struct cpu *); 954 extern void cpuid_pass1(struct cpu *, uchar_t *); 955 extern void cpuid_pass2(struct cpu *); 956 extern void cpuid_pass3(struct cpu *); 957 extern void cpuid_pass4(struct cpu *, uint_t *); 958 extern void cpuid_set_cpu_properties(void *, processorid_t, 959 struct cpuid_info *); 960 extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 961 extern void cpuid_post_ucodeadm(void); 962 963 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 964 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 965 966 #if !defined(__xpv) 967 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 968 extern void cpuid_mwait_free(struct cpu *); 969 extern int cpuid_deep_cstates_supported(void); 970 extern int cpuid_arat_supported(void); 971 extern int cpuid_iepb_supported(struct cpu *); 972 extern int cpuid_deadline_tsc_supported(void); 973 extern void vmware_port(int, uint32_t *); 974 #endif 975 976 struct cpu_ucode_info; 977 978 extern void ucode_alloc_space(struct cpu *); 979 extern void ucode_free_space(struct cpu *); 980 extern void ucode_check(struct cpu *); 981 extern void ucode_cleanup(); 982 983 #if !defined(__xpv) 984 extern char _tsc_mfence_start; 985 extern char _tsc_mfence_end; 986 extern char _tscp_start; 987 extern char _tscp_end; 988 extern char _no_rdtsc_start; 989 extern char _no_rdtsc_end; 990 extern char _tsc_lfence_start; 991 extern char _tsc_lfence_end; 992 #endif 993 994 #if !defined(__xpv) 995 extern char bcopy_patch_start; 996 extern char bcopy_patch_end; 997 extern char bcopy_ck_size; 998 #endif 999 1000 extern void post_startup_cpu_fixups(void); 1001 1002 extern uint_t workaround_errata(struct cpu *); 1003 1004 #if defined(OPTERON_ERRATUM_93) 1005 extern int opteron_erratum_93; 1006 #endif 1007 1008 #if defined(OPTERON_ERRATUM_91) 1009 extern int opteron_erratum_91; 1010 #endif 1011 1012 #if defined(OPTERON_ERRATUM_100) 1013 extern int opteron_erratum_100; 1014 #endif 1015 1016 #if defined(OPTERON_ERRATUM_121) 1017 extern int opteron_erratum_121; 1018 #endif 1019 1020 #if defined(OPTERON_WORKAROUND_6323525) 1021 extern int opteron_workaround_6323525; 1022 extern void patch_workaround_6323525(void); 1023 #endif 1024 1025 #if !defined(__xpv) 1026 extern void determine_platform(void); 1027 #endif 1028 extern int get_hwenv(void); 1029 extern int is_controldom(void); 1030 1031 extern void enable_pcid(void); 1032 1033 extern void xsave_setup_msr(struct cpu *); 1034 1035 #if !defined(__xpv) 1036 extern void reset_gdtr_limit(void); 1037 #endif 1038 1039 /* 1040 * Hypervisor signatures 1041 */ 1042 #define HVSIG_XEN_HVM "XenVMMXenVMM" 1043 #define HVSIG_VMWARE "VMwareVMware" 1044 #define HVSIG_KVM "KVMKVMKVM" 1045 #define HVSIG_MICROSOFT "Microsoft Hv" 1046 #define HVSIG_BHYVE "bhyve bhyve " 1047 1048 /* 1049 * Defined hardware environments 1050 */ 1051 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 1052 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 1053 1054 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 1055 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 1056 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 1057 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 1058 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */ 1059 1060 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \ 1061 HW_BHYVE) 1062 1063 #endif /* _KERNEL */ 1064 1065 #endif /* !_ASM */ 1066 1067 /* 1068 * VMware hypervisor related defines 1069 */ 1070 #define VMWARE_HVMAGIC 0x564d5868 1071 #define VMWARE_HVPORT 0x5658 1072 #define VMWARE_HVCMD_GETVERSION 0x0a 1073 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 1074 1075 #ifdef __cplusplus 1076 } 1077 #endif 1078 1079 #endif /* _SYS_X86_ARCHEXT_H */ 1080