1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright (c) 2019, Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 */ 36 37 #ifndef _SYS_X86_ARCHEXT_H 38 #define _SYS_X86_ARCHEXT_H 39 40 #if !defined(_ASM) 41 #include <sys/regset.h> 42 #include <sys/processor.h> 43 #include <vm/seg_enum.h> 44 #include <vm/page.h> 45 #endif /* _ASM */ 46 47 #ifdef __cplusplus 48 extern "C" { 49 #endif 50 51 /* 52 * cpuid instruction feature flags in %edx (standard function 1) 53 */ 54 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 65 /* 0x400 - reserved */ 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 75 /* 0x100000 - reserved */ 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 87 88 /* 89 * cpuid instruction feature flags in %ecx (standard function 1) 90 */ 91 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 103 /* 0x00000800 - reserved */ 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 108 /* 0x00010000 - reserved */ 109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 124 125 /* 126 * cpuid instruction feature flags in %edx (extended function 0x80000001) 127 */ 128 129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 139 /* 0x00000400 - sysc on K6m6 */ 140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 148 /* 0x00040000 - reserved */ 149 /* 0x00080000 - reserved */ 150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 151 /* 0x00200000 - reserved */ 152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 158 /* 0x10000000 - reserved */ 159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 162 163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 174 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */ 175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 177 /* 0x00004000 - reserved */ 178 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 179 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 180 /* 0x00020000 - reserved */ 181 /* 0x00040000 - reserved */ 182 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 183 /* 0x00100000 - reserved */ 184 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 186 187 /* 188 * AMD uses %ebx for some of their features (extended function 0x80000008). 189 */ 190 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 191 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 192 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 193 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 194 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 195 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 196 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 197 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 198 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 199 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 200 201 /* 202 * Intel now seems to have claimed part of the "extended" function 203 * space that we previously for non-Intel implementors to use. 204 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 205 * is available in long mode i.e. what AMD indicate using bit 0. 206 * On the other hand, everything else is labelled as reserved. 207 */ 208 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 209 210 /* 211 * Intel also uses cpuid leaf 7 to have additional instructions and features. 212 * Like some other leaves, but unlike the current ones we care about, it 213 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 214 * with the potential use of additional sub-leaves in the future, we now 215 * specifically label the EBX features with their leaf and sub-leaf. 216 */ 217 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 218 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 219 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 220 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 221 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 222 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 223 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 224 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 225 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 226 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 227 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 228 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 229 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 230 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 231 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 232 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 233 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 234 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 235 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 236 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 237 238 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 239 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 240 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 241 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 242 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 243 244 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 245 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 246 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 247 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 248 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 249 250 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 251 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 252 253 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 254 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 255 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 256 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 257 #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */ 258 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 259 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 260 261 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 262 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS) 263 264 /* 265 * Intel also uses cpuid leaf 0xd to report additional instructions and features 266 * when the sub-leaf in %ecx == 1. We label these using the same convention as 267 * with leaf 7. 268 */ 269 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 270 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 271 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 272 273 #define REG_PAT 0x277 274 #define REG_TSC 0x10 /* timestamp counter */ 275 #define REG_APIC_BASE_MSR 0x1b 276 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 277 278 #if !defined(__xpv) 279 /* 280 * AMD C1E 281 */ 282 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 283 #define AMD_ACTONCMPHALT_SHIFT 27 284 #define AMD_ACTONCMPHALT_MASK 3 285 #endif 286 287 #define MSR_DEBUGCTL 0x1d9 288 289 #define DEBUGCTL_LBR 0x01 290 #define DEBUGCTL_BTF 0x02 291 292 /* Intel P6, AMD */ 293 #define MSR_LBR_FROM 0x1db 294 #define MSR_LBR_TO 0x1dc 295 #define MSR_LEX_FROM 0x1dd 296 #define MSR_LEX_TO 0x1de 297 298 /* Intel P4 (pre-Prescott, non P4 M) */ 299 #define MSR_P4_LBSTK_TOS 0x1da 300 #define MSR_P4_LBSTK_0 0x1db 301 #define MSR_P4_LBSTK_1 0x1dc 302 #define MSR_P4_LBSTK_2 0x1dd 303 #define MSR_P4_LBSTK_3 0x1de 304 305 /* Intel Pentium M */ 306 #define MSR_P6M_LBSTK_TOS 0x1c9 307 #define MSR_P6M_LBSTK_0 0x040 308 #define MSR_P6M_LBSTK_1 0x041 309 #define MSR_P6M_LBSTK_2 0x042 310 #define MSR_P6M_LBSTK_3 0x043 311 #define MSR_P6M_LBSTK_4 0x044 312 #define MSR_P6M_LBSTK_5 0x045 313 #define MSR_P6M_LBSTK_6 0x046 314 #define MSR_P6M_LBSTK_7 0x047 315 316 /* Intel P4 (Prescott) */ 317 #define MSR_PRP4_LBSTK_TOS 0x1da 318 #define MSR_PRP4_LBSTK_FROM_0 0x680 319 #define MSR_PRP4_LBSTK_FROM_1 0x681 320 #define MSR_PRP4_LBSTK_FROM_2 0x682 321 #define MSR_PRP4_LBSTK_FROM_3 0x683 322 #define MSR_PRP4_LBSTK_FROM_4 0x684 323 #define MSR_PRP4_LBSTK_FROM_5 0x685 324 #define MSR_PRP4_LBSTK_FROM_6 0x686 325 #define MSR_PRP4_LBSTK_FROM_7 0x687 326 #define MSR_PRP4_LBSTK_FROM_8 0x688 327 #define MSR_PRP4_LBSTK_FROM_9 0x689 328 #define MSR_PRP4_LBSTK_FROM_10 0x68a 329 #define MSR_PRP4_LBSTK_FROM_11 0x68b 330 #define MSR_PRP4_LBSTK_FROM_12 0x68c 331 #define MSR_PRP4_LBSTK_FROM_13 0x68d 332 #define MSR_PRP4_LBSTK_FROM_14 0x68e 333 #define MSR_PRP4_LBSTK_FROM_15 0x68f 334 #define MSR_PRP4_LBSTK_TO_0 0x6c0 335 #define MSR_PRP4_LBSTK_TO_1 0x6c1 336 #define MSR_PRP4_LBSTK_TO_2 0x6c2 337 #define MSR_PRP4_LBSTK_TO_3 0x6c3 338 #define MSR_PRP4_LBSTK_TO_4 0x6c4 339 #define MSR_PRP4_LBSTK_TO_5 0x6c5 340 #define MSR_PRP4_LBSTK_TO_6 0x6c6 341 #define MSR_PRP4_LBSTK_TO_7 0x6c7 342 #define MSR_PRP4_LBSTK_TO_8 0x6c8 343 #define MSR_PRP4_LBSTK_TO_9 0x6c9 344 #define MSR_PRP4_LBSTK_TO_10 0x6ca 345 #define MSR_PRP4_LBSTK_TO_11 0x6cb 346 #define MSR_PRP4_LBSTK_TO_12 0x6cc 347 #define MSR_PRP4_LBSTK_TO_13 0x6cd 348 #define MSR_PRP4_LBSTK_TO_14 0x6ce 349 #define MSR_PRP4_LBSTK_TO_15 0x6cf 350 351 /* 352 * General Xeon based MSRs 353 */ 354 #define MSR_PPIN_CTL 0x04e 355 #define MSR_PPIN 0x04f 356 #define MSR_PLATFORM_INFO 0x0ce 357 358 #define MSR_PLATFORM_INFO_PPIN (1 << 23) 359 #define MSR_PPIN_CTL_MASK 0x03 360 #define MSR_PPIN_CTL_LOCKED 0x01 361 #define MSR_PPIN_CTL_ENABLED 0x02 362 363 /* 364 * Intel IA32_ARCH_CAPABILITIES MSR. 365 */ 366 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 367 #define IA32_ARCH_CAP_RDCL_NO 0x0001 368 #define IA32_ARCH_CAP_IBRS_ALL 0x0002 369 #define IA32_ARCH_CAP_RSBA 0x0004 370 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008 371 #define IA32_ARCH_CAP_SSB_NO 0x0010 372 373 /* 374 * Intel Speculation related MSRs 375 */ 376 #define MSR_IA32_SPEC_CTRL 0x48 377 #define IA32_SPEC_CTRL_IBRS 0x01 378 #define IA32_SPEC_CTRL_STIBP 0x02 379 #define IA32_SPEC_CTRL_SSBD 0x04 380 381 #define MSR_IA32_PRED_CMD 0x49 382 #define IA32_PRED_CMD_IBPB 0x01 383 384 #define MSR_IA32_FLUSH_CMD 0x10b 385 #define IA32_FLUSH_CMD_L1D 0x01 386 387 #define MCI_CTL_VALUE 0xffffffff 388 389 #define MTRR_TYPE_UC 0 390 #define MTRR_TYPE_WC 1 391 #define MTRR_TYPE_WT 4 392 #define MTRR_TYPE_WP 5 393 #define MTRR_TYPE_WB 6 394 #define MTRR_TYPE_UC_ 7 395 396 /* 397 * For Solaris we set up the page attritubute table in the following way: 398 * PAT0 Write-Back 399 * PAT1 Write-Through 400 * PAT2 Unchacheable- 401 * PAT3 Uncacheable 402 * PAT4 Write-Back 403 * PAT5 Write-Through 404 * PAT6 Write-Combine 405 * PAT7 Uncacheable 406 * The only difference from h/w default is entry 6. 407 */ 408 #define PAT_DEFAULT_ATTRIBUTE \ 409 ((uint64_t)MTRR_TYPE_WB | \ 410 ((uint64_t)MTRR_TYPE_WT << 8) | \ 411 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 412 ((uint64_t)MTRR_TYPE_UC << 24) | \ 413 ((uint64_t)MTRR_TYPE_WB << 32) | \ 414 ((uint64_t)MTRR_TYPE_WT << 40) | \ 415 ((uint64_t)MTRR_TYPE_WC << 48) | \ 416 ((uint64_t)MTRR_TYPE_UC << 56)) 417 418 #define X86FSET_LARGEPAGE 0 419 #define X86FSET_TSC 1 420 #define X86FSET_MSR 2 421 #define X86FSET_MTRR 3 422 #define X86FSET_PGE 4 423 #define X86FSET_DE 5 424 #define X86FSET_CMOV 6 425 #define X86FSET_MMX 7 426 #define X86FSET_MCA 8 427 #define X86FSET_PAE 9 428 #define X86FSET_CX8 10 429 #define X86FSET_PAT 11 430 #define X86FSET_SEP 12 431 #define X86FSET_SSE 13 432 #define X86FSET_SSE2 14 433 #define X86FSET_HTT 15 434 #define X86FSET_ASYSC 16 435 #define X86FSET_NX 17 436 #define X86FSET_SSE3 18 437 #define X86FSET_CX16 19 438 #define X86FSET_CMP 20 439 #define X86FSET_TSCP 21 440 #define X86FSET_MWAIT 22 441 #define X86FSET_SSE4A 23 442 #define X86FSET_CPUID 24 443 #define X86FSET_SSSE3 25 444 #define X86FSET_SSE4_1 26 445 #define X86FSET_SSE4_2 27 446 #define X86FSET_1GPG 28 447 #define X86FSET_CLFSH 29 448 #define X86FSET_64 30 449 #define X86FSET_AES 31 450 #define X86FSET_PCLMULQDQ 32 451 #define X86FSET_XSAVE 33 452 #define X86FSET_AVX 34 453 #define X86FSET_VMX 35 454 #define X86FSET_SVM 36 455 #define X86FSET_TOPOEXT 37 456 #define X86FSET_F16C 38 457 #define X86FSET_RDRAND 39 458 #define X86FSET_X2APIC 40 459 #define X86FSET_AVX2 41 460 #define X86FSET_BMI1 42 461 #define X86FSET_BMI2 43 462 #define X86FSET_FMA 44 463 #define X86FSET_SMEP 45 464 #define X86FSET_SMAP 46 465 #define X86FSET_ADX 47 466 #define X86FSET_RDSEED 48 467 #define X86FSET_MPX 49 468 #define X86FSET_AVX512F 50 469 #define X86FSET_AVX512DQ 51 470 #define X86FSET_AVX512PF 52 471 #define X86FSET_AVX512ER 53 472 #define X86FSET_AVX512CD 54 473 #define X86FSET_AVX512BW 55 474 #define X86FSET_AVX512VL 56 475 #define X86FSET_AVX512FMA 57 476 #define X86FSET_AVX512VBMI 58 477 #define X86FSET_AVX512VPOPCDQ 59 478 #define X86FSET_AVX512NNIW 60 479 #define X86FSET_AVX512FMAPS 61 480 #define X86FSET_XSAVEOPT 62 481 #define X86FSET_XSAVEC 63 482 #define X86FSET_XSAVES 64 483 #define X86FSET_SHA 65 484 #define X86FSET_UMIP 66 485 #define X86FSET_PKU 67 486 #define X86FSET_OSPKE 68 487 #define X86FSET_PCID 69 488 #define X86FSET_INVPCID 70 489 #define X86FSET_IBRS 71 490 #define X86FSET_IBPB 72 491 #define X86FSET_STIBP 73 492 #define X86FSET_SSBD 74 493 #define X86FSET_SSBD_VIRT 75 494 #define X86FSET_RDCL_NO 76 495 #define X86FSET_IBRS_ALL 77 496 #define X86FSET_RSBA 78 497 #define X86FSET_SSB_NO 79 498 #define X86FSET_STIBP_ALL 80 499 #define X86FSET_FLUSH_CMD 81 500 #define X86FSET_L1D_VM_NO 82 501 502 /* 503 * Intel Deep C-State invariant TSC in leaf 0x80000007. 504 */ 505 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 506 507 /* 508 * Intel Deep C-state always-running local APIC timer 509 */ 510 #define CPUID_CSTATE_ARAT (0x4) 511 512 /* 513 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 514 */ 515 #define CPUID_EPB_SUPPORT (1 << 3) 516 517 /* 518 * Intel TSC deadline timer 519 */ 520 #define CPUID_DEADLINE_TSC (1 << 24) 521 522 /* 523 * x86_type is a legacy concept; this is supplanted 524 * for most purposes by x86_featureset; modern CPUs 525 * should be X86_TYPE_OTHER 526 */ 527 #define X86_TYPE_OTHER 0 528 #define X86_TYPE_486 1 529 #define X86_TYPE_P5 2 530 #define X86_TYPE_P6 3 531 #define X86_TYPE_CYRIX_486 4 532 #define X86_TYPE_CYRIX_6x86L 5 533 #define X86_TYPE_CYRIX_6x86 6 534 #define X86_TYPE_CYRIX_GXm 7 535 #define X86_TYPE_CYRIX_6x86MX 8 536 #define X86_TYPE_CYRIX_MediaGX 9 537 #define X86_TYPE_CYRIX_MII 10 538 #define X86_TYPE_VIA_CYRIX_III 11 539 #define X86_TYPE_P4 12 540 541 /* 542 * x86_vendor allows us to select between 543 * implementation features and helps guide 544 * the interpretation of the cpuid instruction. 545 */ 546 #define X86_VENDOR_Intel 0 547 #define X86_VENDORSTR_Intel "GenuineIntel" 548 549 #define X86_VENDOR_IntelClone 1 550 551 #define X86_VENDOR_AMD 2 552 #define X86_VENDORSTR_AMD "AuthenticAMD" 553 554 #define X86_VENDOR_Cyrix 3 555 #define X86_VENDORSTR_CYRIX "CyrixInstead" 556 557 #define X86_VENDOR_UMC 4 558 #define X86_VENDORSTR_UMC "UMC UMC UMC " 559 560 #define X86_VENDOR_NexGen 5 561 #define X86_VENDORSTR_NexGen "NexGenDriven" 562 563 #define X86_VENDOR_Centaur 6 564 #define X86_VENDORSTR_Centaur "CentaurHauls" 565 566 #define X86_VENDOR_Rise 7 567 #define X86_VENDORSTR_Rise "RiseRiseRise" 568 569 #define X86_VENDOR_SiS 8 570 #define X86_VENDORSTR_SiS "SiS SiS SiS " 571 572 #define X86_VENDOR_TM 9 573 #define X86_VENDORSTR_TM "GenuineTMx86" 574 575 #define X86_VENDOR_NSC 10 576 #define X86_VENDORSTR_NSC "Geode by NSC" 577 578 /* 579 * Vendor string max len + \0 580 */ 581 #define X86_VENDOR_STRLEN 13 582 583 /* 584 * Some vendor/family/model/stepping ranges are commonly grouped under 585 * a single identifying banner by the vendor. The following encode 586 * that "revision" in a uint32_t with the 8 most significant bits 587 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 588 * family, and the remaining 16 typically forming a bitmask of revisions 589 * within that family with more significant bits indicating "later" revisions. 590 */ 591 592 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 593 #define _X86_CHIPREV_VENDOR_SHIFT 24 594 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 595 #define _X86_CHIPREV_FAMILY_SHIFT 16 596 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 597 598 #define _X86_CHIPREV_VENDOR(x) \ 599 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 600 #define _X86_CHIPREV_FAMILY(x) \ 601 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 602 #define _X86_CHIPREV_REV(x) \ 603 ((x) & _X86_CHIPREV_REV_MASK) 604 605 /* True if x matches in vendor and family and if x matches the given rev mask */ 606 #define X86_CHIPREV_MATCH(x, mask) \ 607 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 608 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 609 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 610 611 /* True if x matches in vendor and family, and rev is at least minx */ 612 #define X86_CHIPREV_ATLEAST(x, minx) \ 613 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 614 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 615 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 616 617 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 618 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 619 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 620 621 /* True if x matches in vendor, and family is at least minx */ 622 #define X86_CHIPFAM_ATLEAST(x, minx) \ 623 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 624 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 625 626 /* Revision default */ 627 #define X86_CHIPREV_UNKNOWN 0x0 628 629 /* 630 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 631 * sufficiently different that we will distinguish them; in all other 632 * case we will identify the major revision. 633 */ 634 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 635 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 636 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 637 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 638 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 639 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 640 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 641 642 /* 643 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 644 */ 645 #define X86_CHIPREV_AMD_10_REV_A \ 646 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 647 #define X86_CHIPREV_AMD_10_REV_B \ 648 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 649 #define X86_CHIPREV_AMD_10_REV_C2 \ 650 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 651 #define X86_CHIPREV_AMD_10_REV_C3 \ 652 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 653 #define X86_CHIPREV_AMD_10_REV_D0 \ 654 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 655 #define X86_CHIPREV_AMD_10_REV_D1 \ 656 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 657 #define X86_CHIPREV_AMD_10_REV_E \ 658 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 659 660 /* 661 * Definitions for AMD Family 0x11. 662 */ 663 #define X86_CHIPREV_AMD_11_REV_B \ 664 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 665 666 /* 667 * Definitions for AMD Family 0x12. 668 */ 669 #define X86_CHIPREV_AMD_12_REV_B \ 670 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 671 672 /* 673 * Definitions for AMD Family 0x14. 674 */ 675 #define X86_CHIPREV_AMD_14_REV_B \ 676 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 677 #define X86_CHIPREV_AMD_14_REV_C \ 678 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 679 680 /* 681 * Definitions for AMD Family 0x15 682 */ 683 #define X86_CHIPREV_AMD_15OR_REV_B2 \ 684 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 685 686 #define X86_CHIPREV_AMD_15TN_REV_A1 \ 687 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 688 689 /* 690 * Various socket/package types, extended as the need to distinguish 691 * a new type arises. The top 8 byte identfies the vendor and the 692 * remaining 24 bits describe 24 socket types. 693 */ 694 695 #define _X86_SOCKET_VENDOR_SHIFT 24 696 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 697 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 698 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 699 700 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 701 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 702 703 #define X86_SOCKET_MATCH(s, mask) \ 704 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 705 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 706 707 #define X86_SOCKET_UNKNOWN 0x0 708 /* 709 * AMD socket types 710 */ 711 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 712 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 713 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 714 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 715 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 716 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 717 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 718 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 719 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 720 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 721 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 722 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 723 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 724 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 725 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 726 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 727 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 728 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 729 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 730 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 731 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 732 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 733 734 735 /* 736 * Definitions for Intel processor models. Note, these model values can overlap 737 * in a given family. Processor models are added here on an as needed basis. The 738 * Xeon extension here is to refer to what has been called the EP/EX lines or 739 * E5/E7, generally multi-socket capable processors. 740 */ 741 #define INTC_MODEL_IVYBRIDGE_XEON 0x3E 742 #define INTC_MODEL_HASWELL_XEON 0x3F 743 #define INTC_MODEL_BROADWELL_XEON 0x4F 744 #define INTC_MODEL_BROADWELL_XEON_D 0x56 745 #define INTC_MODEL_SKYLAKE_XEON 0x55 746 747 /* 748 * xgetbv/xsetbv support 749 * See section 13.3 in vol. 1 of the Intel devlopers manual. 750 */ 751 752 #define XFEATURE_ENABLED_MASK 0x0 753 /* 754 * XFEATURE_ENABLED_MASK values (eax) 755 * See setup_xfem(). 756 */ 757 #define XFEATURE_LEGACY_FP 0x1 758 #define XFEATURE_SSE 0x2 759 #define XFEATURE_AVX 0x4 760 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ 761 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ 762 /* bit 8 unused */ 763 #define XFEATURE_PKRU 0x200 764 #define XFEATURE_FP_ALL \ 765 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 766 XFEATURE_AVX512 | XFEATURE_PKRU) 767 768 /* 769 * Define the set of xfeature flags that should be considered valid in the xsave 770 * state vector when we initialize an lwp. This is distinct from the full set so 771 * that all of the processor's normal logic and tracking of the xsave state is 772 * usable. This should correspond to the state that's been initialized by the 773 * ABI to hold meaningful values. Adding additional bits here can have serious 774 * performance implications and cause performance degradations when using the 775 * FPU vector (xmm) registers. 776 */ 777 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 778 779 #if !defined(_ASM) 780 781 #if defined(_KERNEL) || defined(_KMEMUSER) 782 783 #define NUM_X86_FEATURES 83 784 extern uchar_t x86_featureset[]; 785 786 extern void free_x86_featureset(void *featureset); 787 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 788 extern void add_x86_feature(void *featureset, uint_t feature); 789 extern void remove_x86_feature(void *featureset, uint_t feature); 790 extern boolean_t compare_x86_featureset(void *setA, void *setB); 791 extern void print_x86_featureset(void *featureset); 792 793 794 extern uint_t x86_type; 795 extern uint_t x86_vendor; 796 extern uint_t x86_clflush_size; 797 798 extern uint_t pentiumpro_bug4046376; 799 800 extern const char CyrixInstead[]; 801 802 #endif 803 804 #if defined(_KERNEL) 805 806 /* 807 * This structure is used to pass arguments and get return values back 808 * from the CPUID instruction in __cpuid_insn() routine. 809 */ 810 struct cpuid_regs { 811 uint32_t cp_eax; 812 uint32_t cp_ebx; 813 uint32_t cp_ecx; 814 uint32_t cp_edx; 815 }; 816 817 extern int x86_use_pcid; 818 extern int x86_use_invpcid; 819 820 /* 821 * Utility functions to get/set extended control registers (XCR) 822 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 823 */ 824 extern uint64_t get_xcr(uint_t); 825 extern void set_xcr(uint_t, uint64_t); 826 827 extern uint64_t rdmsr(uint_t); 828 extern void wrmsr(uint_t, const uint64_t); 829 extern uint64_t xrdmsr(uint_t); 830 extern void xwrmsr(uint_t, const uint64_t); 831 extern int checked_rdmsr(uint_t, uint64_t *); 832 extern int checked_wrmsr(uint_t, uint64_t); 833 834 extern void invalidate_cache(void); 835 extern ulong_t getcr4(void); 836 extern void setcr4(ulong_t); 837 838 extern void mtrr_sync(void); 839 840 extern void cpu_fast_syscall_enable(void); 841 extern void cpu_fast_syscall_disable(void); 842 843 struct cpu; 844 845 extern int cpuid_checkpass(struct cpu *, int); 846 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 847 extern uint32_t __cpuid_insn(struct cpuid_regs *); 848 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 849 extern int cpuid_getidstr(struct cpu *, char *, size_t); 850 extern const char *cpuid_getvendorstr(struct cpu *); 851 extern uint_t cpuid_getvendor(struct cpu *); 852 extern uint_t cpuid_getfamily(struct cpu *); 853 extern uint_t cpuid_getmodel(struct cpu *); 854 extern uint_t cpuid_getstep(struct cpu *); 855 extern uint_t cpuid_getsig(struct cpu *); 856 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 857 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 858 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 859 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 860 extern int cpuid_get_chipid(struct cpu *); 861 extern id_t cpuid_get_coreid(struct cpu *); 862 extern int cpuid_get_pkgcoreid(struct cpu *); 863 extern int cpuid_get_clogid(struct cpu *); 864 extern int cpuid_get_cacheid(struct cpu *); 865 extern uint32_t cpuid_get_apicid(struct cpu *); 866 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 867 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 868 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 869 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 870 extern size_t cpuid_get_xsave_size(); 871 extern boolean_t cpuid_need_fp_excp_handling(); 872 extern int cpuid_is_cmt(struct cpu *); 873 extern int cpuid_syscall32_insn(struct cpu *); 874 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 875 876 extern uint32_t cpuid_getchiprev(struct cpu *); 877 extern const char *cpuid_getchiprevstr(struct cpu *); 878 extern uint32_t cpuid_getsockettype(struct cpu *); 879 extern const char *cpuid_getsocketstr(struct cpu *); 880 881 extern int cpuid_have_cr8access(struct cpu *); 882 883 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 884 885 struct cpuid_info; 886 887 extern void setx86isalist(void); 888 extern void cpuid_alloc_space(struct cpu *); 889 extern void cpuid_free_space(struct cpu *); 890 extern void cpuid_pass1(struct cpu *, uchar_t *); 891 extern void cpuid_pass2(struct cpu *); 892 extern void cpuid_pass3(struct cpu *); 893 extern void cpuid_pass4(struct cpu *, uint_t *); 894 extern void cpuid_set_cpu_properties(void *, processorid_t, 895 struct cpuid_info *); 896 extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 897 extern void cpuid_post_ucodeadm(void); 898 899 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 900 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 901 902 #if !defined(__xpv) 903 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 904 extern void cpuid_mwait_free(struct cpu *); 905 extern int cpuid_deep_cstates_supported(void); 906 extern int cpuid_arat_supported(void); 907 extern int cpuid_iepb_supported(struct cpu *); 908 extern int cpuid_deadline_tsc_supported(void); 909 extern void vmware_port(int, uint32_t *); 910 #endif 911 912 struct cpu_ucode_info; 913 914 extern void ucode_alloc_space(struct cpu *); 915 extern void ucode_free_space(struct cpu *); 916 extern void ucode_check(struct cpu *); 917 extern void ucode_cleanup(); 918 919 #if !defined(__xpv) 920 extern char _tsc_mfence_start; 921 extern char _tsc_mfence_end; 922 extern char _tscp_start; 923 extern char _tscp_end; 924 extern char _no_rdtsc_start; 925 extern char _no_rdtsc_end; 926 extern char _tsc_lfence_start; 927 extern char _tsc_lfence_end; 928 #endif 929 930 #if !defined(__xpv) 931 extern char bcopy_patch_start; 932 extern char bcopy_patch_end; 933 extern char bcopy_ck_size; 934 #endif 935 936 extern void post_startup_cpu_fixups(void); 937 938 extern uint_t workaround_errata(struct cpu *); 939 940 #if defined(OPTERON_ERRATUM_93) 941 extern int opteron_erratum_93; 942 #endif 943 944 #if defined(OPTERON_ERRATUM_91) 945 extern int opteron_erratum_91; 946 #endif 947 948 #if defined(OPTERON_ERRATUM_100) 949 extern int opteron_erratum_100; 950 #endif 951 952 #if defined(OPTERON_ERRATUM_121) 953 extern int opteron_erratum_121; 954 #endif 955 956 #if defined(OPTERON_WORKAROUND_6323525) 957 extern int opteron_workaround_6323525; 958 extern void patch_workaround_6323525(void); 959 #endif 960 961 #if !defined(__xpv) 962 extern void determine_platform(void); 963 #endif 964 extern int get_hwenv(void); 965 extern int is_controldom(void); 966 967 extern void enable_pcid(void); 968 969 extern void xsave_setup_msr(struct cpu *); 970 971 #if !defined(__xpv) 972 extern void reset_gdtr_limit(void); 973 #endif 974 975 /* 976 * Hypervisor signatures 977 */ 978 #define HVSIG_XEN_HVM "XenVMMXenVMM" 979 #define HVSIG_VMWARE "VMwareVMware" 980 #define HVSIG_KVM "KVMKVMKVM" 981 #define HVSIG_MICROSOFT "Microsoft Hv" 982 #define HVSIG_BHYVE "bhyve bhyve " 983 984 /* 985 * Defined hardware environments 986 */ 987 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 988 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 989 990 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 991 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 992 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 993 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 994 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */ 995 996 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \ 997 HW_BHYVE) 998 999 #endif /* _KERNEL */ 1000 1001 #endif /* !_ASM */ 1002 1003 /* 1004 * VMware hypervisor related defines 1005 */ 1006 #define VMWARE_HVMAGIC 0x564d5868 1007 #define VMWARE_HVPORT 0x5658 1008 #define VMWARE_HVCMD_GETVERSION 0x0a 1009 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 1010 1011 #ifdef __cplusplus 1012 } 1013 #endif 1014 1015 #endif /* _SYS_X86_ARCHEXT_H */ 1016