xref: /illumos-gate/usr/src/uts/intel/sys/x86_archext.h (revision a9cc46cf4c50667eb8eaf3af6c3bc4a74677b725)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23  * Copyright (c) 2011 by Delphix. All rights reserved.
24  */
25 /*
26  * Copyright (c) 2010, Intel Corporation.
27  * All rights reserved.
28  */
29 /*
30  * Copyright 2019 Joyent, Inc.
31  * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32  * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33  * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34  * Copyright 2018 Nexenta Systems, Inc.
35  */
36 
37 #ifndef _SYS_X86_ARCHEXT_H
38 #define	_SYS_X86_ARCHEXT_H
39 
40 #if !defined(_ASM)
41 #include <sys/regset.h>
42 #include <sys/processor.h>
43 #include <vm/seg_enum.h>
44 #include <vm/page.h>
45 #endif	/* _ASM */
46 
47 #ifdef	__cplusplus
48 extern "C" {
49 #endif
50 
51 /*
52  * cpuid instruction feature flags in %edx (standard function 1)
53  */
54 
55 #define	CPUID_INTC_EDX_FPU	0x00000001	/* x87 fpu present */
56 #define	CPUID_INTC_EDX_VME	0x00000002	/* virtual-8086 extension */
57 #define	CPUID_INTC_EDX_DE	0x00000004	/* debugging extensions */
58 #define	CPUID_INTC_EDX_PSE	0x00000008	/* page size extension */
59 #define	CPUID_INTC_EDX_TSC	0x00000010	/* time stamp counter */
60 #define	CPUID_INTC_EDX_MSR	0x00000020	/* rdmsr and wrmsr */
61 #define	CPUID_INTC_EDX_PAE	0x00000040	/* physical addr extension */
62 #define	CPUID_INTC_EDX_MCE	0x00000080	/* machine check exception */
63 #define	CPUID_INTC_EDX_CX8	0x00000100	/* cmpxchg8b instruction */
64 #define	CPUID_INTC_EDX_APIC	0x00000200	/* local APIC */
65 						/* 0x400 - reserved */
66 #define	CPUID_INTC_EDX_SEP	0x00000800	/* sysenter and sysexit */
67 #define	CPUID_INTC_EDX_MTRR	0x00001000	/* memory type range reg */
68 #define	CPUID_INTC_EDX_PGE	0x00002000	/* page global enable */
69 #define	CPUID_INTC_EDX_MCA	0x00004000	/* machine check arch */
70 #define	CPUID_INTC_EDX_CMOV	0x00008000	/* conditional move insns */
71 #define	CPUID_INTC_EDX_PAT	0x00010000	/* page attribute table */
72 #define	CPUID_INTC_EDX_PSE36	0x00020000	/* 36-bit pagesize extension */
73 #define	CPUID_INTC_EDX_PSN	0x00040000	/* processor serial number */
74 #define	CPUID_INTC_EDX_CLFSH	0x00080000	/* clflush instruction */
75 						/* 0x100000 - reserved */
76 #define	CPUID_INTC_EDX_DS	0x00200000	/* debug store exists */
77 #define	CPUID_INTC_EDX_ACPI	0x00400000	/* monitoring + clock ctrl */
78 #define	CPUID_INTC_EDX_MMX	0x00800000	/* MMX instructions */
79 #define	CPUID_INTC_EDX_FXSR	0x01000000	/* fxsave and fxrstor */
80 #define	CPUID_INTC_EDX_SSE	0x02000000	/* streaming SIMD extensions */
81 #define	CPUID_INTC_EDX_SSE2	0x04000000	/* SSE extensions */
82 #define	CPUID_INTC_EDX_SS	0x08000000	/* self-snoop */
83 #define	CPUID_INTC_EDX_HTT	0x10000000	/* Hyper Thread Technology */
84 #define	CPUID_INTC_EDX_TM	0x20000000	/* thermal monitoring */
85 #define	CPUID_INTC_EDX_IA64	0x40000000	/* Itanium emulating IA32 */
86 #define	CPUID_INTC_EDX_PBE	0x80000000	/* Pending Break Enable */
87 
88 /*
89  * cpuid instruction feature flags in %ecx (standard function 1)
90  */
91 
92 #define	CPUID_INTC_ECX_SSE3	0x00000001	/* Yet more SSE extensions */
93 #define	CPUID_INTC_ECX_PCLMULQDQ 0x00000002	/* PCLMULQDQ insn */
94 #define	CPUID_INTC_ECX_DTES64	0x00000004	/* 64-bit DS area */
95 #define	CPUID_INTC_ECX_MON	0x00000008	/* MONITOR/MWAIT */
96 #define	CPUID_INTC_ECX_DSCPL	0x00000010	/* CPL-qualified debug store */
97 #define	CPUID_INTC_ECX_VMX	0x00000020	/* Hardware VM extensions */
98 #define	CPUID_INTC_ECX_SMX	0x00000040	/* Secure mode extensions */
99 #define	CPUID_INTC_ECX_EST	0x00000080	/* enhanced SpeedStep */
100 #define	CPUID_INTC_ECX_TM2	0x00000100	/* thermal monitoring */
101 #define	CPUID_INTC_ECX_SSSE3	0x00000200	/* Supplemental SSE3 insns */
102 #define	CPUID_INTC_ECX_CID	0x00000400	/* L1 context ID */
103 						/* 0x00000800 - reserved */
104 #define	CPUID_INTC_ECX_FMA	0x00001000	/* Fused Multiply Add */
105 #define	CPUID_INTC_ECX_CX16	0x00002000	/* cmpxchg16 */
106 #define	CPUID_INTC_ECX_ETPRD	0x00004000	/* extended task pri messages */
107 #define	CPUID_INTC_ECX_PDCM	0x00008000	/* Perf/Debug Capability MSR */
108 						/* 0x00010000 - reserved */
109 #define	CPUID_INTC_ECX_PCID	0x00020000	/* process-context ids */
110 #define	CPUID_INTC_ECX_DCA	0x00040000	/* direct cache access */
111 #define	CPUID_INTC_ECX_SSE4_1	0x00080000	/* SSE4.1 insns */
112 #define	CPUID_INTC_ECX_SSE4_2	0x00100000	/* SSE4.2 insns */
113 #define	CPUID_INTC_ECX_X2APIC	0x00200000	/* x2APIC */
114 #define	CPUID_INTC_ECX_MOVBE	0x00400000	/* MOVBE insn */
115 #define	CPUID_INTC_ECX_POPCNT	0x00800000	/* POPCNT insn */
116 #define	CPUID_INTC_ECX_TSCDL	0x01000000	/* Deadline TSC */
117 #define	CPUID_INTC_ECX_AES	0x02000000	/* AES insns */
118 #define	CPUID_INTC_ECX_XSAVE	0x04000000	/* XSAVE/XRESTOR insns */
119 #define	CPUID_INTC_ECX_OSXSAVE	0x08000000	/* OS supports XSAVE insns */
120 #define	CPUID_INTC_ECX_AVX	0x10000000	/* AVX supported */
121 #define	CPUID_INTC_ECX_F16C	0x20000000	/* F16C supported */
122 #define	CPUID_INTC_ECX_RDRAND	0x40000000	/* RDRAND supported */
123 #define	CPUID_INTC_ECX_HV	0x80000000	/* Hypervisor */
124 
125 /*
126  * cpuid instruction feature flags in %edx (extended function 0x80000001)
127  */
128 
129 #define	CPUID_AMD_EDX_FPU	0x00000001	/* x87 fpu present */
130 #define	CPUID_AMD_EDX_VME	0x00000002	/* virtual-8086 extension */
131 #define	CPUID_AMD_EDX_DE	0x00000004	/* debugging extensions */
132 #define	CPUID_AMD_EDX_PSE	0x00000008	/* page size extensions */
133 #define	CPUID_AMD_EDX_TSC	0x00000010	/* time stamp counter */
134 #define	CPUID_AMD_EDX_MSR	0x00000020	/* rdmsr and wrmsr */
135 #define	CPUID_AMD_EDX_PAE	0x00000040	/* physical addr extension */
136 #define	CPUID_AMD_EDX_MCE	0x00000080	/* machine check exception */
137 #define	CPUID_AMD_EDX_CX8	0x00000100	/* cmpxchg8b instruction */
138 #define	CPUID_AMD_EDX_APIC	0x00000200	/* local APIC */
139 						/* 0x00000400 - sysc on K6m6 */
140 #define	CPUID_AMD_EDX_SYSC	0x00000800	/* AMD: syscall and sysret */
141 #define	CPUID_AMD_EDX_MTRR	0x00001000	/* memory type and range reg */
142 #define	CPUID_AMD_EDX_PGE	0x00002000	/* page global enable */
143 #define	CPUID_AMD_EDX_MCA	0x00004000	/* machine check arch */
144 #define	CPUID_AMD_EDX_CMOV	0x00008000	/* conditional move insns */
145 #define	CPUID_AMD_EDX_PAT	0x00010000	/* K7: page attribute table */
146 #define	CPUID_AMD_EDX_FCMOV	0x00010000	/* FCMOVcc etc. */
147 #define	CPUID_AMD_EDX_PSE36	0x00020000	/* 36-bit pagesize extension */
148 				/* 0x00040000 - reserved */
149 				/* 0x00080000 - reserved */
150 #define	CPUID_AMD_EDX_NX	0x00100000	/* AMD: no-execute page prot */
151 				/* 0x00200000 - reserved */
152 #define	CPUID_AMD_EDX_MMXamd	0x00400000	/* AMD: MMX extensions */
153 #define	CPUID_AMD_EDX_MMX	0x00800000	/* MMX instructions */
154 #define	CPUID_AMD_EDX_FXSR	0x01000000	/* fxsave and fxrstor */
155 #define	CPUID_AMD_EDX_FFXSR	0x02000000	/* fast fxsave/fxrstor */
156 #define	CPUID_AMD_EDX_1GPG	0x04000000	/* 1GB page */
157 #define	CPUID_AMD_EDX_TSCP	0x08000000	/* rdtscp instruction */
158 				/* 0x10000000 - reserved */
159 #define	CPUID_AMD_EDX_LM	0x20000000	/* AMD: long mode */
160 #define	CPUID_AMD_EDX_3DNowx	0x40000000	/* AMD: extensions to 3DNow! */
161 #define	CPUID_AMD_EDX_3DNow	0x80000000	/* AMD: 3DNow! instructions */
162 
163 /*
164  * AMD extended function 0x80000001 %ecx
165  */
166 
167 #define	CPUID_AMD_ECX_AHF64	0x00000001	/* LAHF and SAHF in long mode */
168 #define	CPUID_AMD_ECX_CMP_LGCY	0x00000002	/* AMD: multicore chip */
169 #define	CPUID_AMD_ECX_SVM	0x00000004	/* AMD: secure VM */
170 #define	CPUID_AMD_ECX_EAS	0x00000008	/* extended apic space */
171 #define	CPUID_AMD_ECX_CR8D	0x00000010	/* AMD: 32-bit mov %cr8 */
172 #define	CPUID_AMD_ECX_LZCNT	0x00000020	/* AMD: LZCNT insn */
173 #define	CPUID_AMD_ECX_SSE4A	0x00000040	/* AMD: SSE4A insns */
174 #define	CPUID_AMD_ECX_MAS	0x00000080	/* AMD: MisAlignSse mnode */
175 #define	CPUID_AMD_ECX_3DNP	0x00000100	/* AMD: 3DNowPrefectch */
176 #define	CPUID_AMD_ECX_OSVW	0x00000200	/* AMD: OSVW */
177 #define	CPUID_AMD_ECX_IBS	0x00000400	/* AMD: IBS */
178 #define	CPUID_AMD_ECX_XOP	0x00000800	/* AMD: Extended Operation */
179 #define	CPUID_AMD_ECX_SKINIT	0x00001000	/* AMD: SKINIT */
180 #define	CPUID_AMD_ECX_WDT	0x00002000	/* AMD: WDT */
181 				/* 0x00004000 - reserved */
182 #define	CPUID_AMD_ECX_LWP	0x00008000	/* AMD: Lightweight profiling */
183 #define	CPUID_AMD_ECX_FMA4	0x00010000	/* AMD: 4-operand FMA support */
184 				/* 0x00020000 - reserved */
185 				/* 0x00040000 - reserved */
186 #define	CPUID_AMD_ECX_NIDMSR	0x00080000	/* AMD: Node ID MSR */
187 				/* 0x00100000 - reserved */
188 #define	CPUID_AMD_ECX_TBM	0x00200000	/* AMD: trailing bit manips. */
189 #define	CPUID_AMD_ECX_TOPOEXT	0x00400000	/* AMD: Topology Extensions */
190 #define	CPUID_AMD_ECX_PCEC	0x00800000	/* AMD: Core ext perf counter */
191 #define	CUPID_AMD_ECX_PCENB	0x01000000	/* AMD: NB ext perf counter */
192 				/* 0x02000000 - reserved */
193 #define	CPUID_AMD_ECX_DBKP	0x40000000	/* AMD: Data breakpoint */
194 #define	CPUID_AMD_ECX_PERFTSC	0x08000000	/* AMD: TSC Perf Counter */
195 #define	CPUID_AMD_ECX_PERFL3	0x10000000	/* AMD: L3 Perf Counter */
196 #define	CPUID_AMD_ECX_MONITORX	0x20000000	/* AMD: clzero */
197 				/* 0x40000000 - reserved */
198 				/* 0x80000000 - reserved */
199 
200 /*
201  * AMD uses %ebx for some of their features (extended function 0x80000008).
202  */
203 #define	CPUID_AMD_EBX_CLZERO		0x000000001 /* AMD: CLZERO instr */
204 #define	CPUID_AMD_EBX_IRCMSR		0x000000002 /* AMD: Ret. instrs MSR */
205 #define	CPUID_AMD_EBX_ERR_PTR_ZERO	0x000000004 /* AMD: FP Err. Ptr. Zero */
206 #define	CPUID_AMD_EBX_IBPB		0x000001000 /* AMD: IBPB */
207 #define	CPUID_AMD_EBX_IBRS		0x000004000 /* AMD: IBRS */
208 #define	CPUID_AMD_EBX_STIBP		0x000008000 /* AMD: STIBP */
209 #define	CPUID_AMD_EBX_IBRS_ALL		0x000010000 /* AMD: Enhanced IBRS */
210 #define	CPUID_AMD_EBX_STIBP_ALL		0x000020000 /* AMD: STIBP ALL */
211 #define	CPUID_AMD_EBX_PREFER_IBRS	0x000040000 /* AMD: Don't retpoline */
212 #define	CPUID_AMD_EBX_SSBD		0x001000000 /* AMD: SSBD */
213 #define	CPUID_AMD_EBX_VIRT_SSBD		0x002000000 /* AMD: VIRT SSBD */
214 #define	CPUID_AMD_EBX_SSB_NO		0x004000000 /* AMD: SSB Fixed */
215 
216 /*
217  * Intel now seems to have claimed part of the "extended" function
218  * space that we previously for non-Intel implementors to use.
219  * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
220  * is available in long mode i.e. what AMD indicate using bit 0.
221  * On the other hand, everything else is labelled as reserved.
222  */
223 #define	CPUID_INTC_ECX_AHF64	0x00100000	/* LAHF and SAHF in long mode */
224 
225 /*
226  * Intel also uses cpuid leaf 7 to have additional instructions and features.
227  * Like some other leaves, but unlike the current ones we care about, it
228  * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
229  * with the potential use of additional sub-leaves in the future, we now
230  * specifically label the EBX features with their leaf and sub-leaf.
231  */
232 #define	CPUID_INTC_EBX_7_0_FSGSBASE	0x00000001	/* FSGSBASE */
233 #define	CPUID_INTC_EBX_7_0_TSC_ADJ	0x00000002	/* TSC adjust MSR */
234 #define	CPUID_INTC_EBX_7_0_SGX		0x00000004	/* SGX */
235 #define	CPUID_INTC_EBX_7_0_BMI1		0x00000008	/* BMI1 instrs */
236 #define	CPUID_INTC_EBX_7_0_HLE		0x00000010	/* HLE */
237 #define	CPUID_INTC_EBX_7_0_AVX2		0x00000020	/* AVX2 supported */
238 /* Bit 6 is reserved */
239 #define	CPUID_INTC_EBX_7_0_SMEP		0x00000080	/* SMEP in CR4 */
240 #define	CPUID_INTC_EBX_7_0_BMI2		0x00000100	/* BMI2 instrs */
241 #define	CPUID_INTC_EBX_7_0_ENH_REP_MOV	0x00000200	/* Enhanced REP MOVSB */
242 #define	CPUID_INTC_EBX_7_0_INVPCID	0x00000400	/* invpcid instr */
243 #define	CPUID_INTC_EBX_7_0_RTM		0x00000800	/* RTM instrs */
244 #define	CPUID_INTC_EBX_7_0_PQM		0x00001000	/* QoS Monitoring */
245 #define	CPUID_INTC_EBX_7_0_DEP_CSDS	0x00002000	/* Deprecates CS/DS */
246 #define	CPUID_INTC_EBX_7_0_MPX		0x00004000	/* Mem. Prot. Ext. */
247 #define	CPUID_INTC_EBX_7_0_PQE		0x00080000	/* QoS Enforcement */
248 #define	CPUID_INTC_EBX_7_0_AVX512F	0x00010000	/* AVX512 foundation */
249 #define	CPUID_INTC_EBX_7_0_AVX512DQ	0x00020000	/* AVX512DQ */
250 #define	CPUID_INTC_EBX_7_0_RDSEED	0x00040000	/* RDSEED instr */
251 #define	CPUID_INTC_EBX_7_0_ADX		0x00080000	/* ADX instrs */
252 #define	CPUID_INTC_EBX_7_0_SMAP		0x00100000	/* SMAP in CR 4 */
253 #define	CPUID_INTC_EBX_7_0_AVX512IFMA	0x00200000	/* AVX512IFMA */
254 /* Bit 22 is reserved */
255 #define	CPUID_INTC_EBX_7_0_CLFLUSHOPT	0x00800000	/* CLFLUSOPT */
256 #define	CPUID_INTC_EBX_7_0_CLWB		0x01000000	/* CLWB */
257 #define	CPUID_INTC_EBX_7_0_PTRACE	0x02000000	/* Processor Trace */
258 #define	CPUID_INTC_EBX_7_0_AVX512PF	0x04000000	/* AVX512PF */
259 #define	CPUID_INTC_EBX_7_0_AVX512ER	0x08000000	/* AVX512ER */
260 #define	CPUID_INTC_EBX_7_0_AVX512CD	0x10000000	/* AVX512CD */
261 #define	CPUID_INTC_EBX_7_0_SHA		0x20000000	/* SHA extensions */
262 #define	CPUID_INTC_EBX_7_0_AVX512BW	0x40000000	/* AVX512BW */
263 #define	CPUID_INTC_EBX_7_0_AVX512VL	0x80000000	/* AVX512VL */
264 
265 #define	CPUID_INTC_EBX_7_0_ALL_AVX512 \
266 	(CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
267 	CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
268 	CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
269 	CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
270 
271 #define	CPUID_INTC_ECX_7_0_PREFETCHWT1	0x00000001	/* PREFETCHWT1 */
272 #define	CPUID_INTC_ECX_7_0_AVX512VBMI	0x00000002	/* AVX512VBMI */
273 #define	CPUID_INTC_ECX_7_0_UMIP		0x00000004	/* UMIP */
274 #define	CPUID_INTC_ECX_7_0_PKU		0x00000008	/* umode prot. keys */
275 #define	CPUID_INTC_ECX_7_0_OSPKE	0x00000010	/* OSPKE */
276 #define	CPUID_INTC_ECX_7_0_WAITPKG	0x00000020	/* WAITPKG */
277 #define	CPUID_INTC_ECX_7_0_AVX512VBMI2	0x00000040	/* AVX512 VBMI2 */
278 /* bit 7 is reserved */
279 #define	CPUID_INTC_ECX_7_0_GFNI		0x00000100	/* GFNI */
280 #define	CPUID_INTC_ECX_7_0_VAES		0x00000200	/* VAES */
281 #define	CPUID_INTC_ECX_7_0_VPCLMULQDQ	0x00000400	/* VPCLMULQDQ */
282 #define	CPUID_INTC_ECX_7_0_AVX512VNNI	0x00000800	/* AVX512 VNNI */
283 #define	CPUID_INTC_ECX_7_0_AVX512BITALG	0x00001000	/* AVX512 BITALG */
284 /* bit 13 is reserved */
285 #define	CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000	/* AVX512 VPOPCNTDQ */
286 /* bits 15-16 are reserved */
287 /* bits 17-21 are the value of MAWAU */
288 #define	CPUID_INTC_ECX_7_0_RDPID	0x00400000	/* RPID, IA32_TSC_AUX */
289 /* bits 23-24 are reserved */
290 #define	CPUID_INTC_ECX_7_0_CLDEMOTE	0x02000000	/* Cache line demote */
291 /* bit 26 is resrved */
292 #define	CPUID_INTC_ECX_7_0_MOVDIRI	0x08000000	/* MOVDIRI insn */
293 #define	CPUID_INTC_ECX_7_0_MOVDIR64B	0x10000000	/* MOVDIR64B insn */
294 /* bit 29 is reserved */
295 #define	CPUID_INTC_ECX_7_0_SGXLC	0x40000000	/* SGX Launch config */
296 /* bit 31 is reserved */
297 
298 /*
299  * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and
300  * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still
301  * valid when AVX512 is not. However, the following flags all are only valid
302  * when AVX512 is present.
303  */
304 #define	CPUID_INTC_ECX_7_0_ALL_AVX512 \
305 	(CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \
306 	CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
307 
308 /* bits 0-1 are reserved */
309 #define	CPUID_INTC_EDX_7_0_AVX5124NNIW	0x00000004	/* AVX512 4NNIW */
310 #define	CPUID_INTC_EDX_7_0_AVX5124FMAPS	0x00000008	/* AVX512 4FMAPS */
311 #define	CPUID_INTC_EDX_7_0_FSREPMOV	0x00000010	/* fast short rep mov */
312 /* bits 5-9 are reserved */
313 #define	CPUID_INTC_EDX_7_0_MD_CLEAR	0x00000400	/* MB VERW */
314 /* bits 11-17 are reserved */
315 #define	CPUID_INTC_EDX_7_0_PCONFIG	0x00040000	/* PCONFIG */
316 /* bits 19-26 are reserved */
317 #define	CPUID_INTC_EDX_7_0_SPEC_CTRL	0x04000000	/* Spec, IBPB, IBRS */
318 #define	CPUID_INTC_EDX_7_0_STIBP	0x08000000	/* STIBP */
319 #define	CPUID_INTC_EDX_7_0_FLUSH_CMD	0x10000000	/* IA32_FLUSH_CMD */
320 #define	CPUID_INTC_EDX_7_0_ARCH_CAPS	0x20000000	/* IA32_ARCH_CAPS */
321 #define	CPUID_INTC_EDX_7_0_SSBD		0x80000000	/* SSBD */
322 
323 #define	CPUID_INTC_EDX_7_0_ALL_AVX512 \
324 	(CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS)
325 
326 /*
327  * Intel also uses cpuid leaf 0xd to report additional instructions and features
328  * when the sub-leaf in %ecx == 1. We label these using the same convention as
329  * with leaf 7.
330  */
331 #define	CPUID_INTC_EAX_D_1_XSAVEOPT	0x00000001	/* xsaveopt inst. */
332 #define	CPUID_INTC_EAX_D_1_XSAVEC	0x00000002	/* xsavec inst. */
333 #define	CPUID_INTC_EAX_D_1_XSAVES	0x00000008	/* xsaves inst. */
334 
335 #define	REG_PAT			0x277
336 #define	REG_TSC			0x10	/* timestamp counter */
337 #define	REG_APIC_BASE_MSR	0x1b
338 #define	REG_X2APIC_BASE_MSR	0x800	/* The MSR address offset of x2APIC */
339 
340 #if !defined(__xpv)
341 /*
342  * AMD C1E
343  */
344 #define	MSR_AMD_INT_PENDING_CMP_HALT	0xC0010055
345 #define	AMD_ACTONCMPHALT_SHIFT	27
346 #define	AMD_ACTONCMPHALT_MASK	3
347 #endif
348 
349 #define	MSR_DEBUGCTL		0x1d9
350 
351 #define	DEBUGCTL_LBR		0x01
352 #define	DEBUGCTL_BTF		0x02
353 
354 /* Intel P6, AMD */
355 #define	MSR_LBR_FROM		0x1db
356 #define	MSR_LBR_TO		0x1dc
357 #define	MSR_LEX_FROM		0x1dd
358 #define	MSR_LEX_TO		0x1de
359 
360 /* Intel P4 (pre-Prescott, non P4 M) */
361 #define	MSR_P4_LBSTK_TOS	0x1da
362 #define	MSR_P4_LBSTK_0		0x1db
363 #define	MSR_P4_LBSTK_1		0x1dc
364 #define	MSR_P4_LBSTK_2		0x1dd
365 #define	MSR_P4_LBSTK_3		0x1de
366 
367 /* Intel Pentium M */
368 #define	MSR_P6M_LBSTK_TOS	0x1c9
369 #define	MSR_P6M_LBSTK_0		0x040
370 #define	MSR_P6M_LBSTK_1		0x041
371 #define	MSR_P6M_LBSTK_2		0x042
372 #define	MSR_P6M_LBSTK_3		0x043
373 #define	MSR_P6M_LBSTK_4		0x044
374 #define	MSR_P6M_LBSTK_5		0x045
375 #define	MSR_P6M_LBSTK_6		0x046
376 #define	MSR_P6M_LBSTK_7		0x047
377 
378 /* Intel P4 (Prescott) */
379 #define	MSR_PRP4_LBSTK_TOS	0x1da
380 #define	MSR_PRP4_LBSTK_FROM_0	0x680
381 #define	MSR_PRP4_LBSTK_FROM_1	0x681
382 #define	MSR_PRP4_LBSTK_FROM_2	0x682
383 #define	MSR_PRP4_LBSTK_FROM_3	0x683
384 #define	MSR_PRP4_LBSTK_FROM_4	0x684
385 #define	MSR_PRP4_LBSTK_FROM_5	0x685
386 #define	MSR_PRP4_LBSTK_FROM_6	0x686
387 #define	MSR_PRP4_LBSTK_FROM_7	0x687
388 #define	MSR_PRP4_LBSTK_FROM_8	0x688
389 #define	MSR_PRP4_LBSTK_FROM_9	0x689
390 #define	MSR_PRP4_LBSTK_FROM_10	0x68a
391 #define	MSR_PRP4_LBSTK_FROM_11	0x68b
392 #define	MSR_PRP4_LBSTK_FROM_12	0x68c
393 #define	MSR_PRP4_LBSTK_FROM_13	0x68d
394 #define	MSR_PRP4_LBSTK_FROM_14	0x68e
395 #define	MSR_PRP4_LBSTK_FROM_15	0x68f
396 #define	MSR_PRP4_LBSTK_TO_0	0x6c0
397 #define	MSR_PRP4_LBSTK_TO_1	0x6c1
398 #define	MSR_PRP4_LBSTK_TO_2	0x6c2
399 #define	MSR_PRP4_LBSTK_TO_3	0x6c3
400 #define	MSR_PRP4_LBSTK_TO_4	0x6c4
401 #define	MSR_PRP4_LBSTK_TO_5	0x6c5
402 #define	MSR_PRP4_LBSTK_TO_6	0x6c6
403 #define	MSR_PRP4_LBSTK_TO_7	0x6c7
404 #define	MSR_PRP4_LBSTK_TO_8	0x6c8
405 #define	MSR_PRP4_LBSTK_TO_9	0x6c9
406 #define	MSR_PRP4_LBSTK_TO_10	0x6ca
407 #define	MSR_PRP4_LBSTK_TO_11	0x6cb
408 #define	MSR_PRP4_LBSTK_TO_12	0x6cc
409 #define	MSR_PRP4_LBSTK_TO_13	0x6cd
410 #define	MSR_PRP4_LBSTK_TO_14	0x6ce
411 #define	MSR_PRP4_LBSTK_TO_15	0x6cf
412 
413 /*
414  * General Xeon based MSRs
415  */
416 #define	MSR_PPIN_CTL		0x04e
417 #define	MSR_PPIN		0x04f
418 #define	MSR_PLATFORM_INFO	0x0ce
419 
420 #define	MSR_PLATFORM_INFO_PPIN	(1 << 23)
421 #define	MSR_PPIN_CTL_MASK	0x03
422 #define	MSR_PPIN_CTL_LOCKED	0x01
423 #define	MSR_PPIN_CTL_ENABLED	0x02
424 
425 /*
426  * Intel IA32_ARCH_CAPABILITIES MSR.
427  */
428 #define	MSR_IA32_ARCH_CAPABILITIES		0x10a
429 #define	IA32_ARCH_CAP_RDCL_NO			0x0001
430 #define	IA32_ARCH_CAP_IBRS_ALL			0x0002
431 #define	IA32_ARCH_CAP_RSBA			0x0004
432 #define	IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY	0x0008
433 #define	IA32_ARCH_CAP_SSB_NO			0x0010
434 #define	IA32_ARCH_CAP_MDS_NO			0x0020
435 
436 /*
437  * Intel Speculation related MSRs
438  */
439 #define	MSR_IA32_SPEC_CTRL	0x48
440 #define	IA32_SPEC_CTRL_IBRS	0x01
441 #define	IA32_SPEC_CTRL_STIBP	0x02
442 #define	IA32_SPEC_CTRL_SSBD	0x04
443 
444 #define	MSR_IA32_PRED_CMD	0x49
445 #define	IA32_PRED_CMD_IBPB	0x01
446 
447 #define	MSR_IA32_FLUSH_CMD	0x10b
448 #define	IA32_FLUSH_CMD_L1D	0x01
449 
450 #define	MCI_CTL_VALUE		0xffffffff
451 
452 #define	MTRR_TYPE_UC		0
453 #define	MTRR_TYPE_WC		1
454 #define	MTRR_TYPE_WT		4
455 #define	MTRR_TYPE_WP		5
456 #define	MTRR_TYPE_WB		6
457 #define	MTRR_TYPE_UC_		7
458 
459 /*
460  * For Solaris we set up the page attritubute table in the following way:
461  * PAT0	Write-Back
462  * PAT1	Write-Through
463  * PAT2	Unchacheable-
464  * PAT3	Uncacheable
465  * PAT4 Write-Back
466  * PAT5	Write-Through
467  * PAT6	Write-Combine
468  * PAT7 Uncacheable
469  * The only difference from h/w default is entry 6.
470  */
471 #define	PAT_DEFAULT_ATTRIBUTE			\
472 	((uint64_t)MTRR_TYPE_WB |		\
473 	((uint64_t)MTRR_TYPE_WT << 8) |		\
474 	((uint64_t)MTRR_TYPE_UC_ << 16) |	\
475 	((uint64_t)MTRR_TYPE_UC << 24) |	\
476 	((uint64_t)MTRR_TYPE_WB << 32) |	\
477 	((uint64_t)MTRR_TYPE_WT << 40) |	\
478 	((uint64_t)MTRR_TYPE_WC << 48) |	\
479 	((uint64_t)MTRR_TYPE_UC << 56))
480 
481 #define	X86FSET_LARGEPAGE	0
482 #define	X86FSET_TSC		1
483 #define	X86FSET_MSR		2
484 #define	X86FSET_MTRR		3
485 #define	X86FSET_PGE		4
486 #define	X86FSET_DE		5
487 #define	X86FSET_CMOV		6
488 #define	X86FSET_MMX		7
489 #define	X86FSET_MCA		8
490 #define	X86FSET_PAE		9
491 #define	X86FSET_CX8		10
492 #define	X86FSET_PAT		11
493 #define	X86FSET_SEP		12
494 #define	X86FSET_SSE		13
495 #define	X86FSET_SSE2		14
496 #define	X86FSET_HTT		15
497 #define	X86FSET_ASYSC		16
498 #define	X86FSET_NX		17
499 #define	X86FSET_SSE3		18
500 #define	X86FSET_CX16		19
501 #define	X86FSET_CMP		20
502 #define	X86FSET_TSCP		21
503 #define	X86FSET_MWAIT		22
504 #define	X86FSET_SSE4A		23
505 #define	X86FSET_CPUID		24
506 #define	X86FSET_SSSE3		25
507 #define	X86FSET_SSE4_1		26
508 #define	X86FSET_SSE4_2		27
509 #define	X86FSET_1GPG		28
510 #define	X86FSET_CLFSH		29
511 #define	X86FSET_64		30
512 #define	X86FSET_AES		31
513 #define	X86FSET_PCLMULQDQ	32
514 #define	X86FSET_XSAVE		33
515 #define	X86FSET_AVX		34
516 #define	X86FSET_VMX		35
517 #define	X86FSET_SVM		36
518 #define	X86FSET_TOPOEXT		37
519 #define	X86FSET_F16C		38
520 #define	X86FSET_RDRAND		39
521 #define	X86FSET_X2APIC		40
522 #define	X86FSET_AVX2		41
523 #define	X86FSET_BMI1		42
524 #define	X86FSET_BMI2		43
525 #define	X86FSET_FMA		44
526 #define	X86FSET_SMEP		45
527 #define	X86FSET_SMAP		46
528 #define	X86FSET_ADX		47
529 #define	X86FSET_RDSEED		48
530 #define	X86FSET_MPX		49
531 #define	X86FSET_AVX512F		50
532 #define	X86FSET_AVX512DQ	51
533 #define	X86FSET_AVX512PF	52
534 #define	X86FSET_AVX512ER	53
535 #define	X86FSET_AVX512CD	54
536 #define	X86FSET_AVX512BW	55
537 #define	X86FSET_AVX512VL	56
538 #define	X86FSET_AVX512FMA	57
539 #define	X86FSET_AVX512VBMI	58
540 #define	X86FSET_AVX512VPOPCDQ	59
541 #define	X86FSET_AVX512NNIW	60
542 #define	X86FSET_AVX512FMAPS	61
543 #define	X86FSET_XSAVEOPT	62
544 #define	X86FSET_XSAVEC		63
545 #define	X86FSET_XSAVES		64
546 #define	X86FSET_SHA		65
547 #define	X86FSET_UMIP		66
548 #define	X86FSET_PKU		67
549 #define	X86FSET_OSPKE		68
550 #define	X86FSET_PCID		69
551 #define	X86FSET_INVPCID		70
552 #define	X86FSET_IBRS		71
553 #define	X86FSET_IBPB		72
554 #define	X86FSET_STIBP		73
555 #define	X86FSET_SSBD		74
556 #define	X86FSET_SSBD_VIRT	75
557 #define	X86FSET_RDCL_NO		76
558 #define	X86FSET_IBRS_ALL	77
559 #define	X86FSET_RSBA		78
560 #define	X86FSET_SSB_NO		79
561 #define	X86FSET_STIBP_ALL	80
562 #define	X86FSET_FLUSH_CMD	81
563 #define	X86FSET_L1D_VM_NO	82
564 #define	X86FSET_FSGSBASE	83
565 #define	X86FSET_CLFLUSHOPT	84
566 #define	X86FSET_CLWB		85
567 #define	X86FSET_MONITORX	86
568 #define	X86FSET_CLZERO		87
569 #define	X86FSET_XOP		88
570 #define	X86FSET_FMA4		89
571 #define	X86FSET_TBM		90
572 #define	X86FSET_AVX512VNNI	91
573 #define	X86FSET_AMD_PCEC	92
574 #define	X86FSET_MD_CLEAR	93
575 #define	X86FSET_MDS_NO		94
576 
577 /*
578  * Intel Deep C-State invariant TSC in leaf 0x80000007.
579  */
580 #define	CPUID_TSC_CSTATE_INVARIANCE	(0x100)
581 
582 /*
583  * Intel Deep C-state always-running local APIC timer
584  */
585 #define	CPUID_CSTATE_ARAT	(0x4)
586 
587 /*
588  * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
589  */
590 #define	CPUID_EPB_SUPPORT	(1 << 3)
591 
592 /*
593  * Intel TSC deadline timer
594  */
595 #define	CPUID_DEADLINE_TSC	(1 << 24)
596 
597 /*
598  * x86_type is a legacy concept; this is supplanted
599  * for most purposes by x86_featureset; modern CPUs
600  * should be X86_TYPE_OTHER
601  */
602 #define	X86_TYPE_OTHER		0
603 #define	X86_TYPE_486		1
604 #define	X86_TYPE_P5		2
605 #define	X86_TYPE_P6		3
606 #define	X86_TYPE_CYRIX_486	4
607 #define	X86_TYPE_CYRIX_6x86L	5
608 #define	X86_TYPE_CYRIX_6x86	6
609 #define	X86_TYPE_CYRIX_GXm	7
610 #define	X86_TYPE_CYRIX_6x86MX	8
611 #define	X86_TYPE_CYRIX_MediaGX	9
612 #define	X86_TYPE_CYRIX_MII	10
613 #define	X86_TYPE_VIA_CYRIX_III	11
614 #define	X86_TYPE_P4		12
615 
616 /*
617  * x86_vendor allows us to select between
618  * implementation features and helps guide
619  * the interpretation of the cpuid instruction.
620  */
621 #define	X86_VENDOR_Intel	0
622 #define	X86_VENDORSTR_Intel	"GenuineIntel"
623 
624 #define	X86_VENDOR_IntelClone	1
625 
626 #define	X86_VENDOR_AMD		2
627 #define	X86_VENDORSTR_AMD	"AuthenticAMD"
628 
629 #define	X86_VENDOR_Cyrix	3
630 #define	X86_VENDORSTR_CYRIX	"CyrixInstead"
631 
632 #define	X86_VENDOR_UMC		4
633 #define	X86_VENDORSTR_UMC	"UMC UMC UMC "
634 
635 #define	X86_VENDOR_NexGen	5
636 #define	X86_VENDORSTR_NexGen	"NexGenDriven"
637 
638 #define	X86_VENDOR_Centaur	6
639 #define	X86_VENDORSTR_Centaur	"CentaurHauls"
640 
641 #define	X86_VENDOR_Rise		7
642 #define	X86_VENDORSTR_Rise	"RiseRiseRise"
643 
644 #define	X86_VENDOR_SiS		8
645 #define	X86_VENDORSTR_SiS	"SiS SiS SiS "
646 
647 #define	X86_VENDOR_TM		9
648 #define	X86_VENDORSTR_TM	"GenuineTMx86"
649 
650 #define	X86_VENDOR_NSC		10
651 #define	X86_VENDORSTR_NSC	"Geode by NSC"
652 
653 /*
654  * Vendor string max len + \0
655  */
656 #define	X86_VENDOR_STRLEN	13
657 
658 /*
659  * Some vendor/family/model/stepping ranges are commonly grouped under
660  * a single identifying banner by the vendor.  The following encode
661  * that "revision" in a uint32_t with the 8 most significant bits
662  * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
663  * family, and the remaining 16 typically forming a bitmask of revisions
664  * within that family with more significant bits indicating "later" revisions.
665  */
666 
667 #define	_X86_CHIPREV_VENDOR_MASK	0xff000000u
668 #define	_X86_CHIPREV_VENDOR_SHIFT	24
669 #define	_X86_CHIPREV_FAMILY_MASK	0x00ff0000u
670 #define	_X86_CHIPREV_FAMILY_SHIFT	16
671 #define	_X86_CHIPREV_REV_MASK		0x0000ffffu
672 
673 #define	_X86_CHIPREV_VENDOR(x) \
674 	(((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
675 #define	_X86_CHIPREV_FAMILY(x) \
676 	(((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
677 #define	_X86_CHIPREV_REV(x) \
678 	((x) & _X86_CHIPREV_REV_MASK)
679 
680 /* True if x matches in vendor and family and if x matches the given rev mask */
681 #define	X86_CHIPREV_MATCH(x, mask) \
682 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
683 	_X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
684 	((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
685 
686 /* True if x matches in vendor and family, and rev is at least minx */
687 #define	X86_CHIPREV_ATLEAST(x, minx) \
688 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
689 	_X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
690 	_X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
691 
692 #define	_X86_CHIPREV_MKREV(vendor, family, rev) \
693 	((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
694 	(family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
695 
696 /* True if x matches in vendor, and family is at least minx */
697 #define	X86_CHIPFAM_ATLEAST(x, minx) \
698 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
699 	_X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
700 
701 /* Revision default */
702 #define	X86_CHIPREV_UNKNOWN	0x0
703 
704 /*
705  * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
706  * sufficiently different that we will distinguish them; in all other
707  * case we will identify the major revision.
708  */
709 #define	X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
710 #define	X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
711 #define	X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
712 #define	X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
713 #define	X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
714 #define	X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
715 #define	X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
716 
717 /*
718  * Definitions for AMD Family 0x10.  Rev A was Engineering Samples only.
719  */
720 #define	X86_CHIPREV_AMD_10_REV_A \
721 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
722 #define	X86_CHIPREV_AMD_10_REV_B \
723 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
724 #define	X86_CHIPREV_AMD_10_REV_C2 \
725 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
726 #define	X86_CHIPREV_AMD_10_REV_C3 \
727 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
728 #define	X86_CHIPREV_AMD_10_REV_D0 \
729 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
730 #define	X86_CHIPREV_AMD_10_REV_D1 \
731 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
732 #define	X86_CHIPREV_AMD_10_REV_E \
733 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
734 
735 /*
736  * Definitions for AMD Family 0x11.
737  */
738 #define	X86_CHIPREV_AMD_11_REV_B \
739 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
740 
741 /*
742  * Definitions for AMD Family 0x12.
743  */
744 #define	X86_CHIPREV_AMD_12_REV_B \
745 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
746 
747 /*
748  * Definitions for AMD Family 0x14.
749  */
750 #define	X86_CHIPREV_AMD_14_REV_B \
751 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
752 #define	X86_CHIPREV_AMD_14_REV_C \
753 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
754 
755 /*
756  * Definitions for AMD Family 0x15
757  */
758 #define	X86_CHIPREV_AMD_15OR_REV_B2 \
759 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
760 
761 #define	X86_CHIPREV_AMD_15TN_REV_A1 \
762 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
763 
764 #define	X86_CHIPREV_AMD_150R_REV_C0 \
765 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0003)
766 
767 #define	X86_CHIPREV_AMD_15KV_REV_A1 \
768 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0004)
769 
770 #define	X86_CHIPREV_AMD_15F60 \
771 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0005)
772 
773 #define	X86_CHIPREV_AMD_15ST_REV_A0 \
774 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0006)
775 
776 /*
777  * Definitions for AMD Family 0x16
778  */
779 #define	X86_CHIPREV_AMD_16_KB_A1 \
780 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0001)
781 
782 #define	X86_CHIPREV_AMD_16_ML_A1 \
783 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0002)
784 
785 /*
786  * Definitions for AMD Family 0x17
787  */
788 
789 #define	X86_CHIPREV_AMD_17_ZP_B1 \
790 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0001)
791 
792 #define	X86_CHIPREV_AMD_17_ZP_B2 \
793 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0002)
794 
795 #define	X86_CHIPREV_AMD_17_PiR_B2 \
796 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0003)
797 
798 /*
799  * Various socket/package types, extended as the need to distinguish
800  * a new type arises.  The top 8 byte identfies the vendor and the
801  * remaining 24 bits describe 24 socket types.
802  */
803 
804 #define	_X86_SOCKET_VENDOR_SHIFT	24
805 #define	_X86_SOCKET_VENDOR(x)	((x) >> _X86_SOCKET_VENDOR_SHIFT)
806 #define	_X86_SOCKET_TYPE_MASK	0x00ffffff
807 #define	_X86_SOCKET_TYPE(x)		((x) & _X86_SOCKET_TYPE_MASK)
808 
809 #define	_X86_SOCKET_MKVAL(vendor, bitval) \
810 	((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
811 
812 #define	X86_SOCKET_MATCH(s, mask) \
813 	(_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
814 	(_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
815 
816 #define	X86_SOCKET_UNKNOWN 0x0
817 	/*
818 	 * AMD socket types
819 	 */
820 #define	X86_SOCKET_754		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01)
821 #define	X86_SOCKET_939		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02)
822 #define	X86_SOCKET_940		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03)
823 #define	X86_SOCKET_S1g1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04)
824 #define	X86_SOCKET_AM2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05)
825 #define	X86_SOCKET_F1207	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06)
826 #define	X86_SOCKET_S1g2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07)
827 #define	X86_SOCKET_S1g3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08)
828 #define	X86_SOCKET_AM		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09)
829 #define	X86_SOCKET_AM2R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a)
830 #define	X86_SOCKET_AM3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b)
831 #define	X86_SOCKET_G34		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c)
832 #define	X86_SOCKET_ASB2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d)
833 #define	X86_SOCKET_C32		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e)
834 #define	X86_SOCKET_S1g4		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f)
835 #define	X86_SOCKET_FT1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10)
836 #define	X86_SOCKET_FM1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11)
837 #define	X86_SOCKET_FS1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12)
838 #define	X86_SOCKET_AM3R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13)
839 #define	X86_SOCKET_FP2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14)
840 #define	X86_SOCKET_FS1R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15)
841 #define	X86_SOCKET_FM2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16)
842 #define	X86_SOCKET_FP3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17)
843 #define	X86_SOCKET_FM2R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18)
844 #define	X86_SOCKET_FP4		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19)
845 #define	X86_SOCKET_AM4		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a)
846 #define	X86_SOCKET_FT3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b)
847 #define	X86_SOCKET_FT4		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c)
848 #define	X86_SOCKET_FS1B		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d)
849 #define	X86_SOCKET_FT3B		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e)
850 #define	X86_SOCKET_SP3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f)
851 #define	X86_SOCKET_SP3R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20)
852 #define	X86_NUM_SOCKETS_AMD	0x21
853 
854 
855 /*
856  * Definitions for Intel processor models. These are all for Family 6
857  * processors. This list and the Atom set below it are not exhuastive.
858  */
859 #define	INTC_MODEL_MEROM		0x0f
860 #define	INTC_MODEL_PENRYN		0x17
861 #define	INTC_MODEL_DUNNINGTON		0x1d
862 
863 #define	INTC_MODEL_NEHALEM		0x1e
864 #define	INTC_MODEL_NEHALEM2		0x1f
865 #define	INTC_MODEL_NEHALEM_EP		0x1a
866 #define	INTC_MODEL_NEHALEM_EX		0x2e
867 
868 #define	INTC_MODEL_WESTMERE		0x25
869 #define	INTC_MODEL_WESTMERE_EP		0x2c
870 #define	INTC_MODEL_WESTMERE_EX		0x2f
871 
872 #define	INTC_MODEL_SANDYBRIDGE		0x2a
873 #define	INTC_MODEL_SANDYBRIDGE_XEON	0x2d
874 #define	INTC_MODEL_IVYBRIDGE		0x3a
875 #define	INTC_MODEL_IVYBRIDGE_XEON	0x3e
876 
877 #define	INTC_MODEL_HASWELL		0x3c
878 #define	INTC_MODEL_HASWELL_ULT		0x45
879 #define	INTC_MODEL_HASWELL_GT3E		0x46
880 #define	INTC_MODEL_HASWELL_XEON		0x3f
881 
882 #define	INTC_MODEL_BROADWELL		0x3d
883 #define	INTC_MODEL_BROADELL_2		0x47
884 #define	INTC_MODEL_BROADWELL_XEON	0x4f
885 #define	INTC_MODEL_BROADWELL_XEON_D	0x56
886 
887 #define	INCC_MODEL_SKYLAKE_MOBILE	0x4e
888 #define	INTC_MODEL_SKYLAKE_XEON		0x55
889 #define	INTC_MODEL_SKYLAKE_DESKTOP	0x5e
890 
891 #define	INTC_MODEL_KABYLAKE_MOBILE	0x8e
892 #define	INTC_MODEL_KABYLAKE_DESKTOP	0x9e
893 
894 /*
895  * Atom Processors
896  */
897 #define	INTC_MODEL_SILVERTHORNE		0x1c
898 #define	INTC_MODEL_LINCROFT		0x26
899 #define	INTC_MODEL_PENWELL		0x27
900 #define	INTC_MODEL_CLOVERVIEW		0x35
901 #define	INTC_MODEL_CEDARVIEW		0x36
902 #define	INTC_MODEL_BAY_TRAIL		0x37
903 #define	INTC_MODEL_AVATON		0x4d
904 #define	INTC_MODEL_AIRMONT		0x4c
905 #define	INTC_MODEL_GOLDMONT		0x5c
906 #define	INTC_MODEL_DENVERTON		0x5f
907 #define	INTC_MODEL_GEMINI_LAKE		0x7a
908 
909 /*
910  * xgetbv/xsetbv support
911  * See section 13.3 in vol. 1 of the Intel devlopers manual.
912  */
913 
914 #define	XFEATURE_ENABLED_MASK	0x0
915 /*
916  * XFEATURE_ENABLED_MASK values (eax)
917  * See setup_xfem().
918  */
919 #define	XFEATURE_LEGACY_FP	0x1
920 #define	XFEATURE_SSE		0x2
921 #define	XFEATURE_AVX		0x4
922 #define	XFEATURE_MPX		0x18	/* 2 bits, both 0 or 1 */
923 #define	XFEATURE_AVX512		0xe0	/* 3 bits, all 0 or 1 */
924 	/* bit 8 unused */
925 #define	XFEATURE_PKRU		0x200
926 #define	XFEATURE_FP_ALL	\
927 	(XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
928 	XFEATURE_AVX512 | XFEATURE_PKRU)
929 
930 /*
931  * Define the set of xfeature flags that should be considered valid in the xsave
932  * state vector when we initialize an lwp. This is distinct from the full set so
933  * that all of the processor's normal logic and tracking of the xsave state is
934  * usable. This should correspond to the state that's been initialized by the
935  * ABI to hold meaningful values. Adding additional bits here can have serious
936  * performance implications and cause performance degradations when using the
937  * FPU vector (xmm) registers.
938  */
939 #define	XFEATURE_FP_INITIAL	(XFEATURE_LEGACY_FP | XFEATURE_SSE)
940 
941 #if !defined(_ASM)
942 
943 #if defined(_KERNEL) || defined(_KMEMUSER)
944 
945 #define	NUM_X86_FEATURES	95
946 extern uchar_t x86_featureset[];
947 
948 extern void free_x86_featureset(void *featureset);
949 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
950 extern void add_x86_feature(void *featureset, uint_t feature);
951 extern void remove_x86_feature(void *featureset, uint_t feature);
952 extern boolean_t compare_x86_featureset(void *setA, void *setB);
953 extern void print_x86_featureset(void *featureset);
954 
955 
956 extern uint_t x86_type;
957 extern uint_t x86_vendor;
958 extern uint_t x86_clflush_size;
959 
960 extern uint_t pentiumpro_bug4046376;
961 
962 extern const char CyrixInstead[];
963 
964 extern void (*spec_uarch_flush)(void);
965 
966 #endif
967 
968 #if defined(_KERNEL)
969 
970 /*
971  * x86_md_clear is the main entry point that should be called to deal with
972  * clearing u-arch buffers. Implementations are below because they're
973  * implemented in ASM. They shouldn't be used.
974  */
975 extern void (*x86_md_clear)(void);
976 extern void x86_md_clear_noop(void);
977 extern void x86_md_clear_verw(void);
978 
979 /*
980  * This structure is used to pass arguments and get return values back
981  * from the CPUID instruction in __cpuid_insn() routine.
982  */
983 struct cpuid_regs {
984 	uint32_t	cp_eax;
985 	uint32_t	cp_ebx;
986 	uint32_t	cp_ecx;
987 	uint32_t	cp_edx;
988 };
989 
990 extern int x86_use_pcid;
991 extern int x86_use_invpcid;
992 
993 /*
994  * Utility functions to get/set extended control registers (XCR)
995  * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
996  */
997 extern uint64_t get_xcr(uint_t);
998 extern void set_xcr(uint_t, uint64_t);
999 
1000 extern uint64_t rdmsr(uint_t);
1001 extern void wrmsr(uint_t, const uint64_t);
1002 extern uint64_t xrdmsr(uint_t);
1003 extern void xwrmsr(uint_t, const uint64_t);
1004 extern int checked_rdmsr(uint_t, uint64_t *);
1005 extern int checked_wrmsr(uint_t, uint64_t);
1006 
1007 extern void invalidate_cache(void);
1008 extern ulong_t getcr4(void);
1009 extern void setcr4(ulong_t);
1010 
1011 extern void mtrr_sync(void);
1012 
1013 extern void cpu_fast_syscall_enable(void);
1014 extern void cpu_fast_syscall_disable(void);
1015 
1016 struct cpu;
1017 
1018 extern int cpuid_checkpass(struct cpu *, int);
1019 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
1020 extern uint32_t __cpuid_insn(struct cpuid_regs *);
1021 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
1022 extern int cpuid_getidstr(struct cpu *, char *, size_t);
1023 extern const char *cpuid_getvendorstr(struct cpu *);
1024 extern uint_t cpuid_getvendor(struct cpu *);
1025 extern uint_t cpuid_getfamily(struct cpu *);
1026 extern uint_t cpuid_getmodel(struct cpu *);
1027 extern uint_t cpuid_getstep(struct cpu *);
1028 extern uint_t cpuid_getsig(struct cpu *);
1029 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
1030 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
1031 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
1032 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
1033 extern int cpuid_get_chipid(struct cpu *);
1034 extern id_t cpuid_get_coreid(struct cpu *);
1035 extern int cpuid_get_pkgcoreid(struct cpu *);
1036 extern int cpuid_get_clogid(struct cpu *);
1037 extern int cpuid_get_cacheid(struct cpu *);
1038 extern uint32_t cpuid_get_apicid(struct cpu *);
1039 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
1040 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
1041 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
1042 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
1043 extern size_t cpuid_get_xsave_size();
1044 extern boolean_t cpuid_need_fp_excp_handling();
1045 extern int cpuid_is_cmt(struct cpu *);
1046 extern int cpuid_syscall32_insn(struct cpu *);
1047 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
1048 
1049 extern uint32_t cpuid_getchiprev(struct cpu *);
1050 extern const char *cpuid_getchiprevstr(struct cpu *);
1051 extern uint32_t cpuid_getsockettype(struct cpu *);
1052 extern const char *cpuid_getsocketstr(struct cpu *);
1053 
1054 extern int cpuid_have_cr8access(struct cpu *);
1055 
1056 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
1057 
1058 struct cpuid_info;
1059 
1060 extern void setx86isalist(void);
1061 extern void cpuid_alloc_space(struct cpu *);
1062 extern void cpuid_free_space(struct cpu *);
1063 extern void cpuid_pass1(struct cpu *, uchar_t *);
1064 extern void cpuid_pass2(struct cpu *);
1065 extern void cpuid_pass3(struct cpu *);
1066 extern void cpuid_pass4(struct cpu *, uint_t *);
1067 extern void cpuid_set_cpu_properties(void *, processorid_t,
1068     struct cpuid_info *);
1069 extern void cpuid_pass_ucode(struct cpu *, uchar_t *);
1070 extern void cpuid_post_ucodeadm(void);
1071 
1072 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
1073 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
1074 
1075 #if !defined(__xpv)
1076 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
1077 extern void cpuid_mwait_free(struct cpu *);
1078 extern int cpuid_deep_cstates_supported(void);
1079 extern int cpuid_arat_supported(void);
1080 extern int cpuid_iepb_supported(struct cpu *);
1081 extern int cpuid_deadline_tsc_supported(void);
1082 extern void vmware_port(int, uint32_t *);
1083 #endif
1084 
1085 struct cpu_ucode_info;
1086 
1087 extern void ucode_alloc_space(struct cpu *);
1088 extern void ucode_free_space(struct cpu *);
1089 extern void ucode_check(struct cpu *);
1090 extern void ucode_cleanup();
1091 
1092 #if !defined(__xpv)
1093 extern	char _tsc_mfence_start;
1094 extern	char _tsc_mfence_end;
1095 extern	char _tscp_start;
1096 extern	char _tscp_end;
1097 extern	char _no_rdtsc_start;
1098 extern	char _no_rdtsc_end;
1099 extern	char _tsc_lfence_start;
1100 extern	char _tsc_lfence_end;
1101 #endif
1102 
1103 #if !defined(__xpv)
1104 extern	char bcopy_patch_start;
1105 extern	char bcopy_patch_end;
1106 extern	char bcopy_ck_size;
1107 #endif
1108 
1109 extern void post_startup_cpu_fixups(void);
1110 
1111 extern uint_t workaround_errata(struct cpu *);
1112 
1113 #if defined(OPTERON_ERRATUM_93)
1114 extern int opteron_erratum_93;
1115 #endif
1116 
1117 #if defined(OPTERON_ERRATUM_91)
1118 extern int opteron_erratum_91;
1119 #endif
1120 
1121 #if defined(OPTERON_ERRATUM_100)
1122 extern int opteron_erratum_100;
1123 #endif
1124 
1125 #if defined(OPTERON_ERRATUM_121)
1126 extern int opteron_erratum_121;
1127 #endif
1128 
1129 #if defined(OPTERON_WORKAROUND_6323525)
1130 extern int opteron_workaround_6323525;
1131 extern void patch_workaround_6323525(void);
1132 #endif
1133 
1134 #if !defined(__xpv)
1135 extern void determine_platform(void);
1136 #endif
1137 extern int get_hwenv(void);
1138 extern int is_controldom(void);
1139 
1140 extern void enable_pcid(void);
1141 
1142 extern void xsave_setup_msr(struct cpu *);
1143 
1144 #if !defined(__xpv)
1145 extern void reset_gdtr_limit(void);
1146 #endif
1147 
1148 /*
1149  * Hypervisor signatures
1150  */
1151 #define	HVSIG_XEN_HVM	"XenVMMXenVMM"
1152 #define	HVSIG_VMWARE	"VMwareVMware"
1153 #define	HVSIG_KVM	"KVMKVMKVM"
1154 #define	HVSIG_MICROSOFT	"Microsoft Hv"
1155 #define	HVSIG_BHYVE	"bhyve bhyve "
1156 
1157 /*
1158  * Defined hardware environments
1159  */
1160 #define	HW_NATIVE	(1 << 0)	/* Running on bare metal */
1161 #define	HW_XEN_PV	(1 << 1)	/* Running on Xen PVM */
1162 
1163 #define	HW_XEN_HVM	(1 << 2)	/* Running on Xen HVM */
1164 #define	HW_VMWARE	(1 << 3)	/* Running on VMware hypervisor */
1165 #define	HW_KVM		(1 << 4)	/* Running on KVM hypervisor */
1166 #define	HW_MICROSOFT	(1 << 5)	/* Running on Microsoft hypervisor */
1167 #define	HW_BHYVE	(1 << 6)	/* Running on bhyve hypervisor */
1168 
1169 #define	HW_VIRTUAL	(HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \
1170 	    HW_BHYVE)
1171 
1172 #endif	/* _KERNEL */
1173 
1174 #endif	/* !_ASM */
1175 
1176 /*
1177  * VMware hypervisor related defines
1178  */
1179 #define	VMWARE_HVMAGIC		0x564d5868
1180 #define	VMWARE_HVPORT		0x5658
1181 #define	VMWARE_HVCMD_GETVERSION	0x0a
1182 #define	VMWARE_HVCMD_GETTSCFREQ	0x2d
1183 
1184 #ifdef	__cplusplus
1185 }
1186 #endif
1187 
1188 #endif	/* _SYS_X86_ARCHEXT_H */
1189