xref: /illumos-gate/usr/src/uts/intel/sys/x86_archext.h (revision 79ec9da85c2648e2e165ce68612ad0cb6e185618)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23  * Copyright (c) 2011 by Delphix. All rights reserved.
24  * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25  */
26 /*
27  * Copyright (c) 2010, Intel Corporation.
28  * All rights reserved.
29  */
30 /*
31  * Copyright (c) 2012, Joyent, Inc. All rights reserved.
32  * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
33  * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
34  */
35 
36 #ifndef _SYS_X86_ARCHEXT_H
37 #define	_SYS_X86_ARCHEXT_H
38 
39 #if !defined(_ASM)
40 #include <sys/regset.h>
41 #include <sys/processor.h>
42 #include <vm/seg_enum.h>
43 #include <vm/page.h>
44 #endif	/* _ASM */
45 
46 #ifdef	__cplusplus
47 extern "C" {
48 #endif
49 
50 /*
51  * cpuid instruction feature flags in %edx (standard function 1)
52  */
53 
54 #define	CPUID_INTC_EDX_FPU	0x00000001	/* x87 fpu present */
55 #define	CPUID_INTC_EDX_VME	0x00000002	/* virtual-8086 extension */
56 #define	CPUID_INTC_EDX_DE	0x00000004	/* debugging extensions */
57 #define	CPUID_INTC_EDX_PSE	0x00000008	/* page size extension */
58 #define	CPUID_INTC_EDX_TSC	0x00000010	/* time stamp counter */
59 #define	CPUID_INTC_EDX_MSR	0x00000020	/* rdmsr and wrmsr */
60 #define	CPUID_INTC_EDX_PAE	0x00000040	/* physical addr extension */
61 #define	CPUID_INTC_EDX_MCE	0x00000080	/* machine check exception */
62 #define	CPUID_INTC_EDX_CX8	0x00000100	/* cmpxchg8b instruction */
63 #define	CPUID_INTC_EDX_APIC	0x00000200	/* local APIC */
64 						/* 0x400 - reserved */
65 #define	CPUID_INTC_EDX_SEP	0x00000800	/* sysenter and sysexit */
66 #define	CPUID_INTC_EDX_MTRR	0x00001000	/* memory type range reg */
67 #define	CPUID_INTC_EDX_PGE	0x00002000	/* page global enable */
68 #define	CPUID_INTC_EDX_MCA	0x00004000	/* machine check arch */
69 #define	CPUID_INTC_EDX_CMOV	0x00008000	/* conditional move insns */
70 #define	CPUID_INTC_EDX_PAT	0x00010000	/* page attribute table */
71 #define	CPUID_INTC_EDX_PSE36	0x00020000	/* 36-bit pagesize extension */
72 #define	CPUID_INTC_EDX_PSN	0x00040000	/* processor serial number */
73 #define	CPUID_INTC_EDX_CLFSH	0x00080000	/* clflush instruction */
74 						/* 0x100000 - reserved */
75 #define	CPUID_INTC_EDX_DS	0x00200000	/* debug store exists */
76 #define	CPUID_INTC_EDX_ACPI	0x00400000	/* monitoring + clock ctrl */
77 #define	CPUID_INTC_EDX_MMX	0x00800000	/* MMX instructions */
78 #define	CPUID_INTC_EDX_FXSR	0x01000000	/* fxsave and fxrstor */
79 #define	CPUID_INTC_EDX_SSE	0x02000000	/* streaming SIMD extensions */
80 #define	CPUID_INTC_EDX_SSE2	0x04000000	/* SSE extensions */
81 #define	CPUID_INTC_EDX_SS	0x08000000	/* self-snoop */
82 #define	CPUID_INTC_EDX_HTT	0x10000000	/* Hyper Thread Technology */
83 #define	CPUID_INTC_EDX_TM	0x20000000	/* thermal monitoring */
84 #define	CPUID_INTC_EDX_IA64	0x40000000	/* Itanium emulating IA32 */
85 #define	CPUID_INTC_EDX_PBE	0x80000000	/* Pending Break Enable */
86 
87 #define	FMT_CPUID_INTC_EDX					\
88 	"\20"							\
89 	"\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr"	\
90 	"\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat"	\
91 	"\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8"		\
92 	"\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
93 
94 /*
95  * cpuid instruction feature flags in %ecx (standard function 1)
96  */
97 
98 #define	CPUID_INTC_ECX_SSE3	0x00000001	/* Yet more SSE extensions */
99 #define	CPUID_INTC_ECX_PCLMULQDQ 0x00000002 	/* PCLMULQDQ insn */
100 						/* 0x00000004 - reserved */
101 #define	CPUID_INTC_ECX_MON	0x00000008	/* MONITOR/MWAIT */
102 #define	CPUID_INTC_ECX_DSCPL	0x00000010	/* CPL-qualified debug store */
103 #define	CPUID_INTC_ECX_VMX	0x00000020	/* Hardware VM extensions */
104 #define	CPUID_INTC_ECX_SMX	0x00000040	/* Secure mode extensions */
105 #define	CPUID_INTC_ECX_EST	0x00000080	/* enhanced SpeedStep */
106 #define	CPUID_INTC_ECX_TM2	0x00000100	/* thermal monitoring */
107 #define	CPUID_INTC_ECX_SSSE3	0x00000200	/* Supplemental SSE3 insns */
108 #define	CPUID_INTC_ECX_CID	0x00000400	/* L1 context ID */
109 						/* 0x00000800 - reserved */
110 						/* 0x00001000 - reserved */
111 #define	CPUID_INTC_ECX_CX16	0x00002000	/* cmpxchg16 */
112 #define	CPUID_INTC_ECX_ETPRD	0x00004000	/* extended task pri messages */
113 						/* 0x00008000 - reserved */
114 						/* 0x00010000 - reserved */
115 						/* 0x00020000 - reserved */
116 #define	CPUID_INTC_ECX_DCA	0x00040000	/* direct cache access */
117 #define	CPUID_INTC_ECX_SSE4_1	0x00080000	/* SSE4.1 insns */
118 #define	CPUID_INTC_ECX_SSE4_2	0x00100000	/* SSE4.2 insns */
119 #define	CPUID_INTC_ECX_MOVBE	0x00400000	/* MOVBE insn */
120 #define	CPUID_INTC_ECX_POPCNT	0x00800000	/* POPCNT insn */
121 #define	CPUID_INTC_ECX_AES	0x02000000	/* AES insns */
122 #define	CPUID_INTC_ECX_XSAVE	0x04000000	/* XSAVE/XRESTOR insns */
123 #define	CPUID_INTC_ECX_OSXSAVE	0x08000000	/* OS supports XSAVE insns */
124 #define	CPUID_INTC_ECX_AVX	0x10000000	/* AVX supported */
125 #define	CPUID_INTC_ECX_F16C	0x20000000	/* F16C supported */
126 #define	CPUID_INTC_ECX_RDRAND	0x40000000	/* RDRAND supported */
127 #define	CPUID_INTC_ECX_HV	0x80000000	/* Hypervisor */
128 
129 #define	FMT_CPUID_INTC_ECX					\
130 	"\20"							\
131 	"\37rdrand\36f16c\35avx\34osxsav\33xsave"		\
132 	"\32aes"						\
133 	"\30popcnt\27movbe\25sse4.2\24sse4.1\23dca"		\
134 	"\20\17etprd\16cx16\13cid\12ssse3\11tm2"		\
135 	"\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
136 
137 /*
138  * cpuid instruction feature flags in %edx (extended function 0x80000001)
139  */
140 
141 #define	CPUID_AMD_EDX_FPU	0x00000001	/* x87 fpu present */
142 #define	CPUID_AMD_EDX_VME	0x00000002	/* virtual-8086 extension */
143 #define	CPUID_AMD_EDX_DE	0x00000004	/* debugging extensions */
144 #define	CPUID_AMD_EDX_PSE	0x00000008	/* page size extensions */
145 #define	CPUID_AMD_EDX_TSC	0x00000010	/* time stamp counter */
146 #define	CPUID_AMD_EDX_MSR	0x00000020	/* rdmsr and wrmsr */
147 #define	CPUID_AMD_EDX_PAE	0x00000040	/* physical addr extension */
148 #define	CPUID_AMD_EDX_MCE	0x00000080	/* machine check exception */
149 #define	CPUID_AMD_EDX_CX8	0x00000100	/* cmpxchg8b instruction */
150 #define	CPUID_AMD_EDX_APIC	0x00000200	/* local APIC */
151 						/* 0x00000400 - sysc on K6m6 */
152 #define	CPUID_AMD_EDX_SYSC	0x00000800	/* AMD: syscall and sysret */
153 #define	CPUID_AMD_EDX_MTRR	0x00001000	/* memory type and range reg */
154 #define	CPUID_AMD_EDX_PGE	0x00002000	/* page global enable */
155 #define	CPUID_AMD_EDX_MCA	0x00004000	/* machine check arch */
156 #define	CPUID_AMD_EDX_CMOV	0x00008000	/* conditional move insns */
157 #define	CPUID_AMD_EDX_PAT	0x00010000	/* K7: page attribute table */
158 #define	CPUID_AMD_EDX_FCMOV	0x00010000	/* FCMOVcc etc. */
159 #define	CPUID_AMD_EDX_PSE36	0x00020000	/* 36-bit pagesize extension */
160 				/* 0x00040000 - reserved */
161 				/* 0x00080000 - reserved */
162 #define	CPUID_AMD_EDX_NX	0x00100000	/* AMD: no-execute page prot */
163 				/* 0x00200000 - reserved */
164 #define	CPUID_AMD_EDX_MMXamd	0x00400000	/* AMD: MMX extensions */
165 #define	CPUID_AMD_EDX_MMX	0x00800000	/* MMX instructions */
166 #define	CPUID_AMD_EDX_FXSR	0x01000000	/* fxsave and fxrstor */
167 #define	CPUID_AMD_EDX_FFXSR	0x02000000	/* fast fxsave/fxrstor */
168 #define	CPUID_AMD_EDX_1GPG	0x04000000	/* 1GB page */
169 #define	CPUID_AMD_EDX_TSCP	0x08000000	/* rdtscp instruction */
170 				/* 0x10000000 - reserved */
171 #define	CPUID_AMD_EDX_LM	0x20000000	/* AMD: long mode */
172 #define	CPUID_AMD_EDX_3DNowx	0x40000000	/* AMD: extensions to 3DNow! */
173 #define	CPUID_AMD_EDX_3DNow	0x80000000	/* AMD: 3DNow! instructions */
174 
175 #define	FMT_CPUID_AMD_EDX					\
176 	"\20"							\
177 	"\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr"		\
178 	"\30mmx\27mmxext\25nx\22pse\21pat"			\
179 	"\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8"	\
180 	"\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
181 
182 #define	CPUID_AMD_ECX_AHF64	0x00000001	/* LAHF and SAHF in long mode */
183 #define	CPUID_AMD_ECX_CMP_LGCY	0x00000002	/* AMD: multicore chip */
184 #define	CPUID_AMD_ECX_SVM	0x00000004	/* AMD: secure VM */
185 #define	CPUID_AMD_ECX_EAS	0x00000008	/* extended apic space */
186 #define	CPUID_AMD_ECX_CR8D	0x00000010	/* AMD: 32-bit mov %cr8 */
187 #define	CPUID_AMD_ECX_LZCNT	0x00000020	/* AMD: LZCNT insn */
188 #define	CPUID_AMD_ECX_SSE4A	0x00000040	/* AMD: SSE4A insns */
189 #define	CPUID_AMD_ECX_MAS	0x00000080	/* AMD: MisAlignSse mnode */
190 #define	CPUID_AMD_ECX_3DNP	0x00000100	/* AMD: 3DNowPrefectch */
191 #define	CPUID_AMD_ECX_OSVW	0x00000200	/* AMD: OSVW */
192 #define	CPUID_AMD_ECX_IBS	0x00000400	/* AMD: IBS */
193 #define	CPUID_AMD_ECX_SSE5	0x00000800	/* AMD: SSE5 */
194 #define	CPUID_AMD_ECX_SKINIT	0x00001000	/* AMD: SKINIT */
195 #define	CPUID_AMD_ECX_WDT	0x00002000	/* AMD: WDT */
196 #define	CPUID_AMD_ECX_TOPOEXT	0x00400000	/* AMD: Topology Extensions */
197 
198 #define	FMT_CPUID_AMD_ECX					\
199 	"\20"							\
200 	"\22topoext"						\
201 	"\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas"	\
202 	"\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
203 
204 /*
205  * Intel now seems to have claimed part of the "extended" function
206  * space that we previously for non-Intel implementors to use.
207  * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
208  * is available in long mode i.e. what AMD indicate using bit 0.
209  * On the other hand, everything else is labelled as reserved.
210  */
211 #define	CPUID_INTC_ECX_AHF64	0x00100000	/* LAHF and SAHF in long mode */
212 
213 
214 #define	P5_MCHADDR	0x0
215 #define	P5_CESR		0x11
216 #define	P5_CTR0		0x12
217 #define	P5_CTR1		0x13
218 
219 #define	K5_MCHADDR	0x0
220 #define	K5_MCHTYPE	0x01
221 #define	K5_TSC		0x10
222 #define	K5_TR12		0x12
223 
224 #define	REG_PAT		0x277
225 
226 #define	REG_MC0_CTL		0x400
227 #define	REG_MC5_MISC		0x417
228 #define	REG_PERFCTR0		0xc1
229 #define	REG_PERFCTR1		0xc2
230 
231 #define	REG_PERFEVNT0		0x186
232 #define	REG_PERFEVNT1		0x187
233 
234 #define	REG_TSC			0x10	/* timestamp counter */
235 #define	REG_APIC_BASE_MSR	0x1b
236 #define	REG_X2APIC_BASE_MSR	0x800	/* The MSR address offset of x2APIC */
237 
238 #if !defined(__xpv)
239 /*
240  * AMD C1E
241  */
242 #define	MSR_AMD_INT_PENDING_CMP_HALT	0xC0010055
243 #define	AMD_ACTONCMPHALT_SHIFT	27
244 #define	AMD_ACTONCMPHALT_MASK	3
245 #endif
246 
247 #define	MSR_DEBUGCTL		0x1d9
248 
249 #define	DEBUGCTL_LBR		0x01
250 #define	DEBUGCTL_BTF		0x02
251 
252 /* Intel P6, AMD */
253 #define	MSR_LBR_FROM		0x1db
254 #define	MSR_LBR_TO		0x1dc
255 #define	MSR_LEX_FROM		0x1dd
256 #define	MSR_LEX_TO		0x1de
257 
258 /* Intel P4 (pre-Prescott, non P4 M) */
259 #define	MSR_P4_LBSTK_TOS	0x1da
260 #define	MSR_P4_LBSTK_0		0x1db
261 #define	MSR_P4_LBSTK_1		0x1dc
262 #define	MSR_P4_LBSTK_2		0x1dd
263 #define	MSR_P4_LBSTK_3		0x1de
264 
265 /* Intel Pentium M */
266 #define	MSR_P6M_LBSTK_TOS	0x1c9
267 #define	MSR_P6M_LBSTK_0		0x040
268 #define	MSR_P6M_LBSTK_1		0x041
269 #define	MSR_P6M_LBSTK_2		0x042
270 #define	MSR_P6M_LBSTK_3		0x043
271 #define	MSR_P6M_LBSTK_4		0x044
272 #define	MSR_P6M_LBSTK_5		0x045
273 #define	MSR_P6M_LBSTK_6		0x046
274 #define	MSR_P6M_LBSTK_7		0x047
275 
276 /* Intel P4 (Prescott) */
277 #define	MSR_PRP4_LBSTK_TOS	0x1da
278 #define	MSR_PRP4_LBSTK_FROM_0	0x680
279 #define	MSR_PRP4_LBSTK_FROM_1	0x681
280 #define	MSR_PRP4_LBSTK_FROM_2	0x682
281 #define	MSR_PRP4_LBSTK_FROM_3	0x683
282 #define	MSR_PRP4_LBSTK_FROM_4	0x684
283 #define	MSR_PRP4_LBSTK_FROM_5	0x685
284 #define	MSR_PRP4_LBSTK_FROM_6	0x686
285 #define	MSR_PRP4_LBSTK_FROM_7	0x687
286 #define	MSR_PRP4_LBSTK_FROM_8 	0x688
287 #define	MSR_PRP4_LBSTK_FROM_9	0x689
288 #define	MSR_PRP4_LBSTK_FROM_10	0x68a
289 #define	MSR_PRP4_LBSTK_FROM_11 	0x68b
290 #define	MSR_PRP4_LBSTK_FROM_12	0x68c
291 #define	MSR_PRP4_LBSTK_FROM_13	0x68d
292 #define	MSR_PRP4_LBSTK_FROM_14	0x68e
293 #define	MSR_PRP4_LBSTK_FROM_15	0x68f
294 #define	MSR_PRP4_LBSTK_TO_0	0x6c0
295 #define	MSR_PRP4_LBSTK_TO_1	0x6c1
296 #define	MSR_PRP4_LBSTK_TO_2	0x6c2
297 #define	MSR_PRP4_LBSTK_TO_3	0x6c3
298 #define	MSR_PRP4_LBSTK_TO_4	0x6c4
299 #define	MSR_PRP4_LBSTK_TO_5	0x6c5
300 #define	MSR_PRP4_LBSTK_TO_6	0x6c6
301 #define	MSR_PRP4_LBSTK_TO_7	0x6c7
302 #define	MSR_PRP4_LBSTK_TO_8	0x6c8
303 #define	MSR_PRP4_LBSTK_TO_9 	0x6c9
304 #define	MSR_PRP4_LBSTK_TO_10	0x6ca
305 #define	MSR_PRP4_LBSTK_TO_11	0x6cb
306 #define	MSR_PRP4_LBSTK_TO_12	0x6cc
307 #define	MSR_PRP4_LBSTK_TO_13	0x6cd
308 #define	MSR_PRP4_LBSTK_TO_14	0x6ce
309 #define	MSR_PRP4_LBSTK_TO_15	0x6cf
310 
311 #define	MCI_CTL_VALUE		0xffffffff
312 
313 #define	MTRR_TYPE_UC		0
314 #define	MTRR_TYPE_WC		1
315 #define	MTRR_TYPE_WT		4
316 #define	MTRR_TYPE_WP		5
317 #define	MTRR_TYPE_WB		6
318 #define	MTRR_TYPE_UC_		7
319 
320 /*
321  * For Solaris we set up the page attritubute table in the following way:
322  * PAT0	Write-Back
323  * PAT1	Write-Through
324  * PAT2	Unchacheable-
325  * PAT3	Uncacheable
326  * PAT4 Write-Back
327  * PAT5	Write-Through
328  * PAT6	Write-Combine
329  * PAT7 Uncacheable
330  * The only difference from h/w default is entry 6.
331  */
332 #define	PAT_DEFAULT_ATTRIBUTE			\
333 	((uint64_t)MTRR_TYPE_WB |		\
334 	((uint64_t)MTRR_TYPE_WT << 8) |		\
335 	((uint64_t)MTRR_TYPE_UC_ << 16) |	\
336 	((uint64_t)MTRR_TYPE_UC << 24) |	\
337 	((uint64_t)MTRR_TYPE_WB << 32) |	\
338 	((uint64_t)MTRR_TYPE_WT << 40) |	\
339 	((uint64_t)MTRR_TYPE_WC << 48) |	\
340 	((uint64_t)MTRR_TYPE_UC << 56))
341 
342 #define	X86FSET_LARGEPAGE	0
343 #define	X86FSET_TSC		1
344 #define	X86FSET_MSR		2
345 #define	X86FSET_MTRR		3
346 #define	X86FSET_PGE		4
347 #define	X86FSET_DE		5
348 #define	X86FSET_CMOV		6
349 #define	X86FSET_MMX 		7
350 #define	X86FSET_MCA		8
351 #define	X86FSET_PAE		9
352 #define	X86FSET_CX8		10
353 #define	X86FSET_PAT		11
354 #define	X86FSET_SEP		12
355 #define	X86FSET_SSE		13
356 #define	X86FSET_SSE2		14
357 #define	X86FSET_HTT		15
358 #define	X86FSET_ASYSC		16
359 #define	X86FSET_NX		17
360 #define	X86FSET_SSE3		18
361 #define	X86FSET_CX16		19
362 #define	X86FSET_CMP		20
363 #define	X86FSET_TSCP		21
364 #define	X86FSET_MWAIT		22
365 #define	X86FSET_SSE4A		23
366 #define	X86FSET_CPUID		24
367 #define	X86FSET_SSSE3		25
368 #define	X86FSET_SSE4_1		26
369 #define	X86FSET_SSE4_2		27
370 #define	X86FSET_1GPG		28
371 #define	X86FSET_CLFSH		29
372 #define	X86FSET_64		30
373 #define	X86FSET_AES		31
374 #define	X86FSET_PCLMULQDQ	32
375 #define	X86FSET_XSAVE		33
376 #define	X86FSET_AVX		34
377 #define	X86FSET_VMX		35
378 #define	X86FSET_SVM		36
379 #define	X86FSET_TOPOEXT		37
380 #define	X86FSET_F16C		38
381 #define	X86FSET_RDRAND		39
382 
383 /*
384  * flags to patch tsc_read routine.
385  */
386 #define	X86_NO_TSC		0x0
387 #define	X86_HAVE_TSCP		0x1
388 #define	X86_TSC_MFENCE		0x2
389 #define	X86_TSC_LFENCE		0x4
390 
391 /*
392  * Intel Deep C-State invariant TSC in leaf 0x80000007.
393  */
394 #define	CPUID_TSC_CSTATE_INVARIANCE	(0x100)
395 
396 /*
397  * Intel Deep C-state always-running local APIC timer
398  */
399 #define	CPUID_CSTATE_ARAT	(0x4)
400 
401 /*
402  * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
403  */
404 #define	CPUID_EPB_SUPPORT	(1 << 3)
405 
406 /*
407  * Intel TSC deadline timer
408  */
409 #define	CPUID_DEADLINE_TSC	(1 << 24)
410 
411 /*
412  * x86_type is a legacy concept; this is supplanted
413  * for most purposes by x86_featureset; modern CPUs
414  * should be X86_TYPE_OTHER
415  */
416 #define	X86_TYPE_OTHER		0
417 #define	X86_TYPE_486		1
418 #define	X86_TYPE_P5		2
419 #define	X86_TYPE_P6		3
420 #define	X86_TYPE_CYRIX_486	4
421 #define	X86_TYPE_CYRIX_6x86L	5
422 #define	X86_TYPE_CYRIX_6x86	6
423 #define	X86_TYPE_CYRIX_GXm	7
424 #define	X86_TYPE_CYRIX_6x86MX	8
425 #define	X86_TYPE_CYRIX_MediaGX	9
426 #define	X86_TYPE_CYRIX_MII	10
427 #define	X86_TYPE_VIA_CYRIX_III	11
428 #define	X86_TYPE_P4		12
429 
430 /*
431  * x86_vendor allows us to select between
432  * implementation features and helps guide
433  * the interpretation of the cpuid instruction.
434  */
435 #define	X86_VENDOR_Intel	0
436 #define	X86_VENDORSTR_Intel	"GenuineIntel"
437 
438 #define	X86_VENDOR_IntelClone	1
439 
440 #define	X86_VENDOR_AMD		2
441 #define	X86_VENDORSTR_AMD	"AuthenticAMD"
442 
443 #define	X86_VENDOR_Cyrix	3
444 #define	X86_VENDORSTR_CYRIX	"CyrixInstead"
445 
446 #define	X86_VENDOR_UMC		4
447 #define	X86_VENDORSTR_UMC	"UMC UMC UMC "
448 
449 #define	X86_VENDOR_NexGen	5
450 #define	X86_VENDORSTR_NexGen	"NexGenDriven"
451 
452 #define	X86_VENDOR_Centaur	6
453 #define	X86_VENDORSTR_Centaur	"CentaurHauls"
454 
455 #define	X86_VENDOR_Rise		7
456 #define	X86_VENDORSTR_Rise	"RiseRiseRise"
457 
458 #define	X86_VENDOR_SiS		8
459 #define	X86_VENDORSTR_SiS	"SiS SiS SiS "
460 
461 #define	X86_VENDOR_TM		9
462 #define	X86_VENDORSTR_TM	"GenuineTMx86"
463 
464 #define	X86_VENDOR_NSC		10
465 #define	X86_VENDORSTR_NSC	"Geode by NSC"
466 
467 /*
468  * Vendor string max len + \0
469  */
470 #define	X86_VENDOR_STRLEN	13
471 
472 /*
473  * Some vendor/family/model/stepping ranges are commonly grouped under
474  * a single identifying banner by the vendor.  The following encode
475  * that "revision" in a uint32_t with the 8 most significant bits
476  * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
477  * family, and the remaining 16 typically forming a bitmask of revisions
478  * within that family with more significant bits indicating "later" revisions.
479  */
480 
481 #define	_X86_CHIPREV_VENDOR_MASK	0xff000000u
482 #define	_X86_CHIPREV_VENDOR_SHIFT	24
483 #define	_X86_CHIPREV_FAMILY_MASK	0x00ff0000u
484 #define	_X86_CHIPREV_FAMILY_SHIFT	16
485 #define	_X86_CHIPREV_REV_MASK		0x0000ffffu
486 
487 #define	_X86_CHIPREV_VENDOR(x) \
488 	(((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
489 #define	_X86_CHIPREV_FAMILY(x) \
490 	(((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
491 #define	_X86_CHIPREV_REV(x) \
492 	((x) & _X86_CHIPREV_REV_MASK)
493 
494 /* True if x matches in vendor and family and if x matches the given rev mask */
495 #define	X86_CHIPREV_MATCH(x, mask) \
496 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
497 	_X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
498 	((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
499 
500 /* True if x matches in vendor and family, and rev is at least minx */
501 #define	X86_CHIPREV_ATLEAST(x, minx) \
502 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
503 	_X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
504 	_X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
505 
506 #define	_X86_CHIPREV_MKREV(vendor, family, rev) \
507 	((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
508 	(family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
509 
510 /* True if x matches in vendor, and family is at least minx */
511 #define	X86_CHIPFAM_ATLEAST(x, minx) \
512 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
513 	_X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
514 
515 /* Revision default */
516 #define	X86_CHIPREV_UNKNOWN	0x0
517 
518 /*
519  * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
520  * sufficiently different that we will distinguish them; in all other
521  * case we will identify the major revision.
522  */
523 #define	X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
524 #define	X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
525 #define	X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
526 #define	X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
527 #define	X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
528 #define	X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
529 #define	X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
530 
531 /*
532  * Definitions for AMD Family 0x10.  Rev A was Engineering Samples only.
533  */
534 #define	X86_CHIPREV_AMD_10_REV_A \
535 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
536 #define	X86_CHIPREV_AMD_10_REV_B \
537 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
538 #define	X86_CHIPREV_AMD_10_REV_C2 \
539 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
540 #define	X86_CHIPREV_AMD_10_REV_C3 \
541 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
542 #define	X86_CHIPREV_AMD_10_REV_D0 \
543 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
544 #define	X86_CHIPREV_AMD_10_REV_D1 \
545 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
546 #define	X86_CHIPREV_AMD_10_REV_E \
547 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
548 
549 /*
550  * Definitions for AMD Family 0x11.
551  */
552 #define	X86_CHIPREV_AMD_11_REV_B \
553 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
554 
555 /*
556  * Definitions for AMD Family 0x12.
557  */
558 #define	X86_CHIPREV_AMD_12_REV_B \
559 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
560 
561 /*
562  * Definitions for AMD Family 0x14.
563  */
564 #define	X86_CHIPREV_AMD_14_REV_B \
565 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
566 #define	X86_CHIPREV_AMD_14_REV_C \
567 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
568 
569 /*
570  * Definitions for AMD Family 0x15
571  */
572 #define	X86_CHIPREV_AMD_15OR_REV_B2 \
573 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
574 
575 #define	X86_CHIPREV_AMD_15TN_REV_A1 \
576 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
577 
578 /*
579  * Various socket/package types, extended as the need to distinguish
580  * a new type arises.  The top 8 byte identfies the vendor and the
581  * remaining 24 bits describe 24 socket types.
582  */
583 
584 #define	_X86_SOCKET_VENDOR_SHIFT	24
585 #define	_X86_SOCKET_VENDOR(x)	((x) >> _X86_SOCKET_VENDOR_SHIFT)
586 #define	_X86_SOCKET_TYPE_MASK	0x00ffffff
587 #define	_X86_SOCKET_TYPE(x)		((x) & _X86_SOCKET_TYPE_MASK)
588 
589 #define	_X86_SOCKET_MKVAL(vendor, bitval) \
590 	((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
591 
592 #define	X86_SOCKET_MATCH(s, mask) \
593 	(_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
594 	(_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
595 
596 #define	X86_SOCKET_UNKNOWN 0x0
597 	/*
598 	 * AMD socket types
599 	 */
600 #define	X86_SOCKET_754		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
601 #define	X86_SOCKET_939		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
602 #define	X86_SOCKET_940		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
603 #define	X86_SOCKET_S1g1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
604 #define	X86_SOCKET_AM2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
605 #define	X86_SOCKET_F1207	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
606 #define	X86_SOCKET_S1g2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
607 #define	X86_SOCKET_S1g3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
608 #define	X86_SOCKET_AM		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
609 #define	X86_SOCKET_AM2R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
610 #define	X86_SOCKET_AM3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
611 #define	X86_SOCKET_G34		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
612 #define	X86_SOCKET_ASB2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
613 #define	X86_SOCKET_C32		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
614 #define	X86_SOCKET_S1g4		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
615 #define	X86_SOCKET_FT1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
616 #define	X86_SOCKET_FM1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
617 #define	X86_SOCKET_FS1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
618 #define	X86_SOCKET_AM3R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
619 #define	X86_SOCKET_FP2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
620 #define	X86_SOCKET_FS1R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
621 #define	X86_SOCKET_FM2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
622 
623 /*
624  * xgetbv/xsetbv support
625  */
626 
627 #define	XFEATURE_ENABLED_MASK	0x0
628 /*
629  * XFEATURE_ENABLED_MASK values (eax)
630  */
631 #define	XFEATURE_LEGACY_FP	0x1
632 #define	XFEATURE_SSE		0x2
633 #define	XFEATURE_AVX		0x4
634 #define	XFEATURE_MAX		XFEATURE_AVX
635 #define	XFEATURE_FP_ALL	\
636 	(XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
637 
638 #if !defined(_ASM)
639 
640 #if defined(_KERNEL) || defined(_KMEMUSER)
641 
642 #define	NUM_X86_FEATURES	40
643 extern uchar_t x86_featureset[];
644 
645 extern void free_x86_featureset(void *featureset);
646 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
647 extern void add_x86_feature(void *featureset, uint_t feature);
648 extern void remove_x86_feature(void *featureset, uint_t feature);
649 extern boolean_t compare_x86_featureset(void *setA, void *setB);
650 extern void print_x86_featureset(void *featureset);
651 
652 
653 extern uint_t x86_type;
654 extern uint_t x86_vendor;
655 extern uint_t x86_clflush_size;
656 
657 extern uint_t pentiumpro_bug4046376;
658 extern uint_t pentiumpro_bug4064495;
659 
660 extern uint_t enable486;
661 
662 extern const char CyrixInstead[];
663 
664 #endif
665 
666 #if defined(_KERNEL)
667 
668 /*
669  * This structure is used to pass arguments and get return values back
670  * from the CPUID instruction in __cpuid_insn() routine.
671  */
672 struct cpuid_regs {
673 	uint32_t	cp_eax;
674 	uint32_t	cp_ebx;
675 	uint32_t	cp_ecx;
676 	uint32_t	cp_edx;
677 };
678 
679 /*
680  * Utility functions to get/set extended control registers (XCR)
681  * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
682  */
683 extern uint64_t get_xcr(uint_t);
684 extern void set_xcr(uint_t, uint64_t);
685 
686 extern uint64_t rdmsr(uint_t);
687 extern void wrmsr(uint_t, const uint64_t);
688 extern uint64_t xrdmsr(uint_t);
689 extern void xwrmsr(uint_t, const uint64_t);
690 extern int checked_rdmsr(uint_t, uint64_t *);
691 extern int checked_wrmsr(uint_t, uint64_t);
692 
693 extern void invalidate_cache(void);
694 extern ulong_t getcr4(void);
695 extern void setcr4(ulong_t);
696 
697 extern void mtrr_sync(void);
698 
699 extern void cpu_fast_syscall_enable(void *);
700 extern void cpu_fast_syscall_disable(void *);
701 
702 struct cpu;
703 
704 extern int cpuid_checkpass(struct cpu *, int);
705 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
706 extern uint32_t __cpuid_insn(struct cpuid_regs *);
707 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
708 extern int cpuid_getidstr(struct cpu *, char *, size_t);
709 extern const char *cpuid_getvendorstr(struct cpu *);
710 extern uint_t cpuid_getvendor(struct cpu *);
711 extern uint_t cpuid_getfamily(struct cpu *);
712 extern uint_t cpuid_getmodel(struct cpu *);
713 extern uint_t cpuid_getstep(struct cpu *);
714 extern uint_t cpuid_getsig(struct cpu *);
715 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
716 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
717 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
718 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
719 extern int cpuid_get_chipid(struct cpu *);
720 extern id_t cpuid_get_coreid(struct cpu *);
721 extern int cpuid_get_pkgcoreid(struct cpu *);
722 extern int cpuid_get_clogid(struct cpu *);
723 extern int cpuid_get_cacheid(struct cpu *);
724 extern uint32_t cpuid_get_apicid(struct cpu *);
725 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
726 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
727 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
728 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
729 extern int cpuid_is_cmt(struct cpu *);
730 extern int cpuid_syscall32_insn(struct cpu *);
731 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
732 
733 extern uint32_t cpuid_getchiprev(struct cpu *);
734 extern const char *cpuid_getchiprevstr(struct cpu *);
735 extern uint32_t cpuid_getsockettype(struct cpu *);
736 extern const char *cpuid_getsocketstr(struct cpu *);
737 
738 extern int cpuid_have_cr8access(struct cpu *);
739 
740 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
741 
742 struct cpuid_info;
743 
744 extern void setx86isalist(void);
745 extern void cpuid_alloc_space(struct cpu *);
746 extern void cpuid_free_space(struct cpu *);
747 extern void cpuid_pass1(struct cpu *, uchar_t *);
748 extern void cpuid_pass2(struct cpu *);
749 extern void cpuid_pass3(struct cpu *);
750 extern void cpuid_pass4(struct cpu *, uint_t *);
751 extern void cpuid_set_cpu_properties(void *, processorid_t,
752     struct cpuid_info *);
753 
754 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
755 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
756 
757 #if !defined(__xpv)
758 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
759 extern void cpuid_mwait_free(struct cpu *);
760 extern int cpuid_deep_cstates_supported(void);
761 extern int cpuid_arat_supported(void);
762 extern int cpuid_iepb_supported(struct cpu *);
763 extern int cpuid_deadline_tsc_supported(void);
764 extern void vmware_port(int, uint32_t *);
765 #endif
766 
767 struct cpu_ucode_info;
768 
769 extern void ucode_alloc_space(struct cpu *);
770 extern void ucode_free_space(struct cpu *);
771 extern void ucode_check(struct cpu *);
772 extern void ucode_cleanup();
773 
774 #if !defined(__xpv)
775 extern	char _tsc_mfence_start;
776 extern	char _tsc_mfence_end;
777 extern	char _tscp_start;
778 extern	char _tscp_end;
779 extern	char _no_rdtsc_start;
780 extern	char _no_rdtsc_end;
781 extern	char _tsc_lfence_start;
782 extern	char _tsc_lfence_end;
783 #endif
784 
785 #if !defined(__xpv)
786 extern	char bcopy_patch_start;
787 extern	char bcopy_patch_end;
788 extern	char bcopy_ck_size;
789 #endif
790 
791 extern void post_startup_cpu_fixups(void);
792 
793 extern uint_t workaround_errata(struct cpu *);
794 
795 #if defined(OPTERON_ERRATUM_93)
796 extern int opteron_erratum_93;
797 #endif
798 
799 #if defined(OPTERON_ERRATUM_91)
800 extern int opteron_erratum_91;
801 #endif
802 
803 #if defined(OPTERON_ERRATUM_100)
804 extern int opteron_erratum_100;
805 #endif
806 
807 #if defined(OPTERON_ERRATUM_121)
808 extern int opteron_erratum_121;
809 #endif
810 
811 #if defined(OPTERON_WORKAROUND_6323525)
812 extern int opteron_workaround_6323525;
813 extern void patch_workaround_6323525(void);
814 #endif
815 
816 #if !defined(__xpv)
817 extern void determine_platform(void);
818 #endif
819 extern int get_hwenv(void);
820 extern int is_controldom(void);
821 
822 extern void xsave_setup_msr(struct cpu *);
823 
824 /*
825  * Hypervisor signatures
826  */
827 #define	HVSIG_XEN_HVM	"XenVMMXenVMM"
828 #define	HVSIG_VMWARE	"VMwareVMware"
829 #define	HVSIG_KVM	"KVMKVMKVM"
830 #define	HVSIG_MICROSOFT	"Microsoft Hv"
831 
832 /*
833  * Defined hardware environments
834  */
835 #define	HW_NATIVE	(1 << 0)	/* Running on bare metal */
836 #define	HW_XEN_PV	(1 << 1)	/* Running on Xen PVM */
837 
838 #define	HW_XEN_HVM	(1 << 2)	/* Running on Xen HVM */
839 #define	HW_VMWARE	(1 << 3)	/* Running on VMware hypervisor */
840 #define	HW_KVM		(1 << 4)	/* Running on KVM hypervisor */
841 #define	HW_MICROSOFT	(1 << 5)	/* Running on Microsoft hypervisor */
842 
843 #define	HW_VIRTUAL	(HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT)
844 
845 #endif	/* _KERNEL */
846 
847 #endif	/* !_ASM */
848 
849 /*
850  * VMware hypervisor related defines
851  */
852 #define	VMWARE_HVMAGIC		0x564d5868
853 #define	VMWARE_HVPORT		0x5658
854 #define	VMWARE_HVCMD_GETVERSION	0x0a
855 #define	VMWARE_HVCMD_GETTSCFREQ	0x2d
856 
857 #ifdef	__cplusplus
858 }
859 #endif
860 
861 #endif	/* _SYS_X86_ARCHEXT_H */
862