1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_X86_ARCHEXT_H 27 #define _SYS_X86_ARCHEXT_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #if !defined(_ASM) 32 #include <sys/regset.h> 33 #include <sys/processor.h> 34 #include <vm/seg_enum.h> 35 #include <vm/page.h> 36 #endif /* _ASM */ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /* 43 * cpuid instruction feature flags in %edx (standard function 1) 44 */ 45 46 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 47 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 48 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 49 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 50 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 51 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 52 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 53 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 54 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 55 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 56 /* 0x400 - reserved */ 57 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 58 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 59 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 60 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 61 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 62 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 63 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 64 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 65 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 66 /* 0x100000 - reserved */ 67 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 68 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 69 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 70 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 71 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 72 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 73 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 74 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 75 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 76 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 77 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 78 79 #define FMT_CPUID_INTC_EDX \ 80 "\20" \ 81 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 82 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 83 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 84 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 85 86 /* 87 * cpuid instruction feature flags in %ecx (standard function 1) 88 */ 89 90 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 91 /* 0x00000002 - reserved */ 92 /* 0x00000004 - reserved */ 93 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 94 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 95 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 96 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 97 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 98 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 99 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 100 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 101 /* 0x00000800 - reserved */ 102 /* 0x00001000 - reserved */ 103 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 104 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 105 /* 0x00008000 - reserved */ 106 /* 0x00010000 - reserved */ 107 /* 0x00020000 - reserved */ 108 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 109 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 110 111 #define FMT_CPUID_INTC_ECX \ 112 "\20" \ 113 "\30popcnt\23dca" \ 114 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 115 "\10est\7smx\6vmx\5dscpl\4mon\1sse3" 116 117 /* 118 * cpuid instruction feature flags in %edx (extended function 0x80000001) 119 */ 120 121 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 122 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 123 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 124 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 125 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 126 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 127 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 128 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 129 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 130 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 131 /* 0x00000400 - sysc on K6m6 */ 132 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 133 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 134 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 135 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 136 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 137 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 138 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 139 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 140 /* 0x00040000 - reserved */ 141 /* 0x00080000 - reserved */ 142 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 143 /* 0x00200000 - reserved */ 144 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 145 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 146 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 147 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 148 /* 0x04000000 - reserved */ 149 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 150 /* 0x10000000 - reserved */ 151 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 152 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 153 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 154 155 #define FMT_CPUID_AMD_EDX \ 156 "\20" \ 157 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 158 "\30mmx\27mmxext\25nx\22pse\21pat" \ 159 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 160 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 161 162 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 163 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 164 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 165 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 166 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 167 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 168 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 169 170 #define FMT_CPUID_AMD_ECX \ 171 "\20" \ 172 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 173 174 /* 175 * Intel now seems to have claimed part of the "extended" function 176 * space that we previously for non-Intel implementors to use. 177 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 178 * is available in long mode i.e. what AMD indicate using bit 0. 179 * On the other hand, everything else is labelled as reserved. 180 */ 181 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 182 183 184 #define P5_MCHADDR 0x0 185 #define P5_CESR 0x11 186 #define P5_CTR0 0x12 187 #define P5_CTR1 0x13 188 189 #define K5_MCHADDR 0x0 190 #define K5_MCHTYPE 0x01 191 #define K5_TSC 0x10 192 #define K5_TR12 0x12 193 194 #define REG_MTRRCAP 0xfe 195 #define REG_MTRRDEF 0x2ff 196 #define REG_MTRR64K 0x250 197 #define REG_MTRR16K1 0x258 198 #define REG_MTRR16K2 0x259 199 #define REG_MTRR4K1 0x268 200 #define REG_MTRR4K2 0x269 201 #define REG_MTRR4K3 0x26a 202 #define REG_MTRR4K4 0x26b 203 #define REG_MTRR4K5 0x26c 204 #define REG_MTRR4K6 0x26d 205 #define REG_MTRR4K7 0x26e 206 #define REG_MTRR4K8 0x26f 207 #define REG_MTRRPAT 0x277 208 209 #define REG_MTRRPHYSBASE0 0x200 210 #define REG_MTRRPHYSMASK7 0x20f 211 #define REG_MC0_CTL 0x400 212 #define REG_MC5_MISC 0x417 213 #define REG_PERFCTR0 0xc1 214 #define REG_PERFCTR1 0xc2 215 216 #define REG_PERFEVNT0 0x186 217 #define REG_PERFEVNT1 0x187 218 219 #define REG_TSC 0x10 /* timestamp counter */ 220 #define REG_APIC_BASE_MSR 0x1b 221 222 #define MSR_DEBUGCTL 0x1d9 223 224 #define DEBUGCTL_LBR 0x01 225 #define DEBUGCTL_BTF 0x02 226 227 /* Intel P6, AMD */ 228 #define MSR_LBR_FROM 0x1db 229 #define MSR_LBR_TO 0x1dc 230 #define MSR_LEX_FROM 0x1dd 231 #define MSR_LEX_TO 0x1de 232 233 /* Intel P4 (pre-Prescott, non P4 M) */ 234 #define MSR_P4_LBSTK_TOS 0x1da 235 #define MSR_P4_LBSTK_0 0x1db 236 #define MSR_P4_LBSTK_1 0x1dc 237 #define MSR_P4_LBSTK_2 0x1dd 238 #define MSR_P4_LBSTK_3 0x1de 239 240 /* Intel Pentium M */ 241 #define MSR_P6M_LBSTK_TOS 0x1c9 242 #define MSR_P6M_LBSTK_0 0x040 243 #define MSR_P6M_LBSTK_1 0x041 244 #define MSR_P6M_LBSTK_2 0x042 245 #define MSR_P6M_LBSTK_3 0x043 246 #define MSR_P6M_LBSTK_4 0x044 247 #define MSR_P6M_LBSTK_5 0x045 248 #define MSR_P6M_LBSTK_6 0x046 249 #define MSR_P6M_LBSTK_7 0x047 250 251 /* Intel P4 (Prescott) */ 252 #define MSR_PRP4_LBSTK_TOS 0x1da 253 #define MSR_PRP4_LBSTK_FROM_0 0x680 254 #define MSR_PRP4_LBSTK_FROM_1 0x681 255 #define MSR_PRP4_LBSTK_FROM_2 0x682 256 #define MSR_PRP4_LBSTK_FROM_3 0x683 257 #define MSR_PRP4_LBSTK_FROM_4 0x684 258 #define MSR_PRP4_LBSTK_FROM_5 0x685 259 #define MSR_PRP4_LBSTK_FROM_6 0x686 260 #define MSR_PRP4_LBSTK_FROM_7 0x687 261 #define MSR_PRP4_LBSTK_FROM_8 0x688 262 #define MSR_PRP4_LBSTK_FROM_9 0x689 263 #define MSR_PRP4_LBSTK_FROM_10 0x68a 264 #define MSR_PRP4_LBSTK_FROM_11 0x68b 265 #define MSR_PRP4_LBSTK_FROM_12 0x68c 266 #define MSR_PRP4_LBSTK_FROM_13 0x68d 267 #define MSR_PRP4_LBSTK_FROM_14 0x68e 268 #define MSR_PRP4_LBSTK_FROM_15 0x68f 269 #define MSR_PRP4_LBSTK_TO_0 0x6c0 270 #define MSR_PRP4_LBSTK_TO_1 0x6c1 271 #define MSR_PRP4_LBSTK_TO_2 0x6c2 272 #define MSR_PRP4_LBSTK_TO_3 0x6c3 273 #define MSR_PRP4_LBSTK_TO_4 0x6c4 274 #define MSR_PRP4_LBSTK_TO_5 0x6c5 275 #define MSR_PRP4_LBSTK_TO_6 0x6c6 276 #define MSR_PRP4_LBSTK_TO_7 0x6c7 277 #define MSR_PRP4_LBSTK_TO_8 0x6c8 278 #define MSR_PRP4_LBSTK_TO_9 0x6c9 279 #define MSR_PRP4_LBSTK_TO_10 0x6ca 280 #define MSR_PRP4_LBSTK_TO_11 0x6cb 281 #define MSR_PRP4_LBSTK_TO_12 0x6cc 282 #define MSR_PRP4_LBSTK_TO_13 0x6cd 283 #define MSR_PRP4_LBSTK_TO_14 0x6ce 284 #define MSR_PRP4_LBSTK_TO_15 0x6cf 285 286 #define MCI_CTL_VALUE 0xffffffff 287 288 #define MTRRTYPE_MASK 0xff 289 290 291 #define MTRRCAP_FIX 0x100 292 #define MTRRCAP_VCNTMASK 0xff 293 #define MTRRCAP_USWC 0x400 294 295 #define MTRRDEF_E 0x800 296 #define MTRRDEF_FE 0x400 297 298 #define MTRRPHYSMASK_V 0x800 299 300 #define MTRR_TYPE_UC 0 301 #define MTRR_TYPE_WC 1 302 #define MTRR_TYPE_WT 4 303 #define MTRR_TYPE_WP 5 304 #define MTRR_TYPE_WB 6 305 306 /* 307 * Page attribute table is setup in the following way 308 * PAT0 Write-BACK 309 * PAT1 Write-Through 310 * PAT2 Unchacheable 311 * PAT3 Uncacheable 312 * PAT4 Uncacheable 313 * PAT5 Write-Protect 314 * PAT6 Write-Combine 315 * PAT7 Uncacheable 316 */ 317 #define PAT_DEFAULT_ATTRIBUTE \ 318 ((uint64_t)MTRR_TYPE_WC << 48)|((uint64_t)MTRR_TYPE_WP << 40)| \ 319 (MTRR_TYPE_WT << 8)|(MTRR_TYPE_WB) 320 321 322 #define MTRR_SETTYPE(a, t) ((a &= (uint64_t)~0xff),\ 323 (a |= ((t) & 0xff))) 324 #define MTRR_SETVINVALID(a) ((a) &= ~MTRRPHYSMASK_V) 325 326 327 #define MTRR_SETVBASE(a, b, t) ((a) =\ 328 ((((uint64_t)(b)) & 0xffffff000)|\ 329 (((uint32_t)(t)) & 0xff))) 330 331 #define MTRR_SETVMASK(a, s, v) ((a) =\ 332 ((~(((uint64_t)(s)) - 1) & 0xffffff000)|\ 333 (((uint32_t)(v)) << 11))) 334 335 #define MTRR_GETVBASE(a) (((uint64_t)(a)) & 0xffffff000) 336 #define MTRR_GETVTYPE(a) (((uint64_t)(a)) & 0xff) 337 #define MTRR_GETVSIZE(a) ((~((uint64_t)(a)) + 1) & 0xffffff000) 338 339 340 #define MAX_MTRRVAR 8 341 342 #if !defined(_ASM) 343 typedef struct mtrrvar { 344 uint64_t mtrrphys_base; 345 uint64_t mtrrphys_mask; 346 } mtrrvar_t; 347 #endif /* _ASM */ 348 349 #define X86_LARGEPAGE 0x00000001 350 #define X86_TSC 0x00000002 351 #define X86_MSR 0x00000004 352 #define X86_MTRR 0x00000008 353 #define X86_PGE 0x00000010 354 #define X86_DE 0x00000020 355 #define X86_CMOV 0x00000040 356 #define X86_MMX 0x00000080 357 #define X86_MCA 0x00000100 358 #define X86_PAE 0x00000200 359 #define X86_CX8 0x00000400 360 #define X86_PAT 0x00000800 361 #define X86_SEP 0x00001000 362 #define X86_SSE 0x00002000 363 #define X86_SSE2 0x00004000 364 #define X86_HTT 0x00008000 365 #define X86_ASYSC 0x00010000 366 #define X86_NX 0x00020000 367 #define X86_SSE3 0x00040000 368 #define X86_CX16 0x00080000 369 #define X86_CMP 0x00100000 370 #define X86_TSCP 0x00200000 371 #define X86_MWAIT 0x00400000 372 #define X86_SSE4A 0x00800000 373 #define X86_CPUID 0x01000000 374 375 #define FMT_X86_FEATURE \ 376 "\20" \ 377 "\31cpuid" \ 378 "\30sse4a\27mwait\26tscp\25cmp\24cx16\23sse3\22nx\21asysc"\ 379 "\20htt\17sse2\16sse\15sep\14pat\13cx8\12pae\11mca" \ 380 "\10mmx\7cmov\6de\5pge\4mtrr\3msr\2tsc\1lgpg" 381 382 /* 383 * x86_type is a legacy concept; this is supplanted 384 * for most purposes by x86_feature; modern CPUs 385 * should be X86_TYPE_OTHER 386 */ 387 #define X86_TYPE_OTHER 0 388 #define X86_TYPE_486 1 389 #define X86_TYPE_P5 2 390 #define X86_TYPE_P6 3 391 #define X86_TYPE_CYRIX_486 4 392 #define X86_TYPE_CYRIX_6x86L 5 393 #define X86_TYPE_CYRIX_6x86 6 394 #define X86_TYPE_CYRIX_GXm 7 395 #define X86_TYPE_CYRIX_6x86MX 8 396 #define X86_TYPE_CYRIX_MediaGX 9 397 #define X86_TYPE_CYRIX_MII 10 398 #define X86_TYPE_VIA_CYRIX_III 11 399 #define X86_TYPE_P4 12 400 401 /* 402 * x86_vendor allows us to select between 403 * implementation features and helps guide 404 * the interpretation of the cpuid instruction. 405 */ 406 #define X86_VENDOR_Intel 0 /* GenuineIntel */ 407 #define X86_VENDOR_IntelClone 1 /* (an Intel clone) */ 408 #define X86_VENDOR_AMD 2 /* AuthenticAMD */ 409 #define X86_VENDOR_Cyrix 3 /* CyrixInstead */ 410 #define X86_VENDOR_UMC 4 /* UMC UMC UMC */ 411 #define X86_VENDOR_NexGen 5 /* NexGenDriven */ 412 #define X86_VENDOR_Centaur 6 /* CentaurHauls */ 413 #define X86_VENDOR_Rise 7 /* RiseRiseRise */ 414 #define X86_VENDOR_SiS 8 /* SiS SiS SiS */ 415 #define X86_VENDOR_TM 9 /* GenuineTMx86 */ 416 #define X86_VENDOR_NSC 10 /* Geode by NSC */ 417 418 #define X86_VENDOR_STRLEN 13 /* vendor string max len + \0 */ 419 420 /* 421 * Some vendor/family/model/stepping ranges are commonly grouped under 422 * a single identifying banner by the vendor. The following encode 423 * that "revision" in a uint32_t with the 8 most significant bits 424 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 425 * family, and the remaining 16 typically forming a bitmask of revisions 426 * within that family with more significant bits indicating "later" revisions. 427 */ 428 429 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 430 #define _X86_CHIPREV_VENDOR_SHIFT 24 431 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 432 #define _X86_CHIPREV_FAMILY_SHIFT 16 433 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 434 435 #define _X86_CHIPREV_VENDOR(x) \ 436 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 437 #define _X86_CHIPREV_FAMILY(x) \ 438 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 439 #define _X86_CHIPREV_REV(x) \ 440 ((x) & _X86_CHIPREV_REV_MASK) 441 442 /* True if x matches in vendor and family and if x matches the given rev mask */ 443 #define X86_CHIPREV_MATCH(x, mask) \ 444 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 445 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 446 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 447 448 /* True if x matches in vendor and family and rev is at least minx */ 449 #define X86_CHIPREV_ATLEAST(x, minx) \ 450 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 451 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 452 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 453 454 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 455 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 456 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 457 458 /* Revision default */ 459 #define X86_CHIPREV_UNKNOWN 0x0 460 461 /* 462 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 463 * sufficiently different that we will distinguish them; in all other 464 * case we will identify the major revision. 465 */ 466 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 467 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 468 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 469 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 470 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 471 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 472 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 473 474 /* 475 * Various socket/package types, extended as the need to distinguish 476 * a new type arises. The top 8 byte identfies the vendor and the 477 * remaining 24 bits describe 24 socket types. 478 */ 479 480 #define _X86_SOCKET_VENDOR_SHIFT 24 481 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 482 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 483 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 484 485 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 486 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 487 488 #define X86_SOCKET_MATCH(s, mask) \ 489 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 490 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 491 492 #define X86_SOCKET_UNKNOWN 0x0 493 /* 494 * AMD socket types 495 */ 496 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 497 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 498 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 499 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 500 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 501 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 502 503 #if !defined(_ASM) 504 505 #if defined(_KERNEL) || defined(_KMEMUSER) 506 507 extern uint_t x86_feature; 508 extern uint_t x86_type; 509 extern uint_t x86_vendor; 510 511 extern uint_t pentiumpro_bug4046376; 512 extern uint_t pentiumpro_bug4064495; 513 514 extern uint_t enable486; 515 516 extern const char CyrixInstead[]; 517 518 #endif 519 520 #if defined(_KERNEL) 521 522 /* 523 * This structure is used to pass arguments and get return values back 524 * from the CPUID instruction in __cpuid_insn() routine. 525 */ 526 struct cpuid_regs { 527 uint32_t cp_eax; 528 uint32_t cp_ebx; 529 uint32_t cp_ecx; 530 uint32_t cp_edx; 531 }; 532 533 extern uint64_t rdmsr(uint_t); 534 extern void wrmsr(uint_t, const uint64_t); 535 extern uint64_t xrdmsr(uint_t); 536 extern void xwrmsr(uint_t, const uint64_t); 537 extern int checked_rdmsr(uint_t, uint64_t *); 538 extern int checked_wrmsr(uint_t, uint64_t); 539 540 extern void invalidate_cache(void); 541 extern ulong_t getcr4(void); 542 extern void setcr4(ulong_t); 543 544 extern void mtrr_sync(void); 545 546 extern void cpu_fast_syscall_enable(void *); 547 extern void cpu_fast_syscall_disable(void *); 548 549 struct cpu; 550 551 extern int cpuid_checkpass(struct cpu *, int); 552 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 553 extern uint32_t __cpuid_insn(struct cpuid_regs *); 554 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 555 extern int cpuid_getidstr(struct cpu *, char *, size_t); 556 extern const char *cpuid_getvendorstr(struct cpu *); 557 extern uint_t cpuid_getvendor(struct cpu *); 558 extern uint_t cpuid_getfamily(struct cpu *); 559 extern uint_t cpuid_getmodel(struct cpu *); 560 extern uint_t cpuid_getstep(struct cpu *); 561 extern uint_t cpuid_getsig(struct cpu *); 562 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 563 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 564 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 565 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 566 extern int cpuid_get_chipid(struct cpu *); 567 extern id_t cpuid_get_coreid(struct cpu *); 568 extern int cpuid_get_clogid(struct cpu *); 569 extern int cpuid_is_cmt(struct cpu *); 570 extern int cpuid_syscall32_insn(struct cpu *); 571 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 572 573 extern uint32_t cpuid_getchiprev(struct cpu *); 574 extern const char *cpuid_getchiprevstr(struct cpu *); 575 extern uint32_t cpuid_getsockettype(struct cpu *); 576 577 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 578 579 struct cpuid_info; 580 581 extern void setx86isalist(void); 582 extern void cpuid_alloc_space(struct cpu *); 583 extern void cpuid_free_space(struct cpu *); 584 extern uint_t cpuid_pass1(struct cpu *); 585 extern void cpuid_pass2(struct cpu *); 586 extern void cpuid_pass3(struct cpu *); 587 extern uint_t cpuid_pass4(struct cpu *); 588 extern void add_cpunode2devtree(processorid_t, struct cpuid_info *); 589 590 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 591 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 592 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 593 extern void cpuid_mwait_free(struct cpu *); 594 595 struct cpu_ucode_info; 596 597 extern void ucode_alloc_space(struct cpu *); 598 extern void ucode_free_space(struct cpu *); 599 extern void ucode_check(struct cpu *); 600 extern void ucode_free(); 601 602 extern uint_t workaround_errata(struct cpu *); 603 604 #if defined(OPTERON_ERRATUM_93) 605 extern int opteron_erratum_93; 606 #endif 607 608 #if defined(OPTERON_ERRATUM_91) 609 extern int opteron_erratum_91; 610 #endif 611 612 #if defined(OPTERON_ERRATUM_100) 613 extern int opteron_erratum_100; 614 #endif 615 616 #if defined(OPTERON_ERRATUM_121) 617 extern int opteron_erratum_121; 618 #endif 619 620 #if defined(OPTERON_WORKAROUND_6323525) 621 extern int opteron_workaround_6323525; 622 extern void patch_workaround_6323525(void); 623 #endif 624 625 #endif /* _KERNEL */ 626 627 #endif 628 629 #ifdef __cplusplus 630 } 631 #endif 632 633 #endif /* _SYS_X86_ARCHEXT_H */ 634