xref: /illumos-gate/usr/src/uts/intel/sys/x86_archext.h (revision 4cfd297a28611f28d039f8167cb91ca8542ed3e0)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23  * Copyright (c) 2011 by Delphix. All rights reserved.
24  * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25  */
26 /*
27  * Copyright (c) 2010, Intel Corporation.
28  * All rights reserved.
29  */
30 /*
31  * Copyright (c) 2015, Joyent, Inc.
32  * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
33  * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
34  * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
35  */
36 
37 #ifndef _SYS_X86_ARCHEXT_H
38 #define	_SYS_X86_ARCHEXT_H
39 
40 #if !defined(_ASM)
41 #include <sys/regset.h>
42 #include <sys/processor.h>
43 #include <vm/seg_enum.h>
44 #include <vm/page.h>
45 #endif	/* _ASM */
46 
47 #ifdef	__cplusplus
48 extern "C" {
49 #endif
50 
51 /*
52  * cpuid instruction feature flags in %edx (standard function 1)
53  */
54 
55 #define	CPUID_INTC_EDX_FPU	0x00000001	/* x87 fpu present */
56 #define	CPUID_INTC_EDX_VME	0x00000002	/* virtual-8086 extension */
57 #define	CPUID_INTC_EDX_DE	0x00000004	/* debugging extensions */
58 #define	CPUID_INTC_EDX_PSE	0x00000008	/* page size extension */
59 #define	CPUID_INTC_EDX_TSC	0x00000010	/* time stamp counter */
60 #define	CPUID_INTC_EDX_MSR	0x00000020	/* rdmsr and wrmsr */
61 #define	CPUID_INTC_EDX_PAE	0x00000040	/* physical addr extension */
62 #define	CPUID_INTC_EDX_MCE	0x00000080	/* machine check exception */
63 #define	CPUID_INTC_EDX_CX8	0x00000100	/* cmpxchg8b instruction */
64 #define	CPUID_INTC_EDX_APIC	0x00000200	/* local APIC */
65 						/* 0x400 - reserved */
66 #define	CPUID_INTC_EDX_SEP	0x00000800	/* sysenter and sysexit */
67 #define	CPUID_INTC_EDX_MTRR	0x00001000	/* memory type range reg */
68 #define	CPUID_INTC_EDX_PGE	0x00002000	/* page global enable */
69 #define	CPUID_INTC_EDX_MCA	0x00004000	/* machine check arch */
70 #define	CPUID_INTC_EDX_CMOV	0x00008000	/* conditional move insns */
71 #define	CPUID_INTC_EDX_PAT	0x00010000	/* page attribute table */
72 #define	CPUID_INTC_EDX_PSE36	0x00020000	/* 36-bit pagesize extension */
73 #define	CPUID_INTC_EDX_PSN	0x00040000	/* processor serial number */
74 #define	CPUID_INTC_EDX_CLFSH	0x00080000	/* clflush instruction */
75 						/* 0x100000 - reserved */
76 #define	CPUID_INTC_EDX_DS	0x00200000	/* debug store exists */
77 #define	CPUID_INTC_EDX_ACPI	0x00400000	/* monitoring + clock ctrl */
78 #define	CPUID_INTC_EDX_MMX	0x00800000	/* MMX instructions */
79 #define	CPUID_INTC_EDX_FXSR	0x01000000	/* fxsave and fxrstor */
80 #define	CPUID_INTC_EDX_SSE	0x02000000	/* streaming SIMD extensions */
81 #define	CPUID_INTC_EDX_SSE2	0x04000000	/* SSE extensions */
82 #define	CPUID_INTC_EDX_SS	0x08000000	/* self-snoop */
83 #define	CPUID_INTC_EDX_HTT	0x10000000	/* Hyper Thread Technology */
84 #define	CPUID_INTC_EDX_TM	0x20000000	/* thermal monitoring */
85 #define	CPUID_INTC_EDX_IA64	0x40000000	/* Itanium emulating IA32 */
86 #define	CPUID_INTC_EDX_PBE	0x80000000	/* Pending Break Enable */
87 
88 /*
89  * cpuid instruction feature flags in %ecx (standard function 1)
90  */
91 
92 #define	CPUID_INTC_ECX_SSE3	0x00000001	/* Yet more SSE extensions */
93 #define	CPUID_INTC_ECX_PCLMULQDQ 0x00000002 	/* PCLMULQDQ insn */
94 						/* 0x00000004 - reserved */
95 #define	CPUID_INTC_ECX_MON	0x00000008	/* MONITOR/MWAIT */
96 #define	CPUID_INTC_ECX_DSCPL	0x00000010	/* CPL-qualified debug store */
97 #define	CPUID_INTC_ECX_VMX	0x00000020	/* Hardware VM extensions */
98 #define	CPUID_INTC_ECX_SMX	0x00000040	/* Secure mode extensions */
99 #define	CPUID_INTC_ECX_EST	0x00000080	/* enhanced SpeedStep */
100 #define	CPUID_INTC_ECX_TM2	0x00000100	/* thermal monitoring */
101 #define	CPUID_INTC_ECX_SSSE3	0x00000200	/* Supplemental SSE3 insns */
102 #define	CPUID_INTC_ECX_CID	0x00000400	/* L1 context ID */
103 						/* 0x00000800 - reserved */
104 #define	CPUID_INTC_ECX_FMA	0x00001000	/* Fused Multiply Add */
105 #define	CPUID_INTC_ECX_CX16	0x00002000	/* cmpxchg16 */
106 #define	CPUID_INTC_ECX_ETPRD	0x00004000	/* extended task pri messages */
107 						/* 0x00008000 - reserved */
108 						/* 0x00010000 - reserved */
109 						/* 0x00020000 - reserved */
110 #define	CPUID_INTC_ECX_DCA	0x00040000	/* direct cache access */
111 #define	CPUID_INTC_ECX_SSE4_1	0x00080000	/* SSE4.1 insns */
112 #define	CPUID_INTC_ECX_SSE4_2	0x00100000	/* SSE4.2 insns */
113 #define	CPUID_INTC_ECX_X2APIC	0x00200000	/* x2APIC */
114 #define	CPUID_INTC_ECX_MOVBE	0x00400000	/* MOVBE insn */
115 #define	CPUID_INTC_ECX_POPCNT	0x00800000	/* POPCNT insn */
116 #define	CPUID_INTC_ECX_AES	0x02000000	/* AES insns */
117 #define	CPUID_INTC_ECX_XSAVE	0x04000000	/* XSAVE/XRESTOR insns */
118 #define	CPUID_INTC_ECX_OSXSAVE	0x08000000	/* OS supports XSAVE insns */
119 #define	CPUID_INTC_ECX_AVX	0x10000000	/* AVX supported */
120 #define	CPUID_INTC_ECX_F16C	0x20000000	/* F16C supported */
121 #define	CPUID_INTC_ECX_RDRAND	0x40000000	/* RDRAND supported */
122 #define	CPUID_INTC_ECX_HV	0x80000000	/* Hypervisor */
123 
124 /*
125  * cpuid instruction feature flags in %edx (extended function 0x80000001)
126  */
127 
128 #define	CPUID_AMD_EDX_FPU	0x00000001	/* x87 fpu present */
129 #define	CPUID_AMD_EDX_VME	0x00000002	/* virtual-8086 extension */
130 #define	CPUID_AMD_EDX_DE	0x00000004	/* debugging extensions */
131 #define	CPUID_AMD_EDX_PSE	0x00000008	/* page size extensions */
132 #define	CPUID_AMD_EDX_TSC	0x00000010	/* time stamp counter */
133 #define	CPUID_AMD_EDX_MSR	0x00000020	/* rdmsr and wrmsr */
134 #define	CPUID_AMD_EDX_PAE	0x00000040	/* physical addr extension */
135 #define	CPUID_AMD_EDX_MCE	0x00000080	/* machine check exception */
136 #define	CPUID_AMD_EDX_CX8	0x00000100	/* cmpxchg8b instruction */
137 #define	CPUID_AMD_EDX_APIC	0x00000200	/* local APIC */
138 						/* 0x00000400 - sysc on K6m6 */
139 #define	CPUID_AMD_EDX_SYSC	0x00000800	/* AMD: syscall and sysret */
140 #define	CPUID_AMD_EDX_MTRR	0x00001000	/* memory type and range reg */
141 #define	CPUID_AMD_EDX_PGE	0x00002000	/* page global enable */
142 #define	CPUID_AMD_EDX_MCA	0x00004000	/* machine check arch */
143 #define	CPUID_AMD_EDX_CMOV	0x00008000	/* conditional move insns */
144 #define	CPUID_AMD_EDX_PAT	0x00010000	/* K7: page attribute table */
145 #define	CPUID_AMD_EDX_FCMOV	0x00010000	/* FCMOVcc etc. */
146 #define	CPUID_AMD_EDX_PSE36	0x00020000	/* 36-bit pagesize extension */
147 				/* 0x00040000 - reserved */
148 				/* 0x00080000 - reserved */
149 #define	CPUID_AMD_EDX_NX	0x00100000	/* AMD: no-execute page prot */
150 				/* 0x00200000 - reserved */
151 #define	CPUID_AMD_EDX_MMXamd	0x00400000	/* AMD: MMX extensions */
152 #define	CPUID_AMD_EDX_MMX	0x00800000	/* MMX instructions */
153 #define	CPUID_AMD_EDX_FXSR	0x01000000	/* fxsave and fxrstor */
154 #define	CPUID_AMD_EDX_FFXSR	0x02000000	/* fast fxsave/fxrstor */
155 #define	CPUID_AMD_EDX_1GPG	0x04000000	/* 1GB page */
156 #define	CPUID_AMD_EDX_TSCP	0x08000000	/* rdtscp instruction */
157 				/* 0x10000000 - reserved */
158 #define	CPUID_AMD_EDX_LM	0x20000000	/* AMD: long mode */
159 #define	CPUID_AMD_EDX_3DNowx	0x40000000	/* AMD: extensions to 3DNow! */
160 #define	CPUID_AMD_EDX_3DNow	0x80000000	/* AMD: 3DNow! instructions */
161 
162 #define	CPUID_AMD_ECX_AHF64	0x00000001	/* LAHF and SAHF in long mode */
163 #define	CPUID_AMD_ECX_CMP_LGCY	0x00000002	/* AMD: multicore chip */
164 #define	CPUID_AMD_ECX_SVM	0x00000004	/* AMD: secure VM */
165 #define	CPUID_AMD_ECX_EAS	0x00000008	/* extended apic space */
166 #define	CPUID_AMD_ECX_CR8D	0x00000010	/* AMD: 32-bit mov %cr8 */
167 #define	CPUID_AMD_ECX_LZCNT	0x00000020	/* AMD: LZCNT insn */
168 #define	CPUID_AMD_ECX_SSE4A	0x00000040	/* AMD: SSE4A insns */
169 #define	CPUID_AMD_ECX_MAS	0x00000080	/* AMD: MisAlignSse mnode */
170 #define	CPUID_AMD_ECX_3DNP	0x00000100	/* AMD: 3DNowPrefectch */
171 #define	CPUID_AMD_ECX_OSVW	0x00000200	/* AMD: OSVW */
172 #define	CPUID_AMD_ECX_IBS	0x00000400	/* AMD: IBS */
173 #define	CPUID_AMD_ECX_SSE5	0x00000800	/* AMD: SSE5 */
174 #define	CPUID_AMD_ECX_SKINIT	0x00001000	/* AMD: SKINIT */
175 #define	CPUID_AMD_ECX_WDT	0x00002000	/* AMD: WDT */
176 #define	CPUID_AMD_ECX_TOPOEXT	0x00400000	/* AMD: Topology Extensions */
177 
178 /*
179  * Intel now seems to have claimed part of the "extended" function
180  * space that we previously for non-Intel implementors to use.
181  * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
182  * is available in long mode i.e. what AMD indicate using bit 0.
183  * On the other hand, everything else is labelled as reserved.
184  */
185 #define	CPUID_INTC_ECX_AHF64	0x00100000	/* LAHF and SAHF in long mode */
186 
187 /*
188  * Intel also uses cpuid leaf 7 to have additional instructions and features.
189  * Like some other leaves, but unlike the current ones we care about, it
190  * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
191  * with the potential use of additional sub-leaves in the future, we now
192  * specifically label the EBX features with their leaf and sub-leaf.
193  */
194 #define	CPUID_INTC_EBX_7_0_BMI1		0x00000008	/* BMI1 instrs */
195 #define	CPUID_INTC_EBX_7_0_AVX2		0x00000020	/* AVX2 supported */
196 #define	CPUID_INTC_EBX_7_0_SMEP		0x00000080	/* SMEP in CR4 */
197 #define	CPUID_INTC_EBX_7_0_BMI2		0x00000100	/* BMI2 Instrs */
198 
199 #define	P5_MCHADDR	0x0
200 #define	P5_CESR		0x11
201 #define	P5_CTR0		0x12
202 #define	P5_CTR1		0x13
203 
204 #define	K5_MCHADDR	0x0
205 #define	K5_MCHTYPE	0x01
206 #define	K5_TSC		0x10
207 #define	K5_TR12		0x12
208 
209 #define	REG_PAT		0x277
210 
211 #define	REG_MC0_CTL		0x400
212 #define	REG_MC5_MISC		0x417
213 #define	REG_PERFCTR0		0xc1
214 #define	REG_PERFCTR1		0xc2
215 
216 #define	REG_PERFEVNT0		0x186
217 #define	REG_PERFEVNT1		0x187
218 
219 #define	REG_TSC			0x10	/* timestamp counter */
220 #define	REG_APIC_BASE_MSR	0x1b
221 #define	REG_X2APIC_BASE_MSR	0x800	/* The MSR address offset of x2APIC */
222 
223 #if !defined(__xpv)
224 /*
225  * AMD C1E
226  */
227 #define	MSR_AMD_INT_PENDING_CMP_HALT	0xC0010055
228 #define	AMD_ACTONCMPHALT_SHIFT	27
229 #define	AMD_ACTONCMPHALT_MASK	3
230 #endif
231 
232 #define	MSR_DEBUGCTL		0x1d9
233 
234 #define	DEBUGCTL_LBR		0x01
235 #define	DEBUGCTL_BTF		0x02
236 
237 /* Intel P6, AMD */
238 #define	MSR_LBR_FROM		0x1db
239 #define	MSR_LBR_TO		0x1dc
240 #define	MSR_LEX_FROM		0x1dd
241 #define	MSR_LEX_TO		0x1de
242 
243 /* Intel P4 (pre-Prescott, non P4 M) */
244 #define	MSR_P4_LBSTK_TOS	0x1da
245 #define	MSR_P4_LBSTK_0		0x1db
246 #define	MSR_P4_LBSTK_1		0x1dc
247 #define	MSR_P4_LBSTK_2		0x1dd
248 #define	MSR_P4_LBSTK_3		0x1de
249 
250 /* Intel Pentium M */
251 #define	MSR_P6M_LBSTK_TOS	0x1c9
252 #define	MSR_P6M_LBSTK_0		0x040
253 #define	MSR_P6M_LBSTK_1		0x041
254 #define	MSR_P6M_LBSTK_2		0x042
255 #define	MSR_P6M_LBSTK_3		0x043
256 #define	MSR_P6M_LBSTK_4		0x044
257 #define	MSR_P6M_LBSTK_5		0x045
258 #define	MSR_P6M_LBSTK_6		0x046
259 #define	MSR_P6M_LBSTK_7		0x047
260 
261 /* Intel P4 (Prescott) */
262 #define	MSR_PRP4_LBSTK_TOS	0x1da
263 #define	MSR_PRP4_LBSTK_FROM_0	0x680
264 #define	MSR_PRP4_LBSTK_FROM_1	0x681
265 #define	MSR_PRP4_LBSTK_FROM_2	0x682
266 #define	MSR_PRP4_LBSTK_FROM_3	0x683
267 #define	MSR_PRP4_LBSTK_FROM_4	0x684
268 #define	MSR_PRP4_LBSTK_FROM_5	0x685
269 #define	MSR_PRP4_LBSTK_FROM_6	0x686
270 #define	MSR_PRP4_LBSTK_FROM_7	0x687
271 #define	MSR_PRP4_LBSTK_FROM_8 	0x688
272 #define	MSR_PRP4_LBSTK_FROM_9	0x689
273 #define	MSR_PRP4_LBSTK_FROM_10	0x68a
274 #define	MSR_PRP4_LBSTK_FROM_11 	0x68b
275 #define	MSR_PRP4_LBSTK_FROM_12	0x68c
276 #define	MSR_PRP4_LBSTK_FROM_13	0x68d
277 #define	MSR_PRP4_LBSTK_FROM_14	0x68e
278 #define	MSR_PRP4_LBSTK_FROM_15	0x68f
279 #define	MSR_PRP4_LBSTK_TO_0	0x6c0
280 #define	MSR_PRP4_LBSTK_TO_1	0x6c1
281 #define	MSR_PRP4_LBSTK_TO_2	0x6c2
282 #define	MSR_PRP4_LBSTK_TO_3	0x6c3
283 #define	MSR_PRP4_LBSTK_TO_4	0x6c4
284 #define	MSR_PRP4_LBSTK_TO_5	0x6c5
285 #define	MSR_PRP4_LBSTK_TO_6	0x6c6
286 #define	MSR_PRP4_LBSTK_TO_7	0x6c7
287 #define	MSR_PRP4_LBSTK_TO_8	0x6c8
288 #define	MSR_PRP4_LBSTK_TO_9 	0x6c9
289 #define	MSR_PRP4_LBSTK_TO_10	0x6ca
290 #define	MSR_PRP4_LBSTK_TO_11	0x6cb
291 #define	MSR_PRP4_LBSTK_TO_12	0x6cc
292 #define	MSR_PRP4_LBSTK_TO_13	0x6cd
293 #define	MSR_PRP4_LBSTK_TO_14	0x6ce
294 #define	MSR_PRP4_LBSTK_TO_15	0x6cf
295 
296 #define	MCI_CTL_VALUE		0xffffffff
297 
298 #define	MTRR_TYPE_UC		0
299 #define	MTRR_TYPE_WC		1
300 #define	MTRR_TYPE_WT		4
301 #define	MTRR_TYPE_WP		5
302 #define	MTRR_TYPE_WB		6
303 #define	MTRR_TYPE_UC_		7
304 
305 /*
306  * For Solaris we set up the page attritubute table in the following way:
307  * PAT0	Write-Back
308  * PAT1	Write-Through
309  * PAT2	Unchacheable-
310  * PAT3	Uncacheable
311  * PAT4 Write-Back
312  * PAT5	Write-Through
313  * PAT6	Write-Combine
314  * PAT7 Uncacheable
315  * The only difference from h/w default is entry 6.
316  */
317 #define	PAT_DEFAULT_ATTRIBUTE			\
318 	((uint64_t)MTRR_TYPE_WB |		\
319 	((uint64_t)MTRR_TYPE_WT << 8) |		\
320 	((uint64_t)MTRR_TYPE_UC_ << 16) |	\
321 	((uint64_t)MTRR_TYPE_UC << 24) |	\
322 	((uint64_t)MTRR_TYPE_WB << 32) |	\
323 	((uint64_t)MTRR_TYPE_WT << 40) |	\
324 	((uint64_t)MTRR_TYPE_WC << 48) |	\
325 	((uint64_t)MTRR_TYPE_UC << 56))
326 
327 #define	X86FSET_LARGEPAGE	0
328 #define	X86FSET_TSC		1
329 #define	X86FSET_MSR		2
330 #define	X86FSET_MTRR		3
331 #define	X86FSET_PGE		4
332 #define	X86FSET_DE		5
333 #define	X86FSET_CMOV		6
334 #define	X86FSET_MMX		7
335 #define	X86FSET_MCA		8
336 #define	X86FSET_PAE		9
337 #define	X86FSET_CX8		10
338 #define	X86FSET_PAT		11
339 #define	X86FSET_SEP		12
340 #define	X86FSET_SSE		13
341 #define	X86FSET_SSE2		14
342 #define	X86FSET_HTT		15
343 #define	X86FSET_ASYSC		16
344 #define	X86FSET_NX		17
345 #define	X86FSET_SSE3		18
346 #define	X86FSET_CX16		19
347 #define	X86FSET_CMP		20
348 #define	X86FSET_TSCP		21
349 #define	X86FSET_MWAIT		22
350 #define	X86FSET_SSE4A		23
351 #define	X86FSET_CPUID		24
352 #define	X86FSET_SSSE3		25
353 #define	X86FSET_SSE4_1		26
354 #define	X86FSET_SSE4_2		27
355 #define	X86FSET_1GPG		28
356 #define	X86FSET_CLFSH		29
357 #define	X86FSET_64		30
358 #define	X86FSET_AES		31
359 #define	X86FSET_PCLMULQDQ	32
360 #define	X86FSET_XSAVE		33
361 #define	X86FSET_AVX		34
362 #define	X86FSET_VMX		35
363 #define	X86FSET_SVM		36
364 #define	X86FSET_TOPOEXT		37
365 #define	X86FSET_F16C		38
366 #define	X86FSET_RDRAND		39
367 #define	X86FSET_X2APIC		40
368 #define	X86FSET_AVX2		41
369 #define	X86FSET_BMI1		42
370 #define	X86FSET_BMI2		43
371 #define	X86FSET_FMA		44
372 #define	X86FSET_SMEP		45
373 
374 /*
375  * flags to patch tsc_read routine.
376  */
377 #define	X86_NO_TSC		0x0
378 #define	X86_HAVE_TSCP		0x1
379 #define	X86_TSC_MFENCE		0x2
380 #define	X86_TSC_LFENCE		0x4
381 
382 /*
383  * Intel Deep C-State invariant TSC in leaf 0x80000007.
384  */
385 #define	CPUID_TSC_CSTATE_INVARIANCE	(0x100)
386 
387 /*
388  * Intel Deep C-state always-running local APIC timer
389  */
390 #define	CPUID_CSTATE_ARAT	(0x4)
391 
392 /*
393  * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
394  */
395 #define	CPUID_EPB_SUPPORT	(1 << 3)
396 
397 /*
398  * Intel TSC deadline timer
399  */
400 #define	CPUID_DEADLINE_TSC	(1 << 24)
401 
402 /*
403  * x86_type is a legacy concept; this is supplanted
404  * for most purposes by x86_featureset; modern CPUs
405  * should be X86_TYPE_OTHER
406  */
407 #define	X86_TYPE_OTHER		0
408 #define	X86_TYPE_486		1
409 #define	X86_TYPE_P5		2
410 #define	X86_TYPE_P6		3
411 #define	X86_TYPE_CYRIX_486	4
412 #define	X86_TYPE_CYRIX_6x86L	5
413 #define	X86_TYPE_CYRIX_6x86	6
414 #define	X86_TYPE_CYRIX_GXm	7
415 #define	X86_TYPE_CYRIX_6x86MX	8
416 #define	X86_TYPE_CYRIX_MediaGX	9
417 #define	X86_TYPE_CYRIX_MII	10
418 #define	X86_TYPE_VIA_CYRIX_III	11
419 #define	X86_TYPE_P4		12
420 
421 /*
422  * x86_vendor allows us to select between
423  * implementation features and helps guide
424  * the interpretation of the cpuid instruction.
425  */
426 #define	X86_VENDOR_Intel	0
427 #define	X86_VENDORSTR_Intel	"GenuineIntel"
428 
429 #define	X86_VENDOR_IntelClone	1
430 
431 #define	X86_VENDOR_AMD		2
432 #define	X86_VENDORSTR_AMD	"AuthenticAMD"
433 
434 #define	X86_VENDOR_Cyrix	3
435 #define	X86_VENDORSTR_CYRIX	"CyrixInstead"
436 
437 #define	X86_VENDOR_UMC		4
438 #define	X86_VENDORSTR_UMC	"UMC UMC UMC "
439 
440 #define	X86_VENDOR_NexGen	5
441 #define	X86_VENDORSTR_NexGen	"NexGenDriven"
442 
443 #define	X86_VENDOR_Centaur	6
444 #define	X86_VENDORSTR_Centaur	"CentaurHauls"
445 
446 #define	X86_VENDOR_Rise		7
447 #define	X86_VENDORSTR_Rise	"RiseRiseRise"
448 
449 #define	X86_VENDOR_SiS		8
450 #define	X86_VENDORSTR_SiS	"SiS SiS SiS "
451 
452 #define	X86_VENDOR_TM		9
453 #define	X86_VENDORSTR_TM	"GenuineTMx86"
454 
455 #define	X86_VENDOR_NSC		10
456 #define	X86_VENDORSTR_NSC	"Geode by NSC"
457 
458 /*
459  * Vendor string max len + \0
460  */
461 #define	X86_VENDOR_STRLEN	13
462 
463 /*
464  * Some vendor/family/model/stepping ranges are commonly grouped under
465  * a single identifying banner by the vendor.  The following encode
466  * that "revision" in a uint32_t with the 8 most significant bits
467  * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
468  * family, and the remaining 16 typically forming a bitmask of revisions
469  * within that family with more significant bits indicating "later" revisions.
470  */
471 
472 #define	_X86_CHIPREV_VENDOR_MASK	0xff000000u
473 #define	_X86_CHIPREV_VENDOR_SHIFT	24
474 #define	_X86_CHIPREV_FAMILY_MASK	0x00ff0000u
475 #define	_X86_CHIPREV_FAMILY_SHIFT	16
476 #define	_X86_CHIPREV_REV_MASK		0x0000ffffu
477 
478 #define	_X86_CHIPREV_VENDOR(x) \
479 	(((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
480 #define	_X86_CHIPREV_FAMILY(x) \
481 	(((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
482 #define	_X86_CHIPREV_REV(x) \
483 	((x) & _X86_CHIPREV_REV_MASK)
484 
485 /* True if x matches in vendor and family and if x matches the given rev mask */
486 #define	X86_CHIPREV_MATCH(x, mask) \
487 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
488 	_X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
489 	((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
490 
491 /* True if x matches in vendor and family, and rev is at least minx */
492 #define	X86_CHIPREV_ATLEAST(x, minx) \
493 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
494 	_X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
495 	_X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
496 
497 #define	_X86_CHIPREV_MKREV(vendor, family, rev) \
498 	((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
499 	(family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
500 
501 /* True if x matches in vendor, and family is at least minx */
502 #define	X86_CHIPFAM_ATLEAST(x, minx) \
503 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
504 	_X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
505 
506 /* Revision default */
507 #define	X86_CHIPREV_UNKNOWN	0x0
508 
509 /*
510  * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
511  * sufficiently different that we will distinguish them; in all other
512  * case we will identify the major revision.
513  */
514 #define	X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
515 #define	X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
516 #define	X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
517 #define	X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
518 #define	X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
519 #define	X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
520 #define	X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
521 
522 /*
523  * Definitions for AMD Family 0x10.  Rev A was Engineering Samples only.
524  */
525 #define	X86_CHIPREV_AMD_10_REV_A \
526 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
527 #define	X86_CHIPREV_AMD_10_REV_B \
528 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
529 #define	X86_CHIPREV_AMD_10_REV_C2 \
530 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
531 #define	X86_CHIPREV_AMD_10_REV_C3 \
532 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
533 #define	X86_CHIPREV_AMD_10_REV_D0 \
534 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
535 #define	X86_CHIPREV_AMD_10_REV_D1 \
536 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
537 #define	X86_CHIPREV_AMD_10_REV_E \
538 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
539 
540 /*
541  * Definitions for AMD Family 0x11.
542  */
543 #define	X86_CHIPREV_AMD_11_REV_B \
544 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
545 
546 /*
547  * Definitions for AMD Family 0x12.
548  */
549 #define	X86_CHIPREV_AMD_12_REV_B \
550 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
551 
552 /*
553  * Definitions for AMD Family 0x14.
554  */
555 #define	X86_CHIPREV_AMD_14_REV_B \
556 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
557 #define	X86_CHIPREV_AMD_14_REV_C \
558 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
559 
560 /*
561  * Definitions for AMD Family 0x15
562  */
563 #define	X86_CHIPREV_AMD_15OR_REV_B2 \
564 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
565 
566 #define	X86_CHIPREV_AMD_15TN_REV_A1 \
567 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
568 
569 /*
570  * Various socket/package types, extended as the need to distinguish
571  * a new type arises.  The top 8 byte identfies the vendor and the
572  * remaining 24 bits describe 24 socket types.
573  */
574 
575 #define	_X86_SOCKET_VENDOR_SHIFT	24
576 #define	_X86_SOCKET_VENDOR(x)	((x) >> _X86_SOCKET_VENDOR_SHIFT)
577 #define	_X86_SOCKET_TYPE_MASK	0x00ffffff
578 #define	_X86_SOCKET_TYPE(x)		((x) & _X86_SOCKET_TYPE_MASK)
579 
580 #define	_X86_SOCKET_MKVAL(vendor, bitval) \
581 	((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
582 
583 #define	X86_SOCKET_MATCH(s, mask) \
584 	(_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
585 	(_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
586 
587 #define	X86_SOCKET_UNKNOWN 0x0
588 	/*
589 	 * AMD socket types
590 	 */
591 #define	X86_SOCKET_754		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
592 #define	X86_SOCKET_939		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
593 #define	X86_SOCKET_940		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
594 #define	X86_SOCKET_S1g1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
595 #define	X86_SOCKET_AM2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
596 #define	X86_SOCKET_F1207	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
597 #define	X86_SOCKET_S1g2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
598 #define	X86_SOCKET_S1g3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
599 #define	X86_SOCKET_AM		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
600 #define	X86_SOCKET_AM2R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
601 #define	X86_SOCKET_AM3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
602 #define	X86_SOCKET_G34		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
603 #define	X86_SOCKET_ASB2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
604 #define	X86_SOCKET_C32		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
605 #define	X86_SOCKET_S1g4		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
606 #define	X86_SOCKET_FT1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
607 #define	X86_SOCKET_FM1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
608 #define	X86_SOCKET_FS1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
609 #define	X86_SOCKET_AM3R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
610 #define	X86_SOCKET_FP2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
611 #define	X86_SOCKET_FS1R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
612 #define	X86_SOCKET_FM2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
613 
614 /*
615  * xgetbv/xsetbv support
616  */
617 
618 #define	XFEATURE_ENABLED_MASK	0x0
619 /*
620  * XFEATURE_ENABLED_MASK values (eax)
621  */
622 #define	XFEATURE_LEGACY_FP	0x1
623 #define	XFEATURE_SSE		0x2
624 #define	XFEATURE_AVX		0x4
625 #define	XFEATURE_MAX		XFEATURE_AVX
626 #define	XFEATURE_FP_ALL	\
627 	(XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
628 
629 #if !defined(_ASM)
630 
631 #if defined(_KERNEL) || defined(_KMEMUSER)
632 
633 #define	NUM_X86_FEATURES	46
634 extern uchar_t x86_featureset[];
635 
636 extern void free_x86_featureset(void *featureset);
637 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
638 extern void add_x86_feature(void *featureset, uint_t feature);
639 extern void remove_x86_feature(void *featureset, uint_t feature);
640 extern boolean_t compare_x86_featureset(void *setA, void *setB);
641 extern void print_x86_featureset(void *featureset);
642 
643 
644 extern uint_t x86_type;
645 extern uint_t x86_vendor;
646 extern uint_t x86_clflush_size;
647 
648 extern uint_t pentiumpro_bug4046376;
649 
650 extern const char CyrixInstead[];
651 
652 #endif
653 
654 #if defined(_KERNEL)
655 
656 /*
657  * This structure is used to pass arguments and get return values back
658  * from the CPUID instruction in __cpuid_insn() routine.
659  */
660 struct cpuid_regs {
661 	uint32_t	cp_eax;
662 	uint32_t	cp_ebx;
663 	uint32_t	cp_ecx;
664 	uint32_t	cp_edx;
665 };
666 
667 /*
668  * Utility functions to get/set extended control registers (XCR)
669  * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
670  */
671 extern uint64_t get_xcr(uint_t);
672 extern void set_xcr(uint_t, uint64_t);
673 
674 extern uint64_t rdmsr(uint_t);
675 extern void wrmsr(uint_t, const uint64_t);
676 extern uint64_t xrdmsr(uint_t);
677 extern void xwrmsr(uint_t, const uint64_t);
678 extern int checked_rdmsr(uint_t, uint64_t *);
679 extern int checked_wrmsr(uint_t, uint64_t);
680 
681 extern void invalidate_cache(void);
682 extern ulong_t getcr4(void);
683 extern void setcr4(ulong_t);
684 
685 extern void mtrr_sync(void);
686 
687 extern void cpu_fast_syscall_enable(void *);
688 extern void cpu_fast_syscall_disable(void *);
689 
690 struct cpu;
691 
692 extern int cpuid_checkpass(struct cpu *, int);
693 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
694 extern uint32_t __cpuid_insn(struct cpuid_regs *);
695 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
696 extern int cpuid_getidstr(struct cpu *, char *, size_t);
697 extern const char *cpuid_getvendorstr(struct cpu *);
698 extern uint_t cpuid_getvendor(struct cpu *);
699 extern uint_t cpuid_getfamily(struct cpu *);
700 extern uint_t cpuid_getmodel(struct cpu *);
701 extern uint_t cpuid_getstep(struct cpu *);
702 extern uint_t cpuid_getsig(struct cpu *);
703 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
704 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
705 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
706 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
707 extern int cpuid_get_chipid(struct cpu *);
708 extern id_t cpuid_get_coreid(struct cpu *);
709 extern int cpuid_get_pkgcoreid(struct cpu *);
710 extern int cpuid_get_clogid(struct cpu *);
711 extern int cpuid_get_cacheid(struct cpu *);
712 extern uint32_t cpuid_get_apicid(struct cpu *);
713 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
714 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
715 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
716 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
717 extern int cpuid_is_cmt(struct cpu *);
718 extern int cpuid_syscall32_insn(struct cpu *);
719 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
720 
721 extern uint32_t cpuid_getchiprev(struct cpu *);
722 extern const char *cpuid_getchiprevstr(struct cpu *);
723 extern uint32_t cpuid_getsockettype(struct cpu *);
724 extern const char *cpuid_getsocketstr(struct cpu *);
725 
726 extern int cpuid_have_cr8access(struct cpu *);
727 
728 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
729 
730 struct cpuid_info;
731 
732 extern void setx86isalist(void);
733 extern void cpuid_alloc_space(struct cpu *);
734 extern void cpuid_free_space(struct cpu *);
735 extern void cpuid_pass1(struct cpu *, uchar_t *);
736 extern void cpuid_pass2(struct cpu *);
737 extern void cpuid_pass3(struct cpu *);
738 extern void cpuid_pass4(struct cpu *, uint_t *);
739 extern void cpuid_set_cpu_properties(void *, processorid_t,
740     struct cpuid_info *);
741 
742 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
743 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
744 
745 #if !defined(__xpv)
746 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
747 extern void cpuid_mwait_free(struct cpu *);
748 extern int cpuid_deep_cstates_supported(void);
749 extern int cpuid_arat_supported(void);
750 extern int cpuid_iepb_supported(struct cpu *);
751 extern int cpuid_deadline_tsc_supported(void);
752 extern void vmware_port(int, uint32_t *);
753 #endif
754 
755 struct cpu_ucode_info;
756 
757 extern void ucode_alloc_space(struct cpu *);
758 extern void ucode_free_space(struct cpu *);
759 extern void ucode_check(struct cpu *);
760 extern void ucode_cleanup();
761 
762 #if !defined(__xpv)
763 extern	char _tsc_mfence_start;
764 extern	char _tsc_mfence_end;
765 extern	char _tscp_start;
766 extern	char _tscp_end;
767 extern	char _no_rdtsc_start;
768 extern	char _no_rdtsc_end;
769 extern	char _tsc_lfence_start;
770 extern	char _tsc_lfence_end;
771 #endif
772 
773 #if !defined(__xpv)
774 extern	char bcopy_patch_start;
775 extern	char bcopy_patch_end;
776 extern	char bcopy_ck_size;
777 #endif
778 
779 extern void post_startup_cpu_fixups(void);
780 
781 extern uint_t workaround_errata(struct cpu *);
782 
783 #if defined(OPTERON_ERRATUM_93)
784 extern int opteron_erratum_93;
785 #endif
786 
787 #if defined(OPTERON_ERRATUM_91)
788 extern int opteron_erratum_91;
789 #endif
790 
791 #if defined(OPTERON_ERRATUM_100)
792 extern int opteron_erratum_100;
793 #endif
794 
795 #if defined(OPTERON_ERRATUM_121)
796 extern int opteron_erratum_121;
797 #endif
798 
799 #if defined(OPTERON_WORKAROUND_6323525)
800 extern int opteron_workaround_6323525;
801 extern void patch_workaround_6323525(void);
802 #endif
803 
804 #if !defined(__xpv)
805 extern void determine_platform(void);
806 #endif
807 extern int get_hwenv(void);
808 extern int is_controldom(void);
809 
810 extern void xsave_setup_msr(struct cpu *);
811 
812 /*
813  * Hypervisor signatures
814  */
815 #define	HVSIG_XEN_HVM	"XenVMMXenVMM"
816 #define	HVSIG_VMWARE	"VMwareVMware"
817 #define	HVSIG_KVM	"KVMKVMKVM"
818 #define	HVSIG_MICROSOFT	"Microsoft Hv"
819 
820 /*
821  * Defined hardware environments
822  */
823 #define	HW_NATIVE	(1 << 0)	/* Running on bare metal */
824 #define	HW_XEN_PV	(1 << 1)	/* Running on Xen PVM */
825 
826 #define	HW_XEN_HVM	(1 << 2)	/* Running on Xen HVM */
827 #define	HW_VMWARE	(1 << 3)	/* Running on VMware hypervisor */
828 #define	HW_KVM		(1 << 4)	/* Running on KVM hypervisor */
829 #define	HW_MICROSOFT	(1 << 5)	/* Running on Microsoft hypervisor */
830 
831 #define	HW_VIRTUAL	(HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT)
832 
833 #endif	/* _KERNEL */
834 
835 #endif	/* !_ASM */
836 
837 /*
838  * VMware hypervisor related defines
839  */
840 #define	VMWARE_HVMAGIC		0x564d5868
841 #define	VMWARE_HVPORT		0x5658
842 #define	VMWARE_HVCMD_GETVERSION	0x0a
843 #define	VMWARE_HVCMD_GETTSCFREQ	0x2d
844 
845 #ifdef	__cplusplus
846 }
847 #endif
848 
849 #endif	/* _SYS_X86_ARCHEXT_H */
850