17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5ee88d2b9Skchow * Common Development and Distribution License (the "License"). 6ee88d2b9Skchow * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 227417cfdeSKuriakose Kuruvilla * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23cfe84b82SMatt Amdur * Copyright (c) 2011 by Delphix. All rights reserved. 247c478bd9Sstevel@tonic-gate */ 25cef70d2cSBill Holler /* 2641afdfa7SKrishnendu Sadhukhan - Sun Microsystems * Copyright (c) 2010, Intel Corporation. 27cef70d2cSBill Holler * All rights reserved. 28cef70d2cSBill Holler */ 29faa20166SBryan Cantrill /* 30*a9cc46cfSRobert Mustacchi * Copyright 2019 Joyent, Inc. 3179321794SJens Elkner * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 3279321794SJens Elkner * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 336eedf6a5SJosef 'Jeff' Sipek * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34b13f152eSYuri Pankov * Copyright 2018 Nexenta Systems, Inc. 35faa20166SBryan Cantrill */ 367c478bd9Sstevel@tonic-gate 377c478bd9Sstevel@tonic-gate #ifndef _SYS_X86_ARCHEXT_H 387c478bd9Sstevel@tonic-gate #define _SYS_X86_ARCHEXT_H 397c478bd9Sstevel@tonic-gate 407c478bd9Sstevel@tonic-gate #if !defined(_ASM) 417c478bd9Sstevel@tonic-gate #include <sys/regset.h> 427c478bd9Sstevel@tonic-gate #include <sys/processor.h> 437c478bd9Sstevel@tonic-gate #include <vm/seg_enum.h> 447c478bd9Sstevel@tonic-gate #include <vm/page.h> 457c478bd9Sstevel@tonic-gate #endif /* _ASM */ 467c478bd9Sstevel@tonic-gate 477c478bd9Sstevel@tonic-gate #ifdef __cplusplus 487c478bd9Sstevel@tonic-gate extern "C" { 497c478bd9Sstevel@tonic-gate #endif 507c478bd9Sstevel@tonic-gate 517c478bd9Sstevel@tonic-gate /* 527c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (standard function 1) 537c478bd9Sstevel@tonic-gate */ 547c478bd9Sstevel@tonic-gate 557c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 567c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 577c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 587c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 597c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 607c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 617c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 627c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 637c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 647c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 657c478bd9Sstevel@tonic-gate /* 0x400 - reserved */ 667c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 677c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 687c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 697c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 707c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 717c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 727c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 737c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 747c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 757c478bd9Sstevel@tonic-gate /* 0x100000 - reserved */ 767c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 777c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 787c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 797c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 807c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 817c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 827c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 837c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 847c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85ae115bc7Smrj #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 867c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 877c478bd9Sstevel@tonic-gate 887c478bd9Sstevel@tonic-gate /* 897c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %ecx (standard function 1) 907c478bd9Sstevel@tonic-gate */ 917c478bd9Sstevel@tonic-gate 927c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 9358b49504SHans Rosenfeld #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 941d9a8ab8SJohn Levon #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 957c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 967c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 97ae115bc7Smrj #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 98ae115bc7Smrj #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 997c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 1007c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 101ae115bc7Smrj #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 1027c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 1037c478bd9Sstevel@tonic-gate /* 0x00000800 - reserved */ 104245ac945SRobert Mustacchi #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 105ae115bc7Smrj #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 106ae115bc7Smrj #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 1071d9a8ab8SJohn Levon #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 108ae115bc7Smrj /* 0x00010000 - reserved */ 1091d9a8ab8SJohn Levon #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 110ae115bc7Smrj #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 111d0f8ff6eSkk #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 112d0f8ff6eSkk #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 1136eedf6a5SJosef 'Jeff' Sipek #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 1145087e485SKrishnendu Sadhukhan - Sun Microsystems #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 115f8801251Skk #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 1161d9a8ab8SJohn Levon #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 117a50a8b93SKuriakose Kuruvilla #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 1187af88ac7SKuriakose Kuruvilla #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 1197af88ac7SKuriakose Kuruvilla #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 1207af88ac7SKuriakose Kuruvilla #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 121ebb8ac07SRobert Mustacchi #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 122ebb8ac07SRobert Mustacchi #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 12379ec9da8SYuri Pankov #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 124ae115bc7Smrj 1257c478bd9Sstevel@tonic-gate /* 1267c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (extended function 0x80000001) 1277c478bd9Sstevel@tonic-gate */ 1287c478bd9Sstevel@tonic-gate 1297c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 1307c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 1317c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 1327c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 1337c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 1347c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 1357c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 1367c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 1377c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 1387c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 1397c478bd9Sstevel@tonic-gate /* 0x00000400 - sysc on K6m6 */ 1407c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 1417c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 1427c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 1437c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 1447c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 145ae115bc7Smrj #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 146ae115bc7Smrj #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 1477c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 1487c478bd9Sstevel@tonic-gate /* 0x00040000 - reserved */ 1497c478bd9Sstevel@tonic-gate /* 0x00080000 - reserved */ 1507c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 1517c478bd9Sstevel@tonic-gate /* 0x00200000 - reserved */ 1527c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 1537c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 1547c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 155ae115bc7Smrj #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 15602bc52beSkchow #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 157ae115bc7Smrj #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 1587c478bd9Sstevel@tonic-gate /* 0x10000000 - reserved */ 1597c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 1607c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 1617c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 1627c478bd9Sstevel@tonic-gate 163d0e58ef5SRobert Mustacchi /* 164d0e58ef5SRobert Mustacchi * AMD extended function 0x80000001 %ecx 165d0e58ef5SRobert Mustacchi */ 166d0e58ef5SRobert Mustacchi 167ae115bc7Smrj #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 168ae115bc7Smrj #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 169ae115bc7Smrj #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 170ae115bc7Smrj #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 171ae115bc7Smrj #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 172f8801251Skk #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 173f8801251Skk #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 174512cf780Skchow #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 175512cf780Skchow #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 176512cf780Skchow #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 177512cf780Skchow #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 178cff040f3SRobert Mustacchi #define CPUID_AMD_ECX_XOP 0x00000800 /* AMD: Extended Operation */ 179512cf780Skchow #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 180512cf780Skchow #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 1811d9a8ab8SJohn Levon /* 0x00004000 - reserved */ 1821d9a8ab8SJohn Levon #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 1831d9a8ab8SJohn Levon #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 1841d9a8ab8SJohn Levon /* 0x00020000 - reserved */ 1851d9a8ab8SJohn Levon /* 0x00040000 - reserved */ 1861d9a8ab8SJohn Levon #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 1871d9a8ab8SJohn Levon /* 0x00100000 - reserved */ 1881d9a8ab8SJohn Levon #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 1897660e73fSHans Rosenfeld #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 190cff040f3SRobert Mustacchi #define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */ 191cff040f3SRobert Mustacchi #define CUPID_AMD_ECX_PCENB 0x01000000 /* AMD: NB ext perf counter */ 192cff040f3SRobert Mustacchi /* 0x02000000 - reserved */ 193cff040f3SRobert Mustacchi #define CPUID_AMD_ECX_DBKP 0x40000000 /* AMD: Data breakpoint */ 194cff040f3SRobert Mustacchi #define CPUID_AMD_ECX_PERFTSC 0x08000000 /* AMD: TSC Perf Counter */ 195cff040f3SRobert Mustacchi #define CPUID_AMD_ECX_PERFL3 0x10000000 /* AMD: L3 Perf Counter */ 196cff040f3SRobert Mustacchi #define CPUID_AMD_ECX_MONITORX 0x20000000 /* AMD: clzero */ 197cff040f3SRobert Mustacchi /* 0x40000000 - reserved */ 198cff040f3SRobert Mustacchi /* 0x80000000 - reserved */ 1997c478bd9Sstevel@tonic-gate 200088d69f8SJerry Jelinek /* 201088d69f8SJerry Jelinek * AMD uses %ebx for some of their features (extended function 0x80000008). 202088d69f8SJerry Jelinek */ 203cff040f3SRobert Mustacchi #define CPUID_AMD_EBX_CLZERO 0x000000001 /* AMD: CLZERO instr */ 204cff040f3SRobert Mustacchi #define CPUID_AMD_EBX_IRCMSR 0x000000002 /* AMD: Ret. instrs MSR */ 20501add34aSRobert Mustacchi #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 20601add34aSRobert Mustacchi #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 20701add34aSRobert Mustacchi #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 20801add34aSRobert Mustacchi #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 20901add34aSRobert Mustacchi #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 21001add34aSRobert Mustacchi #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 21101add34aSRobert Mustacchi #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 21201add34aSRobert Mustacchi #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 21301add34aSRobert Mustacchi #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 21401add34aSRobert Mustacchi #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 215088d69f8SJerry Jelinek 216ae115bc7Smrj /* 217ae115bc7Smrj * Intel now seems to have claimed part of the "extended" function 218ae115bc7Smrj * space that we previously for non-Intel implementors to use. 219ae115bc7Smrj * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 220ae115bc7Smrj * is available in long mode i.e. what AMD indicate using bit 0. 221ae115bc7Smrj * On the other hand, everything else is labelled as reserved. 222ae115bc7Smrj */ 223ae115bc7Smrj #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 224ae115bc7Smrj 225245ac945SRobert Mustacchi /* 226245ac945SRobert Mustacchi * Intel also uses cpuid leaf 7 to have additional instructions and features. 227799823bbSRobert Mustacchi * Like some other leaves, but unlike the current ones we care about, it 228245ac945SRobert Mustacchi * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 229245ac945SRobert Mustacchi * with the potential use of additional sub-leaves in the future, we now 230245ac945SRobert Mustacchi * specifically label the EBX features with their leaf and sub-leaf. 231245ac945SRobert Mustacchi */ 232cff040f3SRobert Mustacchi #define CPUID_INTC_EBX_7_0_FSGSBASE 0x00000001 /* FSGSBASE */ 233cff040f3SRobert Mustacchi #define CPUID_INTC_EBX_7_0_TSC_ADJ 0x00000002 /* TSC adjust MSR */ 234cff040f3SRobert Mustacchi #define CPUID_INTC_EBX_7_0_SGX 0x00000004 /* SGX */ 235245ac945SRobert Mustacchi #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 236088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 237245ac945SRobert Mustacchi #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 238cff040f3SRobert Mustacchi /* Bit 6 is reserved */ 239799823bbSRobert Mustacchi #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 2408889c875SRobert Mustacchi #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 241cff040f3SRobert Mustacchi #define CPUID_INTC_EBX_7_0_ENH_REP_MOV 0x00000200 /* Enhanced REP MOVSB */ 24274ecdb51SJohn Levon #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 243cff040f3SRobert Mustacchi #define CPUID_INTC_EBX_7_0_RTM 0x00000800 /* RTM instrs */ 244cff040f3SRobert Mustacchi #define CPUID_INTC_EBX_7_0_PQM 0x00001000 /* QoS Monitoring */ 245cff040f3SRobert Mustacchi #define CPUID_INTC_EBX_7_0_DEP_CSDS 0x00002000 /* Deprecates CS/DS */ 246088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 247cff040f3SRobert Mustacchi #define CPUID_INTC_EBX_7_0_PQE 0x00080000 /* QoS Enforcement */ 248088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 249088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 2508889c875SRobert Mustacchi #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 2518889c875SRobert Mustacchi #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 2523ce2fcdcSRobert Mustacchi #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 253088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 254cff040f3SRobert Mustacchi /* Bit 22 is reserved */ 255cff040f3SRobert Mustacchi #define CPUID_INTC_EBX_7_0_CLFLUSHOPT 0x00800000 /* CLFLUSOPT */ 256088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 257cff040f3SRobert Mustacchi #define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */ 258088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 259088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 260088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 261088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 262088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 263088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 264088d69f8SJerry Jelinek 265088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 266088d69f8SJerry Jelinek (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 267088d69f8SJerry Jelinek CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 268088d69f8SJerry Jelinek CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 269088d69f8SJerry Jelinek CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 270088d69f8SJerry Jelinek 271cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_PREFETCHWT1 0x00000001 /* PREFETCHWT1 */ 272088d69f8SJerry Jelinek #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 273088d69f8SJerry Jelinek #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 274088d69f8SJerry Jelinek #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 275088d69f8SJerry Jelinek #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 276cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_WAITPKG 0x00000020 /* WAITPKG */ 277cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_AVX512VBMI2 0x00000040 /* AVX512 VBMI2 */ 278cff040f3SRobert Mustacchi /* bit 7 is reserved */ 279cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_GFNI 0x00000100 /* GFNI */ 280cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_VAES 0x00000200 /* VAES */ 281cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_VPCLMULQDQ 0x00000400 /* VPCLMULQDQ */ 282cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_AVX512VNNI 0x00000800 /* AVX512 VNNI */ 283cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000 /* AVX512 BITALG */ 284cff040f3SRobert Mustacchi /* bit 13 is reserved */ 285088d69f8SJerry Jelinek #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 286cff040f3SRobert Mustacchi /* bits 15-16 are reserved */ 287cff040f3SRobert Mustacchi /* bits 17-21 are the value of MAWAU */ 288cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_RDPID 0x00400000 /* RPID, IA32_TSC_AUX */ 289cff040f3SRobert Mustacchi /* bits 23-24 are reserved */ 290cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_CLDEMOTE 0x02000000 /* Cache line demote */ 291cff040f3SRobert Mustacchi /* bit 26 is resrved */ 292cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_MOVDIRI 0x08000000 /* MOVDIRI insn */ 293cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_MOVDIR64B 0x10000000 /* MOVDIR64B insn */ 294cff040f3SRobert Mustacchi /* bit 29 is reserved */ 295cff040f3SRobert Mustacchi #define CPUID_INTC_ECX_7_0_SGXLC 0x40000000 /* SGX Launch config */ 296cff040f3SRobert Mustacchi /* bit 31 is reserved */ 297cff040f3SRobert Mustacchi 298cff040f3SRobert Mustacchi /* 299cff040f3SRobert Mustacchi * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and 300cff040f3SRobert Mustacchi * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still 301cff040f3SRobert Mustacchi * valid when AVX512 is not. However, the following flags all are only valid 302cff040f3SRobert Mustacchi * when AVX512 is present. 303cff040f3SRobert Mustacchi */ 304088d69f8SJerry Jelinek #define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 305cff040f3SRobert Mustacchi (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \ 306cff040f3SRobert Mustacchi CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 307088d69f8SJerry Jelinek 308cff040f3SRobert Mustacchi /* bits 0-1 are reserved */ 309088d69f8SJerry Jelinek #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 310088d69f8SJerry Jelinek #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 311cff040f3SRobert Mustacchi #define CPUID_INTC_EDX_7_0_FSREPMOV 0x00000010 /* fast short rep mov */ 312*a9cc46cfSRobert Mustacchi /* bits 5-9 are reserved */ 313*a9cc46cfSRobert Mustacchi #define CPUID_INTC_EDX_7_0_MD_CLEAR 0x00000400 /* MB VERW */ 314*a9cc46cfSRobert Mustacchi /* bits 11-17 are reserved */ 315cff040f3SRobert Mustacchi #define CPUID_INTC_EDX_7_0_PCONFIG 0x00040000 /* PCONFIG */ 316cff040f3SRobert Mustacchi /* bits 19-26 are reserved */ 31701add34aSRobert Mustacchi #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 31801add34aSRobert Mustacchi #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 319c7749d0fSJohn Levon #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */ 32001add34aSRobert Mustacchi #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 32101add34aSRobert Mustacchi #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 322088d69f8SJerry Jelinek 323088d69f8SJerry Jelinek #define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 324088d69f8SJerry Jelinek (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS) 325088d69f8SJerry Jelinek 326088d69f8SJerry Jelinek /* 327088d69f8SJerry Jelinek * Intel also uses cpuid leaf 0xd to report additional instructions and features 328088d69f8SJerry Jelinek * when the sub-leaf in %ecx == 1. We label these using the same convention as 329088d69f8SJerry Jelinek * with leaf 7. 330088d69f8SJerry Jelinek */ 331088d69f8SJerry Jelinek #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 332088d69f8SJerry Jelinek #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 333088d69f8SJerry Jelinek #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 3347c478bd9Sstevel@tonic-gate 335b13f152eSYuri Pankov #define REG_PAT 0x277 3367c478bd9Sstevel@tonic-gate #define REG_TSC 0x10 /* timestamp counter */ 3377c478bd9Sstevel@tonic-gate #define REG_APIC_BASE_MSR 0x1b 338b6917abeSmishra #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 3397c478bd9Sstevel@tonic-gate 340e774b42bSBill Holler #if !defined(__xpv) 341e774b42bSBill Holler /* 342e774b42bSBill Holler * AMD C1E 343e774b42bSBill Holler */ 344e774b42bSBill Holler #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 345e774b42bSBill Holler #define AMD_ACTONCMPHALT_SHIFT 27 346e774b42bSBill Holler #define AMD_ACTONCMPHALT_MASK 3 347e774b42bSBill Holler #endif 348e774b42bSBill Holler 3497c478bd9Sstevel@tonic-gate #define MSR_DEBUGCTL 0x1d9 3507c478bd9Sstevel@tonic-gate 3517c478bd9Sstevel@tonic-gate #define DEBUGCTL_LBR 0x01 3527c478bd9Sstevel@tonic-gate #define DEBUGCTL_BTF 0x02 3537c478bd9Sstevel@tonic-gate 3547c478bd9Sstevel@tonic-gate /* Intel P6, AMD */ 3557c478bd9Sstevel@tonic-gate #define MSR_LBR_FROM 0x1db 3567c478bd9Sstevel@tonic-gate #define MSR_LBR_TO 0x1dc 3577c478bd9Sstevel@tonic-gate #define MSR_LEX_FROM 0x1dd 3587c478bd9Sstevel@tonic-gate #define MSR_LEX_TO 0x1de 3597c478bd9Sstevel@tonic-gate 3607c478bd9Sstevel@tonic-gate /* Intel P4 (pre-Prescott, non P4 M) */ 3617c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_TOS 0x1da 3627c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_0 0x1db 3637c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_1 0x1dc 3647c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_2 0x1dd 3657c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_3 0x1de 3667c478bd9Sstevel@tonic-gate 3677c478bd9Sstevel@tonic-gate /* Intel Pentium M */ 3687c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_TOS 0x1c9 3697c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_0 0x040 3707c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_1 0x041 3717c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_2 0x042 3727c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_3 0x043 3737c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_4 0x044 3747c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_5 0x045 3757c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_6 0x046 3767c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_7 0x047 3777c478bd9Sstevel@tonic-gate 3787c478bd9Sstevel@tonic-gate /* Intel P4 (Prescott) */ 3797c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TOS 0x1da 3807c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_0 0x680 3817c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_1 0x681 3827c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_2 0x682 3837c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_3 0x683 3847c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_4 0x684 3857c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_5 0x685 3867c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_6 0x686 3877c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_7 0x687 38858b49504SHans Rosenfeld #define MSR_PRP4_LBSTK_FROM_8 0x688 3897c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_9 0x689 3907c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_10 0x68a 39158b49504SHans Rosenfeld #define MSR_PRP4_LBSTK_FROM_11 0x68b 3927c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_12 0x68c 3937c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_13 0x68d 3947c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_14 0x68e 3957c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_15 0x68f 3967c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_0 0x6c0 3977c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_1 0x6c1 3987c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_2 0x6c2 3997c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_3 0x6c3 4007c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_4 0x6c4 4017c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_5 0x6c5 4027c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_6 0x6c6 4037c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_7 0x6c7 4047c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_8 0x6c8 40558b49504SHans Rosenfeld #define MSR_PRP4_LBSTK_TO_9 0x6c9 4067c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_10 0x6ca 4077c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_11 0x6cb 4087c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_12 0x6cc 4097c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_13 0x6cd 4107c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_14 0x6ce 4117c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_15 0x6cf 4127c478bd9Sstevel@tonic-gate 4132a613b59SRobert Mustacchi /* 4142a613b59SRobert Mustacchi * General Xeon based MSRs 4152a613b59SRobert Mustacchi */ 4162a613b59SRobert Mustacchi #define MSR_PPIN_CTL 0x04e 4172a613b59SRobert Mustacchi #define MSR_PPIN 0x04f 4182a613b59SRobert Mustacchi #define MSR_PLATFORM_INFO 0x0ce 4192a613b59SRobert Mustacchi 4202a613b59SRobert Mustacchi #define MSR_PLATFORM_INFO_PPIN (1 << 23) 4212a613b59SRobert Mustacchi #define MSR_PPIN_CTL_MASK 0x03 4222a613b59SRobert Mustacchi #define MSR_PPIN_CTL_LOCKED 0x01 4232a613b59SRobert Mustacchi #define MSR_PPIN_CTL_ENABLED 0x02 4242a613b59SRobert Mustacchi 42501add34aSRobert Mustacchi /* 42601add34aSRobert Mustacchi * Intel IA32_ARCH_CAPABILITIES MSR. 42701add34aSRobert Mustacchi */ 428c7749d0fSJohn Levon #define MSR_IA32_ARCH_CAPABILITIES 0x10a 429c7749d0fSJohn Levon #define IA32_ARCH_CAP_RDCL_NO 0x0001 430c7749d0fSJohn Levon #define IA32_ARCH_CAP_IBRS_ALL 0x0002 431c7749d0fSJohn Levon #define IA32_ARCH_CAP_RSBA 0x0004 432c7749d0fSJohn Levon #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008 433c7749d0fSJohn Levon #define IA32_ARCH_CAP_SSB_NO 0x0010 434*a9cc46cfSRobert Mustacchi #define IA32_ARCH_CAP_MDS_NO 0x0020 43501add34aSRobert Mustacchi 43601add34aSRobert Mustacchi /* 43701add34aSRobert Mustacchi * Intel Speculation related MSRs 43801add34aSRobert Mustacchi */ 43901add34aSRobert Mustacchi #define MSR_IA32_SPEC_CTRL 0x48 44001add34aSRobert Mustacchi #define IA32_SPEC_CTRL_IBRS 0x01 44101add34aSRobert Mustacchi #define IA32_SPEC_CTRL_STIBP 0x02 44201add34aSRobert Mustacchi #define IA32_SPEC_CTRL_SSBD 0x04 44301add34aSRobert Mustacchi 44401add34aSRobert Mustacchi #define MSR_IA32_PRED_CMD 0x49 44501add34aSRobert Mustacchi #define IA32_PRED_CMD_IBPB 0x01 44601add34aSRobert Mustacchi 447c7749d0fSJohn Levon #define MSR_IA32_FLUSH_CMD 0x10b 448c7749d0fSJohn Levon #define IA32_FLUSH_CMD_L1D 0x01 449c7749d0fSJohn Levon 4507c478bd9Sstevel@tonic-gate #define MCI_CTL_VALUE 0xffffffff 4517c478bd9Sstevel@tonic-gate 4527c478bd9Sstevel@tonic-gate #define MTRR_TYPE_UC 0 4537c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WC 1 4547c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WT 4 4557c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WP 5 4567c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WB 6 4571d03c31eSjohnlev #define MTRR_TYPE_UC_ 7 4587c478bd9Sstevel@tonic-gate 4597c478bd9Sstevel@tonic-gate /* 4601d03c31eSjohnlev * For Solaris we set up the page attritubute table in the following way: 4611d03c31eSjohnlev * PAT0 Write-Back 4627c478bd9Sstevel@tonic-gate * PAT1 Write-Through 4631d03c31eSjohnlev * PAT2 Unchacheable- 4647c478bd9Sstevel@tonic-gate * PAT3 Uncacheable 4651d03c31eSjohnlev * PAT4 Write-Back 4661d03c31eSjohnlev * PAT5 Write-Through 4677c478bd9Sstevel@tonic-gate * PAT6 Write-Combine 4687c478bd9Sstevel@tonic-gate * PAT7 Uncacheable 4691d03c31eSjohnlev * The only difference from h/w default is entry 6. 4707c478bd9Sstevel@tonic-gate */ 4711d03c31eSjohnlev #define PAT_DEFAULT_ATTRIBUTE \ 4721d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WB | \ 4731d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WT << 8) | \ 4741d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 4751d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC << 24) | \ 4761d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WB << 32) | \ 4771d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WT << 40) | \ 4781d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WC << 48) | \ 4791d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC << 56)) 4807c478bd9Sstevel@tonic-gate 4817417cfdeSKuriakose Kuruvilla #define X86FSET_LARGEPAGE 0 4827417cfdeSKuriakose Kuruvilla #define X86FSET_TSC 1 4837417cfdeSKuriakose Kuruvilla #define X86FSET_MSR 2 4847417cfdeSKuriakose Kuruvilla #define X86FSET_MTRR 3 4857417cfdeSKuriakose Kuruvilla #define X86FSET_PGE 4 4867417cfdeSKuriakose Kuruvilla #define X86FSET_DE 5 4877417cfdeSKuriakose Kuruvilla #define X86FSET_CMOV 6 4886eedf6a5SJosef 'Jeff' Sipek #define X86FSET_MMX 7 4897417cfdeSKuriakose Kuruvilla #define X86FSET_MCA 8 4907417cfdeSKuriakose Kuruvilla #define X86FSET_PAE 9 4917417cfdeSKuriakose Kuruvilla #define X86FSET_CX8 10 4927417cfdeSKuriakose Kuruvilla #define X86FSET_PAT 11 4937417cfdeSKuriakose Kuruvilla #define X86FSET_SEP 12 4947417cfdeSKuriakose Kuruvilla #define X86FSET_SSE 13 4957417cfdeSKuriakose Kuruvilla #define X86FSET_SSE2 14 4967417cfdeSKuriakose Kuruvilla #define X86FSET_HTT 15 4977417cfdeSKuriakose Kuruvilla #define X86FSET_ASYSC 16 4987417cfdeSKuriakose Kuruvilla #define X86FSET_NX 17 4997417cfdeSKuriakose Kuruvilla #define X86FSET_SSE3 18 5007417cfdeSKuriakose Kuruvilla #define X86FSET_CX16 19 5017417cfdeSKuriakose Kuruvilla #define X86FSET_CMP 20 5027417cfdeSKuriakose Kuruvilla #define X86FSET_TSCP 21 5037417cfdeSKuriakose Kuruvilla #define X86FSET_MWAIT 22 5047417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4A 23 5057417cfdeSKuriakose Kuruvilla #define X86FSET_CPUID 24 5067417cfdeSKuriakose Kuruvilla #define X86FSET_SSSE3 25 5077417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4_1 26 5087417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4_2 27 5097417cfdeSKuriakose Kuruvilla #define X86FSET_1GPG 28 5107417cfdeSKuriakose Kuruvilla #define X86FSET_CLFSH 29 5117417cfdeSKuriakose Kuruvilla #define X86FSET_64 30 5127417cfdeSKuriakose Kuruvilla #define X86FSET_AES 31 5137417cfdeSKuriakose Kuruvilla #define X86FSET_PCLMULQDQ 32 5147af88ac7SKuriakose Kuruvilla #define X86FSET_XSAVE 33 5157af88ac7SKuriakose Kuruvilla #define X86FSET_AVX 34 516faa20166SBryan Cantrill #define X86FSET_VMX 35 517faa20166SBryan Cantrill #define X86FSET_SVM 36 5187660e73fSHans Rosenfeld #define X86FSET_TOPOEXT 37 519ebb8ac07SRobert Mustacchi #define X86FSET_F16C 38 520ebb8ac07SRobert Mustacchi #define X86FSET_RDRAND 39 5216eedf6a5SJosef 'Jeff' Sipek #define X86FSET_X2APIC 40 522245ac945SRobert Mustacchi #define X86FSET_AVX2 41 523245ac945SRobert Mustacchi #define X86FSET_BMI1 42 524245ac945SRobert Mustacchi #define X86FSET_BMI2 43 525245ac945SRobert Mustacchi #define X86FSET_FMA 44 526799823bbSRobert Mustacchi #define X86FSET_SMEP 45 5273ce2fcdcSRobert Mustacchi #define X86FSET_SMAP 46 5288889c875SRobert Mustacchi #define X86FSET_ADX 47 5298889c875SRobert Mustacchi #define X86FSET_RDSEED 48 530088d69f8SJerry Jelinek #define X86FSET_MPX 49 531088d69f8SJerry Jelinek #define X86FSET_AVX512F 50 532088d69f8SJerry Jelinek #define X86FSET_AVX512DQ 51 533088d69f8SJerry Jelinek #define X86FSET_AVX512PF 52 534088d69f8SJerry Jelinek #define X86FSET_AVX512ER 53 535088d69f8SJerry Jelinek #define X86FSET_AVX512CD 54 536088d69f8SJerry Jelinek #define X86FSET_AVX512BW 55 537088d69f8SJerry Jelinek #define X86FSET_AVX512VL 56 538088d69f8SJerry Jelinek #define X86FSET_AVX512FMA 57 539088d69f8SJerry Jelinek #define X86FSET_AVX512VBMI 58 540088d69f8SJerry Jelinek #define X86FSET_AVX512VPOPCDQ 59 541088d69f8SJerry Jelinek #define X86FSET_AVX512NNIW 60 542088d69f8SJerry Jelinek #define X86FSET_AVX512FMAPS 61 543088d69f8SJerry Jelinek #define X86FSET_XSAVEOPT 62 544088d69f8SJerry Jelinek #define X86FSET_XSAVEC 63 545088d69f8SJerry Jelinek #define X86FSET_XSAVES 64 546088d69f8SJerry Jelinek #define X86FSET_SHA 65 547088d69f8SJerry Jelinek #define X86FSET_UMIP 66 548088d69f8SJerry Jelinek #define X86FSET_PKU 67 549088d69f8SJerry Jelinek #define X86FSET_OSPKE 68 55074ecdb51SJohn Levon #define X86FSET_PCID 69 55174ecdb51SJohn Levon #define X86FSET_INVPCID 70 55201add34aSRobert Mustacchi #define X86FSET_IBRS 71 55301add34aSRobert Mustacchi #define X86FSET_IBPB 72 55401add34aSRobert Mustacchi #define X86FSET_STIBP 73 55501add34aSRobert Mustacchi #define X86FSET_SSBD 74 55601add34aSRobert Mustacchi #define X86FSET_SSBD_VIRT 75 55701add34aSRobert Mustacchi #define X86FSET_RDCL_NO 76 55801add34aSRobert Mustacchi #define X86FSET_IBRS_ALL 77 55901add34aSRobert Mustacchi #define X86FSET_RSBA 78 56001add34aSRobert Mustacchi #define X86FSET_SSB_NO 79 56101add34aSRobert Mustacchi #define X86FSET_STIBP_ALL 80 562c7749d0fSJohn Levon #define X86FSET_FLUSH_CMD 81 563c7749d0fSJohn Levon #define X86FSET_L1D_VM_NO 82 564cff040f3SRobert Mustacchi #define X86FSET_FSGSBASE 83 565cff040f3SRobert Mustacchi #define X86FSET_CLFLUSHOPT 84 566cff040f3SRobert Mustacchi #define X86FSET_CLWB 85 567cff040f3SRobert Mustacchi #define X86FSET_MONITORX 86 568cff040f3SRobert Mustacchi #define X86FSET_CLZERO 87 569cff040f3SRobert Mustacchi #define X86FSET_XOP 88 570cff040f3SRobert Mustacchi #define X86FSET_FMA4 89 571cff040f3SRobert Mustacchi #define X86FSET_TBM 90 572e4f6ce70SRobert Mustacchi #define X86FSET_AVX512VNNI 91 573d0e58ef5SRobert Mustacchi #define X86FSET_AMD_PCEC 92 574*a9cc46cfSRobert Mustacchi #define X86FSET_MD_CLEAR 93 575*a9cc46cfSRobert Mustacchi #define X86FSET_MDS_NO 94 5767c478bd9Sstevel@tonic-gate 5770e751525SEric Saxe /* 5780e751525SEric Saxe * Intel Deep C-State invariant TSC in leaf 0x80000007. 5790e751525SEric Saxe */ 5800e751525SEric Saxe #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 5810e751525SEric Saxe 582cef70d2cSBill Holler /* 583cef70d2cSBill Holler * Intel Deep C-state always-running local APIC timer 584cef70d2cSBill Holler */ 585cef70d2cSBill Holler #define CPUID_CSTATE_ARAT (0x4) 586cef70d2cSBill Holler 587f21ed392Saubrey.li@intel.com /* 588f21ed392Saubrey.li@intel.com * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 589f21ed392Saubrey.li@intel.com */ 590f21ed392Saubrey.li@intel.com #define CPUID_EPB_SUPPORT (1 << 3) 591f21ed392Saubrey.li@intel.com 59241afdfa7SKrishnendu Sadhukhan - Sun Microsystems /* 59341afdfa7SKrishnendu Sadhukhan - Sun Microsystems * Intel TSC deadline timer 59441afdfa7SKrishnendu Sadhukhan - Sun Microsystems */ 59541afdfa7SKrishnendu Sadhukhan - Sun Microsystems #define CPUID_DEADLINE_TSC (1 << 24) 59641afdfa7SKrishnendu Sadhukhan - Sun Microsystems 5977c478bd9Sstevel@tonic-gate /* 5987c478bd9Sstevel@tonic-gate * x86_type is a legacy concept; this is supplanted 5997417cfdeSKuriakose Kuruvilla * for most purposes by x86_featureset; modern CPUs 6007c478bd9Sstevel@tonic-gate * should be X86_TYPE_OTHER 6017c478bd9Sstevel@tonic-gate */ 6027c478bd9Sstevel@tonic-gate #define X86_TYPE_OTHER 0 6037c478bd9Sstevel@tonic-gate #define X86_TYPE_486 1 6047c478bd9Sstevel@tonic-gate #define X86_TYPE_P5 2 6057c478bd9Sstevel@tonic-gate #define X86_TYPE_P6 3 6067c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_486 4 6077c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86L 5 6087c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86 6 6097c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_GXm 7 6107c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86MX 8 6117c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MediaGX 9 6127c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MII 10 6137c478bd9Sstevel@tonic-gate #define X86_TYPE_VIA_CYRIX_III 11 6147c478bd9Sstevel@tonic-gate #define X86_TYPE_P4 12 6157c478bd9Sstevel@tonic-gate 6167c478bd9Sstevel@tonic-gate /* 6177c478bd9Sstevel@tonic-gate * x86_vendor allows us to select between 6187c478bd9Sstevel@tonic-gate * implementation features and helps guide 6197c478bd9Sstevel@tonic-gate * the interpretation of the cpuid instruction. 6207c478bd9Sstevel@tonic-gate */ 621e4b86885SCheng Sean Ye #define X86_VENDOR_Intel 0 622e4b86885SCheng Sean Ye #define X86_VENDORSTR_Intel "GenuineIntel" 623e4b86885SCheng Sean Ye 624e4b86885SCheng Sean Ye #define X86_VENDOR_IntelClone 1 625e4b86885SCheng Sean Ye 626e4b86885SCheng Sean Ye #define X86_VENDOR_AMD 2 627e4b86885SCheng Sean Ye #define X86_VENDORSTR_AMD "AuthenticAMD" 628e4b86885SCheng Sean Ye 629e4b86885SCheng Sean Ye #define X86_VENDOR_Cyrix 3 630e4b86885SCheng Sean Ye #define X86_VENDORSTR_CYRIX "CyrixInstead" 631e4b86885SCheng Sean Ye 632e4b86885SCheng Sean Ye #define X86_VENDOR_UMC 4 633e4b86885SCheng Sean Ye #define X86_VENDORSTR_UMC "UMC UMC UMC " 634e4b86885SCheng Sean Ye 635e4b86885SCheng Sean Ye #define X86_VENDOR_NexGen 5 636e4b86885SCheng Sean Ye #define X86_VENDORSTR_NexGen "NexGenDriven" 637e4b86885SCheng Sean Ye 638e4b86885SCheng Sean Ye #define X86_VENDOR_Centaur 6 639e4b86885SCheng Sean Ye #define X86_VENDORSTR_Centaur "CentaurHauls" 640e4b86885SCheng Sean Ye 641e4b86885SCheng Sean Ye #define X86_VENDOR_Rise 7 642e4b86885SCheng Sean Ye #define X86_VENDORSTR_Rise "RiseRiseRise" 643e4b86885SCheng Sean Ye 644e4b86885SCheng Sean Ye #define X86_VENDOR_SiS 8 645e4b86885SCheng Sean Ye #define X86_VENDORSTR_SiS "SiS SiS SiS " 646e4b86885SCheng Sean Ye 647e4b86885SCheng Sean Ye #define X86_VENDOR_TM 9 648e4b86885SCheng Sean Ye #define X86_VENDORSTR_TM "GenuineTMx86" 649e4b86885SCheng Sean Ye 650e4b86885SCheng Sean Ye #define X86_VENDOR_NSC 10 651e4b86885SCheng Sean Ye #define X86_VENDORSTR_NSC "Geode by NSC" 652e4b86885SCheng Sean Ye 653e4b86885SCheng Sean Ye /* 654e4b86885SCheng Sean Ye * Vendor string max len + \0 655e4b86885SCheng Sean Ye */ 656e4b86885SCheng Sean Ye #define X86_VENDOR_STRLEN 13 6577aec1d6eScindi 6588a40a695Sgavinm /* 6598a40a695Sgavinm * Some vendor/family/model/stepping ranges are commonly grouped under 6608a40a695Sgavinm * a single identifying banner by the vendor. The following encode 6618a40a695Sgavinm * that "revision" in a uint32_t with the 8 most significant bits 6628a40a695Sgavinm * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 6638a40a695Sgavinm * family, and the remaining 16 typically forming a bitmask of revisions 6648a40a695Sgavinm * within that family with more significant bits indicating "later" revisions. 6658a40a695Sgavinm */ 6668a40a695Sgavinm 6678a40a695Sgavinm #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 6688a40a695Sgavinm #define _X86_CHIPREV_VENDOR_SHIFT 24 6698a40a695Sgavinm #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 6708a40a695Sgavinm #define _X86_CHIPREV_FAMILY_SHIFT 16 6718a40a695Sgavinm #define _X86_CHIPREV_REV_MASK 0x0000ffffu 6728a40a695Sgavinm 6738a40a695Sgavinm #define _X86_CHIPREV_VENDOR(x) \ 6748a40a695Sgavinm (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 6758a40a695Sgavinm #define _X86_CHIPREV_FAMILY(x) \ 6768a40a695Sgavinm (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 6778a40a695Sgavinm #define _X86_CHIPREV_REV(x) \ 6788a40a695Sgavinm ((x) & _X86_CHIPREV_REV_MASK) 6798a40a695Sgavinm 6808a40a695Sgavinm /* True if x matches in vendor and family and if x matches the given rev mask */ 6818a40a695Sgavinm #define X86_CHIPREV_MATCH(x, mask) \ 6828a40a695Sgavinm (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 6838a40a695Sgavinm _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 6848a40a695Sgavinm ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 6858a40a695Sgavinm 6862c8230b0SSrihari Venkatesan /* True if x matches in vendor and family, and rev is at least minx */ 6878a40a695Sgavinm #define X86_CHIPREV_ATLEAST(x, minx) \ 6888a40a695Sgavinm (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 6898a40a695Sgavinm _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 6908a40a695Sgavinm _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 6918a40a695Sgavinm 6928a40a695Sgavinm #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 6938a40a695Sgavinm ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 6948a40a695Sgavinm (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 6958a40a695Sgavinm 6962c8230b0SSrihari Venkatesan /* True if x matches in vendor, and family is at least minx */ 6972c8230b0SSrihari Venkatesan #define X86_CHIPFAM_ATLEAST(x, minx) \ 6982c8230b0SSrihari Venkatesan (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 6992c8230b0SSrihari Venkatesan _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 7002c8230b0SSrihari Venkatesan 7018a40a695Sgavinm /* Revision default */ 7028a40a695Sgavinm #define X86_CHIPREV_UNKNOWN 0x0 7038a40a695Sgavinm 7048a40a695Sgavinm /* 70520c794b3Sgavinm * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 70620c794b3Sgavinm * sufficiently different that we will distinguish them; in all other 7078a40a695Sgavinm * case we will identify the major revision. 7088a40a695Sgavinm */ 7098a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 7108a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 7118a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 7128a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 7138a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 7148a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 7158a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 71620c794b3Sgavinm 71720c794b3Sgavinm /* 71820c794b3Sgavinm * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 71920c794b3Sgavinm */ 72020c794b3Sgavinm #define X86_CHIPREV_AMD_10_REV_A \ 72131725658Sksadhukh _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 72220c794b3Sgavinm #define X86_CHIPREV_AMD_10_REV_B \ 72320c794b3Sgavinm _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 72479321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_C2 \ 72564452efdSKit Chow _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 72679321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_C3 \ 72789e921d5SKuriakose Kuruvilla _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 72879321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_D0 \ 72979321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 73079321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_D1 \ 73179321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 73279321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_E \ 73379321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 73489e921d5SKuriakose Kuruvilla 73589e921d5SKuriakose Kuruvilla /* 73689e921d5SKuriakose Kuruvilla * Definitions for AMD Family 0x11. 73789e921d5SKuriakose Kuruvilla */ 73879321794SJens Elkner #define X86_CHIPREV_AMD_11_REV_B \ 73979321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 74089e921d5SKuriakose Kuruvilla 74179321794SJens Elkner /* 74279321794SJens Elkner * Definitions for AMD Family 0x12. 74379321794SJens Elkner */ 74479321794SJens Elkner #define X86_CHIPREV_AMD_12_REV_B \ 74579321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 74679321794SJens Elkner 74779321794SJens Elkner /* 74879321794SJens Elkner * Definitions for AMD Family 0x14. 74979321794SJens Elkner */ 75079321794SJens Elkner #define X86_CHIPREV_AMD_14_REV_B \ 75179321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 75279321794SJens Elkner #define X86_CHIPREV_AMD_14_REV_C \ 75379321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 75479321794SJens Elkner 75579321794SJens Elkner /* 75679321794SJens Elkner * Definitions for AMD Family 0x15 75779321794SJens Elkner */ 75879321794SJens Elkner #define X86_CHIPREV_AMD_15OR_REV_B2 \ 75979321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 76079321794SJens Elkner 76179321794SJens Elkner #define X86_CHIPREV_AMD_15TN_REV_A1 \ 76279321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 7638a40a695Sgavinm 7642ce06f32SRobert Mustacchi #define X86_CHIPREV_AMD_150R_REV_C0 \ 7652ce06f32SRobert Mustacchi _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0003) 7662ce06f32SRobert Mustacchi 7672ce06f32SRobert Mustacchi #define X86_CHIPREV_AMD_15KV_REV_A1 \ 7682ce06f32SRobert Mustacchi _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0004) 7692ce06f32SRobert Mustacchi 7702ce06f32SRobert Mustacchi #define X86_CHIPREV_AMD_15F60 \ 7712ce06f32SRobert Mustacchi _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0005) 7722ce06f32SRobert Mustacchi 7732ce06f32SRobert Mustacchi #define X86_CHIPREV_AMD_15ST_REV_A0 \ 7742ce06f32SRobert Mustacchi _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0006) 7752ce06f32SRobert Mustacchi 7762ce06f32SRobert Mustacchi /* 7772ce06f32SRobert Mustacchi * Definitions for AMD Family 0x16 7782ce06f32SRobert Mustacchi */ 7792ce06f32SRobert Mustacchi #define X86_CHIPREV_AMD_16_KB_A1 \ 7802ce06f32SRobert Mustacchi _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0001) 7812ce06f32SRobert Mustacchi 7822ce06f32SRobert Mustacchi #define X86_CHIPREV_AMD_16_ML_A1 \ 7832ce06f32SRobert Mustacchi _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0002) 7842ce06f32SRobert Mustacchi 7852ce06f32SRobert Mustacchi /* 7862ce06f32SRobert Mustacchi * Definitions for AMD Family 0x17 7872ce06f32SRobert Mustacchi */ 7882ce06f32SRobert Mustacchi 7892ce06f32SRobert Mustacchi #define X86_CHIPREV_AMD_17_ZP_B1 \ 7902ce06f32SRobert Mustacchi _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0001) 7912ce06f32SRobert Mustacchi 7922ce06f32SRobert Mustacchi #define X86_CHIPREV_AMD_17_ZP_B2 \ 7932ce06f32SRobert Mustacchi _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0002) 7942ce06f32SRobert Mustacchi 7952ce06f32SRobert Mustacchi #define X86_CHIPREV_AMD_17_PiR_B2 \ 7962ce06f32SRobert Mustacchi _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0003) 7972ce06f32SRobert Mustacchi 7988a40a695Sgavinm /* 7998a40a695Sgavinm * Various socket/package types, extended as the need to distinguish 8008a40a695Sgavinm * a new type arises. The top 8 byte identfies the vendor and the 8018a40a695Sgavinm * remaining 24 bits describe 24 socket types. 8028a40a695Sgavinm */ 8038a40a695Sgavinm 8048a40a695Sgavinm #define _X86_SOCKET_VENDOR_SHIFT 24 8058a40a695Sgavinm #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 8068a40a695Sgavinm #define _X86_SOCKET_TYPE_MASK 0x00ffffff 8078a40a695Sgavinm #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 8088a40a695Sgavinm 8098a40a695Sgavinm #define _X86_SOCKET_MKVAL(vendor, bitval) \ 8108a40a695Sgavinm ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 8118a40a695Sgavinm 8128a40a695Sgavinm #define X86_SOCKET_MATCH(s, mask) \ 8138a40a695Sgavinm (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 814a24e89c4SKuriakose Kuruvilla (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 8158a40a695Sgavinm 8168a40a695Sgavinm #define X86_SOCKET_UNKNOWN 0x0 8178a40a695Sgavinm /* 8188a40a695Sgavinm * AMD socket types 8198a40a695Sgavinm */ 8202ce06f32SRobert Mustacchi #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01) 8212ce06f32SRobert Mustacchi #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02) 8222ce06f32SRobert Mustacchi #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03) 8232ce06f32SRobert Mustacchi #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04) 8242ce06f32SRobert Mustacchi #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05) 8252ce06f32SRobert Mustacchi #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06) 8262ce06f32SRobert Mustacchi #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07) 8272ce06f32SRobert Mustacchi #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08) 8282ce06f32SRobert Mustacchi #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09) 8292ce06f32SRobert Mustacchi #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a) 8302ce06f32SRobert Mustacchi #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b) 8312ce06f32SRobert Mustacchi #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c) 8322ce06f32SRobert Mustacchi #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d) 8332ce06f32SRobert Mustacchi #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e) 8342ce06f32SRobert Mustacchi #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f) 8352ce06f32SRobert Mustacchi #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10) 8362ce06f32SRobert Mustacchi #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11) 8372ce06f32SRobert Mustacchi #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12) 8382ce06f32SRobert Mustacchi #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13) 8392ce06f32SRobert Mustacchi #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14) 8402ce06f32SRobert Mustacchi #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15) 8412ce06f32SRobert Mustacchi #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16) 8422ce06f32SRobert Mustacchi #define X86_SOCKET_FP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17) 8432ce06f32SRobert Mustacchi #define X86_SOCKET_FM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18) 8442ce06f32SRobert Mustacchi #define X86_SOCKET_FP4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19) 8452ce06f32SRobert Mustacchi #define X86_SOCKET_AM4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a) 8462ce06f32SRobert Mustacchi #define X86_SOCKET_FT3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b) 8472ce06f32SRobert Mustacchi #define X86_SOCKET_FT4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c) 8482ce06f32SRobert Mustacchi #define X86_SOCKET_FS1B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d) 8492ce06f32SRobert Mustacchi #define X86_SOCKET_FT3B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e) 8502ce06f32SRobert Mustacchi #define X86_SOCKET_SP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f) 8512ce06f32SRobert Mustacchi #define X86_SOCKET_SP3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20) 8522ce06f32SRobert Mustacchi #define X86_NUM_SOCKETS_AMD 0x21 8538a40a695Sgavinm 8542a613b59SRobert Mustacchi 8552a613b59SRobert Mustacchi /* 8567e3dbbacSRobert Mustacchi * Definitions for Intel processor models. These are all for Family 6 8577e3dbbacSRobert Mustacchi * processors. This list and the Atom set below it are not exhuastive. 8587e3dbbacSRobert Mustacchi */ 8597e3dbbacSRobert Mustacchi #define INTC_MODEL_MEROM 0x0f 8607e3dbbacSRobert Mustacchi #define INTC_MODEL_PENRYN 0x17 8617e3dbbacSRobert Mustacchi #define INTC_MODEL_DUNNINGTON 0x1d 8627e3dbbacSRobert Mustacchi 8637e3dbbacSRobert Mustacchi #define INTC_MODEL_NEHALEM 0x1e 8647e3dbbacSRobert Mustacchi #define INTC_MODEL_NEHALEM2 0x1f 8657e3dbbacSRobert Mustacchi #define INTC_MODEL_NEHALEM_EP 0x1a 8667e3dbbacSRobert Mustacchi #define INTC_MODEL_NEHALEM_EX 0x2e 8677e3dbbacSRobert Mustacchi 8687e3dbbacSRobert Mustacchi #define INTC_MODEL_WESTMERE 0x25 8697e3dbbacSRobert Mustacchi #define INTC_MODEL_WESTMERE_EP 0x2c 8707e3dbbacSRobert Mustacchi #define INTC_MODEL_WESTMERE_EX 0x2f 8717e3dbbacSRobert Mustacchi 8727e3dbbacSRobert Mustacchi #define INTC_MODEL_SANDYBRIDGE 0x2a 8737e3dbbacSRobert Mustacchi #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d 8747e3dbbacSRobert Mustacchi #define INTC_MODEL_IVYBRIDGE 0x3a 8757e3dbbacSRobert Mustacchi #define INTC_MODEL_IVYBRIDGE_XEON 0x3e 8767e3dbbacSRobert Mustacchi 8777e3dbbacSRobert Mustacchi #define INTC_MODEL_HASWELL 0x3c 8787e3dbbacSRobert Mustacchi #define INTC_MODEL_HASWELL_ULT 0x45 8797e3dbbacSRobert Mustacchi #define INTC_MODEL_HASWELL_GT3E 0x46 8807e3dbbacSRobert Mustacchi #define INTC_MODEL_HASWELL_XEON 0x3f 8817e3dbbacSRobert Mustacchi 8827e3dbbacSRobert Mustacchi #define INTC_MODEL_BROADWELL 0x3d 8837e3dbbacSRobert Mustacchi #define INTC_MODEL_BROADELL_2 0x47 8847e3dbbacSRobert Mustacchi #define INTC_MODEL_BROADWELL_XEON 0x4f 8852a613b59SRobert Mustacchi #define INTC_MODEL_BROADWELL_XEON_D 0x56 8867e3dbbacSRobert Mustacchi 8877e3dbbacSRobert Mustacchi #define INCC_MODEL_SKYLAKE_MOBILE 0x4e 8882a613b59SRobert Mustacchi #define INTC_MODEL_SKYLAKE_XEON 0x55 8897e3dbbacSRobert Mustacchi #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e 8907e3dbbacSRobert Mustacchi 8917e3dbbacSRobert Mustacchi #define INTC_MODEL_KABYLAKE_MOBILE 0x8e 8927e3dbbacSRobert Mustacchi #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e 8937e3dbbacSRobert Mustacchi 8947e3dbbacSRobert Mustacchi /* 8957e3dbbacSRobert Mustacchi * Atom Processors 8967e3dbbacSRobert Mustacchi */ 8977e3dbbacSRobert Mustacchi #define INTC_MODEL_SILVERTHORNE 0x1c 8987e3dbbacSRobert Mustacchi #define INTC_MODEL_LINCROFT 0x26 8997e3dbbacSRobert Mustacchi #define INTC_MODEL_PENWELL 0x27 9007e3dbbacSRobert Mustacchi #define INTC_MODEL_CLOVERVIEW 0x35 9017e3dbbacSRobert Mustacchi #define INTC_MODEL_CEDARVIEW 0x36 9027e3dbbacSRobert Mustacchi #define INTC_MODEL_BAY_TRAIL 0x37 9037e3dbbacSRobert Mustacchi #define INTC_MODEL_AVATON 0x4d 9047e3dbbacSRobert Mustacchi #define INTC_MODEL_AIRMONT 0x4c 9057e3dbbacSRobert Mustacchi #define INTC_MODEL_GOLDMONT 0x5c 9067e3dbbacSRobert Mustacchi #define INTC_MODEL_DENVERTON 0x5f 9077e3dbbacSRobert Mustacchi #define INTC_MODEL_GEMINI_LAKE 0x7a 9082a613b59SRobert Mustacchi 9097af88ac7SKuriakose Kuruvilla /* 9107af88ac7SKuriakose Kuruvilla * xgetbv/xsetbv support 911088d69f8SJerry Jelinek * See section 13.3 in vol. 1 of the Intel devlopers manual. 9127af88ac7SKuriakose Kuruvilla */ 9137af88ac7SKuriakose Kuruvilla 9147af88ac7SKuriakose Kuruvilla #define XFEATURE_ENABLED_MASK 0x0 9157af88ac7SKuriakose Kuruvilla /* 9167af88ac7SKuriakose Kuruvilla * XFEATURE_ENABLED_MASK values (eax) 917088d69f8SJerry Jelinek * See setup_xfem(). 9187af88ac7SKuriakose Kuruvilla */ 9197af88ac7SKuriakose Kuruvilla #define XFEATURE_LEGACY_FP 0x1 9207af88ac7SKuriakose Kuruvilla #define XFEATURE_SSE 0x2 9217af88ac7SKuriakose Kuruvilla #define XFEATURE_AVX 0x4 922088d69f8SJerry Jelinek #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ 923088d69f8SJerry Jelinek #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ 924088d69f8SJerry Jelinek /* bit 8 unused */ 925088d69f8SJerry Jelinek #define XFEATURE_PKRU 0x200 926ebb8ac07SRobert Mustacchi #define XFEATURE_FP_ALL \ 927088d69f8SJerry Jelinek (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 928088d69f8SJerry Jelinek XFEATURE_AVX512 | XFEATURE_PKRU) 9297af88ac7SKuriakose Kuruvilla 930d0158222SRobert Mustacchi /* 931d0158222SRobert Mustacchi * Define the set of xfeature flags that should be considered valid in the xsave 932d0158222SRobert Mustacchi * state vector when we initialize an lwp. This is distinct from the full set so 933d0158222SRobert Mustacchi * that all of the processor's normal logic and tracking of the xsave state is 934d0158222SRobert Mustacchi * usable. This should correspond to the state that's been initialized by the 935d0158222SRobert Mustacchi * ABI to hold meaningful values. Adding additional bits here can have serious 936d0158222SRobert Mustacchi * performance implications and cause performance degradations when using the 937d0158222SRobert Mustacchi * FPU vector (xmm) registers. 938d0158222SRobert Mustacchi */ 939d0158222SRobert Mustacchi #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 940d0158222SRobert Mustacchi 9417c478bd9Sstevel@tonic-gate #if !defined(_ASM) 9427c478bd9Sstevel@tonic-gate 9437c478bd9Sstevel@tonic-gate #if defined(_KERNEL) || defined(_KMEMUSER) 9447c478bd9Sstevel@tonic-gate 945*a9cc46cfSRobert Mustacchi #define NUM_X86_FEATURES 95 946dfea898aSKuriakose Kuruvilla extern uchar_t x86_featureset[]; 9477417cfdeSKuriakose Kuruvilla 9487417cfdeSKuriakose Kuruvilla extern void free_x86_featureset(void *featureset); 9497417cfdeSKuriakose Kuruvilla extern boolean_t is_x86_feature(void *featureset, uint_t feature); 9507417cfdeSKuriakose Kuruvilla extern void add_x86_feature(void *featureset, uint_t feature); 9517417cfdeSKuriakose Kuruvilla extern void remove_x86_feature(void *featureset, uint_t feature); 9527417cfdeSKuriakose Kuruvilla extern boolean_t compare_x86_featureset(void *setA, void *setB); 9537417cfdeSKuriakose Kuruvilla extern void print_x86_featureset(void *featureset); 9547417cfdeSKuriakose Kuruvilla 9557417cfdeSKuriakose Kuruvilla 9567c478bd9Sstevel@tonic-gate extern uint_t x86_type; 9577c478bd9Sstevel@tonic-gate extern uint_t x86_vendor; 95886c1f4dcSVikram Hegde extern uint_t x86_clflush_size; 9597c478bd9Sstevel@tonic-gate 9607c478bd9Sstevel@tonic-gate extern uint_t pentiumpro_bug4046376; 9617c478bd9Sstevel@tonic-gate 9627c478bd9Sstevel@tonic-gate extern const char CyrixInstead[]; 963455e370cSJohn Levon 964*a9cc46cfSRobert Mustacchi extern void (*spec_uarch_flush)(void); 9657c478bd9Sstevel@tonic-gate 9667c478bd9Sstevel@tonic-gate #endif 9677c478bd9Sstevel@tonic-gate 9687c478bd9Sstevel@tonic-gate #if defined(_KERNEL) 9697c478bd9Sstevel@tonic-gate 970*a9cc46cfSRobert Mustacchi /* 971*a9cc46cfSRobert Mustacchi * x86_md_clear is the main entry point that should be called to deal with 972*a9cc46cfSRobert Mustacchi * clearing u-arch buffers. Implementations are below because they're 973*a9cc46cfSRobert Mustacchi * implemented in ASM. They shouldn't be used. 974*a9cc46cfSRobert Mustacchi */ 975*a9cc46cfSRobert Mustacchi extern void (*x86_md_clear)(void); 976*a9cc46cfSRobert Mustacchi extern void x86_md_clear_noop(void); 977*a9cc46cfSRobert Mustacchi extern void x86_md_clear_verw(void); 978*a9cc46cfSRobert Mustacchi 9798949bcd6Sandrei /* 9808949bcd6Sandrei * This structure is used to pass arguments and get return values back 9818949bcd6Sandrei * from the CPUID instruction in __cpuid_insn() routine. 9828949bcd6Sandrei */ 9838949bcd6Sandrei struct cpuid_regs { 9848949bcd6Sandrei uint32_t cp_eax; 9858949bcd6Sandrei uint32_t cp_ebx; 9868949bcd6Sandrei uint32_t cp_ecx; 9878949bcd6Sandrei uint32_t cp_edx; 9888949bcd6Sandrei }; 9897c478bd9Sstevel@tonic-gate 99074ecdb51SJohn Levon extern int x86_use_pcid; 99174ecdb51SJohn Levon extern int x86_use_invpcid; 99274ecdb51SJohn Levon 9937af88ac7SKuriakose Kuruvilla /* 9947af88ac7SKuriakose Kuruvilla * Utility functions to get/set extended control registers (XCR) 9957af88ac7SKuriakose Kuruvilla * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 9967af88ac7SKuriakose Kuruvilla */ 9977af88ac7SKuriakose Kuruvilla extern uint64_t get_xcr(uint_t); 9987af88ac7SKuriakose Kuruvilla extern void set_xcr(uint_t, uint64_t); 9997af88ac7SKuriakose Kuruvilla 10000ac7d7d8Skucharsk extern uint64_t rdmsr(uint_t); 10010ac7d7d8Skucharsk extern void wrmsr(uint_t, const uint64_t); 1002ee88d2b9Skchow extern uint64_t xrdmsr(uint_t); 1003ee88d2b9Skchow extern void xwrmsr(uint_t, const uint64_t); 1004ae115bc7Smrj extern int checked_rdmsr(uint_t, uint64_t *); 1005ae115bc7Smrj extern int checked_wrmsr(uint_t, uint64_t); 1006ae115bc7Smrj 10077c478bd9Sstevel@tonic-gate extern void invalidate_cache(void); 10087c478bd9Sstevel@tonic-gate extern ulong_t getcr4(void); 10097c478bd9Sstevel@tonic-gate extern void setcr4(ulong_t); 1010ae115bc7Smrj 10117c478bd9Sstevel@tonic-gate extern void mtrr_sync(void); 10127c478bd9Sstevel@tonic-gate 1013a0955b86SJohn Levon extern void cpu_fast_syscall_enable(void); 1014a0955b86SJohn Levon extern void cpu_fast_syscall_disable(void); 10157c478bd9Sstevel@tonic-gate 10167c478bd9Sstevel@tonic-gate struct cpu; 10177c478bd9Sstevel@tonic-gate 10187c478bd9Sstevel@tonic-gate extern int cpuid_checkpass(struct cpu *, int); 10198949bcd6Sandrei extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 10208949bcd6Sandrei extern uint32_t __cpuid_insn(struct cpuid_regs *); 10217c478bd9Sstevel@tonic-gate extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 10227c478bd9Sstevel@tonic-gate extern int cpuid_getidstr(struct cpu *, char *, size_t); 10237c478bd9Sstevel@tonic-gate extern const char *cpuid_getvendorstr(struct cpu *); 10247c478bd9Sstevel@tonic-gate extern uint_t cpuid_getvendor(struct cpu *); 10257c478bd9Sstevel@tonic-gate extern uint_t cpuid_getfamily(struct cpu *); 10267c478bd9Sstevel@tonic-gate extern uint_t cpuid_getmodel(struct cpu *); 10277c478bd9Sstevel@tonic-gate extern uint_t cpuid_getstep(struct cpu *); 10282449e17fSsherrym extern uint_t cpuid_getsig(struct cpu *); 10297c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 10308949bcd6Sandrei extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 1031d129bde2Sesaxe extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 1032d129bde2Sesaxe extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 1033fb2f18f8Sesaxe extern int cpuid_get_chipid(struct cpu *); 1034fb2f18f8Sesaxe extern id_t cpuid_get_coreid(struct cpu *); 103510569901Sgavinm extern int cpuid_get_pkgcoreid(struct cpu *); 1036fb2f18f8Sesaxe extern int cpuid_get_clogid(struct cpu *); 1037b885580bSAlexander Kolbasov extern int cpuid_get_cacheid(struct cpu *); 1038fa96bd91SMichael Corcoran extern uint32_t cpuid_get_apicid(struct cpu *); 10398031591dSSrihari Venkatesan extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 10408031591dSSrihari Venkatesan extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 10417660e73fSHans Rosenfeld extern uint_t cpuid_get_compunitid(struct cpu *cpu); 10427660e73fSHans Rosenfeld extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 1043088d69f8SJerry Jelinek extern size_t cpuid_get_xsave_size(); 1044088d69f8SJerry Jelinek extern boolean_t cpuid_need_fp_excp_handling(); 10458949bcd6Sandrei extern int cpuid_is_cmt(struct cpu *); 10467c478bd9Sstevel@tonic-gate extern int cpuid_syscall32_insn(struct cpu *); 10477c478bd9Sstevel@tonic-gate extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 10488a40a695Sgavinm 10498a40a695Sgavinm extern uint32_t cpuid_getchiprev(struct cpu *); 10508a40a695Sgavinm extern const char *cpuid_getchiprevstr(struct cpu *); 10518a40a695Sgavinm extern uint32_t cpuid_getsockettype(struct cpu *); 105289e921d5SKuriakose Kuruvilla extern const char *cpuid_getsocketstr(struct cpu *); 10537c478bd9Sstevel@tonic-gate 10542ef50f01SJoe Bonasera extern int cpuid_have_cr8access(struct cpu *); 10552ef50f01SJoe Bonasera 10567c478bd9Sstevel@tonic-gate extern int cpuid_opteron_erratum(struct cpu *, uint_t); 10577c478bd9Sstevel@tonic-gate 10587c478bd9Sstevel@tonic-gate struct cpuid_info; 10597c478bd9Sstevel@tonic-gate 10607c478bd9Sstevel@tonic-gate extern void setx86isalist(void); 1061ae115bc7Smrj extern void cpuid_alloc_space(struct cpu *); 1062ae115bc7Smrj extern void cpuid_free_space(struct cpu *); 1063dfea898aSKuriakose Kuruvilla extern void cpuid_pass1(struct cpu *, uchar_t *); 10647c478bd9Sstevel@tonic-gate extern void cpuid_pass2(struct cpu *); 10657c478bd9Sstevel@tonic-gate extern void cpuid_pass3(struct cpu *); 1066ebb8ac07SRobert Mustacchi extern void cpuid_pass4(struct cpu *, uint_t *); 1067fa96bd91SMichael Corcoran extern void cpuid_set_cpu_properties(void *, processorid_t, 1068fa96bd91SMichael Corcoran struct cpuid_info *); 106901add34aSRobert Mustacchi extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 107001add34aSRobert Mustacchi extern void cpuid_post_ucodeadm(void); 10717c478bd9Sstevel@tonic-gate 10727c478bd9Sstevel@tonic-gate extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 10737c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 1074843e1988Sjohnlev 1075843e1988Sjohnlev #if !defined(__xpv) 10765b8a6efeSbholler extern uint32_t *cpuid_mwait_alloc(struct cpu *); 10775b8a6efeSbholler extern void cpuid_mwait_free(struct cpu *); 10780e751525SEric Saxe extern int cpuid_deep_cstates_supported(void); 1079cef70d2cSBill Holler extern int cpuid_arat_supported(void); 1080f21ed392Saubrey.li@intel.com extern int cpuid_iepb_supported(struct cpu *); 108141afdfa7SKrishnendu Sadhukhan - Sun Microsystems extern int cpuid_deadline_tsc_supported(void); 108279ec9da8SYuri Pankov extern void vmware_port(int, uint32_t *); 1083843e1988Sjohnlev #endif 10847c478bd9Sstevel@tonic-gate 10852449e17fSsherrym struct cpu_ucode_info; 10862449e17fSsherrym 10872449e17fSsherrym extern void ucode_alloc_space(struct cpu *); 10882449e17fSsherrym extern void ucode_free_space(struct cpu *); 10892449e17fSsherrym extern void ucode_check(struct cpu *); 1090adc586deSMark Johnson extern void ucode_cleanup(); 10912449e17fSsherrym 1092247dbb3dSsudheer #if !defined(__xpv) 1093247dbb3dSsudheer extern char _tsc_mfence_start; 1094247dbb3dSsudheer extern char _tsc_mfence_end; 1095247dbb3dSsudheer extern char _tscp_start; 1096247dbb3dSsudheer extern char _tscp_end; 1097247dbb3dSsudheer extern char _no_rdtsc_start; 1098247dbb3dSsudheer extern char _no_rdtsc_end; 109915363b27Ssudheer extern char _tsc_lfence_start; 110015363b27Ssudheer extern char _tsc_lfence_end; 1101247dbb3dSsudheer #endif 1102247dbb3dSsudheer 110322cc0e45SBill Holler #if !defined(__xpv) 110422cc0e45SBill Holler extern char bcopy_patch_start; 110522cc0e45SBill Holler extern char bcopy_patch_end; 110622cc0e45SBill Holler extern char bcopy_ck_size; 110722cc0e45SBill Holler #endif 110822cc0e45SBill Holler 1109e774b42bSBill Holler extern void post_startup_cpu_fixups(void); 1110e774b42bSBill Holler 11117c478bd9Sstevel@tonic-gate extern uint_t workaround_errata(struct cpu *); 11127c478bd9Sstevel@tonic-gate 11137c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 11147c478bd9Sstevel@tonic-gate extern int opteron_erratum_93; 11157c478bd9Sstevel@tonic-gate #endif 11167c478bd9Sstevel@tonic-gate 11177c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 11187c478bd9Sstevel@tonic-gate extern int opteron_erratum_91; 11197c478bd9Sstevel@tonic-gate #endif 11207c478bd9Sstevel@tonic-gate 11217c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 11227c478bd9Sstevel@tonic-gate extern int opteron_erratum_100; 11237c478bd9Sstevel@tonic-gate #endif 11247c478bd9Sstevel@tonic-gate 11257c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 11267c478bd9Sstevel@tonic-gate extern int opteron_erratum_121; 11277c478bd9Sstevel@tonic-gate #endif 11287c478bd9Sstevel@tonic-gate 1129ee88d2b9Skchow #if defined(OPTERON_WORKAROUND_6323525) 1130ee88d2b9Skchow extern int opteron_workaround_6323525; 1131ee88d2b9Skchow extern void patch_workaround_6323525(void); 1132ee88d2b9Skchow #endif 1133ee88d2b9Skchow 1134cfe84b82SMatt Amdur #if !defined(__xpv) 1135cfe84b82SMatt Amdur extern void determine_platform(void); 1136cfe84b82SMatt Amdur #endif 1137b9bfdccdSStuart Maybee extern int get_hwenv(void); 1138b9bfdccdSStuart Maybee extern int is_controldom(void); 1139b9bfdccdSStuart Maybee 114074ecdb51SJohn Levon extern void enable_pcid(void); 114174ecdb51SJohn Levon 11427af88ac7SKuriakose Kuruvilla extern void xsave_setup_msr(struct cpu *); 11437af88ac7SKuriakose Kuruvilla 1144309b04b8SJohn Levon #if !defined(__xpv) 1145309b04b8SJohn Levon extern void reset_gdtr_limit(void); 1146309b04b8SJohn Levon #endif 1147309b04b8SJohn Levon 114879ec9da8SYuri Pankov /* 114979ec9da8SYuri Pankov * Hypervisor signatures 115079ec9da8SYuri Pankov */ 115179ec9da8SYuri Pankov #define HVSIG_XEN_HVM "XenVMMXenVMM" 115279ec9da8SYuri Pankov #define HVSIG_VMWARE "VMwareVMware" 115379ec9da8SYuri Pankov #define HVSIG_KVM "KVMKVMKVM" 115479ec9da8SYuri Pankov #define HVSIG_MICROSOFT "Microsoft Hv" 1155fbd54cb5SHans Rosenfeld #define HVSIG_BHYVE "bhyve bhyve " 115679ec9da8SYuri Pankov 1157b9bfdccdSStuart Maybee /* 1158b9bfdccdSStuart Maybee * Defined hardware environments 1159b9bfdccdSStuart Maybee */ 116079ec9da8SYuri Pankov #define HW_NATIVE (1 << 0) /* Running on bare metal */ 116179ec9da8SYuri Pankov #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 116279ec9da8SYuri Pankov 116379ec9da8SYuri Pankov #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 116479ec9da8SYuri Pankov #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 116579ec9da8SYuri Pankov #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 116679ec9da8SYuri Pankov #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 1167fbd54cb5SHans Rosenfeld #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */ 116879ec9da8SYuri Pankov 1169fbd54cb5SHans Rosenfeld #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \ 1170fbd54cb5SHans Rosenfeld HW_BHYVE) 1171b9bfdccdSStuart Maybee 11727c478bd9Sstevel@tonic-gate #endif /* _KERNEL */ 11737c478bd9Sstevel@tonic-gate 117479ec9da8SYuri Pankov #endif /* !_ASM */ 117579ec9da8SYuri Pankov 117679ec9da8SYuri Pankov /* 117779ec9da8SYuri Pankov * VMware hypervisor related defines 117879ec9da8SYuri Pankov */ 117979ec9da8SYuri Pankov #define VMWARE_HVMAGIC 0x564d5868 118079ec9da8SYuri Pankov #define VMWARE_HVPORT 0x5658 118179ec9da8SYuri Pankov #define VMWARE_HVCMD_GETVERSION 0x0a 118279ec9da8SYuri Pankov #define VMWARE_HVCMD_GETTSCFREQ 0x2d 11837c478bd9Sstevel@tonic-gate 11847c478bd9Sstevel@tonic-gate #ifdef __cplusplus 11857c478bd9Sstevel@tonic-gate } 11867c478bd9Sstevel@tonic-gate #endif 11877c478bd9Sstevel@tonic-gate 11887c478bd9Sstevel@tonic-gate #endif /* _SYS_X86_ARCHEXT_H */ 1189