1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*7c478bd9Sstevel@tonic-gate * Use is subject to license terms. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #ifndef _SYS_X86_ARCHEXT_H 28*7c478bd9Sstevel@tonic-gate #define _SYS_X86_ARCHEXT_H 29*7c478bd9Sstevel@tonic-gate 30*7c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*7c478bd9Sstevel@tonic-gate 32*7c478bd9Sstevel@tonic-gate #if !defined(_ASM) 33*7c478bd9Sstevel@tonic-gate #include <sys/regset.h> 34*7c478bd9Sstevel@tonic-gate #include <sys/processor.h> 35*7c478bd9Sstevel@tonic-gate #include <vm/seg_enum.h> 36*7c478bd9Sstevel@tonic-gate #include <vm/page.h> 37*7c478bd9Sstevel@tonic-gate #endif /* _ASM */ 38*7c478bd9Sstevel@tonic-gate 39*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 40*7c478bd9Sstevel@tonic-gate extern "C" { 41*7c478bd9Sstevel@tonic-gate #endif 42*7c478bd9Sstevel@tonic-gate 43*7c478bd9Sstevel@tonic-gate /* 44*7c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (standard function 1) 45*7c478bd9Sstevel@tonic-gate */ 46*7c478bd9Sstevel@tonic-gate 47*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 48*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 49*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 50*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 51*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 52*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 53*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 54*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 55*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 56*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 57*7c478bd9Sstevel@tonic-gate /* 0x400 - reserved */ 58*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 59*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 60*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 61*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 62*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 63*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 64*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 65*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 66*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 67*7c478bd9Sstevel@tonic-gate /* 0x100000 - reserved */ 68*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 69*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 70*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 71*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 72*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 73*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 74*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 75*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 76*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 77*7c478bd9Sstevel@tonic-gate /* 0x40000000 - reserved */ 78*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 79*7c478bd9Sstevel@tonic-gate 80*7c478bd9Sstevel@tonic-gate #define FMT_CPUID_INTC_EDX \ 81*7c478bd9Sstevel@tonic-gate "\20" \ 82*7c478bd9Sstevel@tonic-gate "\40pbe\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 83*7c478bd9Sstevel@tonic-gate "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat"\ 84*7c478bd9Sstevel@tonic-gate "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 85*7c478bd9Sstevel@tonic-gate "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 86*7c478bd9Sstevel@tonic-gate 87*7c478bd9Sstevel@tonic-gate /* 88*7c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %ecx (standard function 1) 89*7c478bd9Sstevel@tonic-gate */ 90*7c478bd9Sstevel@tonic-gate 91*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 92*7c478bd9Sstevel@tonic-gate /* 0x00000002 - reserved */ 93*7c478bd9Sstevel@tonic-gate /* 0x00000004 - reserved */ 94*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 95*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 96*7c478bd9Sstevel@tonic-gate /* 0x00000020 - reserved */ 97*7c478bd9Sstevel@tonic-gate /* 0x00000040 - reserved */ 98*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 99*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 100*7c478bd9Sstevel@tonic-gate /* 0x00000200 - reserved */ 101*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 102*7c478bd9Sstevel@tonic-gate /* 0x00000800 - reserved */ 103*7c478bd9Sstevel@tonic-gate /* 0x00001000 - reserved */ 104*7c478bd9Sstevel@tonic-gate /* 0x00002000 - reserved */ 105*7c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_XTPR 0x00004000 /* disable task pri messages */ 106*7c478bd9Sstevel@tonic-gate 107*7c478bd9Sstevel@tonic-gate #define FMT_CPUID_INTC_ECX \ 108*7c478bd9Sstevel@tonic-gate "\20" \ 109*7c478bd9Sstevel@tonic-gate "\20\17xtpr\13cid\11tm2" \ 110*7c478bd9Sstevel@tonic-gate "\10est\5dscpl\4monitor\1sse3" 111*7c478bd9Sstevel@tonic-gate 112*7c478bd9Sstevel@tonic-gate /* 113*7c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (extended function 0x80000001) 114*7c478bd9Sstevel@tonic-gate */ 115*7c478bd9Sstevel@tonic-gate 116*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 117*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 118*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 119*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 120*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 121*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 122*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 123*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 124*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 125*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 126*7c478bd9Sstevel@tonic-gate /* 0x00000400 - sysc on K6m6 */ 127*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 128*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 129*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 130*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 131*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 132*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PAT 0x00010000 /* page attribute table */ 133*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 134*7c478bd9Sstevel@tonic-gate /* 0x00040000 - reserved */ 135*7c478bd9Sstevel@tonic-gate /* 0x00080000 - reserved */ 136*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 137*7c478bd9Sstevel@tonic-gate /* 0x00200000 - reserved */ 138*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 139*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 140*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 141*7c478bd9Sstevel@tonic-gate /* 0x02000000 - reserved */ 142*7c478bd9Sstevel@tonic-gate /* 0x04000000 - reserved */ 143*7c478bd9Sstevel@tonic-gate /* 0x08000000 - reserved */ 144*7c478bd9Sstevel@tonic-gate /* 0x10000000 - reserved */ 145*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 146*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 147*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 148*7c478bd9Sstevel@tonic-gate 149*7c478bd9Sstevel@tonic-gate #define FMT_CPUID_AMD_EDX \ 150*7c478bd9Sstevel@tonic-gate "\20" \ 151*7c478bd9Sstevel@tonic-gate "\40a3d\37a3d+\36lm\31fxsr" \ 152*7c478bd9Sstevel@tonic-gate "\30mmx\27mmxext\25nx\22pse\21pat" \ 153*7c478bd9Sstevel@tonic-gate "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 154*7c478bd9Sstevel@tonic-gate "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 155*7c478bd9Sstevel@tonic-gate 156*7c478bd9Sstevel@tonic-gate #define CPUID_AMD_ECX_HTvalid 0x00000001 /* AMD: HTT bit valid */ 157*7c478bd9Sstevel@tonic-gate 158*7c478bd9Sstevel@tonic-gate #define FMT_CPUID_AMD_ECX \ 159*7c478bd9Sstevel@tonic-gate "\20" \ 160*7c478bd9Sstevel@tonic-gate "\1htvalid" 161*7c478bd9Sstevel@tonic-gate 162*7c478bd9Sstevel@tonic-gate #define P5_MCHADDR 0x0 163*7c478bd9Sstevel@tonic-gate #define P5_CESR 0x11 164*7c478bd9Sstevel@tonic-gate #define P5_CTR0 0x12 165*7c478bd9Sstevel@tonic-gate #define P5_CTR1 0x13 166*7c478bd9Sstevel@tonic-gate 167*7c478bd9Sstevel@tonic-gate #define K5_MCHADDR 0x0 168*7c478bd9Sstevel@tonic-gate #define K5_MCHTYPE 0x01 169*7c478bd9Sstevel@tonic-gate #define K5_TSC 0x10 170*7c478bd9Sstevel@tonic-gate #define K5_TR12 0x12 171*7c478bd9Sstevel@tonic-gate 172*7c478bd9Sstevel@tonic-gate #define REG_MTRRCAP 0xfe 173*7c478bd9Sstevel@tonic-gate #define REG_MTRRDEF 0x2ff 174*7c478bd9Sstevel@tonic-gate #define REG_MTRR64K 0x250 175*7c478bd9Sstevel@tonic-gate #define REG_MTRR16K1 0x258 176*7c478bd9Sstevel@tonic-gate #define REG_MTRR16K2 0x259 177*7c478bd9Sstevel@tonic-gate #define REG_MTRR4K1 0x268 178*7c478bd9Sstevel@tonic-gate #define REG_MTRR4K2 0x269 179*7c478bd9Sstevel@tonic-gate #define REG_MTRR4K3 0x26a 180*7c478bd9Sstevel@tonic-gate #define REG_MTRR4K4 0x26b 181*7c478bd9Sstevel@tonic-gate #define REG_MTRR4K5 0x26c 182*7c478bd9Sstevel@tonic-gate #define REG_MTRR4K6 0x26d 183*7c478bd9Sstevel@tonic-gate #define REG_MTRR4K7 0x26e 184*7c478bd9Sstevel@tonic-gate #define REG_MTRR4K8 0x26f 185*7c478bd9Sstevel@tonic-gate #define REG_MTRRPAT 0x277 186*7c478bd9Sstevel@tonic-gate 187*7c478bd9Sstevel@tonic-gate #define REG_MTRRPHYSBASE0 0x200 188*7c478bd9Sstevel@tonic-gate #define REG_MTRRPHYSMASK7 0x20f 189*7c478bd9Sstevel@tonic-gate #define REG_MC0_CTL 0x400 190*7c478bd9Sstevel@tonic-gate #define REG_MC5_MISC 0x417 191*7c478bd9Sstevel@tonic-gate #define REG_PERFCTR0 0xc1 192*7c478bd9Sstevel@tonic-gate #define REG_PERFCTR1 0xc2 193*7c478bd9Sstevel@tonic-gate 194*7c478bd9Sstevel@tonic-gate #define REG_PERFEVNT0 0x186 195*7c478bd9Sstevel@tonic-gate #define REG_PERFEVNT1 0x187 196*7c478bd9Sstevel@tonic-gate 197*7c478bd9Sstevel@tonic-gate #define REG_TSC 0x10 /* timestamp counter */ 198*7c478bd9Sstevel@tonic-gate #define REG_APIC_BASE_MSR 0x1b 199*7c478bd9Sstevel@tonic-gate 200*7c478bd9Sstevel@tonic-gate #define MSR_DEBUGCTL 0x1d9 201*7c478bd9Sstevel@tonic-gate 202*7c478bd9Sstevel@tonic-gate #define DEBUGCTL_LBR 0x01 203*7c478bd9Sstevel@tonic-gate #define DEBUGCTL_BTF 0x02 204*7c478bd9Sstevel@tonic-gate 205*7c478bd9Sstevel@tonic-gate /* Intel P6, AMD */ 206*7c478bd9Sstevel@tonic-gate #define MSR_LBR_FROM 0x1db 207*7c478bd9Sstevel@tonic-gate #define MSR_LBR_TO 0x1dc 208*7c478bd9Sstevel@tonic-gate #define MSR_LEX_FROM 0x1dd 209*7c478bd9Sstevel@tonic-gate #define MSR_LEX_TO 0x1de 210*7c478bd9Sstevel@tonic-gate 211*7c478bd9Sstevel@tonic-gate /* Intel P4 (pre-Prescott, non P4 M) */ 212*7c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_TOS 0x1da 213*7c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_0 0x1db 214*7c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_1 0x1dc 215*7c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_2 0x1dd 216*7c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_3 0x1de 217*7c478bd9Sstevel@tonic-gate 218*7c478bd9Sstevel@tonic-gate /* Intel Pentium M */ 219*7c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_TOS 0x1c9 220*7c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_0 0x040 221*7c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_1 0x041 222*7c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_2 0x042 223*7c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_3 0x043 224*7c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_4 0x044 225*7c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_5 0x045 226*7c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_6 0x046 227*7c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_7 0x047 228*7c478bd9Sstevel@tonic-gate 229*7c478bd9Sstevel@tonic-gate /* Intel P4 (Prescott) */ 230*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TOS 0x1da 231*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_0 0x680 232*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_1 0x681 233*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_2 0x682 234*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_3 0x683 235*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_4 0x684 236*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_5 0x685 237*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_6 0x686 238*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_7 0x687 239*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_8 0x688 240*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_9 0x689 241*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_10 0x68a 242*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_11 0x68b 243*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_12 0x68c 244*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_13 0x68d 245*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_14 0x68e 246*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_15 0x68f 247*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_0 0x6c0 248*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_1 0x6c1 249*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_2 0x6c2 250*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_3 0x6c3 251*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_4 0x6c4 252*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_5 0x6c5 253*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_6 0x6c6 254*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_7 0x6c7 255*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_8 0x6c8 256*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_9 0x6c9 257*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_10 0x6ca 258*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_11 0x6cb 259*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_12 0x6cc 260*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_13 0x6cd 261*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_14 0x6ce 262*7c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_15 0x6cf 263*7c478bd9Sstevel@tonic-gate 264*7c478bd9Sstevel@tonic-gate #define REG_MCG_CAP 0x179 265*7c478bd9Sstevel@tonic-gate #define REG_MCG_STATUS 0x17a 266*7c478bd9Sstevel@tonic-gate #define REG_MCG_CTL 0x17b 267*7c478bd9Sstevel@tonic-gate 268*7c478bd9Sstevel@tonic-gate #define REG_MC0_CTL 0x400 269*7c478bd9Sstevel@tonic-gate #define REG_MC0_STATUS 0x401 270*7c478bd9Sstevel@tonic-gate #define REG_MC0_ADDR 0x402 271*7c478bd9Sstevel@tonic-gate #define REG_MC0_MISC 0x403 272*7c478bd9Sstevel@tonic-gate #define REG_MC1_CTL 0x404 273*7c478bd9Sstevel@tonic-gate #define REG_MC1_STATUS 0x405 274*7c478bd9Sstevel@tonic-gate #define REG_MC1_ADDR 0x406 275*7c478bd9Sstevel@tonic-gate #define REG_MC1_MISC 0x407 276*7c478bd9Sstevel@tonic-gate #define REG_MC2_CTL 0x408 277*7c478bd9Sstevel@tonic-gate #define REG_MC2_STATUS 0x409 278*7c478bd9Sstevel@tonic-gate #define REG_MC2_ADDR 0x40a 279*7c478bd9Sstevel@tonic-gate #define REG_MC2_MISC 0x40b 280*7c478bd9Sstevel@tonic-gate #define REG_MC4_CTL 0x40c 281*7c478bd9Sstevel@tonic-gate #define REG_MC4_STATUS 0x40d 282*7c478bd9Sstevel@tonic-gate #define REG_MC4_ADDR 0x40e 283*7c478bd9Sstevel@tonic-gate #define REG_MC4_MISC 0x40f 284*7c478bd9Sstevel@tonic-gate #define REG_MC3_CTL 0x410 285*7c478bd9Sstevel@tonic-gate #define REG_MC3_STATUS 0x411 286*7c478bd9Sstevel@tonic-gate #define REG_MC3_ADDR 0x412 287*7c478bd9Sstevel@tonic-gate #define REG_MC3_MISC 0x413 288*7c478bd9Sstevel@tonic-gate 289*7c478bd9Sstevel@tonic-gate #define P6_MCG_CAP_COUNT 5 290*7c478bd9Sstevel@tonic-gate #define MCG_CAP_COUNT_MASK 0xff 291*7c478bd9Sstevel@tonic-gate #define MCG_CAP_CTL_P 0x100 292*7c478bd9Sstevel@tonic-gate 293*7c478bd9Sstevel@tonic-gate #define MCG_STATUS_RIPV 0x01 294*7c478bd9Sstevel@tonic-gate #define MCG_STATUS_EIPV 0x02 295*7c478bd9Sstevel@tonic-gate #define MCG_STATUS_MCIP 0x04 296*7c478bd9Sstevel@tonic-gate 297*7c478bd9Sstevel@tonic-gate #define MCG_CTL_VALUE 0xffffffff 298*7c478bd9Sstevel@tonic-gate 299*7c478bd9Sstevel@tonic-gate #define MCI_CTL_VALUE 0xffffffff 300*7c478bd9Sstevel@tonic-gate #define MCI_STATUS_ERRCODE 0xffff 301*7c478bd9Sstevel@tonic-gate #define MCI_STATUS_MSERRCODE 0xffff0000 302*7c478bd9Sstevel@tonic-gate #define MCI_STATUS_PCC ((long long)0x200000000000000) 303*7c478bd9Sstevel@tonic-gate #define MCI_STATUS_ADDRV ((long long)0x400000000000000) 304*7c478bd9Sstevel@tonic-gate #define MCI_STATUS_MISCV ((long long)0x800000000000000) 305*7c478bd9Sstevel@tonic-gate #define MCI_STATUS_EN ((long long)0x1000000000000000) 306*7c478bd9Sstevel@tonic-gate #define MCI_STATUS_UC ((long long)0x2000000000000000) 307*7c478bd9Sstevel@tonic-gate #define MCI_STATUS_O ((long long)0x4000000000000000) 308*7c478bd9Sstevel@tonic-gate #define MCI_STATUS_VAL ((long long)0x8000000000000000) 309*7c478bd9Sstevel@tonic-gate 310*7c478bd9Sstevel@tonic-gate #define MSERRCODE_SHFT 16 311*7c478bd9Sstevel@tonic-gate 312*7c478bd9Sstevel@tonic-gate 313*7c478bd9Sstevel@tonic-gate #define MTRRTYPE_MASK 0xff 314*7c478bd9Sstevel@tonic-gate 315*7c478bd9Sstevel@tonic-gate 316*7c478bd9Sstevel@tonic-gate #define MTRRCAP_FIX 0x100 317*7c478bd9Sstevel@tonic-gate #define MTRRCAP_VCNTMASK 0xff 318*7c478bd9Sstevel@tonic-gate #define MTRRCAP_USWC 0x400 319*7c478bd9Sstevel@tonic-gate 320*7c478bd9Sstevel@tonic-gate #define MTRRDEF_E 0x800 321*7c478bd9Sstevel@tonic-gate #define MTRRDEF_FE 0x400 322*7c478bd9Sstevel@tonic-gate 323*7c478bd9Sstevel@tonic-gate #define MTRRPHYSMASK_V 0x800 324*7c478bd9Sstevel@tonic-gate 325*7c478bd9Sstevel@tonic-gate #define MTRR_TYPE_UC 0 326*7c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WC 1 327*7c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WT 4 328*7c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WP 5 329*7c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WB 6 330*7c478bd9Sstevel@tonic-gate 331*7c478bd9Sstevel@tonic-gate /* 332*7c478bd9Sstevel@tonic-gate * Page attribute table is setup in the following way 333*7c478bd9Sstevel@tonic-gate * PAT0 Write-BACK 334*7c478bd9Sstevel@tonic-gate * PAT1 Write-Through 335*7c478bd9Sstevel@tonic-gate * PAT2 Unchacheable 336*7c478bd9Sstevel@tonic-gate * PAT3 Uncacheable 337*7c478bd9Sstevel@tonic-gate * PAT4 Uncacheable 338*7c478bd9Sstevel@tonic-gate * PAT5 Write-Protect 339*7c478bd9Sstevel@tonic-gate * PAT6 Write-Combine 340*7c478bd9Sstevel@tonic-gate * PAT7 Uncacheable 341*7c478bd9Sstevel@tonic-gate */ 342*7c478bd9Sstevel@tonic-gate #define PAT_DEFAULT_ATTRIBUTE \ 343*7c478bd9Sstevel@tonic-gate ((uint64_t)MTRR_TYPE_WC << 48)|((uint64_t)MTRR_TYPE_WP << 40)| \ 344*7c478bd9Sstevel@tonic-gate (MTRR_TYPE_WT << 8)|(MTRR_TYPE_WB) 345*7c478bd9Sstevel@tonic-gate 346*7c478bd9Sstevel@tonic-gate 347*7c478bd9Sstevel@tonic-gate #define MTRR_SETTYPE(a, t) ((a &= (uint64_t)~0xff),\ 348*7c478bd9Sstevel@tonic-gate (a |= ((t) & 0xff))) 349*7c478bd9Sstevel@tonic-gate #define MTRR_SETVINVALID(a) ((a) &= ~MTRRPHYSMASK_V) 350*7c478bd9Sstevel@tonic-gate 351*7c478bd9Sstevel@tonic-gate 352*7c478bd9Sstevel@tonic-gate #define MTRR_SETVBASE(a, b, t) ((a) =\ 353*7c478bd9Sstevel@tonic-gate ((((uint64_t)(b)) & 0xffffff000)|\ 354*7c478bd9Sstevel@tonic-gate (((uint32_t)(t)) & 0xff))) 355*7c478bd9Sstevel@tonic-gate 356*7c478bd9Sstevel@tonic-gate #define MTRR_SETVMASK(a, s, v) ((a) =\ 357*7c478bd9Sstevel@tonic-gate ((~(((uint64_t)(s)) - 1) & 0xffffff000)|\ 358*7c478bd9Sstevel@tonic-gate (((uint32_t)(v)) << 11))) 359*7c478bd9Sstevel@tonic-gate 360*7c478bd9Sstevel@tonic-gate #define MTRR_GETVBASE(a) (((uint64_t)(a)) & 0xffffff000) 361*7c478bd9Sstevel@tonic-gate #define MTRR_GETVTYPE(a) (((uint64_t)(a)) & 0xff) 362*7c478bd9Sstevel@tonic-gate #define MTRR_GETVSIZE(a) ((~((uint64_t)(a)) + 1) & 0xffffff000) 363*7c478bd9Sstevel@tonic-gate 364*7c478bd9Sstevel@tonic-gate 365*7c478bd9Sstevel@tonic-gate #define MAX_MTRRVAR 8 366*7c478bd9Sstevel@tonic-gate 367*7c478bd9Sstevel@tonic-gate #if !defined(_ASM) 368*7c478bd9Sstevel@tonic-gate typedef struct mtrrvar { 369*7c478bd9Sstevel@tonic-gate uint64_t mtrrphys_base; 370*7c478bd9Sstevel@tonic-gate uint64_t mtrrphys_mask; 371*7c478bd9Sstevel@tonic-gate } mtrrvar_t; 372*7c478bd9Sstevel@tonic-gate #endif /* _ASM */ 373*7c478bd9Sstevel@tonic-gate 374*7c478bd9Sstevel@tonic-gate #define X86_LARGEPAGE 0x00000001 375*7c478bd9Sstevel@tonic-gate #define X86_TSC 0x00000002 376*7c478bd9Sstevel@tonic-gate #define X86_MSR 0x00000004 377*7c478bd9Sstevel@tonic-gate #define X86_MTRR 0x00000008 378*7c478bd9Sstevel@tonic-gate #define X86_PGE 0x00000010 379*7c478bd9Sstevel@tonic-gate #define X86_CMOV 0x00000040 380*7c478bd9Sstevel@tonic-gate #define X86_MMX 0x00000080 381*7c478bd9Sstevel@tonic-gate #define X86_MCA 0x00000100 382*7c478bd9Sstevel@tonic-gate #define X86_PAE 0x00000200 383*7c478bd9Sstevel@tonic-gate #define X86_CX8 0x00000400 384*7c478bd9Sstevel@tonic-gate #define X86_PAT 0x00000800 385*7c478bd9Sstevel@tonic-gate #define X86_SEP 0x00001000 386*7c478bd9Sstevel@tonic-gate #define X86_SSE 0x00002000 387*7c478bd9Sstevel@tonic-gate #define X86_SSE2 0x00004000 388*7c478bd9Sstevel@tonic-gate #define X86_HTT 0x00008000 389*7c478bd9Sstevel@tonic-gate #define X86_ASYSC 0x00010000 390*7c478bd9Sstevel@tonic-gate #define X86_NX 0x00020000 391*7c478bd9Sstevel@tonic-gate #define X86_SSE3 0x00040000 392*7c478bd9Sstevel@tonic-gate #define X86_CX16 0x00080000 393*7c478bd9Sstevel@tonic-gate #define X86_CMP 0x00100000 394*7c478bd9Sstevel@tonic-gate #define X86_CPUID 0x01000000 395*7c478bd9Sstevel@tonic-gate 396*7c478bd9Sstevel@tonic-gate #define FMT_X86_FEATURE \ 397*7c478bd9Sstevel@tonic-gate "\20" \ 398*7c478bd9Sstevel@tonic-gate "\31cpuid" \ 399*7c478bd9Sstevel@tonic-gate "\25cmp\24cx16\23sse3\22nx\21asysc" \ 400*7c478bd9Sstevel@tonic-gate "\20htt\17sse2\16sse\15sep\14pat\13cx8\12pae\11mca" \ 401*7c478bd9Sstevel@tonic-gate "\10mmx\7cmov\5pge\4mtrr\3msr\2tsc\1lgpg" 402*7c478bd9Sstevel@tonic-gate 403*7c478bd9Sstevel@tonic-gate /* 404*7c478bd9Sstevel@tonic-gate * x86_type is a legacy concept; this is supplanted 405*7c478bd9Sstevel@tonic-gate * for most purposes by x86_feature; modern CPUs 406*7c478bd9Sstevel@tonic-gate * should be X86_TYPE_OTHER 407*7c478bd9Sstevel@tonic-gate */ 408*7c478bd9Sstevel@tonic-gate #define X86_TYPE_OTHER 0 409*7c478bd9Sstevel@tonic-gate #define X86_TYPE_486 1 410*7c478bd9Sstevel@tonic-gate #define X86_TYPE_P5 2 411*7c478bd9Sstevel@tonic-gate #define X86_TYPE_P6 3 412*7c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_486 4 413*7c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86L 5 414*7c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86 6 415*7c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_GXm 7 416*7c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86MX 8 417*7c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MediaGX 9 418*7c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MII 10 419*7c478bd9Sstevel@tonic-gate #define X86_TYPE_VIA_CYRIX_III 11 420*7c478bd9Sstevel@tonic-gate #define X86_TYPE_P4 12 421*7c478bd9Sstevel@tonic-gate 422*7c478bd9Sstevel@tonic-gate /* 423*7c478bd9Sstevel@tonic-gate * x86_vendor allows us to select between 424*7c478bd9Sstevel@tonic-gate * implementation features and helps guide 425*7c478bd9Sstevel@tonic-gate * the interpretation of the cpuid instruction. 426*7c478bd9Sstevel@tonic-gate */ 427*7c478bd9Sstevel@tonic-gate #define X86_VENDOR_Intel 0 /* GenuineIntel */ 428*7c478bd9Sstevel@tonic-gate #define X86_VENDOR_IntelClone 1 /* (an Intel clone) */ 429*7c478bd9Sstevel@tonic-gate #define X86_VENDOR_AMD 2 /* AuthenticAMD */ 430*7c478bd9Sstevel@tonic-gate #define X86_VENDOR_Cyrix 3 /* CyrixInstead */ 431*7c478bd9Sstevel@tonic-gate #define X86_VENDOR_UMC 4 /* UMC UMC UMC */ 432*7c478bd9Sstevel@tonic-gate #define X86_VENDOR_NexGen 5 /* NexGenDriven */ 433*7c478bd9Sstevel@tonic-gate #define X86_VENDOR_Centaur 6 /* CentaurHauls */ 434*7c478bd9Sstevel@tonic-gate #define X86_VENDOR_Rise 7 /* RiseRiseRise */ 435*7c478bd9Sstevel@tonic-gate #define X86_VENDOR_SiS 8 /* SiS SiS SiS */ 436*7c478bd9Sstevel@tonic-gate #define X86_VENDOR_TM 9 /* GenuineTMx86 */ 437*7c478bd9Sstevel@tonic-gate #define X86_VENDOR_NSC 10 /* Geode by NSC */ 438*7c478bd9Sstevel@tonic-gate 439*7c478bd9Sstevel@tonic-gate #if !defined(_ASM) 440*7c478bd9Sstevel@tonic-gate 441*7c478bd9Sstevel@tonic-gate #if defined(_KERNEL) || defined(_KMEMUSER) 442*7c478bd9Sstevel@tonic-gate 443*7c478bd9Sstevel@tonic-gate extern uint_t x86_feature; 444*7c478bd9Sstevel@tonic-gate extern uint_t x86_type; 445*7c478bd9Sstevel@tonic-gate extern uint_t x86_vendor; 446*7c478bd9Sstevel@tonic-gate 447*7c478bd9Sstevel@tonic-gate extern ulong_t cr4_value; 448*7c478bd9Sstevel@tonic-gate extern uint_t pentiumpro_bug4046376; 449*7c478bd9Sstevel@tonic-gate extern uint_t pentiumpro_bug4064495; 450*7c478bd9Sstevel@tonic-gate 451*7c478bd9Sstevel@tonic-gate extern uint_t enable486; 452*7c478bd9Sstevel@tonic-gate 453*7c478bd9Sstevel@tonic-gate extern const char CyrixInstead[]; 454*7c478bd9Sstevel@tonic-gate 455*7c478bd9Sstevel@tonic-gate #endif 456*7c478bd9Sstevel@tonic-gate 457*7c478bd9Sstevel@tonic-gate #if defined(_KERNEL) 458*7c478bd9Sstevel@tonic-gate 459*7c478bd9Sstevel@tonic-gate 460*7c478bd9Sstevel@tonic-gate extern uint64_t rdmsr(uint_t, uint64_t *); 461*7c478bd9Sstevel@tonic-gate extern void wrmsr(uint_t, const uint64_t *); 462*7c478bd9Sstevel@tonic-gate extern void invalidate_cache(void); 463*7c478bd9Sstevel@tonic-gate struct regs; 464*7c478bd9Sstevel@tonic-gate extern int mca_exception(struct regs *); 465*7c478bd9Sstevel@tonic-gate extern ulong_t getcr4(void); 466*7c478bd9Sstevel@tonic-gate extern void setcr4(ulong_t); 467*7c478bd9Sstevel@tonic-gate extern void mtrr_sync(void); 468*7c478bd9Sstevel@tonic-gate 469*7c478bd9Sstevel@tonic-gate extern void cpu_fast_syscall_enable(void *); 470*7c478bd9Sstevel@tonic-gate extern void cpu_fast_syscall_disable(void *); 471*7c478bd9Sstevel@tonic-gate 472*7c478bd9Sstevel@tonic-gate struct cpu; 473*7c478bd9Sstevel@tonic-gate 474*7c478bd9Sstevel@tonic-gate extern int cpuid_checkpass(struct cpu *, int); 475*7c478bd9Sstevel@tonic-gate extern uint32_t cpuid_insn(struct cpu *, 476*7c478bd9Sstevel@tonic-gate uint32_t, uint32_t *, uint32_t *, uint32_t *); 477*7c478bd9Sstevel@tonic-gate extern uint32_t __cpuid_insn(uint32_t, uint32_t *, uint32_t *, uint32_t *); 478*7c478bd9Sstevel@tonic-gate extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 479*7c478bd9Sstevel@tonic-gate extern int cpuid_getidstr(struct cpu *, char *, size_t); 480*7c478bd9Sstevel@tonic-gate extern const char *cpuid_getvendorstr(struct cpu *); 481*7c478bd9Sstevel@tonic-gate extern uint_t cpuid_getvendor(struct cpu *); 482*7c478bd9Sstevel@tonic-gate extern uint_t cpuid_getfamily(struct cpu *); 483*7c478bd9Sstevel@tonic-gate extern uint_t cpuid_getmodel(struct cpu *); 484*7c478bd9Sstevel@tonic-gate extern uint_t cpuid_getstep(struct cpu *); 485*7c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 486*7c478bd9Sstevel@tonic-gate extern int cpuid_is_ht(struct cpu *); 487*7c478bd9Sstevel@tonic-gate extern int cpuid_syscall32_insn(struct cpu *); 488*7c478bd9Sstevel@tonic-gate extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 489*7c478bd9Sstevel@tonic-gate 490*7c478bd9Sstevel@tonic-gate extern int cpuid_opteron_erratum(struct cpu *, uint_t); 491*7c478bd9Sstevel@tonic-gate 492*7c478bd9Sstevel@tonic-gate struct cpuid_info; 493*7c478bd9Sstevel@tonic-gate 494*7c478bd9Sstevel@tonic-gate extern void setx86isalist(void); 495*7c478bd9Sstevel@tonic-gate extern uint_t cpuid_pass1(struct cpu *); 496*7c478bd9Sstevel@tonic-gate extern void cpuid_pass2(struct cpu *); 497*7c478bd9Sstevel@tonic-gate extern void cpuid_pass3(struct cpu *); 498*7c478bd9Sstevel@tonic-gate extern uint_t cpuid_pass4(struct cpu *); 499*7c478bd9Sstevel@tonic-gate extern void add_cpunode2devtree(processorid_t, struct cpuid_info *); 500*7c478bd9Sstevel@tonic-gate 501*7c478bd9Sstevel@tonic-gate extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 502*7c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 503*7c478bd9Sstevel@tonic-gate 504*7c478bd9Sstevel@tonic-gate extern uint_t workaround_errata(struct cpu *); 505*7c478bd9Sstevel@tonic-gate 506*7c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 507*7c478bd9Sstevel@tonic-gate extern int opteron_erratum_93; 508*7c478bd9Sstevel@tonic-gate #endif 509*7c478bd9Sstevel@tonic-gate 510*7c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 511*7c478bd9Sstevel@tonic-gate extern int opteron_erratum_91; 512*7c478bd9Sstevel@tonic-gate #endif 513*7c478bd9Sstevel@tonic-gate 514*7c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 515*7c478bd9Sstevel@tonic-gate extern int opteron_erratum_100; 516*7c478bd9Sstevel@tonic-gate #endif 517*7c478bd9Sstevel@tonic-gate 518*7c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 519*7c478bd9Sstevel@tonic-gate extern int opteron_erratum_121; 520*7c478bd9Sstevel@tonic-gate #endif 521*7c478bd9Sstevel@tonic-gate 522*7c478bd9Sstevel@tonic-gate #endif /* _KERNEL */ 523*7c478bd9Sstevel@tonic-gate 524*7c478bd9Sstevel@tonic-gate #endif 525*7c478bd9Sstevel@tonic-gate 526*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 527*7c478bd9Sstevel@tonic-gate } 528*7c478bd9Sstevel@tonic-gate #endif 529*7c478bd9Sstevel@tonic-gate 530*7c478bd9Sstevel@tonic-gate #endif /* _SYS_X86_ARCHEXT_H */ 531