17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5ee88d2b9Skchow * Common Development and Distribution License (the "License"). 6ee88d2b9Skchow * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 227417cfdeSKuriakose Kuruvilla * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23cfe84b82SMatt Amdur * Copyright (c) 2011 by Delphix. All rights reserved. 24*79ec9da8SYuri Pankov * Copyright 2012 Nexenta Systems, Inc. All rights reserved. 257c478bd9Sstevel@tonic-gate */ 26cef70d2cSBill Holler /* 2741afdfa7SKrishnendu Sadhukhan - Sun Microsystems * Copyright (c) 2010, Intel Corporation. 28cef70d2cSBill Holler * All rights reserved. 29cef70d2cSBill Holler */ 30faa20166SBryan Cantrill /* 31ebb8ac07SRobert Mustacchi * Copyright (c) 2012, Joyent, Inc. All rights reserved. 3279321794SJens Elkner * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 3379321794SJens Elkner * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 34faa20166SBryan Cantrill */ 357c478bd9Sstevel@tonic-gate 367c478bd9Sstevel@tonic-gate #ifndef _SYS_X86_ARCHEXT_H 377c478bd9Sstevel@tonic-gate #define _SYS_X86_ARCHEXT_H 387c478bd9Sstevel@tonic-gate 397c478bd9Sstevel@tonic-gate #if !defined(_ASM) 407c478bd9Sstevel@tonic-gate #include <sys/regset.h> 417c478bd9Sstevel@tonic-gate #include <sys/processor.h> 427c478bd9Sstevel@tonic-gate #include <vm/seg_enum.h> 437c478bd9Sstevel@tonic-gate #include <vm/page.h> 447c478bd9Sstevel@tonic-gate #endif /* _ASM */ 457c478bd9Sstevel@tonic-gate 467c478bd9Sstevel@tonic-gate #ifdef __cplusplus 477c478bd9Sstevel@tonic-gate extern "C" { 487c478bd9Sstevel@tonic-gate #endif 497c478bd9Sstevel@tonic-gate 507c478bd9Sstevel@tonic-gate /* 517c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (standard function 1) 527c478bd9Sstevel@tonic-gate */ 537c478bd9Sstevel@tonic-gate 547c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 557c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 567c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 577c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 587c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 597c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 607c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 617c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 627c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 637c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 647c478bd9Sstevel@tonic-gate /* 0x400 - reserved */ 657c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 667c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 677c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 687c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 697c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 707c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 717c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 727c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 737c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 747c478bd9Sstevel@tonic-gate /* 0x100000 - reserved */ 757c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 767c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 777c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 787c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 797c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 807c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 817c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 827c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 837c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 84ae115bc7Smrj #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 857c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 867c478bd9Sstevel@tonic-gate 87ae115bc7Smrj #define FMT_CPUID_INTC_EDX \ 88ae115bc7Smrj "\20" \ 89ae115bc7Smrj "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 90ae115bc7Smrj "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 91ae115bc7Smrj "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 927c478bd9Sstevel@tonic-gate "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 937c478bd9Sstevel@tonic-gate 947c478bd9Sstevel@tonic-gate /* 957c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %ecx (standard function 1) 967c478bd9Sstevel@tonic-gate */ 977c478bd9Sstevel@tonic-gate 987c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 99a50a8b93SKuriakose Kuruvilla #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 1007c478bd9Sstevel@tonic-gate /* 0x00000004 - reserved */ 1017c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 1027c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 103ae115bc7Smrj #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 104ae115bc7Smrj #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 1057c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 1067c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 107ae115bc7Smrj #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 1087c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 1097c478bd9Sstevel@tonic-gate /* 0x00000800 - reserved */ 1107c478bd9Sstevel@tonic-gate /* 0x00001000 - reserved */ 111ae115bc7Smrj #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 112ae115bc7Smrj #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 113ae115bc7Smrj /* 0x00008000 - reserved */ 114ae115bc7Smrj /* 0x00010000 - reserved */ 115ae115bc7Smrj /* 0x00020000 - reserved */ 116ae115bc7Smrj #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 117d0f8ff6eSkk #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 118d0f8ff6eSkk #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 1195087e485SKrishnendu Sadhukhan - Sun Microsystems #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 120f8801251Skk #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 121a50a8b93SKuriakose Kuruvilla #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 1227af88ac7SKuriakose Kuruvilla #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 1237af88ac7SKuriakose Kuruvilla #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 1247af88ac7SKuriakose Kuruvilla #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 125ebb8ac07SRobert Mustacchi #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 126ebb8ac07SRobert Mustacchi #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 127*79ec9da8SYuri Pankov #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 128ae115bc7Smrj 129ae115bc7Smrj #define FMT_CPUID_INTC_ECX \ 130ae115bc7Smrj "\20" \ 131ebb8ac07SRobert Mustacchi "\37rdrand\36f16c\35avx\34osxsav\33xsave" \ 132a50a8b93SKuriakose Kuruvilla "\32aes" \ 1335087e485SKrishnendu Sadhukhan - Sun Microsystems "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \ 134ae115bc7Smrj "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 135a50a8b93SKuriakose Kuruvilla "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3" 1367c478bd9Sstevel@tonic-gate 1377c478bd9Sstevel@tonic-gate /* 1387c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (extended function 0x80000001) 1397c478bd9Sstevel@tonic-gate */ 1407c478bd9Sstevel@tonic-gate 1417c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 1427c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 1437c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 1447c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 1457c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 1467c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 1477c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 1487c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 1497c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 1507c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 1517c478bd9Sstevel@tonic-gate /* 0x00000400 - sysc on K6m6 */ 1527c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 1537c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 1547c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 1557c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 1567c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 157ae115bc7Smrj #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 158ae115bc7Smrj #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 1597c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 1607c478bd9Sstevel@tonic-gate /* 0x00040000 - reserved */ 1617c478bd9Sstevel@tonic-gate /* 0x00080000 - reserved */ 1627c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 1637c478bd9Sstevel@tonic-gate /* 0x00200000 - reserved */ 1647c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 1657c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 1667c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 167ae115bc7Smrj #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 16802bc52beSkchow #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 169ae115bc7Smrj #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 1707c478bd9Sstevel@tonic-gate /* 0x10000000 - reserved */ 1717c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 1727c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 1737c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 1747c478bd9Sstevel@tonic-gate 1757c478bd9Sstevel@tonic-gate #define FMT_CPUID_AMD_EDX \ 1767c478bd9Sstevel@tonic-gate "\20" \ 177ae115bc7Smrj "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 1787c478bd9Sstevel@tonic-gate "\30mmx\27mmxext\25nx\22pse\21pat" \ 1797c478bd9Sstevel@tonic-gate "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 1807c478bd9Sstevel@tonic-gate "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 1817c478bd9Sstevel@tonic-gate 182ae115bc7Smrj #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 183ae115bc7Smrj #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 184ae115bc7Smrj #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 185ae115bc7Smrj #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 186ae115bc7Smrj #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 187f8801251Skk #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 188f8801251Skk #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 189512cf780Skchow #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 190512cf780Skchow #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 191512cf780Skchow #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 192512cf780Skchow #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 193512cf780Skchow #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ 194512cf780Skchow #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 195512cf780Skchow #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 1967660e73fSHans Rosenfeld #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 1977c478bd9Sstevel@tonic-gate 1987c478bd9Sstevel@tonic-gate #define FMT_CPUID_AMD_ECX \ 1997c478bd9Sstevel@tonic-gate "\20" \ 2007660e73fSHans Rosenfeld "\22topoext" \ 201512cf780Skchow "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \ 202f8801251Skk "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 203ae115bc7Smrj 204ae115bc7Smrj /* 205ae115bc7Smrj * Intel now seems to have claimed part of the "extended" function 206ae115bc7Smrj * space that we previously for non-Intel implementors to use. 207ae115bc7Smrj * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 208ae115bc7Smrj * is available in long mode i.e. what AMD indicate using bit 0. 209ae115bc7Smrj * On the other hand, everything else is labelled as reserved. 210ae115bc7Smrj */ 211ae115bc7Smrj #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 212ae115bc7Smrj 2137c478bd9Sstevel@tonic-gate 2147c478bd9Sstevel@tonic-gate #define P5_MCHADDR 0x0 2157c478bd9Sstevel@tonic-gate #define P5_CESR 0x11 2167c478bd9Sstevel@tonic-gate #define P5_CTR0 0x12 2177c478bd9Sstevel@tonic-gate #define P5_CTR1 0x13 2187c478bd9Sstevel@tonic-gate 2197c478bd9Sstevel@tonic-gate #define K5_MCHADDR 0x0 2207c478bd9Sstevel@tonic-gate #define K5_MCHTYPE 0x01 2217c478bd9Sstevel@tonic-gate #define K5_TSC 0x10 2227c478bd9Sstevel@tonic-gate #define K5_TR12 0x12 2237c478bd9Sstevel@tonic-gate 2241d03c31eSjohnlev #define REG_PAT 0x277 2251d03c31eSjohnlev 2267c478bd9Sstevel@tonic-gate #define REG_MC0_CTL 0x400 2277c478bd9Sstevel@tonic-gate #define REG_MC5_MISC 0x417 2287c478bd9Sstevel@tonic-gate #define REG_PERFCTR0 0xc1 2297c478bd9Sstevel@tonic-gate #define REG_PERFCTR1 0xc2 2307c478bd9Sstevel@tonic-gate 2317c478bd9Sstevel@tonic-gate #define REG_PERFEVNT0 0x186 2327c478bd9Sstevel@tonic-gate #define REG_PERFEVNT1 0x187 2337c478bd9Sstevel@tonic-gate 2347c478bd9Sstevel@tonic-gate #define REG_TSC 0x10 /* timestamp counter */ 2357c478bd9Sstevel@tonic-gate #define REG_APIC_BASE_MSR 0x1b 236b6917abeSmishra #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 2377c478bd9Sstevel@tonic-gate 238e774b42bSBill Holler #if !defined(__xpv) 239e774b42bSBill Holler /* 240e774b42bSBill Holler * AMD C1E 241e774b42bSBill Holler */ 242e774b42bSBill Holler #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 243e774b42bSBill Holler #define AMD_ACTONCMPHALT_SHIFT 27 244e774b42bSBill Holler #define AMD_ACTONCMPHALT_MASK 3 245e774b42bSBill Holler #endif 246e774b42bSBill Holler 2477c478bd9Sstevel@tonic-gate #define MSR_DEBUGCTL 0x1d9 2487c478bd9Sstevel@tonic-gate 2497c478bd9Sstevel@tonic-gate #define DEBUGCTL_LBR 0x01 2507c478bd9Sstevel@tonic-gate #define DEBUGCTL_BTF 0x02 2517c478bd9Sstevel@tonic-gate 2527c478bd9Sstevel@tonic-gate /* Intel P6, AMD */ 2537c478bd9Sstevel@tonic-gate #define MSR_LBR_FROM 0x1db 2547c478bd9Sstevel@tonic-gate #define MSR_LBR_TO 0x1dc 2557c478bd9Sstevel@tonic-gate #define MSR_LEX_FROM 0x1dd 2567c478bd9Sstevel@tonic-gate #define MSR_LEX_TO 0x1de 2577c478bd9Sstevel@tonic-gate 2587c478bd9Sstevel@tonic-gate /* Intel P4 (pre-Prescott, non P4 M) */ 2597c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_TOS 0x1da 2607c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_0 0x1db 2617c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_1 0x1dc 2627c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_2 0x1dd 2637c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_3 0x1de 2647c478bd9Sstevel@tonic-gate 2657c478bd9Sstevel@tonic-gate /* Intel Pentium M */ 2667c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_TOS 0x1c9 2677c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_0 0x040 2687c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_1 0x041 2697c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_2 0x042 2707c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_3 0x043 2717c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_4 0x044 2727c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_5 0x045 2737c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_6 0x046 2747c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_7 0x047 2757c478bd9Sstevel@tonic-gate 2767c478bd9Sstevel@tonic-gate /* Intel P4 (Prescott) */ 2777c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TOS 0x1da 2787c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_0 0x680 2797c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_1 0x681 2807c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_2 0x682 2817c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_3 0x683 2827c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_4 0x684 2837c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_5 0x685 2847c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_6 0x686 2857c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_7 0x687 2867c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_8 0x688 2877c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_9 0x689 2887c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_10 0x68a 2897c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_11 0x68b 2907c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_12 0x68c 2917c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_13 0x68d 2927c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_14 0x68e 2937c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_15 0x68f 2947c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_0 0x6c0 2957c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_1 0x6c1 2967c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_2 0x6c2 2977c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_3 0x6c3 2987c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_4 0x6c4 2997c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_5 0x6c5 3007c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_6 0x6c6 3017c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_7 0x6c7 3027c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_8 0x6c8 3037c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_9 0x6c9 3047c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_10 0x6ca 3057c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_11 0x6cb 3067c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_12 0x6cc 3077c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_13 0x6cd 3087c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_14 0x6ce 3097c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_15 0x6cf 3107c478bd9Sstevel@tonic-gate 3117c478bd9Sstevel@tonic-gate #define MCI_CTL_VALUE 0xffffffff 3127c478bd9Sstevel@tonic-gate 3137c478bd9Sstevel@tonic-gate #define MTRR_TYPE_UC 0 3147c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WC 1 3157c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WT 4 3167c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WP 5 3177c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WB 6 3181d03c31eSjohnlev #define MTRR_TYPE_UC_ 7 3197c478bd9Sstevel@tonic-gate 3207c478bd9Sstevel@tonic-gate /* 3211d03c31eSjohnlev * For Solaris we set up the page attritubute table in the following way: 3221d03c31eSjohnlev * PAT0 Write-Back 3237c478bd9Sstevel@tonic-gate * PAT1 Write-Through 3241d03c31eSjohnlev * PAT2 Unchacheable- 3257c478bd9Sstevel@tonic-gate * PAT3 Uncacheable 3261d03c31eSjohnlev * PAT4 Write-Back 3271d03c31eSjohnlev * PAT5 Write-Through 3287c478bd9Sstevel@tonic-gate * PAT6 Write-Combine 3297c478bd9Sstevel@tonic-gate * PAT7 Uncacheable 3301d03c31eSjohnlev * The only difference from h/w default is entry 6. 3317c478bd9Sstevel@tonic-gate */ 3321d03c31eSjohnlev #define PAT_DEFAULT_ATTRIBUTE \ 3331d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WB | \ 3341d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WT << 8) | \ 3351d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 3361d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC << 24) | \ 3371d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WB << 32) | \ 3381d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WT << 40) | \ 3391d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WC << 48) | \ 3401d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC << 56)) 3417c478bd9Sstevel@tonic-gate 3427417cfdeSKuriakose Kuruvilla #define X86FSET_LARGEPAGE 0 3437417cfdeSKuriakose Kuruvilla #define X86FSET_TSC 1 3447417cfdeSKuriakose Kuruvilla #define X86FSET_MSR 2 3457417cfdeSKuriakose Kuruvilla #define X86FSET_MTRR 3 3467417cfdeSKuriakose Kuruvilla #define X86FSET_PGE 4 3477417cfdeSKuriakose Kuruvilla #define X86FSET_DE 5 3487417cfdeSKuriakose Kuruvilla #define X86FSET_CMOV 6 3497417cfdeSKuriakose Kuruvilla #define X86FSET_MMX 7 3507417cfdeSKuriakose Kuruvilla #define X86FSET_MCA 8 3517417cfdeSKuriakose Kuruvilla #define X86FSET_PAE 9 3527417cfdeSKuriakose Kuruvilla #define X86FSET_CX8 10 3537417cfdeSKuriakose Kuruvilla #define X86FSET_PAT 11 3547417cfdeSKuriakose Kuruvilla #define X86FSET_SEP 12 3557417cfdeSKuriakose Kuruvilla #define X86FSET_SSE 13 3567417cfdeSKuriakose Kuruvilla #define X86FSET_SSE2 14 3577417cfdeSKuriakose Kuruvilla #define X86FSET_HTT 15 3587417cfdeSKuriakose Kuruvilla #define X86FSET_ASYSC 16 3597417cfdeSKuriakose Kuruvilla #define X86FSET_NX 17 3607417cfdeSKuriakose Kuruvilla #define X86FSET_SSE3 18 3617417cfdeSKuriakose Kuruvilla #define X86FSET_CX16 19 3627417cfdeSKuriakose Kuruvilla #define X86FSET_CMP 20 3637417cfdeSKuriakose Kuruvilla #define X86FSET_TSCP 21 3647417cfdeSKuriakose Kuruvilla #define X86FSET_MWAIT 22 3657417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4A 23 3667417cfdeSKuriakose Kuruvilla #define X86FSET_CPUID 24 3677417cfdeSKuriakose Kuruvilla #define X86FSET_SSSE3 25 3687417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4_1 26 3697417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4_2 27 3707417cfdeSKuriakose Kuruvilla #define X86FSET_1GPG 28 3717417cfdeSKuriakose Kuruvilla #define X86FSET_CLFSH 29 3727417cfdeSKuriakose Kuruvilla #define X86FSET_64 30 3737417cfdeSKuriakose Kuruvilla #define X86FSET_AES 31 3747417cfdeSKuriakose Kuruvilla #define X86FSET_PCLMULQDQ 32 3757af88ac7SKuriakose Kuruvilla #define X86FSET_XSAVE 33 3767af88ac7SKuriakose Kuruvilla #define X86FSET_AVX 34 377faa20166SBryan Cantrill #define X86FSET_VMX 35 378faa20166SBryan Cantrill #define X86FSET_SVM 36 3797660e73fSHans Rosenfeld #define X86FSET_TOPOEXT 37 380ebb8ac07SRobert Mustacchi #define X86FSET_F16C 38 381ebb8ac07SRobert Mustacchi #define X86FSET_RDRAND 39 3827c478bd9Sstevel@tonic-gate 383247dbb3dSsudheer /* 384247dbb3dSsudheer * flags to patch tsc_read routine. 385247dbb3dSsudheer */ 386247dbb3dSsudheer #define X86_NO_TSC 0x0 387247dbb3dSsudheer #define X86_HAVE_TSCP 0x1 388247dbb3dSsudheer #define X86_TSC_MFENCE 0x2 38915363b27Ssudheer #define X86_TSC_LFENCE 0x4 390247dbb3dSsudheer 3910e751525SEric Saxe /* 3920e751525SEric Saxe * Intel Deep C-State invariant TSC in leaf 0x80000007. 3930e751525SEric Saxe */ 3940e751525SEric Saxe #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 3950e751525SEric Saxe 396cef70d2cSBill Holler /* 397cef70d2cSBill Holler * Intel Deep C-state always-running local APIC timer 398cef70d2cSBill Holler */ 399cef70d2cSBill Holler #define CPUID_CSTATE_ARAT (0x4) 400cef70d2cSBill Holler 401f21ed392Saubrey.li@intel.com /* 402f21ed392Saubrey.li@intel.com * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 403f21ed392Saubrey.li@intel.com */ 404f21ed392Saubrey.li@intel.com #define CPUID_EPB_SUPPORT (1 << 3) 405f21ed392Saubrey.li@intel.com 40641afdfa7SKrishnendu Sadhukhan - Sun Microsystems /* 40741afdfa7SKrishnendu Sadhukhan - Sun Microsystems * Intel TSC deadline timer 40841afdfa7SKrishnendu Sadhukhan - Sun Microsystems */ 40941afdfa7SKrishnendu Sadhukhan - Sun Microsystems #define CPUID_DEADLINE_TSC (1 << 24) 41041afdfa7SKrishnendu Sadhukhan - Sun Microsystems 4117c478bd9Sstevel@tonic-gate /* 4127c478bd9Sstevel@tonic-gate * x86_type is a legacy concept; this is supplanted 4137417cfdeSKuriakose Kuruvilla * for most purposes by x86_featureset; modern CPUs 4147c478bd9Sstevel@tonic-gate * should be X86_TYPE_OTHER 4157c478bd9Sstevel@tonic-gate */ 4167c478bd9Sstevel@tonic-gate #define X86_TYPE_OTHER 0 4177c478bd9Sstevel@tonic-gate #define X86_TYPE_486 1 4187c478bd9Sstevel@tonic-gate #define X86_TYPE_P5 2 4197c478bd9Sstevel@tonic-gate #define X86_TYPE_P6 3 4207c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_486 4 4217c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86L 5 4227c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86 6 4237c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_GXm 7 4247c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86MX 8 4257c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MediaGX 9 4267c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MII 10 4277c478bd9Sstevel@tonic-gate #define X86_TYPE_VIA_CYRIX_III 11 4287c478bd9Sstevel@tonic-gate #define X86_TYPE_P4 12 4297c478bd9Sstevel@tonic-gate 4307c478bd9Sstevel@tonic-gate /* 4317c478bd9Sstevel@tonic-gate * x86_vendor allows us to select between 4327c478bd9Sstevel@tonic-gate * implementation features and helps guide 4337c478bd9Sstevel@tonic-gate * the interpretation of the cpuid instruction. 4347c478bd9Sstevel@tonic-gate */ 435e4b86885SCheng Sean Ye #define X86_VENDOR_Intel 0 436e4b86885SCheng Sean Ye #define X86_VENDORSTR_Intel "GenuineIntel" 437e4b86885SCheng Sean Ye 438e4b86885SCheng Sean Ye #define X86_VENDOR_IntelClone 1 439e4b86885SCheng Sean Ye 440e4b86885SCheng Sean Ye #define X86_VENDOR_AMD 2 441e4b86885SCheng Sean Ye #define X86_VENDORSTR_AMD "AuthenticAMD" 442e4b86885SCheng Sean Ye 443e4b86885SCheng Sean Ye #define X86_VENDOR_Cyrix 3 444e4b86885SCheng Sean Ye #define X86_VENDORSTR_CYRIX "CyrixInstead" 445e4b86885SCheng Sean Ye 446e4b86885SCheng Sean Ye #define X86_VENDOR_UMC 4 447e4b86885SCheng Sean Ye #define X86_VENDORSTR_UMC "UMC UMC UMC " 448e4b86885SCheng Sean Ye 449e4b86885SCheng Sean Ye #define X86_VENDOR_NexGen 5 450e4b86885SCheng Sean Ye #define X86_VENDORSTR_NexGen "NexGenDriven" 451e4b86885SCheng Sean Ye 452e4b86885SCheng Sean Ye #define X86_VENDOR_Centaur 6 453e4b86885SCheng Sean Ye #define X86_VENDORSTR_Centaur "CentaurHauls" 454e4b86885SCheng Sean Ye 455e4b86885SCheng Sean Ye #define X86_VENDOR_Rise 7 456e4b86885SCheng Sean Ye #define X86_VENDORSTR_Rise "RiseRiseRise" 457e4b86885SCheng Sean Ye 458e4b86885SCheng Sean Ye #define X86_VENDOR_SiS 8 459e4b86885SCheng Sean Ye #define X86_VENDORSTR_SiS "SiS SiS SiS " 460e4b86885SCheng Sean Ye 461e4b86885SCheng Sean Ye #define X86_VENDOR_TM 9 462e4b86885SCheng Sean Ye #define X86_VENDORSTR_TM "GenuineTMx86" 463e4b86885SCheng Sean Ye 464e4b86885SCheng Sean Ye #define X86_VENDOR_NSC 10 465e4b86885SCheng Sean Ye #define X86_VENDORSTR_NSC "Geode by NSC" 466e4b86885SCheng Sean Ye 467e4b86885SCheng Sean Ye /* 468e4b86885SCheng Sean Ye * Vendor string max len + \0 469e4b86885SCheng Sean Ye */ 470e4b86885SCheng Sean Ye #define X86_VENDOR_STRLEN 13 4717aec1d6eScindi 4728a40a695Sgavinm /* 4738a40a695Sgavinm * Some vendor/family/model/stepping ranges are commonly grouped under 4748a40a695Sgavinm * a single identifying banner by the vendor. The following encode 4758a40a695Sgavinm * that "revision" in a uint32_t with the 8 most significant bits 4768a40a695Sgavinm * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 4778a40a695Sgavinm * family, and the remaining 16 typically forming a bitmask of revisions 4788a40a695Sgavinm * within that family with more significant bits indicating "later" revisions. 4798a40a695Sgavinm */ 4808a40a695Sgavinm 4818a40a695Sgavinm #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 4828a40a695Sgavinm #define _X86_CHIPREV_VENDOR_SHIFT 24 4838a40a695Sgavinm #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 4848a40a695Sgavinm #define _X86_CHIPREV_FAMILY_SHIFT 16 4858a40a695Sgavinm #define _X86_CHIPREV_REV_MASK 0x0000ffffu 4868a40a695Sgavinm 4878a40a695Sgavinm #define _X86_CHIPREV_VENDOR(x) \ 4888a40a695Sgavinm (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 4898a40a695Sgavinm #define _X86_CHIPREV_FAMILY(x) \ 4908a40a695Sgavinm (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 4918a40a695Sgavinm #define _X86_CHIPREV_REV(x) \ 4928a40a695Sgavinm ((x) & _X86_CHIPREV_REV_MASK) 4938a40a695Sgavinm 4948a40a695Sgavinm /* True if x matches in vendor and family and if x matches the given rev mask */ 4958a40a695Sgavinm #define X86_CHIPREV_MATCH(x, mask) \ 4968a40a695Sgavinm (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 4978a40a695Sgavinm _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 4988a40a695Sgavinm ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 4998a40a695Sgavinm 5002c8230b0SSrihari Venkatesan /* True if x matches in vendor and family, and rev is at least minx */ 5018a40a695Sgavinm #define X86_CHIPREV_ATLEAST(x, minx) \ 5028a40a695Sgavinm (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 5038a40a695Sgavinm _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 5048a40a695Sgavinm _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 5058a40a695Sgavinm 5068a40a695Sgavinm #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 5078a40a695Sgavinm ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 5088a40a695Sgavinm (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 5098a40a695Sgavinm 5102c8230b0SSrihari Venkatesan /* True if x matches in vendor, and family is at least minx */ 5112c8230b0SSrihari Venkatesan #define X86_CHIPFAM_ATLEAST(x, minx) \ 5122c8230b0SSrihari Venkatesan (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 5132c8230b0SSrihari Venkatesan _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 5142c8230b0SSrihari Venkatesan 5158a40a695Sgavinm /* Revision default */ 5168a40a695Sgavinm #define X86_CHIPREV_UNKNOWN 0x0 5178a40a695Sgavinm 5188a40a695Sgavinm /* 51920c794b3Sgavinm * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 52020c794b3Sgavinm * sufficiently different that we will distinguish them; in all other 5218a40a695Sgavinm * case we will identify the major revision. 5228a40a695Sgavinm */ 5238a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 5248a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 5258a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 5268a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 5278a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 5288a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 5298a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 53020c794b3Sgavinm 53120c794b3Sgavinm /* 53220c794b3Sgavinm * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 53320c794b3Sgavinm */ 53420c794b3Sgavinm #define X86_CHIPREV_AMD_10_REV_A \ 53531725658Sksadhukh _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 53620c794b3Sgavinm #define X86_CHIPREV_AMD_10_REV_B \ 53720c794b3Sgavinm _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 53879321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_C2 \ 53964452efdSKit Chow _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 54079321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_C3 \ 54189e921d5SKuriakose Kuruvilla _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 54279321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_D0 \ 54379321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 54479321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_D1 \ 54579321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 54679321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_E \ 54779321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 54889e921d5SKuriakose Kuruvilla 54989e921d5SKuriakose Kuruvilla /* 55089e921d5SKuriakose Kuruvilla * Definitions for AMD Family 0x11. 55189e921d5SKuriakose Kuruvilla */ 55279321794SJens Elkner #define X86_CHIPREV_AMD_11_REV_B \ 55379321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 55489e921d5SKuriakose Kuruvilla 55579321794SJens Elkner /* 55679321794SJens Elkner * Definitions for AMD Family 0x12. 55779321794SJens Elkner */ 55879321794SJens Elkner #define X86_CHIPREV_AMD_12_REV_B \ 55979321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 56079321794SJens Elkner 56179321794SJens Elkner /* 56279321794SJens Elkner * Definitions for AMD Family 0x14. 56379321794SJens Elkner */ 56479321794SJens Elkner #define X86_CHIPREV_AMD_14_REV_B \ 56579321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 56679321794SJens Elkner #define X86_CHIPREV_AMD_14_REV_C \ 56779321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 56879321794SJens Elkner 56979321794SJens Elkner /* 57079321794SJens Elkner * Definitions for AMD Family 0x15 57179321794SJens Elkner */ 57279321794SJens Elkner #define X86_CHIPREV_AMD_15OR_REV_B2 \ 57379321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 57479321794SJens Elkner 57579321794SJens Elkner #define X86_CHIPREV_AMD_15TN_REV_A1 \ 57679321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 5778a40a695Sgavinm 5788a40a695Sgavinm /* 5798a40a695Sgavinm * Various socket/package types, extended as the need to distinguish 5808a40a695Sgavinm * a new type arises. The top 8 byte identfies the vendor and the 5818a40a695Sgavinm * remaining 24 bits describe 24 socket types. 5828a40a695Sgavinm */ 5838a40a695Sgavinm 5848a40a695Sgavinm #define _X86_SOCKET_VENDOR_SHIFT 24 5858a40a695Sgavinm #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 5868a40a695Sgavinm #define _X86_SOCKET_TYPE_MASK 0x00ffffff 5878a40a695Sgavinm #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 5888a40a695Sgavinm 5898a40a695Sgavinm #define _X86_SOCKET_MKVAL(vendor, bitval) \ 5908a40a695Sgavinm ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 5918a40a695Sgavinm 5928a40a695Sgavinm #define X86_SOCKET_MATCH(s, mask) \ 5938a40a695Sgavinm (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 594a24e89c4SKuriakose Kuruvilla (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 5958a40a695Sgavinm 5968a40a695Sgavinm #define X86_SOCKET_UNKNOWN 0x0 5978a40a695Sgavinm /* 5988a40a695Sgavinm * AMD socket types 5998a40a695Sgavinm */ 6008a40a695Sgavinm #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 6018a40a695Sgavinm #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 6028a40a695Sgavinm #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 6038a40a695Sgavinm #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 6048a40a695Sgavinm #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 6058a40a695Sgavinm #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 606a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 607a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 608a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 609a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 610a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 611a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 612bd15239eSSrihari Venkatesan #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 613bd15239eSSrihari Venkatesan #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 61479321794SJens Elkner #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 61579321794SJens Elkner #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 61679321794SJens Elkner #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 61779321794SJens Elkner #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 61879321794SJens Elkner #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 61979321794SJens Elkner #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 62079321794SJens Elkner #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 62179321794SJens Elkner #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 6228a40a695Sgavinm 6237af88ac7SKuriakose Kuruvilla /* 6247af88ac7SKuriakose Kuruvilla * xgetbv/xsetbv support 6257af88ac7SKuriakose Kuruvilla */ 6267af88ac7SKuriakose Kuruvilla 6277af88ac7SKuriakose Kuruvilla #define XFEATURE_ENABLED_MASK 0x0 6287af88ac7SKuriakose Kuruvilla /* 6297af88ac7SKuriakose Kuruvilla * XFEATURE_ENABLED_MASK values (eax) 6307af88ac7SKuriakose Kuruvilla */ 6317af88ac7SKuriakose Kuruvilla #define XFEATURE_LEGACY_FP 0x1 6327af88ac7SKuriakose Kuruvilla #define XFEATURE_SSE 0x2 6337af88ac7SKuriakose Kuruvilla #define XFEATURE_AVX 0x4 6347af88ac7SKuriakose Kuruvilla #define XFEATURE_MAX XFEATURE_AVX 635ebb8ac07SRobert Mustacchi #define XFEATURE_FP_ALL \ 636ebb8ac07SRobert Mustacchi (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX) 6377af88ac7SKuriakose Kuruvilla 6387c478bd9Sstevel@tonic-gate #if !defined(_ASM) 6397c478bd9Sstevel@tonic-gate 6407c478bd9Sstevel@tonic-gate #if defined(_KERNEL) || defined(_KMEMUSER) 6417c478bd9Sstevel@tonic-gate 642ebb8ac07SRobert Mustacchi #define NUM_X86_FEATURES 40 643dfea898aSKuriakose Kuruvilla extern uchar_t x86_featureset[]; 6447417cfdeSKuriakose Kuruvilla 6457417cfdeSKuriakose Kuruvilla extern void free_x86_featureset(void *featureset); 6467417cfdeSKuriakose Kuruvilla extern boolean_t is_x86_feature(void *featureset, uint_t feature); 6477417cfdeSKuriakose Kuruvilla extern void add_x86_feature(void *featureset, uint_t feature); 6487417cfdeSKuriakose Kuruvilla extern void remove_x86_feature(void *featureset, uint_t feature); 6497417cfdeSKuriakose Kuruvilla extern boolean_t compare_x86_featureset(void *setA, void *setB); 6507417cfdeSKuriakose Kuruvilla extern void print_x86_featureset(void *featureset); 6517417cfdeSKuriakose Kuruvilla 6527417cfdeSKuriakose Kuruvilla 6537c478bd9Sstevel@tonic-gate extern uint_t x86_type; 6547c478bd9Sstevel@tonic-gate extern uint_t x86_vendor; 65586c1f4dcSVikram Hegde extern uint_t x86_clflush_size; 6567c478bd9Sstevel@tonic-gate 6577c478bd9Sstevel@tonic-gate extern uint_t pentiumpro_bug4046376; 6587c478bd9Sstevel@tonic-gate extern uint_t pentiumpro_bug4064495; 6597c478bd9Sstevel@tonic-gate 6607c478bd9Sstevel@tonic-gate extern uint_t enable486; 6617c478bd9Sstevel@tonic-gate 6627c478bd9Sstevel@tonic-gate extern const char CyrixInstead[]; 6637c478bd9Sstevel@tonic-gate 6647c478bd9Sstevel@tonic-gate #endif 6657c478bd9Sstevel@tonic-gate 6667c478bd9Sstevel@tonic-gate #if defined(_KERNEL) 6677c478bd9Sstevel@tonic-gate 6688949bcd6Sandrei /* 6698949bcd6Sandrei * This structure is used to pass arguments and get return values back 6708949bcd6Sandrei * from the CPUID instruction in __cpuid_insn() routine. 6718949bcd6Sandrei */ 6728949bcd6Sandrei struct cpuid_regs { 6738949bcd6Sandrei uint32_t cp_eax; 6748949bcd6Sandrei uint32_t cp_ebx; 6758949bcd6Sandrei uint32_t cp_ecx; 6768949bcd6Sandrei uint32_t cp_edx; 6778949bcd6Sandrei }; 6787c478bd9Sstevel@tonic-gate 6797af88ac7SKuriakose Kuruvilla /* 6807af88ac7SKuriakose Kuruvilla * Utility functions to get/set extended control registers (XCR) 6817af88ac7SKuriakose Kuruvilla * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 6827af88ac7SKuriakose Kuruvilla */ 6837af88ac7SKuriakose Kuruvilla extern uint64_t get_xcr(uint_t); 6847af88ac7SKuriakose Kuruvilla extern void set_xcr(uint_t, uint64_t); 6857af88ac7SKuriakose Kuruvilla 6860ac7d7d8Skucharsk extern uint64_t rdmsr(uint_t); 6870ac7d7d8Skucharsk extern void wrmsr(uint_t, const uint64_t); 688ee88d2b9Skchow extern uint64_t xrdmsr(uint_t); 689ee88d2b9Skchow extern void xwrmsr(uint_t, const uint64_t); 690ae115bc7Smrj extern int checked_rdmsr(uint_t, uint64_t *); 691ae115bc7Smrj extern int checked_wrmsr(uint_t, uint64_t); 692ae115bc7Smrj 6937c478bd9Sstevel@tonic-gate extern void invalidate_cache(void); 6947c478bd9Sstevel@tonic-gate extern ulong_t getcr4(void); 6957c478bd9Sstevel@tonic-gate extern void setcr4(ulong_t); 696ae115bc7Smrj 6977c478bd9Sstevel@tonic-gate extern void mtrr_sync(void); 6987c478bd9Sstevel@tonic-gate 6997c478bd9Sstevel@tonic-gate extern void cpu_fast_syscall_enable(void *); 7007c478bd9Sstevel@tonic-gate extern void cpu_fast_syscall_disable(void *); 7017c478bd9Sstevel@tonic-gate 7027c478bd9Sstevel@tonic-gate struct cpu; 7037c478bd9Sstevel@tonic-gate 7047c478bd9Sstevel@tonic-gate extern int cpuid_checkpass(struct cpu *, int); 7058949bcd6Sandrei extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 7068949bcd6Sandrei extern uint32_t __cpuid_insn(struct cpuid_regs *); 7077c478bd9Sstevel@tonic-gate extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 7087c478bd9Sstevel@tonic-gate extern int cpuid_getidstr(struct cpu *, char *, size_t); 7097c478bd9Sstevel@tonic-gate extern const char *cpuid_getvendorstr(struct cpu *); 7107c478bd9Sstevel@tonic-gate extern uint_t cpuid_getvendor(struct cpu *); 7117c478bd9Sstevel@tonic-gate extern uint_t cpuid_getfamily(struct cpu *); 7127c478bd9Sstevel@tonic-gate extern uint_t cpuid_getmodel(struct cpu *); 7137c478bd9Sstevel@tonic-gate extern uint_t cpuid_getstep(struct cpu *); 7142449e17fSsherrym extern uint_t cpuid_getsig(struct cpu *); 7157c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 7168949bcd6Sandrei extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 717d129bde2Sesaxe extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 718d129bde2Sesaxe extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 719fb2f18f8Sesaxe extern int cpuid_get_chipid(struct cpu *); 720fb2f18f8Sesaxe extern id_t cpuid_get_coreid(struct cpu *); 72110569901Sgavinm extern int cpuid_get_pkgcoreid(struct cpu *); 722fb2f18f8Sesaxe extern int cpuid_get_clogid(struct cpu *); 723b885580bSAlexander Kolbasov extern int cpuid_get_cacheid(struct cpu *); 724fa96bd91SMichael Corcoran extern uint32_t cpuid_get_apicid(struct cpu *); 7258031591dSSrihari Venkatesan extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 7268031591dSSrihari Venkatesan extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 7277660e73fSHans Rosenfeld extern uint_t cpuid_get_compunitid(struct cpu *cpu); 7287660e73fSHans Rosenfeld extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 7298949bcd6Sandrei extern int cpuid_is_cmt(struct cpu *); 7307c478bd9Sstevel@tonic-gate extern int cpuid_syscall32_insn(struct cpu *); 7317c478bd9Sstevel@tonic-gate extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 7328a40a695Sgavinm 7338a40a695Sgavinm extern uint32_t cpuid_getchiprev(struct cpu *); 7348a40a695Sgavinm extern const char *cpuid_getchiprevstr(struct cpu *); 7358a40a695Sgavinm extern uint32_t cpuid_getsockettype(struct cpu *); 73689e921d5SKuriakose Kuruvilla extern const char *cpuid_getsocketstr(struct cpu *); 7377c478bd9Sstevel@tonic-gate 7382ef50f01SJoe Bonasera extern int cpuid_have_cr8access(struct cpu *); 7392ef50f01SJoe Bonasera 7407c478bd9Sstevel@tonic-gate extern int cpuid_opteron_erratum(struct cpu *, uint_t); 7417c478bd9Sstevel@tonic-gate 7427c478bd9Sstevel@tonic-gate struct cpuid_info; 7437c478bd9Sstevel@tonic-gate 7447c478bd9Sstevel@tonic-gate extern void setx86isalist(void); 745ae115bc7Smrj extern void cpuid_alloc_space(struct cpu *); 746ae115bc7Smrj extern void cpuid_free_space(struct cpu *); 747dfea898aSKuriakose Kuruvilla extern void cpuid_pass1(struct cpu *, uchar_t *); 7487c478bd9Sstevel@tonic-gate extern void cpuid_pass2(struct cpu *); 7497c478bd9Sstevel@tonic-gate extern void cpuid_pass3(struct cpu *); 750ebb8ac07SRobert Mustacchi extern void cpuid_pass4(struct cpu *, uint_t *); 751fa96bd91SMichael Corcoran extern void cpuid_set_cpu_properties(void *, processorid_t, 752fa96bd91SMichael Corcoran struct cpuid_info *); 7537c478bd9Sstevel@tonic-gate 7547c478bd9Sstevel@tonic-gate extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 7557c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 756843e1988Sjohnlev 757843e1988Sjohnlev #if !defined(__xpv) 7585b8a6efeSbholler extern uint32_t *cpuid_mwait_alloc(struct cpu *); 7595b8a6efeSbholler extern void cpuid_mwait_free(struct cpu *); 7600e751525SEric Saxe extern int cpuid_deep_cstates_supported(void); 761cef70d2cSBill Holler extern int cpuid_arat_supported(void); 762f21ed392Saubrey.li@intel.com extern int cpuid_iepb_supported(struct cpu *); 76341afdfa7SKrishnendu Sadhukhan - Sun Microsystems extern int cpuid_deadline_tsc_supported(void); 764*79ec9da8SYuri Pankov extern void vmware_port(int, uint32_t *); 765843e1988Sjohnlev #endif 7667c478bd9Sstevel@tonic-gate 7672449e17fSsherrym struct cpu_ucode_info; 7682449e17fSsherrym 7692449e17fSsherrym extern void ucode_alloc_space(struct cpu *); 7702449e17fSsherrym extern void ucode_free_space(struct cpu *); 7712449e17fSsherrym extern void ucode_check(struct cpu *); 772adc586deSMark Johnson extern void ucode_cleanup(); 7732449e17fSsherrym 774247dbb3dSsudheer #if !defined(__xpv) 775247dbb3dSsudheer extern char _tsc_mfence_start; 776247dbb3dSsudheer extern char _tsc_mfence_end; 777247dbb3dSsudheer extern char _tscp_start; 778247dbb3dSsudheer extern char _tscp_end; 779247dbb3dSsudheer extern char _no_rdtsc_start; 780247dbb3dSsudheer extern char _no_rdtsc_end; 78115363b27Ssudheer extern char _tsc_lfence_start; 78215363b27Ssudheer extern char _tsc_lfence_end; 783247dbb3dSsudheer #endif 784247dbb3dSsudheer 78522cc0e45SBill Holler #if !defined(__xpv) 78622cc0e45SBill Holler extern char bcopy_patch_start; 78722cc0e45SBill Holler extern char bcopy_patch_end; 78822cc0e45SBill Holler extern char bcopy_ck_size; 78922cc0e45SBill Holler #endif 79022cc0e45SBill Holler 791e774b42bSBill Holler extern void post_startup_cpu_fixups(void); 792e774b42bSBill Holler 7937c478bd9Sstevel@tonic-gate extern uint_t workaround_errata(struct cpu *); 7947c478bd9Sstevel@tonic-gate 7957c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 7967c478bd9Sstevel@tonic-gate extern int opteron_erratum_93; 7977c478bd9Sstevel@tonic-gate #endif 7987c478bd9Sstevel@tonic-gate 7997c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 8007c478bd9Sstevel@tonic-gate extern int opteron_erratum_91; 8017c478bd9Sstevel@tonic-gate #endif 8027c478bd9Sstevel@tonic-gate 8037c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 8047c478bd9Sstevel@tonic-gate extern int opteron_erratum_100; 8057c478bd9Sstevel@tonic-gate #endif 8067c478bd9Sstevel@tonic-gate 8077c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 8087c478bd9Sstevel@tonic-gate extern int opteron_erratum_121; 8097c478bd9Sstevel@tonic-gate #endif 8107c478bd9Sstevel@tonic-gate 811ee88d2b9Skchow #if defined(OPTERON_WORKAROUND_6323525) 812ee88d2b9Skchow extern int opteron_workaround_6323525; 813ee88d2b9Skchow extern void patch_workaround_6323525(void); 814ee88d2b9Skchow #endif 815ee88d2b9Skchow 816cfe84b82SMatt Amdur #if !defined(__xpv) 817cfe84b82SMatt Amdur extern void determine_platform(void); 818cfe84b82SMatt Amdur #endif 819b9bfdccdSStuart Maybee extern int get_hwenv(void); 820b9bfdccdSStuart Maybee extern int is_controldom(void); 821b9bfdccdSStuart Maybee 8227af88ac7SKuriakose Kuruvilla extern void xsave_setup_msr(struct cpu *); 8237af88ac7SKuriakose Kuruvilla 824*79ec9da8SYuri Pankov /* 825*79ec9da8SYuri Pankov * Hypervisor signatures 826*79ec9da8SYuri Pankov */ 827*79ec9da8SYuri Pankov #define HVSIG_XEN_HVM "XenVMMXenVMM" 828*79ec9da8SYuri Pankov #define HVSIG_VMWARE "VMwareVMware" 829*79ec9da8SYuri Pankov #define HVSIG_KVM "KVMKVMKVM" 830*79ec9da8SYuri Pankov #define HVSIG_MICROSOFT "Microsoft Hv" 831*79ec9da8SYuri Pankov 832b9bfdccdSStuart Maybee /* 833b9bfdccdSStuart Maybee * Defined hardware environments 834b9bfdccdSStuart Maybee */ 835*79ec9da8SYuri Pankov #define HW_NATIVE (1 << 0) /* Running on bare metal */ 836*79ec9da8SYuri Pankov #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 837*79ec9da8SYuri Pankov 838*79ec9da8SYuri Pankov #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 839*79ec9da8SYuri Pankov #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 840*79ec9da8SYuri Pankov #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 841*79ec9da8SYuri Pankov #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 842*79ec9da8SYuri Pankov 843*79ec9da8SYuri Pankov #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT) 844b9bfdccdSStuart Maybee 8457c478bd9Sstevel@tonic-gate #endif /* _KERNEL */ 8467c478bd9Sstevel@tonic-gate 847*79ec9da8SYuri Pankov #endif /* !_ASM */ 848*79ec9da8SYuri Pankov 849*79ec9da8SYuri Pankov /* 850*79ec9da8SYuri Pankov * VMware hypervisor related defines 851*79ec9da8SYuri Pankov */ 852*79ec9da8SYuri Pankov #define VMWARE_HVMAGIC 0x564d5868 853*79ec9da8SYuri Pankov #define VMWARE_HVPORT 0x5658 854*79ec9da8SYuri Pankov #define VMWARE_HVCMD_GETVERSION 0x0a 855*79ec9da8SYuri Pankov #define VMWARE_HVCMD_GETTSCFREQ 0x2d 8567c478bd9Sstevel@tonic-gate 8577c478bd9Sstevel@tonic-gate #ifdef __cplusplus 8587c478bd9Sstevel@tonic-gate } 8597c478bd9Sstevel@tonic-gate #endif 8607c478bd9Sstevel@tonic-gate 8617c478bd9Sstevel@tonic-gate #endif /* _SYS_X86_ARCHEXT_H */ 862