17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5ee88d2b9Skchow * Common Development and Distribution License (the "License"). 6ee88d2b9Skchow * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 227417cfdeSKuriakose Kuruvilla * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23cfe84b82SMatt Amdur * Copyright (c) 2011 by Delphix. All rights reserved. 247c478bd9Sstevel@tonic-gate */ 25cef70d2cSBill Holler /* 2641afdfa7SKrishnendu Sadhukhan - Sun Microsystems * Copyright (c) 2010, Intel Corporation. 27cef70d2cSBill Holler * All rights reserved. 28cef70d2cSBill Holler */ 29faa20166SBryan Cantrill /* 301d9a8ab8SJohn Levon * Copyright 2018 Joyent, Inc. 3179321794SJens Elkner * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 3279321794SJens Elkner * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 336eedf6a5SJosef 'Jeff' Sipek * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34b13f152eSYuri Pankov * Copyright 2018 Nexenta Systems, Inc. 35faa20166SBryan Cantrill */ 367c478bd9Sstevel@tonic-gate 377c478bd9Sstevel@tonic-gate #ifndef _SYS_X86_ARCHEXT_H 387c478bd9Sstevel@tonic-gate #define _SYS_X86_ARCHEXT_H 397c478bd9Sstevel@tonic-gate 407c478bd9Sstevel@tonic-gate #if !defined(_ASM) 417c478bd9Sstevel@tonic-gate #include <sys/regset.h> 427c478bd9Sstevel@tonic-gate #include <sys/processor.h> 437c478bd9Sstevel@tonic-gate #include <vm/seg_enum.h> 447c478bd9Sstevel@tonic-gate #include <vm/page.h> 457c478bd9Sstevel@tonic-gate #endif /* _ASM */ 467c478bd9Sstevel@tonic-gate 477c478bd9Sstevel@tonic-gate #ifdef __cplusplus 487c478bd9Sstevel@tonic-gate extern "C" { 497c478bd9Sstevel@tonic-gate #endif 507c478bd9Sstevel@tonic-gate 517c478bd9Sstevel@tonic-gate /* 527c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (standard function 1) 537c478bd9Sstevel@tonic-gate */ 547c478bd9Sstevel@tonic-gate 557c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 567c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 577c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 587c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 597c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 607c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 617c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 627c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 637c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 647c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 657c478bd9Sstevel@tonic-gate /* 0x400 - reserved */ 667c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 677c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 687c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 697c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 707c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 717c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 727c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 737c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 747c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 757c478bd9Sstevel@tonic-gate /* 0x100000 - reserved */ 767c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 777c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 787c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 797c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 807c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 817c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 827c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 837c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 847c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85ae115bc7Smrj #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 867c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 877c478bd9Sstevel@tonic-gate 887c478bd9Sstevel@tonic-gate /* 897c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %ecx (standard function 1) 907c478bd9Sstevel@tonic-gate */ 917c478bd9Sstevel@tonic-gate 927c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 93*58b49504SHans Rosenfeld #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 941d9a8ab8SJohn Levon #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 957c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 967c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 97ae115bc7Smrj #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 98ae115bc7Smrj #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 997c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 1007c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 101ae115bc7Smrj #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 1027c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 1037c478bd9Sstevel@tonic-gate /* 0x00000800 - reserved */ 104245ac945SRobert Mustacchi #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 105ae115bc7Smrj #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 106ae115bc7Smrj #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 1071d9a8ab8SJohn Levon #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 108ae115bc7Smrj /* 0x00010000 - reserved */ 1091d9a8ab8SJohn Levon #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 110ae115bc7Smrj #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 111d0f8ff6eSkk #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 112d0f8ff6eSkk #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 1136eedf6a5SJosef 'Jeff' Sipek #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 1145087e485SKrishnendu Sadhukhan - Sun Microsystems #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 115f8801251Skk #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 1161d9a8ab8SJohn Levon #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 117a50a8b93SKuriakose Kuruvilla #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 1187af88ac7SKuriakose Kuruvilla #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 1197af88ac7SKuriakose Kuruvilla #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 1207af88ac7SKuriakose Kuruvilla #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 121ebb8ac07SRobert Mustacchi #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 122ebb8ac07SRobert Mustacchi #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 12379ec9da8SYuri Pankov #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 124ae115bc7Smrj 1257c478bd9Sstevel@tonic-gate /* 1267c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (extended function 0x80000001) 1277c478bd9Sstevel@tonic-gate */ 1287c478bd9Sstevel@tonic-gate 1297c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 1307c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 1317c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 1327c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 1337c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 1347c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 1357c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 1367c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 1377c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 1387c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 1397c478bd9Sstevel@tonic-gate /* 0x00000400 - sysc on K6m6 */ 1407c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 1417c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 1427c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 1437c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 1447c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 145ae115bc7Smrj #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 146ae115bc7Smrj #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 1477c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 1487c478bd9Sstevel@tonic-gate /* 0x00040000 - reserved */ 1497c478bd9Sstevel@tonic-gate /* 0x00080000 - reserved */ 1507c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 1517c478bd9Sstevel@tonic-gate /* 0x00200000 - reserved */ 1527c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 1537c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 1547c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 155ae115bc7Smrj #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 15602bc52beSkchow #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 157ae115bc7Smrj #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 1587c478bd9Sstevel@tonic-gate /* 0x10000000 - reserved */ 1597c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 1607c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 1617c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 1627c478bd9Sstevel@tonic-gate 163ae115bc7Smrj #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 164ae115bc7Smrj #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 165ae115bc7Smrj #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 166ae115bc7Smrj #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 167ae115bc7Smrj #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 168f8801251Skk #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 169f8801251Skk #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 170512cf780Skchow #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 171512cf780Skchow #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 172512cf780Skchow #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 173512cf780Skchow #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 1741d9a8ab8SJohn Levon #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */ 175512cf780Skchow #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 176512cf780Skchow #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 1771d9a8ab8SJohn Levon /* 0x00004000 - reserved */ 1781d9a8ab8SJohn Levon #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 1791d9a8ab8SJohn Levon #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 1801d9a8ab8SJohn Levon /* 0x00020000 - reserved */ 1811d9a8ab8SJohn Levon /* 0x00040000 - reserved */ 1821d9a8ab8SJohn Levon #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 1831d9a8ab8SJohn Levon /* 0x00100000 - reserved */ 1841d9a8ab8SJohn Levon #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 1857660e73fSHans Rosenfeld #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 1867c478bd9Sstevel@tonic-gate 187088d69f8SJerry Jelinek /* 188088d69f8SJerry Jelinek * AMD uses %ebx for some of their features (extended function 0x80000008). 189088d69f8SJerry Jelinek */ 19001add34aSRobert Mustacchi #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 19101add34aSRobert Mustacchi #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 19201add34aSRobert Mustacchi #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 19301add34aSRobert Mustacchi #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 19401add34aSRobert Mustacchi #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 19501add34aSRobert Mustacchi #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 19601add34aSRobert Mustacchi #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 19701add34aSRobert Mustacchi #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 19801add34aSRobert Mustacchi #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 19901add34aSRobert Mustacchi #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 200088d69f8SJerry Jelinek 201ae115bc7Smrj /* 202ae115bc7Smrj * Intel now seems to have claimed part of the "extended" function 203ae115bc7Smrj * space that we previously for non-Intel implementors to use. 204ae115bc7Smrj * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 205ae115bc7Smrj * is available in long mode i.e. what AMD indicate using bit 0. 206ae115bc7Smrj * On the other hand, everything else is labelled as reserved. 207ae115bc7Smrj */ 208ae115bc7Smrj #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 209ae115bc7Smrj 210245ac945SRobert Mustacchi /* 211245ac945SRobert Mustacchi * Intel also uses cpuid leaf 7 to have additional instructions and features. 212799823bbSRobert Mustacchi * Like some other leaves, but unlike the current ones we care about, it 213245ac945SRobert Mustacchi * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 214245ac945SRobert Mustacchi * with the potential use of additional sub-leaves in the future, we now 215245ac945SRobert Mustacchi * specifically label the EBX features with their leaf and sub-leaf. 216245ac945SRobert Mustacchi */ 217245ac945SRobert Mustacchi #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 218088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 219245ac945SRobert Mustacchi #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 220799823bbSRobert Mustacchi #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 2218889c875SRobert Mustacchi #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 22274ecdb51SJohn Levon #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 223088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 224088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 225088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 2268889c875SRobert Mustacchi #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 2278889c875SRobert Mustacchi #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 2283ce2fcdcSRobert Mustacchi #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 229088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 230088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 231088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 232088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 233088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 234088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 235088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 236088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 237088d69f8SJerry Jelinek 238088d69f8SJerry Jelinek #define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 239088d69f8SJerry Jelinek (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 240088d69f8SJerry Jelinek CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 241088d69f8SJerry Jelinek CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 242088d69f8SJerry Jelinek CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 243088d69f8SJerry Jelinek 244088d69f8SJerry Jelinek #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 245088d69f8SJerry Jelinek #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 246088d69f8SJerry Jelinek #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 247088d69f8SJerry Jelinek #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 248088d69f8SJerry Jelinek #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 249088d69f8SJerry Jelinek 250088d69f8SJerry Jelinek #define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 251088d69f8SJerry Jelinek (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 252088d69f8SJerry Jelinek 253088d69f8SJerry Jelinek #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 254088d69f8SJerry Jelinek #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 25501add34aSRobert Mustacchi #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 25601add34aSRobert Mustacchi #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 25701add34aSRobert Mustacchi #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 25801add34aSRobert Mustacchi #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 259088d69f8SJerry Jelinek 260088d69f8SJerry Jelinek #define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 261088d69f8SJerry Jelinek (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS) 262088d69f8SJerry Jelinek 263088d69f8SJerry Jelinek /* 264088d69f8SJerry Jelinek * Intel also uses cpuid leaf 0xd to report additional instructions and features 265088d69f8SJerry Jelinek * when the sub-leaf in %ecx == 1. We label these using the same convention as 266088d69f8SJerry Jelinek * with leaf 7. 267088d69f8SJerry Jelinek */ 268088d69f8SJerry Jelinek #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 269088d69f8SJerry Jelinek #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 270088d69f8SJerry Jelinek #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 2717c478bd9Sstevel@tonic-gate 272b13f152eSYuri Pankov #define REG_PAT 0x277 2737c478bd9Sstevel@tonic-gate #define REG_TSC 0x10 /* timestamp counter */ 2747c478bd9Sstevel@tonic-gate #define REG_APIC_BASE_MSR 0x1b 275b6917abeSmishra #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 2767c478bd9Sstevel@tonic-gate 277e774b42bSBill Holler #if !defined(__xpv) 278e774b42bSBill Holler /* 279e774b42bSBill Holler * AMD C1E 280e774b42bSBill Holler */ 281e774b42bSBill Holler #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 282e774b42bSBill Holler #define AMD_ACTONCMPHALT_SHIFT 27 283e774b42bSBill Holler #define AMD_ACTONCMPHALT_MASK 3 284e774b42bSBill Holler #endif 285e774b42bSBill Holler 2867c478bd9Sstevel@tonic-gate #define MSR_DEBUGCTL 0x1d9 2877c478bd9Sstevel@tonic-gate 2887c478bd9Sstevel@tonic-gate #define DEBUGCTL_LBR 0x01 2897c478bd9Sstevel@tonic-gate #define DEBUGCTL_BTF 0x02 2907c478bd9Sstevel@tonic-gate 2917c478bd9Sstevel@tonic-gate /* Intel P6, AMD */ 2927c478bd9Sstevel@tonic-gate #define MSR_LBR_FROM 0x1db 2937c478bd9Sstevel@tonic-gate #define MSR_LBR_TO 0x1dc 2947c478bd9Sstevel@tonic-gate #define MSR_LEX_FROM 0x1dd 2957c478bd9Sstevel@tonic-gate #define MSR_LEX_TO 0x1de 2967c478bd9Sstevel@tonic-gate 2977c478bd9Sstevel@tonic-gate /* Intel P4 (pre-Prescott, non P4 M) */ 2987c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_TOS 0x1da 2997c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_0 0x1db 3007c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_1 0x1dc 3017c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_2 0x1dd 3027c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_3 0x1de 3037c478bd9Sstevel@tonic-gate 3047c478bd9Sstevel@tonic-gate /* Intel Pentium M */ 3057c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_TOS 0x1c9 3067c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_0 0x040 3077c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_1 0x041 3087c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_2 0x042 3097c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_3 0x043 3107c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_4 0x044 3117c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_5 0x045 3127c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_6 0x046 3137c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_7 0x047 3147c478bd9Sstevel@tonic-gate 3157c478bd9Sstevel@tonic-gate /* Intel P4 (Prescott) */ 3167c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TOS 0x1da 3177c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_0 0x680 3187c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_1 0x681 3197c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_2 0x682 3207c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_3 0x683 3217c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_4 0x684 3227c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_5 0x685 3237c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_6 0x686 3247c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_7 0x687 325*58b49504SHans Rosenfeld #define MSR_PRP4_LBSTK_FROM_8 0x688 3267c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_9 0x689 3277c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_10 0x68a 328*58b49504SHans Rosenfeld #define MSR_PRP4_LBSTK_FROM_11 0x68b 3297c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_12 0x68c 3307c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_13 0x68d 3317c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_14 0x68e 3327c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_15 0x68f 3337c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_0 0x6c0 3347c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_1 0x6c1 3357c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_2 0x6c2 3367c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_3 0x6c3 3377c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_4 0x6c4 3387c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_5 0x6c5 3397c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_6 0x6c6 3407c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_7 0x6c7 3417c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_8 0x6c8 342*58b49504SHans Rosenfeld #define MSR_PRP4_LBSTK_TO_9 0x6c9 3437c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_10 0x6ca 3447c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_11 0x6cb 3457c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_12 0x6cc 3467c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_13 0x6cd 3477c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_14 0x6ce 3487c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_15 0x6cf 3497c478bd9Sstevel@tonic-gate 35001add34aSRobert Mustacchi /* 35101add34aSRobert Mustacchi * Intel IA32_ARCH_CAPABILITIES MSR. 35201add34aSRobert Mustacchi */ 35301add34aSRobert Mustacchi #define MSR_IA32_ARCH_CAPABILITIES 0x10a 35401add34aSRobert Mustacchi #define IA32_ARCH_CAP_RDCL_NO 0x0001 35501add34aSRobert Mustacchi #define IA32_ARCH_CAP_IBRS_ALL 0x0002 35601add34aSRobert Mustacchi #define IA32_ARCH_CAP_RSBA 0x0004 35701add34aSRobert Mustacchi #define IA32_ARCH_CAP_SSB_NO 0x0010 35801add34aSRobert Mustacchi 35901add34aSRobert Mustacchi /* 36001add34aSRobert Mustacchi * Intel Speculation related MSRs 36101add34aSRobert Mustacchi */ 36201add34aSRobert Mustacchi #define MSR_IA32_SPEC_CTRL 0x48 36301add34aSRobert Mustacchi #define IA32_SPEC_CTRL_IBRS 0x01 36401add34aSRobert Mustacchi #define IA32_SPEC_CTRL_STIBP 0x02 36501add34aSRobert Mustacchi #define IA32_SPEC_CTRL_SSBD 0x04 36601add34aSRobert Mustacchi 36701add34aSRobert Mustacchi #define MSR_IA32_PRED_CMD 0x49 36801add34aSRobert Mustacchi #define IA32_PRED_CMD_IBPB 0x01 36901add34aSRobert Mustacchi 3707c478bd9Sstevel@tonic-gate #define MCI_CTL_VALUE 0xffffffff 3717c478bd9Sstevel@tonic-gate 3727c478bd9Sstevel@tonic-gate #define MTRR_TYPE_UC 0 3737c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WC 1 3747c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WT 4 3757c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WP 5 3767c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WB 6 3771d03c31eSjohnlev #define MTRR_TYPE_UC_ 7 3787c478bd9Sstevel@tonic-gate 3797c478bd9Sstevel@tonic-gate /* 3801d03c31eSjohnlev * For Solaris we set up the page attritubute table in the following way: 3811d03c31eSjohnlev * PAT0 Write-Back 3827c478bd9Sstevel@tonic-gate * PAT1 Write-Through 3831d03c31eSjohnlev * PAT2 Unchacheable- 3847c478bd9Sstevel@tonic-gate * PAT3 Uncacheable 3851d03c31eSjohnlev * PAT4 Write-Back 3861d03c31eSjohnlev * PAT5 Write-Through 3877c478bd9Sstevel@tonic-gate * PAT6 Write-Combine 3887c478bd9Sstevel@tonic-gate * PAT7 Uncacheable 3891d03c31eSjohnlev * The only difference from h/w default is entry 6. 3907c478bd9Sstevel@tonic-gate */ 3911d03c31eSjohnlev #define PAT_DEFAULT_ATTRIBUTE \ 3921d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WB | \ 3931d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WT << 8) | \ 3941d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 3951d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC << 24) | \ 3961d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WB << 32) | \ 3971d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WT << 40) | \ 3981d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WC << 48) | \ 3991d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC << 56)) 4007c478bd9Sstevel@tonic-gate 4017417cfdeSKuriakose Kuruvilla #define X86FSET_LARGEPAGE 0 4027417cfdeSKuriakose Kuruvilla #define X86FSET_TSC 1 4037417cfdeSKuriakose Kuruvilla #define X86FSET_MSR 2 4047417cfdeSKuriakose Kuruvilla #define X86FSET_MTRR 3 4057417cfdeSKuriakose Kuruvilla #define X86FSET_PGE 4 4067417cfdeSKuriakose Kuruvilla #define X86FSET_DE 5 4077417cfdeSKuriakose Kuruvilla #define X86FSET_CMOV 6 4086eedf6a5SJosef 'Jeff' Sipek #define X86FSET_MMX 7 4097417cfdeSKuriakose Kuruvilla #define X86FSET_MCA 8 4107417cfdeSKuriakose Kuruvilla #define X86FSET_PAE 9 4117417cfdeSKuriakose Kuruvilla #define X86FSET_CX8 10 4127417cfdeSKuriakose Kuruvilla #define X86FSET_PAT 11 4137417cfdeSKuriakose Kuruvilla #define X86FSET_SEP 12 4147417cfdeSKuriakose Kuruvilla #define X86FSET_SSE 13 4157417cfdeSKuriakose Kuruvilla #define X86FSET_SSE2 14 4167417cfdeSKuriakose Kuruvilla #define X86FSET_HTT 15 4177417cfdeSKuriakose Kuruvilla #define X86FSET_ASYSC 16 4187417cfdeSKuriakose Kuruvilla #define X86FSET_NX 17 4197417cfdeSKuriakose Kuruvilla #define X86FSET_SSE3 18 4207417cfdeSKuriakose Kuruvilla #define X86FSET_CX16 19 4217417cfdeSKuriakose Kuruvilla #define X86FSET_CMP 20 4227417cfdeSKuriakose Kuruvilla #define X86FSET_TSCP 21 4237417cfdeSKuriakose Kuruvilla #define X86FSET_MWAIT 22 4247417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4A 23 4257417cfdeSKuriakose Kuruvilla #define X86FSET_CPUID 24 4267417cfdeSKuriakose Kuruvilla #define X86FSET_SSSE3 25 4277417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4_1 26 4287417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4_2 27 4297417cfdeSKuriakose Kuruvilla #define X86FSET_1GPG 28 4307417cfdeSKuriakose Kuruvilla #define X86FSET_CLFSH 29 4317417cfdeSKuriakose Kuruvilla #define X86FSET_64 30 4327417cfdeSKuriakose Kuruvilla #define X86FSET_AES 31 4337417cfdeSKuriakose Kuruvilla #define X86FSET_PCLMULQDQ 32 4347af88ac7SKuriakose Kuruvilla #define X86FSET_XSAVE 33 4357af88ac7SKuriakose Kuruvilla #define X86FSET_AVX 34 436faa20166SBryan Cantrill #define X86FSET_VMX 35 437faa20166SBryan Cantrill #define X86FSET_SVM 36 4387660e73fSHans Rosenfeld #define X86FSET_TOPOEXT 37 439ebb8ac07SRobert Mustacchi #define X86FSET_F16C 38 440ebb8ac07SRobert Mustacchi #define X86FSET_RDRAND 39 4416eedf6a5SJosef 'Jeff' Sipek #define X86FSET_X2APIC 40 442245ac945SRobert Mustacchi #define X86FSET_AVX2 41 443245ac945SRobert Mustacchi #define X86FSET_BMI1 42 444245ac945SRobert Mustacchi #define X86FSET_BMI2 43 445245ac945SRobert Mustacchi #define X86FSET_FMA 44 446799823bbSRobert Mustacchi #define X86FSET_SMEP 45 4473ce2fcdcSRobert Mustacchi #define X86FSET_SMAP 46 4488889c875SRobert Mustacchi #define X86FSET_ADX 47 4498889c875SRobert Mustacchi #define X86FSET_RDSEED 48 450088d69f8SJerry Jelinek #define X86FSET_MPX 49 451088d69f8SJerry Jelinek #define X86FSET_AVX512F 50 452088d69f8SJerry Jelinek #define X86FSET_AVX512DQ 51 453088d69f8SJerry Jelinek #define X86FSET_AVX512PF 52 454088d69f8SJerry Jelinek #define X86FSET_AVX512ER 53 455088d69f8SJerry Jelinek #define X86FSET_AVX512CD 54 456088d69f8SJerry Jelinek #define X86FSET_AVX512BW 55 457088d69f8SJerry Jelinek #define X86FSET_AVX512VL 56 458088d69f8SJerry Jelinek #define X86FSET_AVX512FMA 57 459088d69f8SJerry Jelinek #define X86FSET_AVX512VBMI 58 460088d69f8SJerry Jelinek #define X86FSET_AVX512VPOPCDQ 59 461088d69f8SJerry Jelinek #define X86FSET_AVX512NNIW 60 462088d69f8SJerry Jelinek #define X86FSET_AVX512FMAPS 61 463088d69f8SJerry Jelinek #define X86FSET_XSAVEOPT 62 464088d69f8SJerry Jelinek #define X86FSET_XSAVEC 63 465088d69f8SJerry Jelinek #define X86FSET_XSAVES 64 466088d69f8SJerry Jelinek #define X86FSET_SHA 65 467088d69f8SJerry Jelinek #define X86FSET_UMIP 66 468088d69f8SJerry Jelinek #define X86FSET_PKU 67 469088d69f8SJerry Jelinek #define X86FSET_OSPKE 68 47074ecdb51SJohn Levon #define X86FSET_PCID 69 47174ecdb51SJohn Levon #define X86FSET_INVPCID 70 47201add34aSRobert Mustacchi #define X86FSET_IBRS 71 47301add34aSRobert Mustacchi #define X86FSET_IBPB 72 47401add34aSRobert Mustacchi #define X86FSET_STIBP 73 47501add34aSRobert Mustacchi #define X86FSET_SSBD 74 47601add34aSRobert Mustacchi #define X86FSET_SSBD_VIRT 75 47701add34aSRobert Mustacchi #define X86FSET_RDCL_NO 76 47801add34aSRobert Mustacchi #define X86FSET_IBRS_ALL 77 47901add34aSRobert Mustacchi #define X86FSET_RSBA 78 48001add34aSRobert Mustacchi #define X86FSET_SSB_NO 79 48101add34aSRobert Mustacchi #define X86FSET_STIBP_ALL 80 4827c478bd9Sstevel@tonic-gate 4830e751525SEric Saxe /* 4840e751525SEric Saxe * Intel Deep C-State invariant TSC in leaf 0x80000007. 4850e751525SEric Saxe */ 4860e751525SEric Saxe #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 4870e751525SEric Saxe 488cef70d2cSBill Holler /* 489cef70d2cSBill Holler * Intel Deep C-state always-running local APIC timer 490cef70d2cSBill Holler */ 491cef70d2cSBill Holler #define CPUID_CSTATE_ARAT (0x4) 492cef70d2cSBill Holler 493f21ed392Saubrey.li@intel.com /* 494f21ed392Saubrey.li@intel.com * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 495f21ed392Saubrey.li@intel.com */ 496f21ed392Saubrey.li@intel.com #define CPUID_EPB_SUPPORT (1 << 3) 497f21ed392Saubrey.li@intel.com 49841afdfa7SKrishnendu Sadhukhan - Sun Microsystems /* 49941afdfa7SKrishnendu Sadhukhan - Sun Microsystems * Intel TSC deadline timer 50041afdfa7SKrishnendu Sadhukhan - Sun Microsystems */ 50141afdfa7SKrishnendu Sadhukhan - Sun Microsystems #define CPUID_DEADLINE_TSC (1 << 24) 50241afdfa7SKrishnendu Sadhukhan - Sun Microsystems 5037c478bd9Sstevel@tonic-gate /* 5047c478bd9Sstevel@tonic-gate * x86_type is a legacy concept; this is supplanted 5057417cfdeSKuriakose Kuruvilla * for most purposes by x86_featureset; modern CPUs 5067c478bd9Sstevel@tonic-gate * should be X86_TYPE_OTHER 5077c478bd9Sstevel@tonic-gate */ 5087c478bd9Sstevel@tonic-gate #define X86_TYPE_OTHER 0 5097c478bd9Sstevel@tonic-gate #define X86_TYPE_486 1 5107c478bd9Sstevel@tonic-gate #define X86_TYPE_P5 2 5117c478bd9Sstevel@tonic-gate #define X86_TYPE_P6 3 5127c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_486 4 5137c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86L 5 5147c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86 6 5157c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_GXm 7 5167c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86MX 8 5177c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MediaGX 9 5187c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MII 10 5197c478bd9Sstevel@tonic-gate #define X86_TYPE_VIA_CYRIX_III 11 5207c478bd9Sstevel@tonic-gate #define X86_TYPE_P4 12 5217c478bd9Sstevel@tonic-gate 5227c478bd9Sstevel@tonic-gate /* 5237c478bd9Sstevel@tonic-gate * x86_vendor allows us to select between 5247c478bd9Sstevel@tonic-gate * implementation features and helps guide 5257c478bd9Sstevel@tonic-gate * the interpretation of the cpuid instruction. 5267c478bd9Sstevel@tonic-gate */ 527e4b86885SCheng Sean Ye #define X86_VENDOR_Intel 0 528e4b86885SCheng Sean Ye #define X86_VENDORSTR_Intel "GenuineIntel" 529e4b86885SCheng Sean Ye 530e4b86885SCheng Sean Ye #define X86_VENDOR_IntelClone 1 531e4b86885SCheng Sean Ye 532e4b86885SCheng Sean Ye #define X86_VENDOR_AMD 2 533e4b86885SCheng Sean Ye #define X86_VENDORSTR_AMD "AuthenticAMD" 534e4b86885SCheng Sean Ye 535e4b86885SCheng Sean Ye #define X86_VENDOR_Cyrix 3 536e4b86885SCheng Sean Ye #define X86_VENDORSTR_CYRIX "CyrixInstead" 537e4b86885SCheng Sean Ye 538e4b86885SCheng Sean Ye #define X86_VENDOR_UMC 4 539e4b86885SCheng Sean Ye #define X86_VENDORSTR_UMC "UMC UMC UMC " 540e4b86885SCheng Sean Ye 541e4b86885SCheng Sean Ye #define X86_VENDOR_NexGen 5 542e4b86885SCheng Sean Ye #define X86_VENDORSTR_NexGen "NexGenDriven" 543e4b86885SCheng Sean Ye 544e4b86885SCheng Sean Ye #define X86_VENDOR_Centaur 6 545e4b86885SCheng Sean Ye #define X86_VENDORSTR_Centaur "CentaurHauls" 546e4b86885SCheng Sean Ye 547e4b86885SCheng Sean Ye #define X86_VENDOR_Rise 7 548e4b86885SCheng Sean Ye #define X86_VENDORSTR_Rise "RiseRiseRise" 549e4b86885SCheng Sean Ye 550e4b86885SCheng Sean Ye #define X86_VENDOR_SiS 8 551e4b86885SCheng Sean Ye #define X86_VENDORSTR_SiS "SiS SiS SiS " 552e4b86885SCheng Sean Ye 553e4b86885SCheng Sean Ye #define X86_VENDOR_TM 9 554e4b86885SCheng Sean Ye #define X86_VENDORSTR_TM "GenuineTMx86" 555e4b86885SCheng Sean Ye 556e4b86885SCheng Sean Ye #define X86_VENDOR_NSC 10 557e4b86885SCheng Sean Ye #define X86_VENDORSTR_NSC "Geode by NSC" 558e4b86885SCheng Sean Ye 559e4b86885SCheng Sean Ye /* 560e4b86885SCheng Sean Ye * Vendor string max len + \0 561e4b86885SCheng Sean Ye */ 562e4b86885SCheng Sean Ye #define X86_VENDOR_STRLEN 13 5637aec1d6eScindi 5648a40a695Sgavinm /* 5658a40a695Sgavinm * Some vendor/family/model/stepping ranges are commonly grouped under 5668a40a695Sgavinm * a single identifying banner by the vendor. The following encode 5678a40a695Sgavinm * that "revision" in a uint32_t with the 8 most significant bits 5688a40a695Sgavinm * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 5698a40a695Sgavinm * family, and the remaining 16 typically forming a bitmask of revisions 5708a40a695Sgavinm * within that family with more significant bits indicating "later" revisions. 5718a40a695Sgavinm */ 5728a40a695Sgavinm 5738a40a695Sgavinm #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 5748a40a695Sgavinm #define _X86_CHIPREV_VENDOR_SHIFT 24 5758a40a695Sgavinm #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 5768a40a695Sgavinm #define _X86_CHIPREV_FAMILY_SHIFT 16 5778a40a695Sgavinm #define _X86_CHIPREV_REV_MASK 0x0000ffffu 5788a40a695Sgavinm 5798a40a695Sgavinm #define _X86_CHIPREV_VENDOR(x) \ 5808a40a695Sgavinm (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 5818a40a695Sgavinm #define _X86_CHIPREV_FAMILY(x) \ 5828a40a695Sgavinm (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 5838a40a695Sgavinm #define _X86_CHIPREV_REV(x) \ 5848a40a695Sgavinm ((x) & _X86_CHIPREV_REV_MASK) 5858a40a695Sgavinm 5868a40a695Sgavinm /* True if x matches in vendor and family and if x matches the given rev mask */ 5878a40a695Sgavinm #define X86_CHIPREV_MATCH(x, mask) \ 5888a40a695Sgavinm (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 5898a40a695Sgavinm _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 5908a40a695Sgavinm ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 5918a40a695Sgavinm 5922c8230b0SSrihari Venkatesan /* True if x matches in vendor and family, and rev is at least minx */ 5938a40a695Sgavinm #define X86_CHIPREV_ATLEAST(x, minx) \ 5948a40a695Sgavinm (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 5958a40a695Sgavinm _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 5968a40a695Sgavinm _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 5978a40a695Sgavinm 5988a40a695Sgavinm #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 5998a40a695Sgavinm ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 6008a40a695Sgavinm (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 6018a40a695Sgavinm 6022c8230b0SSrihari Venkatesan /* True if x matches in vendor, and family is at least minx */ 6032c8230b0SSrihari Venkatesan #define X86_CHIPFAM_ATLEAST(x, minx) \ 6042c8230b0SSrihari Venkatesan (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 6052c8230b0SSrihari Venkatesan _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 6062c8230b0SSrihari Venkatesan 6078a40a695Sgavinm /* Revision default */ 6088a40a695Sgavinm #define X86_CHIPREV_UNKNOWN 0x0 6098a40a695Sgavinm 6108a40a695Sgavinm /* 61120c794b3Sgavinm * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 61220c794b3Sgavinm * sufficiently different that we will distinguish them; in all other 6138a40a695Sgavinm * case we will identify the major revision. 6148a40a695Sgavinm */ 6158a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 6168a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 6178a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 6188a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 6198a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 6208a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 6218a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 62220c794b3Sgavinm 62320c794b3Sgavinm /* 62420c794b3Sgavinm * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 62520c794b3Sgavinm */ 62620c794b3Sgavinm #define X86_CHIPREV_AMD_10_REV_A \ 62731725658Sksadhukh _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 62820c794b3Sgavinm #define X86_CHIPREV_AMD_10_REV_B \ 62920c794b3Sgavinm _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 63079321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_C2 \ 63164452efdSKit Chow _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 63279321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_C3 \ 63389e921d5SKuriakose Kuruvilla _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 63479321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_D0 \ 63579321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 63679321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_D1 \ 63779321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 63879321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_E \ 63979321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 64089e921d5SKuriakose Kuruvilla 64189e921d5SKuriakose Kuruvilla /* 64289e921d5SKuriakose Kuruvilla * Definitions for AMD Family 0x11. 64389e921d5SKuriakose Kuruvilla */ 64479321794SJens Elkner #define X86_CHIPREV_AMD_11_REV_B \ 64579321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 64689e921d5SKuriakose Kuruvilla 64779321794SJens Elkner /* 64879321794SJens Elkner * Definitions for AMD Family 0x12. 64979321794SJens Elkner */ 65079321794SJens Elkner #define X86_CHIPREV_AMD_12_REV_B \ 65179321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 65279321794SJens Elkner 65379321794SJens Elkner /* 65479321794SJens Elkner * Definitions for AMD Family 0x14. 65579321794SJens Elkner */ 65679321794SJens Elkner #define X86_CHIPREV_AMD_14_REV_B \ 65779321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 65879321794SJens Elkner #define X86_CHIPREV_AMD_14_REV_C \ 65979321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 66079321794SJens Elkner 66179321794SJens Elkner /* 66279321794SJens Elkner * Definitions for AMD Family 0x15 66379321794SJens Elkner */ 66479321794SJens Elkner #define X86_CHIPREV_AMD_15OR_REV_B2 \ 66579321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 66679321794SJens Elkner 66779321794SJens Elkner #define X86_CHIPREV_AMD_15TN_REV_A1 \ 66879321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 6698a40a695Sgavinm 6708a40a695Sgavinm /* 6718a40a695Sgavinm * Various socket/package types, extended as the need to distinguish 6728a40a695Sgavinm * a new type arises. The top 8 byte identfies the vendor and the 6738a40a695Sgavinm * remaining 24 bits describe 24 socket types. 6748a40a695Sgavinm */ 6758a40a695Sgavinm 6768a40a695Sgavinm #define _X86_SOCKET_VENDOR_SHIFT 24 6778a40a695Sgavinm #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 6788a40a695Sgavinm #define _X86_SOCKET_TYPE_MASK 0x00ffffff 6798a40a695Sgavinm #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 6808a40a695Sgavinm 6818a40a695Sgavinm #define _X86_SOCKET_MKVAL(vendor, bitval) \ 6828a40a695Sgavinm ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 6838a40a695Sgavinm 6848a40a695Sgavinm #define X86_SOCKET_MATCH(s, mask) \ 6858a40a695Sgavinm (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 686a24e89c4SKuriakose Kuruvilla (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 6878a40a695Sgavinm 6888a40a695Sgavinm #define X86_SOCKET_UNKNOWN 0x0 6898a40a695Sgavinm /* 6908a40a695Sgavinm * AMD socket types 6918a40a695Sgavinm */ 6928a40a695Sgavinm #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 6938a40a695Sgavinm #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 6948a40a695Sgavinm #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 6958a40a695Sgavinm #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 6968a40a695Sgavinm #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 6978a40a695Sgavinm #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 698a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 699a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 700a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 701a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 702a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 703a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 704bd15239eSSrihari Venkatesan #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 705bd15239eSSrihari Venkatesan #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 70679321794SJens Elkner #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 70779321794SJens Elkner #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 70879321794SJens Elkner #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 70979321794SJens Elkner #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 71079321794SJens Elkner #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 71179321794SJens Elkner #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 71279321794SJens Elkner #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 71379321794SJens Elkner #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 7148a40a695Sgavinm 7157af88ac7SKuriakose Kuruvilla /* 7167af88ac7SKuriakose Kuruvilla * xgetbv/xsetbv support 717088d69f8SJerry Jelinek * See section 13.3 in vol. 1 of the Intel devlopers manual. 7187af88ac7SKuriakose Kuruvilla */ 7197af88ac7SKuriakose Kuruvilla 7207af88ac7SKuriakose Kuruvilla #define XFEATURE_ENABLED_MASK 0x0 7217af88ac7SKuriakose Kuruvilla /* 7227af88ac7SKuriakose Kuruvilla * XFEATURE_ENABLED_MASK values (eax) 723088d69f8SJerry Jelinek * See setup_xfem(). 7247af88ac7SKuriakose Kuruvilla */ 7257af88ac7SKuriakose Kuruvilla #define XFEATURE_LEGACY_FP 0x1 7267af88ac7SKuriakose Kuruvilla #define XFEATURE_SSE 0x2 7277af88ac7SKuriakose Kuruvilla #define XFEATURE_AVX 0x4 728088d69f8SJerry Jelinek #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ 729088d69f8SJerry Jelinek #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ 730088d69f8SJerry Jelinek /* bit 8 unused */ 731088d69f8SJerry Jelinek #define XFEATURE_PKRU 0x200 732ebb8ac07SRobert Mustacchi #define XFEATURE_FP_ALL \ 733088d69f8SJerry Jelinek (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 734088d69f8SJerry Jelinek XFEATURE_AVX512 | XFEATURE_PKRU) 7357af88ac7SKuriakose Kuruvilla 736d0158222SRobert Mustacchi /* 737d0158222SRobert Mustacchi * Define the set of xfeature flags that should be considered valid in the xsave 738d0158222SRobert Mustacchi * state vector when we initialize an lwp. This is distinct from the full set so 739d0158222SRobert Mustacchi * that all of the processor's normal logic and tracking of the xsave state is 740d0158222SRobert Mustacchi * usable. This should correspond to the state that's been initialized by the 741d0158222SRobert Mustacchi * ABI to hold meaningful values. Adding additional bits here can have serious 742d0158222SRobert Mustacchi * performance implications and cause performance degradations when using the 743d0158222SRobert Mustacchi * FPU vector (xmm) registers. 744d0158222SRobert Mustacchi */ 745d0158222SRobert Mustacchi #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 746d0158222SRobert Mustacchi 7477c478bd9Sstevel@tonic-gate #if !defined(_ASM) 7487c478bd9Sstevel@tonic-gate 7497c478bd9Sstevel@tonic-gate #if defined(_KERNEL) || defined(_KMEMUSER) 7507c478bd9Sstevel@tonic-gate 75101add34aSRobert Mustacchi #define NUM_X86_FEATURES 81 752dfea898aSKuriakose Kuruvilla extern uchar_t x86_featureset[]; 7537417cfdeSKuriakose Kuruvilla 7547417cfdeSKuriakose Kuruvilla extern void free_x86_featureset(void *featureset); 7557417cfdeSKuriakose Kuruvilla extern boolean_t is_x86_feature(void *featureset, uint_t feature); 7567417cfdeSKuriakose Kuruvilla extern void add_x86_feature(void *featureset, uint_t feature); 7577417cfdeSKuriakose Kuruvilla extern void remove_x86_feature(void *featureset, uint_t feature); 7587417cfdeSKuriakose Kuruvilla extern boolean_t compare_x86_featureset(void *setA, void *setB); 7597417cfdeSKuriakose Kuruvilla extern void print_x86_featureset(void *featureset); 7607417cfdeSKuriakose Kuruvilla 7617417cfdeSKuriakose Kuruvilla 7627c478bd9Sstevel@tonic-gate extern uint_t x86_type; 7637c478bd9Sstevel@tonic-gate extern uint_t x86_vendor; 76486c1f4dcSVikram Hegde extern uint_t x86_clflush_size; 7657c478bd9Sstevel@tonic-gate 7667c478bd9Sstevel@tonic-gate extern uint_t pentiumpro_bug4046376; 7677c478bd9Sstevel@tonic-gate 7687c478bd9Sstevel@tonic-gate extern const char CyrixInstead[]; 7697c478bd9Sstevel@tonic-gate 7707c478bd9Sstevel@tonic-gate #endif 7717c478bd9Sstevel@tonic-gate 7727c478bd9Sstevel@tonic-gate #if defined(_KERNEL) 7737c478bd9Sstevel@tonic-gate 7748949bcd6Sandrei /* 7758949bcd6Sandrei * This structure is used to pass arguments and get return values back 7768949bcd6Sandrei * from the CPUID instruction in __cpuid_insn() routine. 7778949bcd6Sandrei */ 7788949bcd6Sandrei struct cpuid_regs { 7798949bcd6Sandrei uint32_t cp_eax; 7808949bcd6Sandrei uint32_t cp_ebx; 7818949bcd6Sandrei uint32_t cp_ecx; 7828949bcd6Sandrei uint32_t cp_edx; 7838949bcd6Sandrei }; 7847c478bd9Sstevel@tonic-gate 78574ecdb51SJohn Levon extern int x86_use_pcid; 78674ecdb51SJohn Levon extern int x86_use_invpcid; 78774ecdb51SJohn Levon 7887af88ac7SKuriakose Kuruvilla /* 7897af88ac7SKuriakose Kuruvilla * Utility functions to get/set extended control registers (XCR) 7907af88ac7SKuriakose Kuruvilla * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 7917af88ac7SKuriakose Kuruvilla */ 7927af88ac7SKuriakose Kuruvilla extern uint64_t get_xcr(uint_t); 7937af88ac7SKuriakose Kuruvilla extern void set_xcr(uint_t, uint64_t); 7947af88ac7SKuriakose Kuruvilla 7950ac7d7d8Skucharsk extern uint64_t rdmsr(uint_t); 7960ac7d7d8Skucharsk extern void wrmsr(uint_t, const uint64_t); 797ee88d2b9Skchow extern uint64_t xrdmsr(uint_t); 798ee88d2b9Skchow extern void xwrmsr(uint_t, const uint64_t); 799ae115bc7Smrj extern int checked_rdmsr(uint_t, uint64_t *); 800ae115bc7Smrj extern int checked_wrmsr(uint_t, uint64_t); 801ae115bc7Smrj 8027c478bd9Sstevel@tonic-gate extern void invalidate_cache(void); 8037c478bd9Sstevel@tonic-gate extern ulong_t getcr4(void); 8047c478bd9Sstevel@tonic-gate extern void setcr4(ulong_t); 805ae115bc7Smrj 8067c478bd9Sstevel@tonic-gate extern void mtrr_sync(void); 8077c478bd9Sstevel@tonic-gate 808a0955b86SJohn Levon extern void cpu_fast_syscall_enable(void); 809a0955b86SJohn Levon extern void cpu_fast_syscall_disable(void); 8107c478bd9Sstevel@tonic-gate 8117c478bd9Sstevel@tonic-gate struct cpu; 8127c478bd9Sstevel@tonic-gate 8137c478bd9Sstevel@tonic-gate extern int cpuid_checkpass(struct cpu *, int); 8148949bcd6Sandrei extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 8158949bcd6Sandrei extern uint32_t __cpuid_insn(struct cpuid_regs *); 8167c478bd9Sstevel@tonic-gate extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 8177c478bd9Sstevel@tonic-gate extern int cpuid_getidstr(struct cpu *, char *, size_t); 8187c478bd9Sstevel@tonic-gate extern const char *cpuid_getvendorstr(struct cpu *); 8197c478bd9Sstevel@tonic-gate extern uint_t cpuid_getvendor(struct cpu *); 8207c478bd9Sstevel@tonic-gate extern uint_t cpuid_getfamily(struct cpu *); 8217c478bd9Sstevel@tonic-gate extern uint_t cpuid_getmodel(struct cpu *); 8227c478bd9Sstevel@tonic-gate extern uint_t cpuid_getstep(struct cpu *); 8232449e17fSsherrym extern uint_t cpuid_getsig(struct cpu *); 8247c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 8258949bcd6Sandrei extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 826d129bde2Sesaxe extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 827d129bde2Sesaxe extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 828fb2f18f8Sesaxe extern int cpuid_get_chipid(struct cpu *); 829fb2f18f8Sesaxe extern id_t cpuid_get_coreid(struct cpu *); 83010569901Sgavinm extern int cpuid_get_pkgcoreid(struct cpu *); 831fb2f18f8Sesaxe extern int cpuid_get_clogid(struct cpu *); 832b885580bSAlexander Kolbasov extern int cpuid_get_cacheid(struct cpu *); 833fa96bd91SMichael Corcoran extern uint32_t cpuid_get_apicid(struct cpu *); 8348031591dSSrihari Venkatesan extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 8358031591dSSrihari Venkatesan extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 8367660e73fSHans Rosenfeld extern uint_t cpuid_get_compunitid(struct cpu *cpu); 8377660e73fSHans Rosenfeld extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 838088d69f8SJerry Jelinek extern size_t cpuid_get_xsave_size(); 839088d69f8SJerry Jelinek extern boolean_t cpuid_need_fp_excp_handling(); 8408949bcd6Sandrei extern int cpuid_is_cmt(struct cpu *); 8417c478bd9Sstevel@tonic-gate extern int cpuid_syscall32_insn(struct cpu *); 8427c478bd9Sstevel@tonic-gate extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 8438a40a695Sgavinm 8448a40a695Sgavinm extern uint32_t cpuid_getchiprev(struct cpu *); 8458a40a695Sgavinm extern const char *cpuid_getchiprevstr(struct cpu *); 8468a40a695Sgavinm extern uint32_t cpuid_getsockettype(struct cpu *); 84789e921d5SKuriakose Kuruvilla extern const char *cpuid_getsocketstr(struct cpu *); 8487c478bd9Sstevel@tonic-gate 8492ef50f01SJoe Bonasera extern int cpuid_have_cr8access(struct cpu *); 8502ef50f01SJoe Bonasera 8517c478bd9Sstevel@tonic-gate extern int cpuid_opteron_erratum(struct cpu *, uint_t); 8527c478bd9Sstevel@tonic-gate 8537c478bd9Sstevel@tonic-gate struct cpuid_info; 8547c478bd9Sstevel@tonic-gate 8557c478bd9Sstevel@tonic-gate extern void setx86isalist(void); 856ae115bc7Smrj extern void cpuid_alloc_space(struct cpu *); 857ae115bc7Smrj extern void cpuid_free_space(struct cpu *); 858dfea898aSKuriakose Kuruvilla extern void cpuid_pass1(struct cpu *, uchar_t *); 8597c478bd9Sstevel@tonic-gate extern void cpuid_pass2(struct cpu *); 8607c478bd9Sstevel@tonic-gate extern void cpuid_pass3(struct cpu *); 861ebb8ac07SRobert Mustacchi extern void cpuid_pass4(struct cpu *, uint_t *); 862fa96bd91SMichael Corcoran extern void cpuid_set_cpu_properties(void *, processorid_t, 863fa96bd91SMichael Corcoran struct cpuid_info *); 86401add34aSRobert Mustacchi extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 86501add34aSRobert Mustacchi extern void cpuid_post_ucodeadm(void); 8667c478bd9Sstevel@tonic-gate 8677c478bd9Sstevel@tonic-gate extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 8687c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 869843e1988Sjohnlev 870843e1988Sjohnlev #if !defined(__xpv) 8715b8a6efeSbholler extern uint32_t *cpuid_mwait_alloc(struct cpu *); 8725b8a6efeSbholler extern void cpuid_mwait_free(struct cpu *); 8730e751525SEric Saxe extern int cpuid_deep_cstates_supported(void); 874cef70d2cSBill Holler extern int cpuid_arat_supported(void); 875f21ed392Saubrey.li@intel.com extern int cpuid_iepb_supported(struct cpu *); 87641afdfa7SKrishnendu Sadhukhan - Sun Microsystems extern int cpuid_deadline_tsc_supported(void); 87779ec9da8SYuri Pankov extern void vmware_port(int, uint32_t *); 878843e1988Sjohnlev #endif 8797c478bd9Sstevel@tonic-gate 8802449e17fSsherrym struct cpu_ucode_info; 8812449e17fSsherrym 8822449e17fSsherrym extern void ucode_alloc_space(struct cpu *); 8832449e17fSsherrym extern void ucode_free_space(struct cpu *); 8842449e17fSsherrym extern void ucode_check(struct cpu *); 885adc586deSMark Johnson extern void ucode_cleanup(); 8862449e17fSsherrym 887247dbb3dSsudheer #if !defined(__xpv) 888247dbb3dSsudheer extern char _tsc_mfence_start; 889247dbb3dSsudheer extern char _tsc_mfence_end; 890247dbb3dSsudheer extern char _tscp_start; 891247dbb3dSsudheer extern char _tscp_end; 892247dbb3dSsudheer extern char _no_rdtsc_start; 893247dbb3dSsudheer extern char _no_rdtsc_end; 89415363b27Ssudheer extern char _tsc_lfence_start; 89515363b27Ssudheer extern char _tsc_lfence_end; 896247dbb3dSsudheer #endif 897247dbb3dSsudheer 89822cc0e45SBill Holler #if !defined(__xpv) 89922cc0e45SBill Holler extern char bcopy_patch_start; 90022cc0e45SBill Holler extern char bcopy_patch_end; 90122cc0e45SBill Holler extern char bcopy_ck_size; 90222cc0e45SBill Holler #endif 90322cc0e45SBill Holler 904e774b42bSBill Holler extern void post_startup_cpu_fixups(void); 905e774b42bSBill Holler 9067c478bd9Sstevel@tonic-gate extern uint_t workaround_errata(struct cpu *); 9077c478bd9Sstevel@tonic-gate 9087c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 9097c478bd9Sstevel@tonic-gate extern int opteron_erratum_93; 9107c478bd9Sstevel@tonic-gate #endif 9117c478bd9Sstevel@tonic-gate 9127c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 9137c478bd9Sstevel@tonic-gate extern int opteron_erratum_91; 9147c478bd9Sstevel@tonic-gate #endif 9157c478bd9Sstevel@tonic-gate 9167c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 9177c478bd9Sstevel@tonic-gate extern int opteron_erratum_100; 9187c478bd9Sstevel@tonic-gate #endif 9197c478bd9Sstevel@tonic-gate 9207c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 9217c478bd9Sstevel@tonic-gate extern int opteron_erratum_121; 9227c478bd9Sstevel@tonic-gate #endif 9237c478bd9Sstevel@tonic-gate 924ee88d2b9Skchow #if defined(OPTERON_WORKAROUND_6323525) 925ee88d2b9Skchow extern int opteron_workaround_6323525; 926ee88d2b9Skchow extern void patch_workaround_6323525(void); 927ee88d2b9Skchow #endif 928ee88d2b9Skchow 929cfe84b82SMatt Amdur #if !defined(__xpv) 930cfe84b82SMatt Amdur extern void determine_platform(void); 931cfe84b82SMatt Amdur #endif 932b9bfdccdSStuart Maybee extern int get_hwenv(void); 933b9bfdccdSStuart Maybee extern int is_controldom(void); 934b9bfdccdSStuart Maybee 93574ecdb51SJohn Levon extern void enable_pcid(void); 93674ecdb51SJohn Levon 9377af88ac7SKuriakose Kuruvilla extern void xsave_setup_msr(struct cpu *); 9387af88ac7SKuriakose Kuruvilla 939309b04b8SJohn Levon #if !defined(__xpv) 940309b04b8SJohn Levon extern void reset_gdtr_limit(void); 941309b04b8SJohn Levon #endif 942309b04b8SJohn Levon 94379ec9da8SYuri Pankov /* 94479ec9da8SYuri Pankov * Hypervisor signatures 94579ec9da8SYuri Pankov */ 94679ec9da8SYuri Pankov #define HVSIG_XEN_HVM "XenVMMXenVMM" 94779ec9da8SYuri Pankov #define HVSIG_VMWARE "VMwareVMware" 94879ec9da8SYuri Pankov #define HVSIG_KVM "KVMKVMKVM" 94979ec9da8SYuri Pankov #define HVSIG_MICROSOFT "Microsoft Hv" 95079ec9da8SYuri Pankov 951b9bfdccdSStuart Maybee /* 952b9bfdccdSStuart Maybee * Defined hardware environments 953b9bfdccdSStuart Maybee */ 95479ec9da8SYuri Pankov #define HW_NATIVE (1 << 0) /* Running on bare metal */ 95579ec9da8SYuri Pankov #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 95679ec9da8SYuri Pankov 95779ec9da8SYuri Pankov #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 95879ec9da8SYuri Pankov #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 95979ec9da8SYuri Pankov #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 96079ec9da8SYuri Pankov #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 96179ec9da8SYuri Pankov 96279ec9da8SYuri Pankov #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT) 963b9bfdccdSStuart Maybee 9647c478bd9Sstevel@tonic-gate #endif /* _KERNEL */ 9657c478bd9Sstevel@tonic-gate 96679ec9da8SYuri Pankov #endif /* !_ASM */ 96779ec9da8SYuri Pankov 96879ec9da8SYuri Pankov /* 96979ec9da8SYuri Pankov * VMware hypervisor related defines 97079ec9da8SYuri Pankov */ 97179ec9da8SYuri Pankov #define VMWARE_HVMAGIC 0x564d5868 97279ec9da8SYuri Pankov #define VMWARE_HVPORT 0x5658 97379ec9da8SYuri Pankov #define VMWARE_HVCMD_GETVERSION 0x0a 97479ec9da8SYuri Pankov #define VMWARE_HVCMD_GETTSCFREQ 0x2d 9757c478bd9Sstevel@tonic-gate 9767c478bd9Sstevel@tonic-gate #ifdef __cplusplus 9777c478bd9Sstevel@tonic-gate } 9787c478bd9Sstevel@tonic-gate #endif 9797c478bd9Sstevel@tonic-gate 9807c478bd9Sstevel@tonic-gate #endif /* _SYS_X86_ARCHEXT_H */ 981