17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5ee88d2b9Skchow * Common Development and Distribution License (the "License"). 6ee88d2b9Skchow * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 227417cfdeSKuriakose Kuruvilla * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 237c478bd9Sstevel@tonic-gate */ 24cef70d2cSBill Holler /* 25*41afdfa7SKrishnendu Sadhukhan - Sun Microsystems * Copyright (c) 2010, Intel Corporation. 26cef70d2cSBill Holler * All rights reserved. 27cef70d2cSBill Holler */ 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #ifndef _SYS_X86_ARCHEXT_H 307c478bd9Sstevel@tonic-gate #define _SYS_X86_ARCHEXT_H 317c478bd9Sstevel@tonic-gate 327c478bd9Sstevel@tonic-gate #if !defined(_ASM) 337c478bd9Sstevel@tonic-gate #include <sys/regset.h> 347c478bd9Sstevel@tonic-gate #include <sys/processor.h> 357c478bd9Sstevel@tonic-gate #include <vm/seg_enum.h> 367c478bd9Sstevel@tonic-gate #include <vm/page.h> 377c478bd9Sstevel@tonic-gate #endif /* _ASM */ 387c478bd9Sstevel@tonic-gate 397c478bd9Sstevel@tonic-gate #ifdef __cplusplus 407c478bd9Sstevel@tonic-gate extern "C" { 417c478bd9Sstevel@tonic-gate #endif 427c478bd9Sstevel@tonic-gate 437c478bd9Sstevel@tonic-gate /* 447c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (standard function 1) 457c478bd9Sstevel@tonic-gate */ 467c478bd9Sstevel@tonic-gate 477c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 487c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 497c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 507c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 517c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 527c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 537c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 547c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 557c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 567c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 577c478bd9Sstevel@tonic-gate /* 0x400 - reserved */ 587c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 597c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 607c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 617c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 627c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 637c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 647c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 657c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 667c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 677c478bd9Sstevel@tonic-gate /* 0x100000 - reserved */ 687c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 697c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 707c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 717c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 727c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 737c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 747c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 757c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 767c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 77ae115bc7Smrj #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 787c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 797c478bd9Sstevel@tonic-gate 80ae115bc7Smrj #define FMT_CPUID_INTC_EDX \ 81ae115bc7Smrj "\20" \ 82ae115bc7Smrj "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 83ae115bc7Smrj "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 84ae115bc7Smrj "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 857c478bd9Sstevel@tonic-gate "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 867c478bd9Sstevel@tonic-gate 877c478bd9Sstevel@tonic-gate /* 887c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %ecx (standard function 1) 897c478bd9Sstevel@tonic-gate */ 907c478bd9Sstevel@tonic-gate 917c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 92a50a8b93SKuriakose Kuruvilla #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 937c478bd9Sstevel@tonic-gate /* 0x00000004 - reserved */ 947c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 957c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 96ae115bc7Smrj #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 97ae115bc7Smrj #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 987c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 997c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 100ae115bc7Smrj #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 1017c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 1027c478bd9Sstevel@tonic-gate /* 0x00000800 - reserved */ 1037c478bd9Sstevel@tonic-gate /* 0x00001000 - reserved */ 104ae115bc7Smrj #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 105ae115bc7Smrj #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 106ae115bc7Smrj /* 0x00008000 - reserved */ 107ae115bc7Smrj /* 0x00010000 - reserved */ 108ae115bc7Smrj /* 0x00020000 - reserved */ 109ae115bc7Smrj #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 110d0f8ff6eSkk #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 111d0f8ff6eSkk #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 1125087e485SKrishnendu Sadhukhan - Sun Microsystems #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 113f8801251Skk #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 114a50a8b93SKuriakose Kuruvilla #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 115ae115bc7Smrj 116ae115bc7Smrj #define FMT_CPUID_INTC_ECX \ 117ae115bc7Smrj "\20" \ 118a50a8b93SKuriakose Kuruvilla "\32aes" \ 1195087e485SKrishnendu Sadhukhan - Sun Microsystems "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \ 120ae115bc7Smrj "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 121a50a8b93SKuriakose Kuruvilla "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3" 1227c478bd9Sstevel@tonic-gate 1237c478bd9Sstevel@tonic-gate /* 1247c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (extended function 0x80000001) 1257c478bd9Sstevel@tonic-gate */ 1267c478bd9Sstevel@tonic-gate 1277c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 1287c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 1297c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 1307c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 1317c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 1327c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 1337c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 1347c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 1357c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 1367c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 1377c478bd9Sstevel@tonic-gate /* 0x00000400 - sysc on K6m6 */ 1387c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 1397c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 1407c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 1417c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 1427c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 143ae115bc7Smrj #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 144ae115bc7Smrj #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 1457c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 1467c478bd9Sstevel@tonic-gate /* 0x00040000 - reserved */ 1477c478bd9Sstevel@tonic-gate /* 0x00080000 - reserved */ 1487c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 1497c478bd9Sstevel@tonic-gate /* 0x00200000 - reserved */ 1507c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 1517c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 1527c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 153ae115bc7Smrj #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 15402bc52beSkchow #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 155ae115bc7Smrj #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 1567c478bd9Sstevel@tonic-gate /* 0x10000000 - reserved */ 1577c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 1587c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 1597c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 1607c478bd9Sstevel@tonic-gate 1617c478bd9Sstevel@tonic-gate #define FMT_CPUID_AMD_EDX \ 1627c478bd9Sstevel@tonic-gate "\20" \ 163ae115bc7Smrj "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 1647c478bd9Sstevel@tonic-gate "\30mmx\27mmxext\25nx\22pse\21pat" \ 1657c478bd9Sstevel@tonic-gate "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 1667c478bd9Sstevel@tonic-gate "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 1677c478bd9Sstevel@tonic-gate 168ae115bc7Smrj #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 169ae115bc7Smrj #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 170ae115bc7Smrj #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 171ae115bc7Smrj #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 172ae115bc7Smrj #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 173f8801251Skk #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 174f8801251Skk #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 175512cf780Skchow #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 176512cf780Skchow #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 177512cf780Skchow #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 178512cf780Skchow #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 179512cf780Skchow #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ 180512cf780Skchow #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 181512cf780Skchow #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 1827c478bd9Sstevel@tonic-gate 1837c478bd9Sstevel@tonic-gate #define FMT_CPUID_AMD_ECX \ 1847c478bd9Sstevel@tonic-gate "\20" \ 185512cf780Skchow "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \ 186f8801251Skk "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 187ae115bc7Smrj 188ae115bc7Smrj /* 189ae115bc7Smrj * Intel now seems to have claimed part of the "extended" function 190ae115bc7Smrj * space that we previously for non-Intel implementors to use. 191ae115bc7Smrj * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 192ae115bc7Smrj * is available in long mode i.e. what AMD indicate using bit 0. 193ae115bc7Smrj * On the other hand, everything else is labelled as reserved. 194ae115bc7Smrj */ 195ae115bc7Smrj #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 196ae115bc7Smrj 1977c478bd9Sstevel@tonic-gate 1987c478bd9Sstevel@tonic-gate #define P5_MCHADDR 0x0 1997c478bd9Sstevel@tonic-gate #define P5_CESR 0x11 2007c478bd9Sstevel@tonic-gate #define P5_CTR0 0x12 2017c478bd9Sstevel@tonic-gate #define P5_CTR1 0x13 2027c478bd9Sstevel@tonic-gate 2037c478bd9Sstevel@tonic-gate #define K5_MCHADDR 0x0 2047c478bd9Sstevel@tonic-gate #define K5_MCHTYPE 0x01 2057c478bd9Sstevel@tonic-gate #define K5_TSC 0x10 2067c478bd9Sstevel@tonic-gate #define K5_TR12 0x12 2077c478bd9Sstevel@tonic-gate 2081d03c31eSjohnlev #define REG_PAT 0x277 2091d03c31eSjohnlev 2107c478bd9Sstevel@tonic-gate #define REG_MC0_CTL 0x400 2117c478bd9Sstevel@tonic-gate #define REG_MC5_MISC 0x417 2127c478bd9Sstevel@tonic-gate #define REG_PERFCTR0 0xc1 2137c478bd9Sstevel@tonic-gate #define REG_PERFCTR1 0xc2 2147c478bd9Sstevel@tonic-gate 2157c478bd9Sstevel@tonic-gate #define REG_PERFEVNT0 0x186 2167c478bd9Sstevel@tonic-gate #define REG_PERFEVNT1 0x187 2177c478bd9Sstevel@tonic-gate 2187c478bd9Sstevel@tonic-gate #define REG_TSC 0x10 /* timestamp counter */ 2197c478bd9Sstevel@tonic-gate #define REG_APIC_BASE_MSR 0x1b 220b6917abeSmishra #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 2217c478bd9Sstevel@tonic-gate 222e774b42bSBill Holler #if !defined(__xpv) 223e774b42bSBill Holler /* 224e774b42bSBill Holler * AMD C1E 225e774b42bSBill Holler */ 226e774b42bSBill Holler #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 227e774b42bSBill Holler #define AMD_ACTONCMPHALT_SHIFT 27 228e774b42bSBill Holler #define AMD_ACTONCMPHALT_MASK 3 229e774b42bSBill Holler #endif 230e774b42bSBill Holler 2317c478bd9Sstevel@tonic-gate #define MSR_DEBUGCTL 0x1d9 2327c478bd9Sstevel@tonic-gate 2337c478bd9Sstevel@tonic-gate #define DEBUGCTL_LBR 0x01 2347c478bd9Sstevel@tonic-gate #define DEBUGCTL_BTF 0x02 2357c478bd9Sstevel@tonic-gate 2367c478bd9Sstevel@tonic-gate /* Intel P6, AMD */ 2377c478bd9Sstevel@tonic-gate #define MSR_LBR_FROM 0x1db 2387c478bd9Sstevel@tonic-gate #define MSR_LBR_TO 0x1dc 2397c478bd9Sstevel@tonic-gate #define MSR_LEX_FROM 0x1dd 2407c478bd9Sstevel@tonic-gate #define MSR_LEX_TO 0x1de 2417c478bd9Sstevel@tonic-gate 2427c478bd9Sstevel@tonic-gate /* Intel P4 (pre-Prescott, non P4 M) */ 2437c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_TOS 0x1da 2447c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_0 0x1db 2457c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_1 0x1dc 2467c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_2 0x1dd 2477c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_3 0x1de 2487c478bd9Sstevel@tonic-gate 2497c478bd9Sstevel@tonic-gate /* Intel Pentium M */ 2507c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_TOS 0x1c9 2517c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_0 0x040 2527c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_1 0x041 2537c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_2 0x042 2547c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_3 0x043 2557c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_4 0x044 2567c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_5 0x045 2577c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_6 0x046 2587c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_7 0x047 2597c478bd9Sstevel@tonic-gate 2607c478bd9Sstevel@tonic-gate /* Intel P4 (Prescott) */ 2617c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TOS 0x1da 2627c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_0 0x680 2637c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_1 0x681 2647c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_2 0x682 2657c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_3 0x683 2667c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_4 0x684 2677c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_5 0x685 2687c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_6 0x686 2697c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_7 0x687 2707c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_8 0x688 2717c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_9 0x689 2727c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_10 0x68a 2737c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_11 0x68b 2747c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_12 0x68c 2757c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_13 0x68d 2767c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_14 0x68e 2777c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_15 0x68f 2787c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_0 0x6c0 2797c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_1 0x6c1 2807c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_2 0x6c2 2817c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_3 0x6c3 2827c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_4 0x6c4 2837c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_5 0x6c5 2847c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_6 0x6c6 2857c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_7 0x6c7 2867c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_8 0x6c8 2877c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_9 0x6c9 2887c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_10 0x6ca 2897c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_11 0x6cb 2907c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_12 0x6cc 2917c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_13 0x6cd 2927c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_14 0x6ce 2937c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_15 0x6cf 2947c478bd9Sstevel@tonic-gate 2957c478bd9Sstevel@tonic-gate #define MCI_CTL_VALUE 0xffffffff 2967c478bd9Sstevel@tonic-gate 2977c478bd9Sstevel@tonic-gate #define MTRR_TYPE_UC 0 2987c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WC 1 2997c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WT 4 3007c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WP 5 3017c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WB 6 3021d03c31eSjohnlev #define MTRR_TYPE_UC_ 7 3037c478bd9Sstevel@tonic-gate 3047c478bd9Sstevel@tonic-gate /* 3051d03c31eSjohnlev * For Solaris we set up the page attritubute table in the following way: 3061d03c31eSjohnlev * PAT0 Write-Back 3077c478bd9Sstevel@tonic-gate * PAT1 Write-Through 3081d03c31eSjohnlev * PAT2 Unchacheable- 3097c478bd9Sstevel@tonic-gate * PAT3 Uncacheable 3101d03c31eSjohnlev * PAT4 Write-Back 3111d03c31eSjohnlev * PAT5 Write-Through 3127c478bd9Sstevel@tonic-gate * PAT6 Write-Combine 3137c478bd9Sstevel@tonic-gate * PAT7 Uncacheable 3141d03c31eSjohnlev * The only difference from h/w default is entry 6. 3157c478bd9Sstevel@tonic-gate */ 3161d03c31eSjohnlev #define PAT_DEFAULT_ATTRIBUTE \ 3171d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WB | \ 3181d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WT << 8) | \ 3191d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 3201d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC << 24) | \ 3211d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WB << 32) | \ 3221d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WT << 40) | \ 3231d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WC << 48) | \ 3241d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC << 56)) 3257c478bd9Sstevel@tonic-gate 3267417cfdeSKuriakose Kuruvilla #define X86FSET_LARGEPAGE 0 3277417cfdeSKuriakose Kuruvilla #define X86FSET_TSC 1 3287417cfdeSKuriakose Kuruvilla #define X86FSET_MSR 2 3297417cfdeSKuriakose Kuruvilla #define X86FSET_MTRR 3 3307417cfdeSKuriakose Kuruvilla #define X86FSET_PGE 4 3317417cfdeSKuriakose Kuruvilla #define X86FSET_DE 5 3327417cfdeSKuriakose Kuruvilla #define X86FSET_CMOV 6 3337417cfdeSKuriakose Kuruvilla #define X86FSET_MMX 7 3347417cfdeSKuriakose Kuruvilla #define X86FSET_MCA 8 3357417cfdeSKuriakose Kuruvilla #define X86FSET_PAE 9 3367417cfdeSKuriakose Kuruvilla #define X86FSET_CX8 10 3377417cfdeSKuriakose Kuruvilla #define X86FSET_PAT 11 3387417cfdeSKuriakose Kuruvilla #define X86FSET_SEP 12 3397417cfdeSKuriakose Kuruvilla #define X86FSET_SSE 13 3407417cfdeSKuriakose Kuruvilla #define X86FSET_SSE2 14 3417417cfdeSKuriakose Kuruvilla #define X86FSET_HTT 15 3427417cfdeSKuriakose Kuruvilla #define X86FSET_ASYSC 16 3437417cfdeSKuriakose Kuruvilla #define X86FSET_NX 17 3447417cfdeSKuriakose Kuruvilla #define X86FSET_SSE3 18 3457417cfdeSKuriakose Kuruvilla #define X86FSET_CX16 19 3467417cfdeSKuriakose Kuruvilla #define X86FSET_CMP 20 3477417cfdeSKuriakose Kuruvilla #define X86FSET_TSCP 21 3487417cfdeSKuriakose Kuruvilla #define X86FSET_MWAIT 22 3497417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4A 23 3507417cfdeSKuriakose Kuruvilla #define X86FSET_CPUID 24 3517417cfdeSKuriakose Kuruvilla #define X86FSET_SSSE3 25 3527417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4_1 26 3537417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4_2 27 3547417cfdeSKuriakose Kuruvilla #define X86FSET_1GPG 28 3557417cfdeSKuriakose Kuruvilla #define X86FSET_CLFSH 29 3567417cfdeSKuriakose Kuruvilla #define X86FSET_64 30 3577417cfdeSKuriakose Kuruvilla #define X86FSET_AES 31 3587417cfdeSKuriakose Kuruvilla #define X86FSET_PCLMULQDQ 32 3597c478bd9Sstevel@tonic-gate 360247dbb3dSsudheer /* 361247dbb3dSsudheer * flags to patch tsc_read routine. 362247dbb3dSsudheer */ 363247dbb3dSsudheer #define X86_NO_TSC 0x0 364247dbb3dSsudheer #define X86_HAVE_TSCP 0x1 365247dbb3dSsudheer #define X86_TSC_MFENCE 0x2 36615363b27Ssudheer #define X86_TSC_LFENCE 0x4 367247dbb3dSsudheer 3680e751525SEric Saxe /* 3690e751525SEric Saxe * Intel Deep C-State invariant TSC in leaf 0x80000007. 3700e751525SEric Saxe */ 3710e751525SEric Saxe #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 3720e751525SEric Saxe 373cef70d2cSBill Holler /* 374cef70d2cSBill Holler * Intel Deep C-state always-running local APIC timer 375cef70d2cSBill Holler */ 376cef70d2cSBill Holler #define CPUID_CSTATE_ARAT (0x4) 377cef70d2cSBill Holler 378f21ed392Saubrey.li@intel.com /* 379f21ed392Saubrey.li@intel.com * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 380f21ed392Saubrey.li@intel.com */ 381f21ed392Saubrey.li@intel.com #define CPUID_EPB_SUPPORT (1 << 3) 382f21ed392Saubrey.li@intel.com 383*41afdfa7SKrishnendu Sadhukhan - Sun Microsystems /* 384*41afdfa7SKrishnendu Sadhukhan - Sun Microsystems * Intel TSC deadline timer 385*41afdfa7SKrishnendu Sadhukhan - Sun Microsystems */ 386*41afdfa7SKrishnendu Sadhukhan - Sun Microsystems #define CPUID_DEADLINE_TSC (1 << 24) 387*41afdfa7SKrishnendu Sadhukhan - Sun Microsystems 3887c478bd9Sstevel@tonic-gate /* 3897c478bd9Sstevel@tonic-gate * x86_type is a legacy concept; this is supplanted 3907417cfdeSKuriakose Kuruvilla * for most purposes by x86_featureset; modern CPUs 3917c478bd9Sstevel@tonic-gate * should be X86_TYPE_OTHER 3927c478bd9Sstevel@tonic-gate */ 3937c478bd9Sstevel@tonic-gate #define X86_TYPE_OTHER 0 3947c478bd9Sstevel@tonic-gate #define X86_TYPE_486 1 3957c478bd9Sstevel@tonic-gate #define X86_TYPE_P5 2 3967c478bd9Sstevel@tonic-gate #define X86_TYPE_P6 3 3977c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_486 4 3987c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86L 5 3997c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86 6 4007c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_GXm 7 4017c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86MX 8 4027c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MediaGX 9 4037c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MII 10 4047c478bd9Sstevel@tonic-gate #define X86_TYPE_VIA_CYRIX_III 11 4057c478bd9Sstevel@tonic-gate #define X86_TYPE_P4 12 4067c478bd9Sstevel@tonic-gate 4077c478bd9Sstevel@tonic-gate /* 4087c478bd9Sstevel@tonic-gate * x86_vendor allows us to select between 4097c478bd9Sstevel@tonic-gate * implementation features and helps guide 4107c478bd9Sstevel@tonic-gate * the interpretation of the cpuid instruction. 4117c478bd9Sstevel@tonic-gate */ 412e4b86885SCheng Sean Ye #define X86_VENDOR_Intel 0 413e4b86885SCheng Sean Ye #define X86_VENDORSTR_Intel "GenuineIntel" 414e4b86885SCheng Sean Ye 415e4b86885SCheng Sean Ye #define X86_VENDOR_IntelClone 1 416e4b86885SCheng Sean Ye 417e4b86885SCheng Sean Ye #define X86_VENDOR_AMD 2 418e4b86885SCheng Sean Ye #define X86_VENDORSTR_AMD "AuthenticAMD" 419e4b86885SCheng Sean Ye 420e4b86885SCheng Sean Ye #define X86_VENDOR_Cyrix 3 421e4b86885SCheng Sean Ye #define X86_VENDORSTR_CYRIX "CyrixInstead" 422e4b86885SCheng Sean Ye 423e4b86885SCheng Sean Ye #define X86_VENDOR_UMC 4 424e4b86885SCheng Sean Ye #define X86_VENDORSTR_UMC "UMC UMC UMC " 425e4b86885SCheng Sean Ye 426e4b86885SCheng Sean Ye #define X86_VENDOR_NexGen 5 427e4b86885SCheng Sean Ye #define X86_VENDORSTR_NexGen "NexGenDriven" 428e4b86885SCheng Sean Ye 429e4b86885SCheng Sean Ye #define X86_VENDOR_Centaur 6 430e4b86885SCheng Sean Ye #define X86_VENDORSTR_Centaur "CentaurHauls" 431e4b86885SCheng Sean Ye 432e4b86885SCheng Sean Ye #define X86_VENDOR_Rise 7 433e4b86885SCheng Sean Ye #define X86_VENDORSTR_Rise "RiseRiseRise" 434e4b86885SCheng Sean Ye 435e4b86885SCheng Sean Ye #define X86_VENDOR_SiS 8 436e4b86885SCheng Sean Ye #define X86_VENDORSTR_SiS "SiS SiS SiS " 437e4b86885SCheng Sean Ye 438e4b86885SCheng Sean Ye #define X86_VENDOR_TM 9 439e4b86885SCheng Sean Ye #define X86_VENDORSTR_TM "GenuineTMx86" 440e4b86885SCheng Sean Ye 441e4b86885SCheng Sean Ye #define X86_VENDOR_NSC 10 442e4b86885SCheng Sean Ye #define X86_VENDORSTR_NSC "Geode by NSC" 443e4b86885SCheng Sean Ye 444e4b86885SCheng Sean Ye /* 445e4b86885SCheng Sean Ye * Vendor string max len + \0 446e4b86885SCheng Sean Ye */ 447e4b86885SCheng Sean Ye #define X86_VENDOR_STRLEN 13 4487aec1d6eScindi 4498a40a695Sgavinm /* 4508a40a695Sgavinm * Some vendor/family/model/stepping ranges are commonly grouped under 4518a40a695Sgavinm * a single identifying banner by the vendor. The following encode 4528a40a695Sgavinm * that "revision" in a uint32_t with the 8 most significant bits 4538a40a695Sgavinm * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 4548a40a695Sgavinm * family, and the remaining 16 typically forming a bitmask of revisions 4558a40a695Sgavinm * within that family with more significant bits indicating "later" revisions. 4568a40a695Sgavinm */ 4578a40a695Sgavinm 4588a40a695Sgavinm #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 4598a40a695Sgavinm #define _X86_CHIPREV_VENDOR_SHIFT 24 4608a40a695Sgavinm #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 4618a40a695Sgavinm #define _X86_CHIPREV_FAMILY_SHIFT 16 4628a40a695Sgavinm #define _X86_CHIPREV_REV_MASK 0x0000ffffu 4638a40a695Sgavinm 4648a40a695Sgavinm #define _X86_CHIPREV_VENDOR(x) \ 4658a40a695Sgavinm (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 4668a40a695Sgavinm #define _X86_CHIPREV_FAMILY(x) \ 4678a40a695Sgavinm (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 4688a40a695Sgavinm #define _X86_CHIPREV_REV(x) \ 4698a40a695Sgavinm ((x) & _X86_CHIPREV_REV_MASK) 4708a40a695Sgavinm 4718a40a695Sgavinm /* True if x matches in vendor and family and if x matches the given rev mask */ 4728a40a695Sgavinm #define X86_CHIPREV_MATCH(x, mask) \ 4738a40a695Sgavinm (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 4748a40a695Sgavinm _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 4758a40a695Sgavinm ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 4768a40a695Sgavinm 4772c8230b0SSrihari Venkatesan /* True if x matches in vendor and family, and rev is at least minx */ 4788a40a695Sgavinm #define X86_CHIPREV_ATLEAST(x, minx) \ 4798a40a695Sgavinm (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 4808a40a695Sgavinm _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 4818a40a695Sgavinm _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 4828a40a695Sgavinm 4838a40a695Sgavinm #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 4848a40a695Sgavinm ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 4858a40a695Sgavinm (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 4868a40a695Sgavinm 4872c8230b0SSrihari Venkatesan /* True if x matches in vendor, and family is at least minx */ 4882c8230b0SSrihari Venkatesan #define X86_CHIPFAM_ATLEAST(x, minx) \ 4892c8230b0SSrihari Venkatesan (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 4902c8230b0SSrihari Venkatesan _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 4912c8230b0SSrihari Venkatesan 4928a40a695Sgavinm /* Revision default */ 4938a40a695Sgavinm #define X86_CHIPREV_UNKNOWN 0x0 4948a40a695Sgavinm 4958a40a695Sgavinm /* 49620c794b3Sgavinm * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 49720c794b3Sgavinm * sufficiently different that we will distinguish them; in all other 4988a40a695Sgavinm * case we will identify the major revision. 4998a40a695Sgavinm */ 5008a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 5018a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 5028a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 5038a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 5048a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 5058a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 5068a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 50720c794b3Sgavinm 50820c794b3Sgavinm /* 50920c794b3Sgavinm * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 51020c794b3Sgavinm */ 51120c794b3Sgavinm #define X86_CHIPREV_AMD_10_REV_A \ 51231725658Sksadhukh _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 51320c794b3Sgavinm #define X86_CHIPREV_AMD_10_REV_B \ 51420c794b3Sgavinm _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 51564452efdSKit Chow #define X86_CHIPREV_AMD_10_REV_C \ 51664452efdSKit Chow _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 51789e921d5SKuriakose Kuruvilla #define X86_CHIPREV_AMD_10_REV_D \ 51889e921d5SKuriakose Kuruvilla _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 51989e921d5SKuriakose Kuruvilla 52089e921d5SKuriakose Kuruvilla /* 52189e921d5SKuriakose Kuruvilla * Definitions for AMD Family 0x11. 52289e921d5SKuriakose Kuruvilla */ 52389e921d5SKuriakose Kuruvilla #define X86_CHIPREV_AMD_11 \ 524a24e89c4SKuriakose Kuruvilla _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0001) 52589e921d5SKuriakose Kuruvilla 5268a40a695Sgavinm 5278a40a695Sgavinm /* 5288a40a695Sgavinm * Various socket/package types, extended as the need to distinguish 5298a40a695Sgavinm * a new type arises. The top 8 byte identfies the vendor and the 5308a40a695Sgavinm * remaining 24 bits describe 24 socket types. 5318a40a695Sgavinm */ 5328a40a695Sgavinm 5338a40a695Sgavinm #define _X86_SOCKET_VENDOR_SHIFT 24 5348a40a695Sgavinm #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 5358a40a695Sgavinm #define _X86_SOCKET_TYPE_MASK 0x00ffffff 5368a40a695Sgavinm #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 5378a40a695Sgavinm 5388a40a695Sgavinm #define _X86_SOCKET_MKVAL(vendor, bitval) \ 5398a40a695Sgavinm ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 5408a40a695Sgavinm 5418a40a695Sgavinm #define X86_SOCKET_MATCH(s, mask) \ 5428a40a695Sgavinm (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 543a24e89c4SKuriakose Kuruvilla (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 5448a40a695Sgavinm 5458a40a695Sgavinm #define X86_SOCKET_UNKNOWN 0x0 5468a40a695Sgavinm /* 5478a40a695Sgavinm * AMD socket types 5488a40a695Sgavinm */ 5498a40a695Sgavinm #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 5508a40a695Sgavinm #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 5518a40a695Sgavinm #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 5528a40a695Sgavinm #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 5538a40a695Sgavinm #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 5548a40a695Sgavinm #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 555a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 556a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 557a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 558a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 559a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 560a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 561bd15239eSSrihari Venkatesan #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 562bd15239eSSrihari Venkatesan #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 5638a40a695Sgavinm 5647c478bd9Sstevel@tonic-gate #if !defined(_ASM) 5657c478bd9Sstevel@tonic-gate 5667c478bd9Sstevel@tonic-gate #if defined(_KERNEL) || defined(_KMEMUSER) 5677c478bd9Sstevel@tonic-gate 5687417cfdeSKuriakose Kuruvilla extern void *x86_featureset; 5697417cfdeSKuriakose Kuruvilla 5707417cfdeSKuriakose Kuruvilla extern void free_x86_featureset(void *featureset); 5717417cfdeSKuriakose Kuruvilla extern boolean_t is_x86_feature(void *featureset, uint_t feature); 5727417cfdeSKuriakose Kuruvilla extern void add_x86_feature(void *featureset, uint_t feature); 5737417cfdeSKuriakose Kuruvilla extern void remove_x86_feature(void *featureset, uint_t feature); 5747417cfdeSKuriakose Kuruvilla extern boolean_t compare_x86_featureset(void *setA, void *setB); 5757417cfdeSKuriakose Kuruvilla extern void print_x86_featureset(void *featureset); 5767417cfdeSKuriakose Kuruvilla 5777417cfdeSKuriakose Kuruvilla 5787c478bd9Sstevel@tonic-gate extern uint_t x86_type; 5797c478bd9Sstevel@tonic-gate extern uint_t x86_vendor; 58086c1f4dcSVikram Hegde extern uint_t x86_clflush_size; 5817c478bd9Sstevel@tonic-gate 5827c478bd9Sstevel@tonic-gate extern uint_t pentiumpro_bug4046376; 5837c478bd9Sstevel@tonic-gate extern uint_t pentiumpro_bug4064495; 5847c478bd9Sstevel@tonic-gate 5857c478bd9Sstevel@tonic-gate extern uint_t enable486; 5867c478bd9Sstevel@tonic-gate 5877c478bd9Sstevel@tonic-gate extern const char CyrixInstead[]; 5887c478bd9Sstevel@tonic-gate 5897c478bd9Sstevel@tonic-gate #endif 5907c478bd9Sstevel@tonic-gate 5917c478bd9Sstevel@tonic-gate #if defined(_KERNEL) 5927c478bd9Sstevel@tonic-gate 5938949bcd6Sandrei /* 5948949bcd6Sandrei * This structure is used to pass arguments and get return values back 5958949bcd6Sandrei * from the CPUID instruction in __cpuid_insn() routine. 5968949bcd6Sandrei */ 5978949bcd6Sandrei struct cpuid_regs { 5988949bcd6Sandrei uint32_t cp_eax; 5998949bcd6Sandrei uint32_t cp_ebx; 6008949bcd6Sandrei uint32_t cp_ecx; 6018949bcd6Sandrei uint32_t cp_edx; 6028949bcd6Sandrei }; 6037c478bd9Sstevel@tonic-gate 6040ac7d7d8Skucharsk extern uint64_t rdmsr(uint_t); 6050ac7d7d8Skucharsk extern void wrmsr(uint_t, const uint64_t); 606ee88d2b9Skchow extern uint64_t xrdmsr(uint_t); 607ee88d2b9Skchow extern void xwrmsr(uint_t, const uint64_t); 608ae115bc7Smrj extern int checked_rdmsr(uint_t, uint64_t *); 609ae115bc7Smrj extern int checked_wrmsr(uint_t, uint64_t); 610ae115bc7Smrj 6117c478bd9Sstevel@tonic-gate extern void invalidate_cache(void); 6127c478bd9Sstevel@tonic-gate extern ulong_t getcr4(void); 6137c478bd9Sstevel@tonic-gate extern void setcr4(ulong_t); 614ae115bc7Smrj 6157c478bd9Sstevel@tonic-gate extern void mtrr_sync(void); 6167c478bd9Sstevel@tonic-gate 6177c478bd9Sstevel@tonic-gate extern void cpu_fast_syscall_enable(void *); 6187c478bd9Sstevel@tonic-gate extern void cpu_fast_syscall_disable(void *); 6197c478bd9Sstevel@tonic-gate 6207c478bd9Sstevel@tonic-gate struct cpu; 6217c478bd9Sstevel@tonic-gate 6227c478bd9Sstevel@tonic-gate extern int cpuid_checkpass(struct cpu *, int); 6238949bcd6Sandrei extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 6248949bcd6Sandrei extern uint32_t __cpuid_insn(struct cpuid_regs *); 6257c478bd9Sstevel@tonic-gate extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 6267c478bd9Sstevel@tonic-gate extern int cpuid_getidstr(struct cpu *, char *, size_t); 6277c478bd9Sstevel@tonic-gate extern const char *cpuid_getvendorstr(struct cpu *); 6287c478bd9Sstevel@tonic-gate extern uint_t cpuid_getvendor(struct cpu *); 6297c478bd9Sstevel@tonic-gate extern uint_t cpuid_getfamily(struct cpu *); 6307c478bd9Sstevel@tonic-gate extern uint_t cpuid_getmodel(struct cpu *); 6317c478bd9Sstevel@tonic-gate extern uint_t cpuid_getstep(struct cpu *); 6322449e17fSsherrym extern uint_t cpuid_getsig(struct cpu *); 6337c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 6348949bcd6Sandrei extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 635d129bde2Sesaxe extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 636d129bde2Sesaxe extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 637fb2f18f8Sesaxe extern int cpuid_get_chipid(struct cpu *); 638fb2f18f8Sesaxe extern id_t cpuid_get_coreid(struct cpu *); 63910569901Sgavinm extern int cpuid_get_pkgcoreid(struct cpu *); 640fb2f18f8Sesaxe extern int cpuid_get_clogid(struct cpu *); 641b885580bSAlexander Kolbasov extern int cpuid_get_cacheid(struct cpu *); 642fa96bd91SMichael Corcoran extern uint32_t cpuid_get_apicid(struct cpu *); 6438031591dSSrihari Venkatesan extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 6448031591dSSrihari Venkatesan extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 6458949bcd6Sandrei extern int cpuid_is_cmt(struct cpu *); 6467c478bd9Sstevel@tonic-gate extern int cpuid_syscall32_insn(struct cpu *); 6477c478bd9Sstevel@tonic-gate extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 6488a40a695Sgavinm 6498a40a695Sgavinm extern uint32_t cpuid_getchiprev(struct cpu *); 6508a40a695Sgavinm extern const char *cpuid_getchiprevstr(struct cpu *); 6518a40a695Sgavinm extern uint32_t cpuid_getsockettype(struct cpu *); 65289e921d5SKuriakose Kuruvilla extern const char *cpuid_getsocketstr(struct cpu *); 6537c478bd9Sstevel@tonic-gate 6542ef50f01SJoe Bonasera extern int cpuid_have_cr8access(struct cpu *); 6552ef50f01SJoe Bonasera 6567c478bd9Sstevel@tonic-gate extern int cpuid_opteron_erratum(struct cpu *, uint_t); 6577c478bd9Sstevel@tonic-gate 6587c478bd9Sstevel@tonic-gate struct cpuid_info; 6597c478bd9Sstevel@tonic-gate 6607c478bd9Sstevel@tonic-gate extern void setx86isalist(void); 661ae115bc7Smrj extern void cpuid_alloc_space(struct cpu *); 662ae115bc7Smrj extern void cpuid_free_space(struct cpu *); 6637417cfdeSKuriakose Kuruvilla extern void *cpuid_pass1(struct cpu *); 6647c478bd9Sstevel@tonic-gate extern void cpuid_pass2(struct cpu *); 6657c478bd9Sstevel@tonic-gate extern void cpuid_pass3(struct cpu *); 6667c478bd9Sstevel@tonic-gate extern uint_t cpuid_pass4(struct cpu *); 667fa96bd91SMichael Corcoran extern void cpuid_set_cpu_properties(void *, processorid_t, 668fa96bd91SMichael Corcoran struct cpuid_info *); 6697c478bd9Sstevel@tonic-gate 6707c478bd9Sstevel@tonic-gate extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 6717c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 672843e1988Sjohnlev 673843e1988Sjohnlev #if !defined(__xpv) 6745b8a6efeSbholler extern uint32_t *cpuid_mwait_alloc(struct cpu *); 6755b8a6efeSbholler extern void cpuid_mwait_free(struct cpu *); 6760e751525SEric Saxe extern int cpuid_deep_cstates_supported(void); 677cef70d2cSBill Holler extern int cpuid_arat_supported(void); 678f21ed392Saubrey.li@intel.com extern int cpuid_iepb_supported(struct cpu *); 679*41afdfa7SKrishnendu Sadhukhan - Sun Microsystems extern int cpuid_deadline_tsc_supported(void); 6807997e108SSurya Prakki extern int vmware_platform(void); 681843e1988Sjohnlev #endif 6827c478bd9Sstevel@tonic-gate 6832449e17fSsherrym struct cpu_ucode_info; 6842449e17fSsherrym 6852449e17fSsherrym extern void ucode_alloc_space(struct cpu *); 6862449e17fSsherrym extern void ucode_free_space(struct cpu *); 6872449e17fSsherrym extern void ucode_check(struct cpu *); 688adc586deSMark Johnson extern void ucode_cleanup(); 6892449e17fSsherrym 690247dbb3dSsudheer #if !defined(__xpv) 691247dbb3dSsudheer extern char _tsc_mfence_start; 692247dbb3dSsudheer extern char _tsc_mfence_end; 693247dbb3dSsudheer extern char _tscp_start; 694247dbb3dSsudheer extern char _tscp_end; 695247dbb3dSsudheer extern char _no_rdtsc_start; 696247dbb3dSsudheer extern char _no_rdtsc_end; 69715363b27Ssudheer extern char _tsc_lfence_start; 69815363b27Ssudheer extern char _tsc_lfence_end; 699247dbb3dSsudheer #endif 700247dbb3dSsudheer 70122cc0e45SBill Holler #if !defined(__xpv) 70222cc0e45SBill Holler extern char bcopy_patch_start; 70322cc0e45SBill Holler extern char bcopy_patch_end; 70422cc0e45SBill Holler extern char bcopy_ck_size; 70522cc0e45SBill Holler #endif 70622cc0e45SBill Holler 707e774b42bSBill Holler extern void post_startup_cpu_fixups(void); 708e774b42bSBill Holler 7097c478bd9Sstevel@tonic-gate extern uint_t workaround_errata(struct cpu *); 7107c478bd9Sstevel@tonic-gate 7117c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 7127c478bd9Sstevel@tonic-gate extern int opteron_erratum_93; 7137c478bd9Sstevel@tonic-gate #endif 7147c478bd9Sstevel@tonic-gate 7157c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 7167c478bd9Sstevel@tonic-gate extern int opteron_erratum_91; 7177c478bd9Sstevel@tonic-gate #endif 7187c478bd9Sstevel@tonic-gate 7197c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 7207c478bd9Sstevel@tonic-gate extern int opteron_erratum_100; 7217c478bd9Sstevel@tonic-gate #endif 7227c478bd9Sstevel@tonic-gate 7237c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 7247c478bd9Sstevel@tonic-gate extern int opteron_erratum_121; 7257c478bd9Sstevel@tonic-gate #endif 7267c478bd9Sstevel@tonic-gate 727ee88d2b9Skchow #if defined(OPTERON_WORKAROUND_6323525) 728ee88d2b9Skchow extern int opteron_workaround_6323525; 729ee88d2b9Skchow extern void patch_workaround_6323525(void); 730ee88d2b9Skchow #endif 731ee88d2b9Skchow 732b9bfdccdSStuart Maybee extern int get_hwenv(void); 733b9bfdccdSStuart Maybee extern int is_controldom(void); 734b9bfdccdSStuart Maybee 735b9bfdccdSStuart Maybee /* 736b9bfdccdSStuart Maybee * Defined hardware environments 737b9bfdccdSStuart Maybee */ 738b9bfdccdSStuart Maybee #define HW_NATIVE 0x00 /* Running on bare metal */ 739b9bfdccdSStuart Maybee #define HW_XEN_PV 0x01 /* Running on Xen Hypervisor paravirutualized */ 740b9bfdccdSStuart Maybee #define HW_XEN_HVM 0x02 /* Running on Xen hypervisor HVM */ 741b9bfdccdSStuart Maybee #define HW_VMWARE 0x03 /* Running on VMware hypervisor */ 742b9bfdccdSStuart Maybee 7437c478bd9Sstevel@tonic-gate #endif /* _KERNEL */ 7447c478bd9Sstevel@tonic-gate 7457c478bd9Sstevel@tonic-gate #endif 7467c478bd9Sstevel@tonic-gate 7477c478bd9Sstevel@tonic-gate #ifdef __cplusplus 7487c478bd9Sstevel@tonic-gate } 7497c478bd9Sstevel@tonic-gate #endif 7507c478bd9Sstevel@tonic-gate 7517c478bd9Sstevel@tonic-gate #endif /* _SYS_X86_ARCHEXT_H */ 752