17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5ee88d2b9Skchow * Common Development and Distribution License (the "License"). 6ee88d2b9Skchow * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 227417cfdeSKuriakose Kuruvilla * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23cfe84b82SMatt Amdur * Copyright (c) 2011 by Delphix. All rights reserved. 2479ec9da8SYuri Pankov * Copyright 2012 Nexenta Systems, Inc. All rights reserved. 257c478bd9Sstevel@tonic-gate */ 26cef70d2cSBill Holler /* 2741afdfa7SKrishnendu Sadhukhan - Sun Microsystems * Copyright (c) 2010, Intel Corporation. 28cef70d2cSBill Holler * All rights reserved. 29cef70d2cSBill Holler */ 30faa20166SBryan Cantrill /* 31*245ac945SRobert Mustacchi * Copyright (c) 2015, Joyent, Inc. 3279321794SJens Elkner * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 3379321794SJens Elkner * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 346eedf6a5SJosef 'Jeff' Sipek * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 35faa20166SBryan Cantrill */ 367c478bd9Sstevel@tonic-gate 377c478bd9Sstevel@tonic-gate #ifndef _SYS_X86_ARCHEXT_H 387c478bd9Sstevel@tonic-gate #define _SYS_X86_ARCHEXT_H 397c478bd9Sstevel@tonic-gate 407c478bd9Sstevel@tonic-gate #if !defined(_ASM) 417c478bd9Sstevel@tonic-gate #include <sys/regset.h> 427c478bd9Sstevel@tonic-gate #include <sys/processor.h> 437c478bd9Sstevel@tonic-gate #include <vm/seg_enum.h> 447c478bd9Sstevel@tonic-gate #include <vm/page.h> 457c478bd9Sstevel@tonic-gate #endif /* _ASM */ 467c478bd9Sstevel@tonic-gate 477c478bd9Sstevel@tonic-gate #ifdef __cplusplus 487c478bd9Sstevel@tonic-gate extern "C" { 497c478bd9Sstevel@tonic-gate #endif 507c478bd9Sstevel@tonic-gate 517c478bd9Sstevel@tonic-gate /* 527c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (standard function 1) 537c478bd9Sstevel@tonic-gate */ 547c478bd9Sstevel@tonic-gate 557c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 567c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 577c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 587c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 597c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 607c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 617c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 627c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 637c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 647c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 657c478bd9Sstevel@tonic-gate /* 0x400 - reserved */ 667c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 677c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 687c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 697c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 707c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 717c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 727c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 737c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 747c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 757c478bd9Sstevel@tonic-gate /* 0x100000 - reserved */ 767c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 777c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 787c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 797c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 807c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 817c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 827c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 837c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 847c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85ae115bc7Smrj #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 867c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 877c478bd9Sstevel@tonic-gate 88ae115bc7Smrj #define FMT_CPUID_INTC_EDX \ 89ae115bc7Smrj "\20" \ 90ae115bc7Smrj "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 91ae115bc7Smrj "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 92ae115bc7Smrj "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 937c478bd9Sstevel@tonic-gate "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 947c478bd9Sstevel@tonic-gate 957c478bd9Sstevel@tonic-gate /* 967c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %ecx (standard function 1) 977c478bd9Sstevel@tonic-gate */ 987c478bd9Sstevel@tonic-gate 997c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 100a50a8b93SKuriakose Kuruvilla #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 1017c478bd9Sstevel@tonic-gate /* 0x00000004 - reserved */ 1027c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 1037c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 104ae115bc7Smrj #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 105ae115bc7Smrj #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 1067c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 1077c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 108ae115bc7Smrj #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 1097c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 1107c478bd9Sstevel@tonic-gate /* 0x00000800 - reserved */ 111*245ac945SRobert Mustacchi #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 112ae115bc7Smrj #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 113ae115bc7Smrj #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 114ae115bc7Smrj /* 0x00008000 - reserved */ 115ae115bc7Smrj /* 0x00010000 - reserved */ 116ae115bc7Smrj /* 0x00020000 - reserved */ 117ae115bc7Smrj #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 118d0f8ff6eSkk #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 119d0f8ff6eSkk #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 1206eedf6a5SJosef 'Jeff' Sipek #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 1215087e485SKrishnendu Sadhukhan - Sun Microsystems #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 122f8801251Skk #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 123a50a8b93SKuriakose Kuruvilla #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 1247af88ac7SKuriakose Kuruvilla #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 1257af88ac7SKuriakose Kuruvilla #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 1267af88ac7SKuriakose Kuruvilla #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 127ebb8ac07SRobert Mustacchi #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 128ebb8ac07SRobert Mustacchi #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 12979ec9da8SYuri Pankov #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 130ae115bc7Smrj 131ae115bc7Smrj #define FMT_CPUID_INTC_ECX \ 132ae115bc7Smrj "\20" \ 133ebb8ac07SRobert Mustacchi "\37rdrand\36f16c\35avx\34osxsav\33xsave" \ 134a50a8b93SKuriakose Kuruvilla "\32aes" \ 1356eedf6a5SJosef 'Jeff' Sipek "\30popcnt\27movbe\26x2apic\25sse4.2\24sse4.1\23dca" \ 136ae115bc7Smrj "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 137a50a8b93SKuriakose Kuruvilla "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3" 1387c478bd9Sstevel@tonic-gate 1397c478bd9Sstevel@tonic-gate /* 1407c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (extended function 0x80000001) 1417c478bd9Sstevel@tonic-gate */ 1427c478bd9Sstevel@tonic-gate 1437c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 1447c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 1457c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 1467c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 1477c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 1487c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 1497c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 1507c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 1517c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 1527c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 1537c478bd9Sstevel@tonic-gate /* 0x00000400 - sysc on K6m6 */ 1547c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 1557c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 1567c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 1577c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 1587c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 159ae115bc7Smrj #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 160ae115bc7Smrj #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 1617c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 1627c478bd9Sstevel@tonic-gate /* 0x00040000 - reserved */ 1637c478bd9Sstevel@tonic-gate /* 0x00080000 - reserved */ 1647c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 1657c478bd9Sstevel@tonic-gate /* 0x00200000 - reserved */ 1667c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 1677c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 1687c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 169ae115bc7Smrj #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 17002bc52beSkchow #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 171ae115bc7Smrj #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 1727c478bd9Sstevel@tonic-gate /* 0x10000000 - reserved */ 1737c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 1747c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 1757c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 1767c478bd9Sstevel@tonic-gate 1777c478bd9Sstevel@tonic-gate #define FMT_CPUID_AMD_EDX \ 1787c478bd9Sstevel@tonic-gate "\20" \ 179ae115bc7Smrj "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 1807c478bd9Sstevel@tonic-gate "\30mmx\27mmxext\25nx\22pse\21pat" \ 1817c478bd9Sstevel@tonic-gate "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 1827c478bd9Sstevel@tonic-gate "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 1837c478bd9Sstevel@tonic-gate 184ae115bc7Smrj #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 185ae115bc7Smrj #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 186ae115bc7Smrj #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 187ae115bc7Smrj #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 188ae115bc7Smrj #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 189f8801251Skk #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 190f8801251Skk #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 191512cf780Skchow #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 192512cf780Skchow #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 193512cf780Skchow #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 194512cf780Skchow #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 195512cf780Skchow #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ 196512cf780Skchow #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 197512cf780Skchow #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 1987660e73fSHans Rosenfeld #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 1997c478bd9Sstevel@tonic-gate 2007c478bd9Sstevel@tonic-gate #define FMT_CPUID_AMD_ECX \ 2017c478bd9Sstevel@tonic-gate "\20" \ 2027660e73fSHans Rosenfeld "\22topoext" \ 203512cf780Skchow "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \ 204f8801251Skk "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 205ae115bc7Smrj 206ae115bc7Smrj /* 207ae115bc7Smrj * Intel now seems to have claimed part of the "extended" function 208ae115bc7Smrj * space that we previously for non-Intel implementors to use. 209ae115bc7Smrj * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 210ae115bc7Smrj * is available in long mode i.e. what AMD indicate using bit 0. 211ae115bc7Smrj * On the other hand, everything else is labelled as reserved. 212ae115bc7Smrj */ 213ae115bc7Smrj #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 214ae115bc7Smrj 215*245ac945SRobert Mustacchi /* 216*245ac945SRobert Mustacchi * Intel also uses cpuid leaf 7 to have additional instructions and features. 217*245ac945SRobert Mustacchi * Like some other leaves, but unlink the current ones we care about, it 218*245ac945SRobert Mustacchi * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 219*245ac945SRobert Mustacchi * with the potential use of additional sub-leaves in the future, we now 220*245ac945SRobert Mustacchi * specifically label the EBX features with their leaf and sub-leaf. 221*245ac945SRobert Mustacchi */ 222*245ac945SRobert Mustacchi #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 223*245ac945SRobert Mustacchi #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 224*245ac945SRobert Mustacchi #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 Instrs */ 2257c478bd9Sstevel@tonic-gate 2267c478bd9Sstevel@tonic-gate #define P5_MCHADDR 0x0 2277c478bd9Sstevel@tonic-gate #define P5_CESR 0x11 2287c478bd9Sstevel@tonic-gate #define P5_CTR0 0x12 2297c478bd9Sstevel@tonic-gate #define P5_CTR1 0x13 2307c478bd9Sstevel@tonic-gate 2317c478bd9Sstevel@tonic-gate #define K5_MCHADDR 0x0 2327c478bd9Sstevel@tonic-gate #define K5_MCHTYPE 0x01 2337c478bd9Sstevel@tonic-gate #define K5_TSC 0x10 2347c478bd9Sstevel@tonic-gate #define K5_TR12 0x12 2357c478bd9Sstevel@tonic-gate 2361d03c31eSjohnlev #define REG_PAT 0x277 2371d03c31eSjohnlev 2387c478bd9Sstevel@tonic-gate #define REG_MC0_CTL 0x400 2397c478bd9Sstevel@tonic-gate #define REG_MC5_MISC 0x417 2407c478bd9Sstevel@tonic-gate #define REG_PERFCTR0 0xc1 2417c478bd9Sstevel@tonic-gate #define REG_PERFCTR1 0xc2 2427c478bd9Sstevel@tonic-gate 2437c478bd9Sstevel@tonic-gate #define REG_PERFEVNT0 0x186 2447c478bd9Sstevel@tonic-gate #define REG_PERFEVNT1 0x187 2457c478bd9Sstevel@tonic-gate 2467c478bd9Sstevel@tonic-gate #define REG_TSC 0x10 /* timestamp counter */ 2477c478bd9Sstevel@tonic-gate #define REG_APIC_BASE_MSR 0x1b 248b6917abeSmishra #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 2497c478bd9Sstevel@tonic-gate 250e774b42bSBill Holler #if !defined(__xpv) 251e774b42bSBill Holler /* 252e774b42bSBill Holler * AMD C1E 253e774b42bSBill Holler */ 254e774b42bSBill Holler #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 255e774b42bSBill Holler #define AMD_ACTONCMPHALT_SHIFT 27 256e774b42bSBill Holler #define AMD_ACTONCMPHALT_MASK 3 257e774b42bSBill Holler #endif 258e774b42bSBill Holler 2597c478bd9Sstevel@tonic-gate #define MSR_DEBUGCTL 0x1d9 2607c478bd9Sstevel@tonic-gate 2617c478bd9Sstevel@tonic-gate #define DEBUGCTL_LBR 0x01 2627c478bd9Sstevel@tonic-gate #define DEBUGCTL_BTF 0x02 2637c478bd9Sstevel@tonic-gate 2647c478bd9Sstevel@tonic-gate /* Intel P6, AMD */ 2657c478bd9Sstevel@tonic-gate #define MSR_LBR_FROM 0x1db 2667c478bd9Sstevel@tonic-gate #define MSR_LBR_TO 0x1dc 2677c478bd9Sstevel@tonic-gate #define MSR_LEX_FROM 0x1dd 2687c478bd9Sstevel@tonic-gate #define MSR_LEX_TO 0x1de 2697c478bd9Sstevel@tonic-gate 2707c478bd9Sstevel@tonic-gate /* Intel P4 (pre-Prescott, non P4 M) */ 2717c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_TOS 0x1da 2727c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_0 0x1db 2737c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_1 0x1dc 2747c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_2 0x1dd 2757c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_3 0x1de 2767c478bd9Sstevel@tonic-gate 2777c478bd9Sstevel@tonic-gate /* Intel Pentium M */ 2787c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_TOS 0x1c9 2797c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_0 0x040 2807c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_1 0x041 2817c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_2 0x042 2827c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_3 0x043 2837c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_4 0x044 2847c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_5 0x045 2857c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_6 0x046 2867c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_7 0x047 2877c478bd9Sstevel@tonic-gate 2887c478bd9Sstevel@tonic-gate /* Intel P4 (Prescott) */ 2897c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TOS 0x1da 2907c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_0 0x680 2917c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_1 0x681 2927c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_2 0x682 2937c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_3 0x683 2947c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_4 0x684 2957c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_5 0x685 2967c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_6 0x686 2977c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_7 0x687 2987c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_8 0x688 2997c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_9 0x689 3007c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_10 0x68a 3017c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_11 0x68b 3027c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_12 0x68c 3037c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_13 0x68d 3047c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_14 0x68e 3057c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_15 0x68f 3067c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_0 0x6c0 3077c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_1 0x6c1 3087c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_2 0x6c2 3097c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_3 0x6c3 3107c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_4 0x6c4 3117c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_5 0x6c5 3127c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_6 0x6c6 3137c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_7 0x6c7 3147c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_8 0x6c8 3157c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_9 0x6c9 3167c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_10 0x6ca 3177c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_11 0x6cb 3187c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_12 0x6cc 3197c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_13 0x6cd 3207c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_14 0x6ce 3217c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_15 0x6cf 3227c478bd9Sstevel@tonic-gate 3237c478bd9Sstevel@tonic-gate #define MCI_CTL_VALUE 0xffffffff 3247c478bd9Sstevel@tonic-gate 3257c478bd9Sstevel@tonic-gate #define MTRR_TYPE_UC 0 3267c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WC 1 3277c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WT 4 3287c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WP 5 3297c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WB 6 3301d03c31eSjohnlev #define MTRR_TYPE_UC_ 7 3317c478bd9Sstevel@tonic-gate 3327c478bd9Sstevel@tonic-gate /* 3331d03c31eSjohnlev * For Solaris we set up the page attritubute table in the following way: 3341d03c31eSjohnlev * PAT0 Write-Back 3357c478bd9Sstevel@tonic-gate * PAT1 Write-Through 3361d03c31eSjohnlev * PAT2 Unchacheable- 3377c478bd9Sstevel@tonic-gate * PAT3 Uncacheable 3381d03c31eSjohnlev * PAT4 Write-Back 3391d03c31eSjohnlev * PAT5 Write-Through 3407c478bd9Sstevel@tonic-gate * PAT6 Write-Combine 3417c478bd9Sstevel@tonic-gate * PAT7 Uncacheable 3421d03c31eSjohnlev * The only difference from h/w default is entry 6. 3437c478bd9Sstevel@tonic-gate */ 3441d03c31eSjohnlev #define PAT_DEFAULT_ATTRIBUTE \ 3451d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WB | \ 3461d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WT << 8) | \ 3471d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 3481d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC << 24) | \ 3491d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WB << 32) | \ 3501d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WT << 40) | \ 3511d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WC << 48) | \ 3521d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC << 56)) 3537c478bd9Sstevel@tonic-gate 3547417cfdeSKuriakose Kuruvilla #define X86FSET_LARGEPAGE 0 3557417cfdeSKuriakose Kuruvilla #define X86FSET_TSC 1 3567417cfdeSKuriakose Kuruvilla #define X86FSET_MSR 2 3577417cfdeSKuriakose Kuruvilla #define X86FSET_MTRR 3 3587417cfdeSKuriakose Kuruvilla #define X86FSET_PGE 4 3597417cfdeSKuriakose Kuruvilla #define X86FSET_DE 5 3607417cfdeSKuriakose Kuruvilla #define X86FSET_CMOV 6 3616eedf6a5SJosef 'Jeff' Sipek #define X86FSET_MMX 7 3627417cfdeSKuriakose Kuruvilla #define X86FSET_MCA 8 3637417cfdeSKuriakose Kuruvilla #define X86FSET_PAE 9 3647417cfdeSKuriakose Kuruvilla #define X86FSET_CX8 10 3657417cfdeSKuriakose Kuruvilla #define X86FSET_PAT 11 3667417cfdeSKuriakose Kuruvilla #define X86FSET_SEP 12 3677417cfdeSKuriakose Kuruvilla #define X86FSET_SSE 13 3687417cfdeSKuriakose Kuruvilla #define X86FSET_SSE2 14 3697417cfdeSKuriakose Kuruvilla #define X86FSET_HTT 15 3707417cfdeSKuriakose Kuruvilla #define X86FSET_ASYSC 16 3717417cfdeSKuriakose Kuruvilla #define X86FSET_NX 17 3727417cfdeSKuriakose Kuruvilla #define X86FSET_SSE3 18 3737417cfdeSKuriakose Kuruvilla #define X86FSET_CX16 19 3747417cfdeSKuriakose Kuruvilla #define X86FSET_CMP 20 3757417cfdeSKuriakose Kuruvilla #define X86FSET_TSCP 21 3767417cfdeSKuriakose Kuruvilla #define X86FSET_MWAIT 22 3777417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4A 23 3787417cfdeSKuriakose Kuruvilla #define X86FSET_CPUID 24 3797417cfdeSKuriakose Kuruvilla #define X86FSET_SSSE3 25 3807417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4_1 26 3817417cfdeSKuriakose Kuruvilla #define X86FSET_SSE4_2 27 3827417cfdeSKuriakose Kuruvilla #define X86FSET_1GPG 28 3837417cfdeSKuriakose Kuruvilla #define X86FSET_CLFSH 29 3847417cfdeSKuriakose Kuruvilla #define X86FSET_64 30 3857417cfdeSKuriakose Kuruvilla #define X86FSET_AES 31 3867417cfdeSKuriakose Kuruvilla #define X86FSET_PCLMULQDQ 32 3877af88ac7SKuriakose Kuruvilla #define X86FSET_XSAVE 33 3887af88ac7SKuriakose Kuruvilla #define X86FSET_AVX 34 389faa20166SBryan Cantrill #define X86FSET_VMX 35 390faa20166SBryan Cantrill #define X86FSET_SVM 36 3917660e73fSHans Rosenfeld #define X86FSET_TOPOEXT 37 392ebb8ac07SRobert Mustacchi #define X86FSET_F16C 38 393ebb8ac07SRobert Mustacchi #define X86FSET_RDRAND 39 3946eedf6a5SJosef 'Jeff' Sipek #define X86FSET_X2APIC 40 395*245ac945SRobert Mustacchi #define X86FSET_AVX2 41 396*245ac945SRobert Mustacchi #define X86FSET_BMI1 42 397*245ac945SRobert Mustacchi #define X86FSET_BMI2 43 398*245ac945SRobert Mustacchi #define X86FSET_FMA 44 3997c478bd9Sstevel@tonic-gate 400247dbb3dSsudheer /* 401247dbb3dSsudheer * flags to patch tsc_read routine. 402247dbb3dSsudheer */ 403247dbb3dSsudheer #define X86_NO_TSC 0x0 404247dbb3dSsudheer #define X86_HAVE_TSCP 0x1 405247dbb3dSsudheer #define X86_TSC_MFENCE 0x2 40615363b27Ssudheer #define X86_TSC_LFENCE 0x4 407247dbb3dSsudheer 4080e751525SEric Saxe /* 4090e751525SEric Saxe * Intel Deep C-State invariant TSC in leaf 0x80000007. 4100e751525SEric Saxe */ 4110e751525SEric Saxe #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 4120e751525SEric Saxe 413cef70d2cSBill Holler /* 414cef70d2cSBill Holler * Intel Deep C-state always-running local APIC timer 415cef70d2cSBill Holler */ 416cef70d2cSBill Holler #define CPUID_CSTATE_ARAT (0x4) 417cef70d2cSBill Holler 418f21ed392Saubrey.li@intel.com /* 419f21ed392Saubrey.li@intel.com * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 420f21ed392Saubrey.li@intel.com */ 421f21ed392Saubrey.li@intel.com #define CPUID_EPB_SUPPORT (1 << 3) 422f21ed392Saubrey.li@intel.com 42341afdfa7SKrishnendu Sadhukhan - Sun Microsystems /* 42441afdfa7SKrishnendu Sadhukhan - Sun Microsystems * Intel TSC deadline timer 42541afdfa7SKrishnendu Sadhukhan - Sun Microsystems */ 42641afdfa7SKrishnendu Sadhukhan - Sun Microsystems #define CPUID_DEADLINE_TSC (1 << 24) 42741afdfa7SKrishnendu Sadhukhan - Sun Microsystems 4287c478bd9Sstevel@tonic-gate /* 4297c478bd9Sstevel@tonic-gate * x86_type is a legacy concept; this is supplanted 4307417cfdeSKuriakose Kuruvilla * for most purposes by x86_featureset; modern CPUs 4317c478bd9Sstevel@tonic-gate * should be X86_TYPE_OTHER 4327c478bd9Sstevel@tonic-gate */ 4337c478bd9Sstevel@tonic-gate #define X86_TYPE_OTHER 0 4347c478bd9Sstevel@tonic-gate #define X86_TYPE_486 1 4357c478bd9Sstevel@tonic-gate #define X86_TYPE_P5 2 4367c478bd9Sstevel@tonic-gate #define X86_TYPE_P6 3 4377c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_486 4 4387c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86L 5 4397c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86 6 4407c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_GXm 7 4417c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86MX 8 4427c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MediaGX 9 4437c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MII 10 4447c478bd9Sstevel@tonic-gate #define X86_TYPE_VIA_CYRIX_III 11 4457c478bd9Sstevel@tonic-gate #define X86_TYPE_P4 12 4467c478bd9Sstevel@tonic-gate 4477c478bd9Sstevel@tonic-gate /* 4487c478bd9Sstevel@tonic-gate * x86_vendor allows us to select between 4497c478bd9Sstevel@tonic-gate * implementation features and helps guide 4507c478bd9Sstevel@tonic-gate * the interpretation of the cpuid instruction. 4517c478bd9Sstevel@tonic-gate */ 452e4b86885SCheng Sean Ye #define X86_VENDOR_Intel 0 453e4b86885SCheng Sean Ye #define X86_VENDORSTR_Intel "GenuineIntel" 454e4b86885SCheng Sean Ye 455e4b86885SCheng Sean Ye #define X86_VENDOR_IntelClone 1 456e4b86885SCheng Sean Ye 457e4b86885SCheng Sean Ye #define X86_VENDOR_AMD 2 458e4b86885SCheng Sean Ye #define X86_VENDORSTR_AMD "AuthenticAMD" 459e4b86885SCheng Sean Ye 460e4b86885SCheng Sean Ye #define X86_VENDOR_Cyrix 3 461e4b86885SCheng Sean Ye #define X86_VENDORSTR_CYRIX "CyrixInstead" 462e4b86885SCheng Sean Ye 463e4b86885SCheng Sean Ye #define X86_VENDOR_UMC 4 464e4b86885SCheng Sean Ye #define X86_VENDORSTR_UMC "UMC UMC UMC " 465e4b86885SCheng Sean Ye 466e4b86885SCheng Sean Ye #define X86_VENDOR_NexGen 5 467e4b86885SCheng Sean Ye #define X86_VENDORSTR_NexGen "NexGenDriven" 468e4b86885SCheng Sean Ye 469e4b86885SCheng Sean Ye #define X86_VENDOR_Centaur 6 470e4b86885SCheng Sean Ye #define X86_VENDORSTR_Centaur "CentaurHauls" 471e4b86885SCheng Sean Ye 472e4b86885SCheng Sean Ye #define X86_VENDOR_Rise 7 473e4b86885SCheng Sean Ye #define X86_VENDORSTR_Rise "RiseRiseRise" 474e4b86885SCheng Sean Ye 475e4b86885SCheng Sean Ye #define X86_VENDOR_SiS 8 476e4b86885SCheng Sean Ye #define X86_VENDORSTR_SiS "SiS SiS SiS " 477e4b86885SCheng Sean Ye 478e4b86885SCheng Sean Ye #define X86_VENDOR_TM 9 479e4b86885SCheng Sean Ye #define X86_VENDORSTR_TM "GenuineTMx86" 480e4b86885SCheng Sean Ye 481e4b86885SCheng Sean Ye #define X86_VENDOR_NSC 10 482e4b86885SCheng Sean Ye #define X86_VENDORSTR_NSC "Geode by NSC" 483e4b86885SCheng Sean Ye 484e4b86885SCheng Sean Ye /* 485e4b86885SCheng Sean Ye * Vendor string max len + \0 486e4b86885SCheng Sean Ye */ 487e4b86885SCheng Sean Ye #define X86_VENDOR_STRLEN 13 4887aec1d6eScindi 4898a40a695Sgavinm /* 4908a40a695Sgavinm * Some vendor/family/model/stepping ranges are commonly grouped under 4918a40a695Sgavinm * a single identifying banner by the vendor. The following encode 4928a40a695Sgavinm * that "revision" in a uint32_t with the 8 most significant bits 4938a40a695Sgavinm * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 4948a40a695Sgavinm * family, and the remaining 16 typically forming a bitmask of revisions 4958a40a695Sgavinm * within that family with more significant bits indicating "later" revisions. 4968a40a695Sgavinm */ 4978a40a695Sgavinm 4988a40a695Sgavinm #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 4998a40a695Sgavinm #define _X86_CHIPREV_VENDOR_SHIFT 24 5008a40a695Sgavinm #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 5018a40a695Sgavinm #define _X86_CHIPREV_FAMILY_SHIFT 16 5028a40a695Sgavinm #define _X86_CHIPREV_REV_MASK 0x0000ffffu 5038a40a695Sgavinm 5048a40a695Sgavinm #define _X86_CHIPREV_VENDOR(x) \ 5058a40a695Sgavinm (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 5068a40a695Sgavinm #define _X86_CHIPREV_FAMILY(x) \ 5078a40a695Sgavinm (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 5088a40a695Sgavinm #define _X86_CHIPREV_REV(x) \ 5098a40a695Sgavinm ((x) & _X86_CHIPREV_REV_MASK) 5108a40a695Sgavinm 5118a40a695Sgavinm /* True if x matches in vendor and family and if x matches the given rev mask */ 5128a40a695Sgavinm #define X86_CHIPREV_MATCH(x, mask) \ 5138a40a695Sgavinm (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 5148a40a695Sgavinm _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 5158a40a695Sgavinm ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 5168a40a695Sgavinm 5172c8230b0SSrihari Venkatesan /* True if x matches in vendor and family, and rev is at least minx */ 5188a40a695Sgavinm #define X86_CHIPREV_ATLEAST(x, minx) \ 5198a40a695Sgavinm (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 5208a40a695Sgavinm _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 5218a40a695Sgavinm _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 5228a40a695Sgavinm 5238a40a695Sgavinm #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 5248a40a695Sgavinm ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 5258a40a695Sgavinm (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 5268a40a695Sgavinm 5272c8230b0SSrihari Venkatesan /* True if x matches in vendor, and family is at least minx */ 5282c8230b0SSrihari Venkatesan #define X86_CHIPFAM_ATLEAST(x, minx) \ 5292c8230b0SSrihari Venkatesan (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 5302c8230b0SSrihari Venkatesan _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 5312c8230b0SSrihari Venkatesan 5328a40a695Sgavinm /* Revision default */ 5338a40a695Sgavinm #define X86_CHIPREV_UNKNOWN 0x0 5348a40a695Sgavinm 5358a40a695Sgavinm /* 53620c794b3Sgavinm * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 53720c794b3Sgavinm * sufficiently different that we will distinguish them; in all other 5388a40a695Sgavinm * case we will identify the major revision. 5398a40a695Sgavinm */ 5408a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 5418a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 5428a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 5438a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 5448a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 5458a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 5468a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 54720c794b3Sgavinm 54820c794b3Sgavinm /* 54920c794b3Sgavinm * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 55020c794b3Sgavinm */ 55120c794b3Sgavinm #define X86_CHIPREV_AMD_10_REV_A \ 55231725658Sksadhukh _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 55320c794b3Sgavinm #define X86_CHIPREV_AMD_10_REV_B \ 55420c794b3Sgavinm _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 55579321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_C2 \ 55664452efdSKit Chow _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 55779321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_C3 \ 55889e921d5SKuriakose Kuruvilla _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 55979321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_D0 \ 56079321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 56179321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_D1 \ 56279321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 56379321794SJens Elkner #define X86_CHIPREV_AMD_10_REV_E \ 56479321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 56589e921d5SKuriakose Kuruvilla 56689e921d5SKuriakose Kuruvilla /* 56789e921d5SKuriakose Kuruvilla * Definitions for AMD Family 0x11. 56889e921d5SKuriakose Kuruvilla */ 56979321794SJens Elkner #define X86_CHIPREV_AMD_11_REV_B \ 57079321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 57189e921d5SKuriakose Kuruvilla 57279321794SJens Elkner /* 57379321794SJens Elkner * Definitions for AMD Family 0x12. 57479321794SJens Elkner */ 57579321794SJens Elkner #define X86_CHIPREV_AMD_12_REV_B \ 57679321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 57779321794SJens Elkner 57879321794SJens Elkner /* 57979321794SJens Elkner * Definitions for AMD Family 0x14. 58079321794SJens Elkner */ 58179321794SJens Elkner #define X86_CHIPREV_AMD_14_REV_B \ 58279321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 58379321794SJens Elkner #define X86_CHIPREV_AMD_14_REV_C \ 58479321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 58579321794SJens Elkner 58679321794SJens Elkner /* 58779321794SJens Elkner * Definitions for AMD Family 0x15 58879321794SJens Elkner */ 58979321794SJens Elkner #define X86_CHIPREV_AMD_15OR_REV_B2 \ 59079321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 59179321794SJens Elkner 59279321794SJens Elkner #define X86_CHIPREV_AMD_15TN_REV_A1 \ 59379321794SJens Elkner _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 5948a40a695Sgavinm 5958a40a695Sgavinm /* 5968a40a695Sgavinm * Various socket/package types, extended as the need to distinguish 5978a40a695Sgavinm * a new type arises. The top 8 byte identfies the vendor and the 5988a40a695Sgavinm * remaining 24 bits describe 24 socket types. 5998a40a695Sgavinm */ 6008a40a695Sgavinm 6018a40a695Sgavinm #define _X86_SOCKET_VENDOR_SHIFT 24 6028a40a695Sgavinm #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 6038a40a695Sgavinm #define _X86_SOCKET_TYPE_MASK 0x00ffffff 6048a40a695Sgavinm #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 6058a40a695Sgavinm 6068a40a695Sgavinm #define _X86_SOCKET_MKVAL(vendor, bitval) \ 6078a40a695Sgavinm ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 6088a40a695Sgavinm 6098a40a695Sgavinm #define X86_SOCKET_MATCH(s, mask) \ 6108a40a695Sgavinm (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 611a24e89c4SKuriakose Kuruvilla (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 6128a40a695Sgavinm 6138a40a695Sgavinm #define X86_SOCKET_UNKNOWN 0x0 6148a40a695Sgavinm /* 6158a40a695Sgavinm * AMD socket types 6168a40a695Sgavinm */ 6178a40a695Sgavinm #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 6188a40a695Sgavinm #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 6198a40a695Sgavinm #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 6208a40a695Sgavinm #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 6218a40a695Sgavinm #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 6228a40a695Sgavinm #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 623a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 624a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 625a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 626a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 627a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 628a24e89c4SKuriakose Kuruvilla #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 629bd15239eSSrihari Venkatesan #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 630bd15239eSSrihari Venkatesan #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 63179321794SJens Elkner #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 63279321794SJens Elkner #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 63379321794SJens Elkner #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 63479321794SJens Elkner #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 63579321794SJens Elkner #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 63679321794SJens Elkner #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 63779321794SJens Elkner #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 63879321794SJens Elkner #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 6398a40a695Sgavinm 6407af88ac7SKuriakose Kuruvilla /* 6417af88ac7SKuriakose Kuruvilla * xgetbv/xsetbv support 6427af88ac7SKuriakose Kuruvilla */ 6437af88ac7SKuriakose Kuruvilla 6447af88ac7SKuriakose Kuruvilla #define XFEATURE_ENABLED_MASK 0x0 6457af88ac7SKuriakose Kuruvilla /* 6467af88ac7SKuriakose Kuruvilla * XFEATURE_ENABLED_MASK values (eax) 6477af88ac7SKuriakose Kuruvilla */ 6487af88ac7SKuriakose Kuruvilla #define XFEATURE_LEGACY_FP 0x1 6497af88ac7SKuriakose Kuruvilla #define XFEATURE_SSE 0x2 6507af88ac7SKuriakose Kuruvilla #define XFEATURE_AVX 0x4 6517af88ac7SKuriakose Kuruvilla #define XFEATURE_MAX XFEATURE_AVX 652ebb8ac07SRobert Mustacchi #define XFEATURE_FP_ALL \ 653ebb8ac07SRobert Mustacchi (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX) 6547af88ac7SKuriakose Kuruvilla 6557c478bd9Sstevel@tonic-gate #if !defined(_ASM) 6567c478bd9Sstevel@tonic-gate 6577c478bd9Sstevel@tonic-gate #if defined(_KERNEL) || defined(_KMEMUSER) 6587c478bd9Sstevel@tonic-gate 659*245ac945SRobert Mustacchi #define NUM_X86_FEATURES 45 660dfea898aSKuriakose Kuruvilla extern uchar_t x86_featureset[]; 6617417cfdeSKuriakose Kuruvilla 6627417cfdeSKuriakose Kuruvilla extern void free_x86_featureset(void *featureset); 6637417cfdeSKuriakose Kuruvilla extern boolean_t is_x86_feature(void *featureset, uint_t feature); 6647417cfdeSKuriakose Kuruvilla extern void add_x86_feature(void *featureset, uint_t feature); 6657417cfdeSKuriakose Kuruvilla extern void remove_x86_feature(void *featureset, uint_t feature); 6667417cfdeSKuriakose Kuruvilla extern boolean_t compare_x86_featureset(void *setA, void *setB); 6677417cfdeSKuriakose Kuruvilla extern void print_x86_featureset(void *featureset); 6687417cfdeSKuriakose Kuruvilla 6697417cfdeSKuriakose Kuruvilla 6707c478bd9Sstevel@tonic-gate extern uint_t x86_type; 6717c478bd9Sstevel@tonic-gate extern uint_t x86_vendor; 67286c1f4dcSVikram Hegde extern uint_t x86_clflush_size; 6737c478bd9Sstevel@tonic-gate 6747c478bd9Sstevel@tonic-gate extern uint_t pentiumpro_bug4046376; 6757c478bd9Sstevel@tonic-gate 6767c478bd9Sstevel@tonic-gate extern const char CyrixInstead[]; 6777c478bd9Sstevel@tonic-gate 6787c478bd9Sstevel@tonic-gate #endif 6797c478bd9Sstevel@tonic-gate 6807c478bd9Sstevel@tonic-gate #if defined(_KERNEL) 6817c478bd9Sstevel@tonic-gate 6828949bcd6Sandrei /* 6838949bcd6Sandrei * This structure is used to pass arguments and get return values back 6848949bcd6Sandrei * from the CPUID instruction in __cpuid_insn() routine. 6858949bcd6Sandrei */ 6868949bcd6Sandrei struct cpuid_regs { 6878949bcd6Sandrei uint32_t cp_eax; 6888949bcd6Sandrei uint32_t cp_ebx; 6898949bcd6Sandrei uint32_t cp_ecx; 6908949bcd6Sandrei uint32_t cp_edx; 6918949bcd6Sandrei }; 6927c478bd9Sstevel@tonic-gate 6937af88ac7SKuriakose Kuruvilla /* 6947af88ac7SKuriakose Kuruvilla * Utility functions to get/set extended control registers (XCR) 6957af88ac7SKuriakose Kuruvilla * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 6967af88ac7SKuriakose Kuruvilla */ 6977af88ac7SKuriakose Kuruvilla extern uint64_t get_xcr(uint_t); 6987af88ac7SKuriakose Kuruvilla extern void set_xcr(uint_t, uint64_t); 6997af88ac7SKuriakose Kuruvilla 7000ac7d7d8Skucharsk extern uint64_t rdmsr(uint_t); 7010ac7d7d8Skucharsk extern void wrmsr(uint_t, const uint64_t); 702ee88d2b9Skchow extern uint64_t xrdmsr(uint_t); 703ee88d2b9Skchow extern void xwrmsr(uint_t, const uint64_t); 704ae115bc7Smrj extern int checked_rdmsr(uint_t, uint64_t *); 705ae115bc7Smrj extern int checked_wrmsr(uint_t, uint64_t); 706ae115bc7Smrj 7077c478bd9Sstevel@tonic-gate extern void invalidate_cache(void); 7087c478bd9Sstevel@tonic-gate extern ulong_t getcr4(void); 7097c478bd9Sstevel@tonic-gate extern void setcr4(ulong_t); 710ae115bc7Smrj 7117c478bd9Sstevel@tonic-gate extern void mtrr_sync(void); 7127c478bd9Sstevel@tonic-gate 7137c478bd9Sstevel@tonic-gate extern void cpu_fast_syscall_enable(void *); 7147c478bd9Sstevel@tonic-gate extern void cpu_fast_syscall_disable(void *); 7157c478bd9Sstevel@tonic-gate 7167c478bd9Sstevel@tonic-gate struct cpu; 7177c478bd9Sstevel@tonic-gate 7187c478bd9Sstevel@tonic-gate extern int cpuid_checkpass(struct cpu *, int); 7198949bcd6Sandrei extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 7208949bcd6Sandrei extern uint32_t __cpuid_insn(struct cpuid_regs *); 7217c478bd9Sstevel@tonic-gate extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 7227c478bd9Sstevel@tonic-gate extern int cpuid_getidstr(struct cpu *, char *, size_t); 7237c478bd9Sstevel@tonic-gate extern const char *cpuid_getvendorstr(struct cpu *); 7247c478bd9Sstevel@tonic-gate extern uint_t cpuid_getvendor(struct cpu *); 7257c478bd9Sstevel@tonic-gate extern uint_t cpuid_getfamily(struct cpu *); 7267c478bd9Sstevel@tonic-gate extern uint_t cpuid_getmodel(struct cpu *); 7277c478bd9Sstevel@tonic-gate extern uint_t cpuid_getstep(struct cpu *); 7282449e17fSsherrym extern uint_t cpuid_getsig(struct cpu *); 7297c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 7308949bcd6Sandrei extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 731d129bde2Sesaxe extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 732d129bde2Sesaxe extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 733fb2f18f8Sesaxe extern int cpuid_get_chipid(struct cpu *); 734fb2f18f8Sesaxe extern id_t cpuid_get_coreid(struct cpu *); 73510569901Sgavinm extern int cpuid_get_pkgcoreid(struct cpu *); 736fb2f18f8Sesaxe extern int cpuid_get_clogid(struct cpu *); 737b885580bSAlexander Kolbasov extern int cpuid_get_cacheid(struct cpu *); 738fa96bd91SMichael Corcoran extern uint32_t cpuid_get_apicid(struct cpu *); 7398031591dSSrihari Venkatesan extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 7408031591dSSrihari Venkatesan extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 7417660e73fSHans Rosenfeld extern uint_t cpuid_get_compunitid(struct cpu *cpu); 7427660e73fSHans Rosenfeld extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 7438949bcd6Sandrei extern int cpuid_is_cmt(struct cpu *); 7447c478bd9Sstevel@tonic-gate extern int cpuid_syscall32_insn(struct cpu *); 7457c478bd9Sstevel@tonic-gate extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 7468a40a695Sgavinm 7478a40a695Sgavinm extern uint32_t cpuid_getchiprev(struct cpu *); 7488a40a695Sgavinm extern const char *cpuid_getchiprevstr(struct cpu *); 7498a40a695Sgavinm extern uint32_t cpuid_getsockettype(struct cpu *); 75089e921d5SKuriakose Kuruvilla extern const char *cpuid_getsocketstr(struct cpu *); 7517c478bd9Sstevel@tonic-gate 7522ef50f01SJoe Bonasera extern int cpuid_have_cr8access(struct cpu *); 7532ef50f01SJoe Bonasera 7547c478bd9Sstevel@tonic-gate extern int cpuid_opteron_erratum(struct cpu *, uint_t); 7557c478bd9Sstevel@tonic-gate 7567c478bd9Sstevel@tonic-gate struct cpuid_info; 7577c478bd9Sstevel@tonic-gate 7587c478bd9Sstevel@tonic-gate extern void setx86isalist(void); 759ae115bc7Smrj extern void cpuid_alloc_space(struct cpu *); 760ae115bc7Smrj extern void cpuid_free_space(struct cpu *); 761dfea898aSKuriakose Kuruvilla extern void cpuid_pass1(struct cpu *, uchar_t *); 7627c478bd9Sstevel@tonic-gate extern void cpuid_pass2(struct cpu *); 7637c478bd9Sstevel@tonic-gate extern void cpuid_pass3(struct cpu *); 764ebb8ac07SRobert Mustacchi extern void cpuid_pass4(struct cpu *, uint_t *); 765fa96bd91SMichael Corcoran extern void cpuid_set_cpu_properties(void *, processorid_t, 766fa96bd91SMichael Corcoran struct cpuid_info *); 7677c478bd9Sstevel@tonic-gate 7687c478bd9Sstevel@tonic-gate extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 7697c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 770843e1988Sjohnlev 771843e1988Sjohnlev #if !defined(__xpv) 7725b8a6efeSbholler extern uint32_t *cpuid_mwait_alloc(struct cpu *); 7735b8a6efeSbholler extern void cpuid_mwait_free(struct cpu *); 7740e751525SEric Saxe extern int cpuid_deep_cstates_supported(void); 775cef70d2cSBill Holler extern int cpuid_arat_supported(void); 776f21ed392Saubrey.li@intel.com extern int cpuid_iepb_supported(struct cpu *); 77741afdfa7SKrishnendu Sadhukhan - Sun Microsystems extern int cpuid_deadline_tsc_supported(void); 77879ec9da8SYuri Pankov extern void vmware_port(int, uint32_t *); 779843e1988Sjohnlev #endif 7807c478bd9Sstevel@tonic-gate 7812449e17fSsherrym struct cpu_ucode_info; 7822449e17fSsherrym 7832449e17fSsherrym extern void ucode_alloc_space(struct cpu *); 7842449e17fSsherrym extern void ucode_free_space(struct cpu *); 7852449e17fSsherrym extern void ucode_check(struct cpu *); 786adc586deSMark Johnson extern void ucode_cleanup(); 7872449e17fSsherrym 788247dbb3dSsudheer #if !defined(__xpv) 789247dbb3dSsudheer extern char _tsc_mfence_start; 790247dbb3dSsudheer extern char _tsc_mfence_end; 791247dbb3dSsudheer extern char _tscp_start; 792247dbb3dSsudheer extern char _tscp_end; 793247dbb3dSsudheer extern char _no_rdtsc_start; 794247dbb3dSsudheer extern char _no_rdtsc_end; 79515363b27Ssudheer extern char _tsc_lfence_start; 79615363b27Ssudheer extern char _tsc_lfence_end; 797247dbb3dSsudheer #endif 798247dbb3dSsudheer 79922cc0e45SBill Holler #if !defined(__xpv) 80022cc0e45SBill Holler extern char bcopy_patch_start; 80122cc0e45SBill Holler extern char bcopy_patch_end; 80222cc0e45SBill Holler extern char bcopy_ck_size; 80322cc0e45SBill Holler #endif 80422cc0e45SBill Holler 805e774b42bSBill Holler extern void post_startup_cpu_fixups(void); 806e774b42bSBill Holler 8077c478bd9Sstevel@tonic-gate extern uint_t workaround_errata(struct cpu *); 8087c478bd9Sstevel@tonic-gate 8097c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 8107c478bd9Sstevel@tonic-gate extern int opteron_erratum_93; 8117c478bd9Sstevel@tonic-gate #endif 8127c478bd9Sstevel@tonic-gate 8137c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 8147c478bd9Sstevel@tonic-gate extern int opteron_erratum_91; 8157c478bd9Sstevel@tonic-gate #endif 8167c478bd9Sstevel@tonic-gate 8177c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 8187c478bd9Sstevel@tonic-gate extern int opteron_erratum_100; 8197c478bd9Sstevel@tonic-gate #endif 8207c478bd9Sstevel@tonic-gate 8217c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 8227c478bd9Sstevel@tonic-gate extern int opteron_erratum_121; 8237c478bd9Sstevel@tonic-gate #endif 8247c478bd9Sstevel@tonic-gate 825ee88d2b9Skchow #if defined(OPTERON_WORKAROUND_6323525) 826ee88d2b9Skchow extern int opteron_workaround_6323525; 827ee88d2b9Skchow extern void patch_workaround_6323525(void); 828ee88d2b9Skchow #endif 829ee88d2b9Skchow 830cfe84b82SMatt Amdur #if !defined(__xpv) 831cfe84b82SMatt Amdur extern void determine_platform(void); 832cfe84b82SMatt Amdur #endif 833b9bfdccdSStuart Maybee extern int get_hwenv(void); 834b9bfdccdSStuart Maybee extern int is_controldom(void); 835b9bfdccdSStuart Maybee 8367af88ac7SKuriakose Kuruvilla extern void xsave_setup_msr(struct cpu *); 8377af88ac7SKuriakose Kuruvilla 83879ec9da8SYuri Pankov /* 83979ec9da8SYuri Pankov * Hypervisor signatures 84079ec9da8SYuri Pankov */ 84179ec9da8SYuri Pankov #define HVSIG_XEN_HVM "XenVMMXenVMM" 84279ec9da8SYuri Pankov #define HVSIG_VMWARE "VMwareVMware" 84379ec9da8SYuri Pankov #define HVSIG_KVM "KVMKVMKVM" 84479ec9da8SYuri Pankov #define HVSIG_MICROSOFT "Microsoft Hv" 84579ec9da8SYuri Pankov 846b9bfdccdSStuart Maybee /* 847b9bfdccdSStuart Maybee * Defined hardware environments 848b9bfdccdSStuart Maybee */ 84979ec9da8SYuri Pankov #define HW_NATIVE (1 << 0) /* Running on bare metal */ 85079ec9da8SYuri Pankov #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 85179ec9da8SYuri Pankov 85279ec9da8SYuri Pankov #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 85379ec9da8SYuri Pankov #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 85479ec9da8SYuri Pankov #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 85579ec9da8SYuri Pankov #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 85679ec9da8SYuri Pankov 85779ec9da8SYuri Pankov #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT) 858b9bfdccdSStuart Maybee 8597c478bd9Sstevel@tonic-gate #endif /* _KERNEL */ 8607c478bd9Sstevel@tonic-gate 86179ec9da8SYuri Pankov #endif /* !_ASM */ 86279ec9da8SYuri Pankov 86379ec9da8SYuri Pankov /* 86479ec9da8SYuri Pankov * VMware hypervisor related defines 86579ec9da8SYuri Pankov */ 86679ec9da8SYuri Pankov #define VMWARE_HVMAGIC 0x564d5868 86779ec9da8SYuri Pankov #define VMWARE_HVPORT 0x5658 86879ec9da8SYuri Pankov #define VMWARE_HVCMD_GETVERSION 0x0a 86979ec9da8SYuri Pankov #define VMWARE_HVCMD_GETTSCFREQ 0x2d 8707c478bd9Sstevel@tonic-gate 8717c478bd9Sstevel@tonic-gate #ifdef __cplusplus 8727c478bd9Sstevel@tonic-gate } 8737c478bd9Sstevel@tonic-gate #endif 8747c478bd9Sstevel@tonic-gate 8757c478bd9Sstevel@tonic-gate #endif /* _SYS_X86_ARCHEXT_H */ 876