27aec1d6cindi * CDDL HEADER START
37aec1d6cindi *
47aec1d6cindi * The contents of this file are subject to the terms of the
58a40a69gavinm * Common Development and Distribution License (the "License").
68a40a69gavinm * You may not use this file except in compliance with the License.
77aec1d6cindi *
87aec1d6cindi * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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107aec1d6cindi * See the License for the specific language governing permissions
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127aec1d6cindi *
137aec1d6cindi * When distributing Covered Code, include this CDDL HEADER in each
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197aec1d6cindi * CDDL HEADER END
207aec1d6cindi *
215667185Srihari Venkatesan * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
227aec1d6cindi * Use is subject to license terms.
237aec1d6cindi */
257aec1d6cindi#ifndef _MC_AMD_H
267aec1d6cindi#define	_MC_AMD_H
288a40a69gavinm#include <sys/mc.h>
2920c794bgavinm#include <sys/isa_defs.h>
308a40a69gavinm#include <sys/x86_archext.h>
329dd0f81cindi#ifdef __cplusplus
339dd0f81cindiextern "C" {
37bb86c34gavinm * Definitions, register offsets, register structure etc pertaining to
38bb86c34gavinm * the memory controller on AMD64 systems.  These are used by both the
39bb86c34gavinm * AMD cpu module and the mc-amd driver.
40bb86c34gavinm */
438a40a69gavinm * The mc-amd driver exports an nvlist to userland, where the primary
448a40a69gavinm * consumer is the "chip" topology enumerator for this platform type which
458a40a69gavinm * builds a full topology subtree from this information.  Others can use
464156fc3gavinm * it, too, but don't depend on it not changing without an ARC contract
474156fc3gavinm * (and the contract should probably concern the topology, not this nvlist).
488a40a69gavinm *
498a40a69gavinm * In the initial mc-amd implementation this nvlist was not versioned;
508a40a69gavinm * we'll think of that as version 0 and it may be recognised by the absence
518a40a69gavinm * of a "mcamd-nvlist-version member.
528a40a69gavinm *
538a40a69gavinm * Version 1 is defined as follows.  A name in square brackets indicates
548a40a69gavinm * that member is optional (only present if the actual value is valid).
558a40a69gavinm *
568a40a69gavinm * Name			Type		Description
578a40a69gavinm * -------------------- --------------- ---------------------------------------
588a40a69gavinm * mcamd-nvlist-version	uint8		Exported nvlist version number
598a40a69gavinm * num			uint64		Chip id of this memory controller
608a40a69gavinm * revision		uint64		cpuid_getchiprev() result
618a40a69gavinm * revname		string		cpuid_getchiprevstr() result
628a40a69gavinm * socket		string		"Socket 755|939|940|AM2|F(1207)|S1g1"
638a40a69gavinm * ecc-type		string		"ChipKill 128/16" or "Normal 64/8"
648a40a69gavinm * base-addr		uint64		Node base address
658a40a69gavinm * lim-addr		uint64		Node limit address
668a40a69gavinm * node-ilen		uint64		0|1|3|7 for 0/2/4/8 way node interleave
678a40a69gavinm * node-ilsel		uint64		Node interleave position of this node
688a40a69gavinm * cs-intlv-factor	uint64		chip-select interleave: 1/2/4/8
698a40a69gavinm * dram-hole-size	uint64		size in bytes from dram hole addr reg
708a40a69gavinm * access-width		uint64		MC mode, 64 or 128 bit
718a40a69gavinm * bank-mapping		uint64		Raw DRAM Bank Address Mapping Register
728a40a69gavinm * bankswizzle		uint64		1 if bank swizzling enabled; else 0
738a40a69gavinm * mismatched-dimm-support uint64	1 if active; else 0
748a40a69gavinm * [spare-csnum]	uint64		Chip-select pair number of any spare
758a40a69gavinm * [bad-csnum]		uint64		Chip-select pair number of swapped cs
768a40a69gavinm * cslist		nvlist array	See below; may have 0 members
778a40a69gavinm * dimmlist		nvlist array	See below; may have 0 members
788a40a69gavinm *
798a40a69gavinm * cslist is an array of nvlist, each as follows:
808a40a69gavinm *
818a40a69gavinm * Name			Type		Description
828a40a69gavinm * -------------------- --------------- ---------------------------------------
838a40a69gavinm * num			uint64		Chip-select base/mask pair number
848a40a69gavinm * base-addr		uint64		Chip-select base address (rel to node)
858a40a69gavinm * mask			uint64		Chip-select mask
868a40a69gavinm * size			uint64		Chip-select size in bytes
878a40a69gavinm * dimm1-num		uint64		First dimm (lodimm if a pair)
888a40a69gavinm * dimm1-csname		string		Socket cs# line name for 1st dimm rank
898a40a69gavinm * [dimm2-num]		uint64		Second dimm if applicable (updimm)
908a40a69gavinm * [dimm2-csname]	string		Socket cs# line name for 2nd dimm rank
918a40a69gavinm *
928a40a69gavinm * dimmlist is an array of nvlist, each as follows:
938a40a69gavinm *
948a40a69gavinm * Name			Type		Description
958a40a69gavinm * -------------------- --------------- ---------------------------------------
968a40a69gavinm * num			uint64		DIMM instance number
978a40a69gavinm * size			uint64		DIMM size in bytes
988a40a69gavinm * csnums		uint64 array	CS base/mask pair(s) on this DIMM
998a40a69gavinm * csnames		string array	Socket cs# line name(s) on this DIMM
1008a40a69gavinm *
1018a40a69gavinm *	The n'th csnums entry corresponds to the n'th csnames entry
1028a40a69gavinm */
1038a40a69gavinm#define	MC_NVLIST_VERSTR	"mcamd-nvlist-version"
1048a40a69gavinm#define	MC_NVLIST_VERS0		0
1058a40a69gavinm#define	MC_NVLIST_VERS1		1
1068a40a69gavinm#define	MC_NVLIST_VERS		MC_NVLIST_VERS1
1098a40a69gavinm * Constants and feature/revision test macros that are not expected to vary
1108a40a69gavinm * among different AMD family 0xf processor revisions.
1118a40a69gavinm */
1147aec1d6cindi * Configuration constants