1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MACHLOCK_H 27 #define _SYS_MACHLOCK_H 28 29 #ifndef _ASM 30 #include <sys/types.h> 31 #include <sys/time.h> 32 #endif /* _ASM */ 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #ifndef _ASM 39 40 #ifdef _KERNEL 41 42 extern void lock_set(lock_t *lp); 43 extern int lock_try(lock_t *lp); 44 extern int lock_spin_try(lock_t *lp); 45 extern int ulock_try(lock_t *lp); 46 extern void lock_clear(lock_t *lp); 47 extern void ulock_clear(lock_t *lp); 48 extern void lock_set_spl(lock_t *lp, int new_pil, ushort_t *old_pil); 49 extern void lock_clear_splx(lock_t *lp, int s); 50 51 #endif /* _KERNEL */ 52 53 #define LOCK_HELD_VALUE 0xff 54 #define LOCK_INIT_CLEAR(lp) (*(lp) = 0) 55 #define LOCK_INIT_HELD(lp) (*(lp) = LOCK_HELD_VALUE) 56 #define LOCK_HELD(lp) (*(volatile lock_t *)(lp) != 0) 57 58 typedef lock_t disp_lock_t; /* dispatcher lock type */ 59 60 /* 61 * SPIN_LOCK() macro indicates whether lock is implemented as a spin lock or 62 * an adaptive mutex, depending on what interrupt levels use it. 63 */ 64 #define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL)) 65 66 /* 67 * Macro to control loops which spin on a lock and then check state 68 * periodically. Its passed an integer, and returns a boolean value 69 * that if true indicates its a good time to get the scheduler lock and 70 * check the state of the current owner of the lock. 71 */ 72 #define LOCK_SAMPLE_INTERVAL(i) (((i) & 0xff) == 0) 73 74 /* 75 * Externs for CLOCK_LOCK and clock resolution 76 */ 77 extern volatile int hres_lock; 78 extern hrtime_t hrtime_base; 79 extern int clock_res; 80 81 #endif /* _ASM */ 82 83 /* 84 * The definitions of the symbolic interrupt levels: 85 * 86 * CLOCK_LEVEL => The level at which one must be to block the clock. 87 * 88 * LOCK_LEVEL => The highest level at which one may block (and thus the 89 * highest level at which one may acquire adaptive locks) 90 * Also the highest level at which one may be preempted. 91 * 92 * DISP_LEVEL => The level at which one must be to perform dispatcher 93 * operations. 94 * 95 * The constraints on the platform: 96 * 97 * - CLOCK_LEVEL must be less than or equal to LOCK_LEVEL 98 * - LOCK_LEVEL must be less than DISP_LEVEL 99 * - DISP_LEVEL should be as close to LOCK_LEVEL as possible 100 * 101 * Note that LOCK_LEVEL and CLOCK_LEVEL have historically always been equal; 102 * changing this relationship is probably possible but not advised. 103 * 104 */ 105 106 #define PIL_MAX 15 107 108 #define CLOCK_LEVEL 10 109 #define LOCK_LEVEL 10 110 #define DISP_LEVEL (LOCK_LEVEL + 1) 111 112 #define HIGH_LEVELS (PIL_MAX - LOCK_LEVEL) 113 114 /* 115 * The following mask is for the cpu_intr_actv bits corresponding to 116 * high-level PILs. It should equal: 117 * ((((1 << PIL_MAX + 1) - 1) >> LOCK_LEVEL + 1) << LOCK_LEVEL + 1) 118 */ 119 #define CPU_INTR_ACTV_HIGH_LEVEL_MASK 0xF800 120 121 /* 122 * The semaphore code depends on being able to represent a lock plus 123 * owner in a single 32-bit word. (Mutexes used to have a similar 124 * dependency, but no longer.) Thus the owner must contain at most 125 * 24 significant bits. At present only threads and semaphores 126 * must be aware of this vile constraint. Different ISAs may handle this 127 * differently depending on their capabilities (e.g. compare-and-swap) 128 * and limitations (e.g. constraints on alignment and/or KERNELBASE). 129 */ 130 #define PTR24_LSB 5 /* lower bits all zero */ 131 #define PTR24_MSB (PTR24_LSB + 24) /* upper bits all one */ 132 #define PTR24_ALIGN 32 /* minimum alignment (1 << lsb) */ 133 #define PTR24_BASE 0xe0000000 /* minimum ptr value (-1 >> (32-msb)) */ 134 135 #ifdef __cplusplus 136 } 137 #endif 138 139 #endif /* _SYS_MACHLOCK_H */ 140