17c478bdstevel@tonic-gate/*
27c478bdstevel@tonic-gate * CDDL HEADER START
37c478bdstevel@tonic-gate *
47c478bdstevel@tonic-gate * The contents of this file are subject to the terms of the
5b5b48ccsudheer * Common Development and Distribution License (the "License").
6b5b48ccsudheer * You may not use this file except in compliance with the License.
77c478bdstevel@tonic-gate *
87c478bdstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bdstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bdstevel@tonic-gate * See the License for the specific language governing permissions
117c478bdstevel@tonic-gate * and limitations under the License.
127c478bdstevel@tonic-gate *
137c478bdstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bdstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bdstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bdstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bdstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bdstevel@tonic-gate *
197c478bdstevel@tonic-gate * CDDL HEADER END
207c478bdstevel@tonic-gate */
217c478bdstevel@tonic-gate/*
22b5b48ccsudheer * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
237c478bdstevel@tonic-gate * Use is subject to license terms.
242428aadPatrick Mooney * Copyright 2016 Joyent, Inc.
257c478bdstevel@tonic-gate */
267c478bdstevel@tonic-gate
277c478bdstevel@tonic-gate#ifndef _SYS_MACHLOCK_H
287c478bdstevel@tonic-gate#define	_SYS_MACHLOCK_H
297c478bdstevel@tonic-gate
307c478bdstevel@tonic-gate#ifndef _ASM
317c478bdstevel@tonic-gate#include <sys/types.h>
327c478bdstevel@tonic-gate#include <sys/time.h>
337c478bdstevel@tonic-gate#endif /* _ASM */
347c478bdstevel@tonic-gate
357c478bdstevel@tonic-gate#ifdef	__cplusplus
367c478bdstevel@tonic-gateextern "C" {
377c478bdstevel@tonic-gate#endif
387c478bdstevel@tonic-gate
397c478bdstevel@tonic-gate#ifndef	_ASM
407c478bdstevel@tonic-gate
417c478bdstevel@tonic-gate#ifdef _KERNEL
427c478bdstevel@tonic-gate
437c478bdstevel@tonic-gateextern void	lock_set(lock_t *lp);
447c478bdstevel@tonic-gateextern int	lock_try(lock_t *lp);
457c478bdstevel@tonic-gateextern int	lock_spin_try(lock_t *lp);
467c478bdstevel@tonic-gateextern int	ulock_try(lock_t *lp);
477c478bdstevel@tonic-gateextern void	lock_clear(lock_t *lp);
487c478bdstevel@tonic-gateextern void	ulock_clear(lock_t *lp);
497c478bdstevel@tonic-gateextern void	lock_set_spl(lock_t *lp, int new_pil, ushort_t *old_pil);
507c478bdstevel@tonic-gateextern void	lock_clear_splx(lock_t *lp, int s);
517c478bdstevel@tonic-gate
527c478bdstevel@tonic-gate#endif	/* _KERNEL */
537c478bdstevel@tonic-gate
547c478bdstevel@tonic-gate#define	LOCK_HELD_VALUE		0xff
557c478bdstevel@tonic-gate#define	LOCK_INIT_CLEAR(lp)	(*(lp) = 0)
567c478bdstevel@tonic-gate#define	LOCK_INIT_HELD(lp)	(*(lp) = LOCK_HELD_VALUE)
577c478bdstevel@tonic-gate#define	LOCK_HELD(lp)		(*(volatile lock_t *)(lp) != 0)
587c478bdstevel@tonic-gate
597c478bdstevel@tonic-gatetypedef	lock_t	disp_lock_t;		/* dispatcher lock type */
607c478bdstevel@tonic-gate
617c478bdstevel@tonic-gate/*
627c478bdstevel@tonic-gate * SPIN_LOCK() macro indicates whether lock is implemented as a spin lock or
637c478bdstevel@tonic-gate * an adaptive mutex, depending on what interrupt levels use it.
647c478bdstevel@tonic-gate */
657c478bdstevel@tonic-gate#define	SPIN_LOCK(pl)	((pl) > ipltospl(LOCK_LEVEL))
667c478bdstevel@tonic-gate
677c478bdstevel@tonic-gate/*
687c478bdstevel@tonic-gate * Macro to control loops which spin on a lock and then check state
697c478bdstevel@tonic-gate * periodically.  Its passed an integer, and returns a boolean value
707c478bdstevel@tonic-gate * that if true indicates its a good time to get the scheduler lock and
717c478bdstevel@tonic-gate * check the state of the current owner of the lock.
727c478bdstevel@tonic-gate */
737c478bdstevel@tonic-gate#define	LOCK_SAMPLE_INTERVAL(i)	(((i) & 0xff) == 0)
747c478bdstevel@tonic-gate
757c478bdstevel@tonic-gate/*
767c478bdstevel@tonic-gate * Externs for CLOCK_LOCK and clock resolution
777c478bdstevel@tonic-gate */
782428aadPatrick Mooneyextern volatile uint32_t hres_lock;
797c478bdstevel@tonic-gateextern hrtime_t hrtime_base;
807c478bdstevel@tonic-gateextern int clock_res;
817c478bdstevel@tonic-gate
827c478bdstevel@tonic-gate#endif	/* _ASM */
837c478bdstevel@tonic-gate
847c478bdstevel@tonic-gate/*
857c478bdstevel@tonic-gate * The definitions of the symbolic interrupt levels:
867c478bdstevel@tonic-gate *
877c478bdstevel@tonic-gate *   CLOCK_LEVEL =>  The level at which one must be to block the clock.
887c478bdstevel@tonic-gate *
897c478bdstevel@tonic-gate *   LOCK_LEVEL  =>  The highest level at which one may block (and thus the
907c478bdstevel@tonic-gate *                   highest level at which one may acquire adaptive locks)
917c478bdstevel@tonic-gate *                   Also the highest level at which one may be preempted.
927c478bdstevel@tonic-gate *
937c478bdstevel@tonic-gate *   DISP_LEVEL  =>  The level at which one must be to perform dispatcher
947c478bdstevel@tonic-gate *                   operations.
957c478bdstevel@tonic-gate *
967c478bdstevel@tonic-gate * The constraints on the platform:
977c478bdstevel@tonic-gate *
987c478bdstevel@tonic-gate *  - CLOCK_LEVEL must be less than or equal to LOCK_LEVEL
997c478bdstevel@tonic-gate *  - LOCK_LEVEL must be less than DISP_LEVEL
1007c478bdstevel@tonic-gate *  - DISP_LEVEL should be as close to LOCK_LEVEL as possible
1017c478bdstevel@tonic-gate *
1027c478bdstevel@tonic-gate * Note that LOCK_LEVEL and CLOCK_LEVEL have historically always been equal;
1037c478bdstevel@tonic-gate * changing this relationship is probably possible but not advised.
1047c478bdstevel@tonic-gate *
1057c478bdstevel@tonic-gate */
1067c478bdstevel@tonic-gate
1077c478bdstevel@tonic-gate#define	PIL_MAX		15
1087c478bdstevel@tonic-gate
1097c478bdstevel@tonic-gate#define	CLOCK_LEVEL	10
1107c478bdstevel@tonic-gate#define	LOCK_LEVEL	10
1117c478bdstevel@tonic-gate#define	DISP_LEVEL	(LOCK_LEVEL + 1)
1127c478bdstevel@tonic-gate
1137c478bdstevel@tonic-gate#define	HIGH_LEVELS	(PIL_MAX - LOCK_LEVEL)
1147c478bdstevel@tonic-gate
1157c478bdstevel@tonic-gate/*
1167c478bdstevel@tonic-gate * The following mask is for the cpu_intr_actv bits corresponding to
1177c478bdstevel@tonic-gate * high-level PILs. It should equal:
1187c478bdstevel@tonic-gate * ((((1 << PIL_MAX + 1) - 1) >> LOCK_LEVEL + 1) << LOCK_LEVEL + 1)
1197c478bdstevel@tonic-gate */
1207c478bdstevel@tonic-gate#define	CPU_INTR_ACTV_HIGH_LEVEL_MASK	0xF800
1217c478bdstevel@tonic-gate
1227c478bdstevel@tonic-gate/*
1237c478bdstevel@tonic-gate * The semaphore code depends on being able to represent a lock plus
1247c478bdstevel@tonic-gate * owner in a single 32-bit word.  (Mutexes used to have a similar
1257c478bdstevel@tonic-gate * dependency, but no longer.)  Thus the owner must contain at most
1267c478bdstevel@tonic-gate * 24 significant bits.  At present only threads and semaphores
1277c478bdstevel@tonic-gate * must be aware of this vile constraint.  Different ISAs may handle this
1287c478bdstevel@tonic-gate * differently depending on their capabilities (e.g. compare-and-swap)
1297c478bdstevel@tonic-gate * and limitations (e.g. constraints on alignment and/or KERNELBASE).
1307c478bdstevel@tonic-gate */
1317c478bdstevel@tonic-gate#define	PTR24_LSB	5			/* lower bits all zero */
1327c478bdstevel@tonic-gate#define	PTR24_MSB	(PTR24_LSB + 24)	/* upper bits all one */
1337c478bdstevel@tonic-gate#define	PTR24_ALIGN	32		/* minimum alignment (1 << lsb) */
1347c478bdstevel@tonic-gate#define	PTR24_BASE	0xe0000000	/* minimum ptr value (-1 >> (32-msb)) */
1357c478bdstevel@tonic-gate
1367c478bdstevel@tonic-gate#ifdef	__cplusplus
1377c478bdstevel@tonic-gate}
1387c478bdstevel@tonic-gate#endif
1397c478bdstevel@tonic-gate
1407c478bdstevel@tonic-gate#endif	/* _SYS_MACHLOCK_H */
141