27c478bdstevel@tonic-gate * CDDL HEADER START
37c478bdstevel@tonic-gate *
47c478bdstevel@tonic-gate * The contents of this file are subject to the terms of the
53ad553agavinm * Common Development and Distribution License (the "License").
63ad553agavinm * You may not use this file except in compliance with the License.
77c478bdstevel@tonic-gate *
87c478bdstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bdstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bdstevel@tonic-gate * See the License for the specific language governing permissions
117c478bdstevel@tonic-gate * and limitations under the License.
127c478bdstevel@tonic-gate *
137c478bdstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bdstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bdstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bdstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bdstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bdstevel@tonic-gate *
197c478bdstevel@tonic-gate * CDDL HEADER END
207c478bdstevel@tonic-gate */
23a311483Gerry Liu * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
247c478bdstevel@tonic-gate * Use is subject to license terms.
25eb00b1cRobert Mustacchi * Copyright 2019 Joyent, Inc.
267c478bdstevel@tonic-gate */
287aec1d6cindi#ifndef _SYS_CPU_MODULE_H
297aec1d6cindi#define	_SYS_CPU_MODULE_H
317aec1d6cindi#include <sys/types.h>
327aec1d6cindi#include <sys/cpuvar.h>
337aec1d6cindi#include <sys/nvpair.h>
347aec1d6cindi#include <sys/mc.h>
3520c794bgavinm#include <sys/sunddi.h>
377aec1d6cindi#ifdef __cplusplus
387c478bdstevel@tonic-gateextern "C" {
4120c794bgavinm#ifdef _KERNEL
4320c794bgavinm#define	CMIERR_BASE	0xc000
4520c794bgavinmtypedef enum cmi_errno {
4620c794bgavinm	CMI_SUCCESS = 0,
4720c794bgavinm	/*
4820c794bgavinm	 * CPU Module Interface API error return values/
4920c794bgavinm	 */
5020c794bgavinm	CMIERR_UNKNOWN = CMIERR_BASE,	/* no specific error reason reported */
5120c794bgavinm	CMIERR_API,			/* API usage error caught */
5220c794bgavinm	CMIERR_NOTSUP,			/* Unsupported operation */
5320c794bgavinm	CMIERR_HDL_CLASS,		/* Inappropriate handle class */
5420c794bgavinm	CMIERR_HDL_NOTFOUND,		/* Can't find handle for resource */
5520c794bgavinm	CMIERR_MSRGPF,			/* #GP during cmi_hdl_{wr,rd}msr */
5620c794bgavinm	CMIERR_INTERPOSE,		/* MSR/PCICFG interposition error */
5720c794bgavinm	CMIERR_DEADLOCK,		/* Deadlock avoidance */
5820c794bgavinm	/*
5920c794bgavinm	 * Memory-controller related errors
6020c794bgavinm	 */
6120c794bgavinm	CMIERR_MC_ABSENT,		/* No, or not yet registered, MC ops */
6220c794bgavinm	CMIERR_MC_NOTSUP,		/* Requested functionality unimpld */
6320c794bgavinm	CMIERR_MC_NOMEMSCRUB,		/* No dram scrubber, or disabled */
6420c794bgavinm	CMIERR_MC_SYNDROME,		/* Invalid syndrome or syndrome type */
6520c794bgavinm	CMIERR_MC_BADSTATE,		/* MC driver state is invalid */
6620c794bgavinm	CMIERR_MC_NOADDR,		/* Address not found */
6720c794bgavinm	CMIERR_MC_RSRCNOTPRESENT,	/* Resource not present in system */
6820c794bgavinm	CMIERR_MC_ADDRBITS,		/* Too few valid addr bits */
6920c794bgavinm	CMIERR_MC_INVALUNUM,		/* Invalid input unum */
70eb00b1cRobert Mustacchi	CMIERR_MC_PARTIALUNUMTOPA,	/* unum to pa reflected physaddr */
71eb00b1cRobert Mustacchi	CMIERR_MC_NOTDIMMADDR		/* Address not backed by DRAM */
7220c794bgavinm} cmi_errno_t;
7520c794bgavinm * All access to cpu information is made via a handle, in order to get
7620c794bgavinm * the desired info even when running non-natively.
7720c794bgavinm *
7820c794bgavinm * A CMI_HDL_NATIVE handle is used when we believe we are running on
7920c794bgavinm * bare-metal.  If we *are* on bare metal then this handle type will
8020c794bgavinm * get us through to the real hardware, and there will be a 1:1 correspondence
8120c794bgavinm * between handles and cpu_t structures; if not, say we are a domU to
8220c794bgavinm * some unknown/undetected/unannounced hypervisor then chances are the
8320c794bgavinm * hypervisor is not exposing much hardware detail to us so we should
8420c794bgavinm * be prepared for some operations that "cannot fail" to fail or return
8520c794bgavinm * odd data.
8620c794bgavinm *
87e4b8688Cheng Sean Ye * A CMI_HDL_SOLARIS_xVM_MCA handle is used when we are running
8820c794bgavinm * in i86xpv architecture - dom0 to a Solaris xVM hypervisor - and want to
8920c794bgavinm * use a handle on each real execution core (as opposed to vcpu)
9020c794bgavinm * to perform MCA related activities.  The model for this handle type
9120c794bgavinm * is that the hypervisor continues to own the real hardware and
9220c794bgavinm * includes a polling service and #MC handler which forward error
9320c794bgavinm * telemetry to dom0 for logging and diagnosis.  As such, the operations
9420c794bgavinm * such as RDMSR and WRMSR for this handle type do *not* read and write
9520c794bgavinm * real MSRs via hypercalls- instead they should provide the values from
9620c794bgavinm * already-read MCA bank telemetry, and writes are discarded.
9720c794bgavinm *
9820c794bgavinm * If some application requires real MSR read and write access another
9920c794bgavinm * handle class should be introduced.
10020c794bgavinm */
10220c794bgavinmtypedef struct cmi_hdl *cmi_hdl_t;	/* opaque chip/core/strand handle */
10420c794bgavinmenum cmi_hdl_class {
10520c794bgavinm	CMI_HDL_NATIVE,
106e4b8688Cheng Sean Ye	CMI_HDL_SOLARIS_xVM_MCA,
107e4b8688Cheng Sean Ye	CMI_HDL_NEUTRAL
1107aec1d6cindistruct regs;
112e4b8688Cheng Sean Yetypedef struct cmi_mc_ops {
113e4b8688Cheng Sean Ye	cmi_errno_t (*cmi_mc_patounum)(void *, uint64_t, uint8_t, uint8_t,
114e4b8688Cheng Sean Ye	    uint32_t, int, mc_unum_t *);
115e4b8688Cheng Sean Ye	cmi_errno_t (*cmi_mc_unumtopa)(void *, mc_unum_t *, nvlist_t *,
116e4b8688Cheng Sean Ye	    uint64_t *);
117e4b8688Cheng Sean Ye	void (*cmi_mc_logout)(cmi_hdl_t, boolean_t, boolean_t);
118e4b8688Cheng Sean Ye} cmi_mc_ops_t;
119e4b8688Cheng Sean Ye
120e4b8688Cheng Sean Yeextern cmi_hdl_t cmi_init(enum cmi_hdl_class, uint_t, uint_t, uint_t);
12120c794bgavinmextern void cmi_post_startup(void);
12220c794bgavinmextern void cmi_post_mpstartup(void);
12320c794bgavinmextern void cmi_fini(cmi_hdl_t);
12520c794bgavinmextern void cmi_hdl_hold(cmi_hdl_t);
12620c794bgavinmextern void cmi_hdl_rele(cmi_hdl_t);
12720c794bgavinmextern void *cmi_hdl_getcmidata(cmi_hdl_t);
12820c794bgavinmextern void cmi_hdl_setspecific(cmi_hdl_t, void *);
12920c794bgavinmextern void *cmi_hdl_getspecific(cmi_hdl_t);
13020c794bgavinmextern const struct cmi_mc_ops *cmi_hdl_getmcops(cmi_hdl_t);
13120c794bgavinmextern void *cmi_hdl_getmcdata(cmi_hdl_t);
13220c794bgavinmextern enum cmi_hdl_class cmi_hdl_class(cmi_hdl_t);
133e4b8688Cheng Sean Ye
13420c794bgavinmextern cmi_hdl_t cmi_hdl_lookup(enum cmi_hdl_class, uint_t, uint_t, uint_t);
13520c794bgavinmextern cmi_hdl_t cmi_hdl_any(void);
13720c794bgavinm#define	CMI_HDL_WALK_NEXT	0
13820c794bgavinm#define	CMI_HDL_WALK_DONE	1
13920c794bgavinmextern void cmi_hdl_walk(int (*)(cmi_hdl_t, void *, void *, void *),
14020c794bgavinm    void *, void *, void *);
14220c794bgavinmextern void cmi_hdlconf_rdmsr_nohw(cmi_hdl_t);
14320c794bgavinmextern void cmi_hdlconf_wrmsr_nohw(cmi_hdl_t);
14420c794bgavinmextern cmi_errno_t cmi_hdl_rdmsr(cmi_hdl_t, uint_t, uint64_t *);
14520c794bgavinmextern cmi_errno_t cmi_hdl_wrmsr(cmi_hdl_t, uint_t, uint64_t);
14720c794bgavinmextern void cmi_hdl_enable_mce(cmi_hdl_t);
14820c794bgavinmextern uint_t cmi_hdl_vendor(cmi_hdl_t);
14920c794bgavinmextern const char *cmi_hdl_vendorstr(cmi_hdl_t);
15020c794bgavinmextern uint_t cmi_hdl_family(cmi_hdl_t);
15120c794bgavinmextern uint_t cmi_hdl_model(cmi_hdl_t);
15220c794bgavinmextern uint_t cmi_hdl_stepping(cmi_hdl_t);
15320c794bgavinmextern uint_t cmi_hdl_chipid(cmi_hdl_t);
1548031591Srihari Venkatesanextern uint_t cmi_hdl_procnodeid(cmi_hdl_t);
15520c794bgavinmextern uint_t cmi_hdl_coreid(cmi_hdl_t);
15620c794bgavinmextern uint_t cmi_hdl_strandid(cmi_hdl_t);
157074bb90Tom Pothierextern uint_t cmi_hdl_strand_apicid(cmi_hdl_t);
1588031591Srihari Venkatesanextern uint_t cmi_hdl_procnodes_per_pkg(cmi_hdl_t);
159e4b8688Cheng Sean Yeextern boolean_t cmi_hdl_is_cmt(cmi_hdl_t);
16020c794bgavinmextern uint32_t cmi_hdl_chiprev(cmi_hdl_t);
16120c794bgavinmextern const char *cmi_hdl_chiprevstr(cmi_hdl_t);
16220c794bgavinmextern uint32_t cmi_hdl_getsockettype(cmi_hdl_t);
16389e921dKuriakose Kuruvillaextern const char *cmi_hdl_getsocketstr(cmi_hdl_t);
164e4b8688Cheng Sean Yeextern id_t cmi_hdl_logical_id(cmi_hdl_t);
165074bb90Tom Pothierextern uint16_t cmi_hdl_smbiosid(cmi_hdl_t);
166074bb90Tom Pothierextern uint_t cmi_hdl_smb_chipid(cmi_hdl_t);
167074bb90Tom Pothierextern nvlist_t *cmi_hdl_smb_bboard(cmi_hdl_t);
1682a613b5Robert Mustacchiextern uint_t cmi_hdl_chipsig(cmi_hdl_t);
1692a613b5Robert Mustacchiextern const char *cmi_hdl_chipident(cmi_hdl_t);
170e4b8688Cheng Sean Ye
171e4b8688Cheng Sean Yeextern int cmi_hdl_online(cmi_hdl_t, int, int *);
17320c794bgavinm#ifndef	__xpv
17420c794bgavinmextern uint_t cmi_ntv_hwchipid(cpu_t *);
1758031591Srihari Venkatesanextern uint_t cmi_ntv_hwprocnodeid(cpu_t *);
17620c794bgavinmextern uint_t cmi_ntv_hwcoreid(cpu_t *);
17720c794bgavinmextern uint_t cmi_ntv_hwstrandid(cpu_t *);
178a311483Gerry Liuextern void cmi_ntv_hwdisable_mce(cmi_hdl_t);
17920c794bgavinm#endif	/* __xpv */
1817aec1d6cinditypedef struct cmi_mca_regs {
1827aec1d6cindi	uint_t cmr_msrnum;
1837aec1d6cindi	uint64_t cmr_msrval;
1847aec1d6cindi} cmi_mca_regs_t;
18620c794bgavinmextern cmi_errno_t cmi_hdl_msrinject(cmi_hdl_t, cmi_mca_regs_t *, uint_t,
18720c794bgavinm    int);
18820c794bgavinmextern void cmi_hdl_msrinterpose(cmi_hdl_t, cmi_mca_regs_t *, uint_t);
189e4b8688Cheng Sean Yeextern void cmi_hdl_msrforward(cmi_hdl_t, cmi_mca_regs_t *, uint_t);
190e4b8688Cheng Sean Yeextern boolean_t cmi_inj_tainted(void);
19220c794bgavinmextern void cmi_faulted_enter(cmi_hdl_t);
19320c794bgavinmextern void cmi_faulted_exit(cmi_hdl_t);
19520c794bgavinmextern void cmi_pcird_nohw(void);
19620c794bgavinmextern void cmi_pciwr_nohw(void);
19720c794bgavinmextern uint8_t cmi_pci_getb(int, int, int, int, int *, ddi_acc_handle_t);
19820c794bgavinmextern uint16_t cmi_pci_getw(int, int, int, int, int *, ddi_acc_handle_t);
19920c794bgavinmextern uint32_t cmi_pci_getl(int, int, int, int, int *, ddi_acc_handle_t);
20020c794bgavinmextern void cmi_pci_interposeb(int, int, int, int, uint8_t);
20120c794bgavinmextern void cmi_pci_interposew(int, int, int, int, uint16_t);
20220c794bgavinmextern void cmi_pci_interposel(int, int, int, int, uint32_t);
20320c794bgavinmextern void cmi_pci_putb(int, int, int, int, ddi_acc_handle_t, uint8_t);
20420c794bgavinmextern void cmi_pci_putw(int, int, int, int, ddi_acc_handle_t, uint16_t);
20520c794bgavinmextern void cmi_pci_putl(int, int, int, int, ddi_acc_handle_t, uint32_t);
20720c794bgavinmextern void cmi_mca_init(cmi_hdl_t);
20920c794bgavinmextern void cmi_hdl_poke(cmi_hdl_t);
210e3d60c9Adrian Frostextern void cmi_hdl_int(cmi_hdl_t, int);
21220c794bgavinmextern void cmi_mca_trap(struct regs *);
21420c794bgavinmextern boolean_t cmi_panic_on_ue(void);
21620c794bgavinmextern void cmi_mc_register(cmi_hdl_t, const struct cmi_mc_ops *, void *);
217a311483Gerry Liuextern cmi_errno_t cmi_mc_register_global(const struct cmi_mc_ops *, void *);
218e4b8688Cheng Sean Yeextern void cmi_mc_sw_memscrub_disable(void);
21920c794bgavinmextern cmi_errno_t cmi_mc_patounum(uint64_t, uint8_t, uint8_t, uint32_t, int,
2204156fc3gavinm    mc_unum_t *);
22120c794bgavinmextern cmi_errno_t cmi_mc_unumtopa(mc_unum_t *, nvlist_t *, uint64_t *);
22220c794bgavinmextern void cmi_mc_logout(cmi_hdl_t, boolean_t, boolean_t);
224e4b8688Cheng Sean Yeextern void cmi_panic_callback(void);
225e4b8688Cheng Sean Ye
22620c794bgavinm#endif /* _KERNEL */
2287c478bdstevel@tonic-gate#ifdef __cplusplus
2327aec1d6cindi#endif /* _SYS_CPU_MODULE_H */