17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5346af85bScwb  * Common Development and Distribution License (the "License").
6346af85bScwb  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
22e850fb01SKuriakose Kuruvilla  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
237c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
247c478bd9Sstevel@tonic-gate  */
257c478bd9Sstevel@tonic-gate 
26c7a079a8SJonathan Haslam /*
27c7a079a8SJonathan Haslam  * This file contains preset event names from the Performance Application
28c7a079a8SJonathan Haslam  * Programming Interface v3.5 which included the following notice:
29c7a079a8SJonathan Haslam  *
30c7a079a8SJonathan Haslam  *                             Copyright (c) 2005,6
31c7a079a8SJonathan Haslam  *                           Innovative Computing Labs
32c7a079a8SJonathan Haslam  *                         Computer Science Department,
33c7a079a8SJonathan Haslam  *                            University of Tennessee,
34c7a079a8SJonathan Haslam  *                                 Knoxville, TN.
35c7a079a8SJonathan Haslam  *                              All Rights Reserved.
36c7a079a8SJonathan Haslam  *
37c7a079a8SJonathan Haslam  *
38c7a079a8SJonathan Haslam  * Redistribution and use in source and binary forms, with or without
39c7a079a8SJonathan Haslam  * modification, are permitted provided that the following conditions are met:
40c7a079a8SJonathan Haslam  *
41c7a079a8SJonathan Haslam  *    * Redistributions of source code must retain the above copyright notice,
42c7a079a8SJonathan Haslam  *      this list of conditions and the following disclaimer.
43c7a079a8SJonathan Haslam  *    * Redistributions in binary form must reproduce the above copyright
44c7a079a8SJonathan Haslam  *	notice, this list of conditions and the following disclaimer in the
45c7a079a8SJonathan Haslam  *	documentation and/or other materials provided with the distribution.
46c7a079a8SJonathan Haslam  *    * Neither the name of the University of Tennessee nor the names of its
47c7a079a8SJonathan Haslam  *      contributors may be used to endorse or promote products derived from
48c7a079a8SJonathan Haslam  *	this software without specific prior written permission.
49c7a079a8SJonathan Haslam  *
50c7a079a8SJonathan Haslam  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
51c7a079a8SJonathan Haslam  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52c7a079a8SJonathan Haslam  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53c7a079a8SJonathan Haslam  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
54c7a079a8SJonathan Haslam  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55c7a079a8SJonathan Haslam  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56c7a079a8SJonathan Haslam  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57c7a079a8SJonathan Haslam  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58c7a079a8SJonathan Haslam  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59c7a079a8SJonathan Haslam  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
60c7a079a8SJonathan Haslam  * POSSIBILITY OF SUCH DAMAGE.
61c7a079a8SJonathan Haslam  *
62c7a079a8SJonathan Haslam  *
63c7a079a8SJonathan Haslam  * This open source software license conforms to the BSD License template.
64c7a079a8SJonathan Haslam  */
657c478bd9Sstevel@tonic-gate 
66e850fb01SKuriakose Kuruvilla /*
67e850fb01SKuriakose Kuruvilla  * Portions Copyright 2009 Advanced Micro Devices, Inc.
68d0e58ef5SRobert Mustacchi  * Copyright 2019 Joyent, Inc.
69281939dfSRobert Mustacchi  * Copyright 2021 Oxide Computer Company
70e850fb01SKuriakose Kuruvilla  */
71e850fb01SKuriakose Kuruvilla 
727c478bd9Sstevel@tonic-gate /*
737c478bd9Sstevel@tonic-gate  * Performance Counter Back-End for AMD Opteron and AMD Athlon 64 processors.
747c478bd9Sstevel@tonic-gate  */
757c478bd9Sstevel@tonic-gate 
767c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h>
777c478bd9Sstevel@tonic-gate #include <sys/param.h>
787c478bd9Sstevel@tonic-gate #include <sys/systm.h>
797c478bd9Sstevel@tonic-gate #include <sys/cpc_pcbe.h>
807c478bd9Sstevel@tonic-gate #include <sys/kmem.h>
817c478bd9Sstevel@tonic-gate #include <sys/sdt.h>
827c478bd9Sstevel@tonic-gate #include <sys/modctl.h>
837c478bd9Sstevel@tonic-gate #include <sys/errno.h>
847c478bd9Sstevel@tonic-gate #include <sys/debug.h>
857c478bd9Sstevel@tonic-gate #include <sys/archsystm.h>
867c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h>
877c478bd9Sstevel@tonic-gate #include <sys/privregs.h>
885d3a5ad8Srab #include <sys/ddi.h>
895d3a5ad8Srab #include <sys/sunddi.h>
907c478bd9Sstevel@tonic-gate 
91d0e58ef5SRobert Mustacchi #include "opteron_pcbe_table.h"
92d0e58ef5SRobert Mustacchi #include <opteron_pcbe_cpcgen.h>
93d0e58ef5SRobert Mustacchi 
947c478bd9Sstevel@tonic-gate static int opt_pcbe_init(void);
957c478bd9Sstevel@tonic-gate static uint_t opt_pcbe_ncounters(void);
967c478bd9Sstevel@tonic-gate static const char *opt_pcbe_impl_name(void);
977c478bd9Sstevel@tonic-gate static const char *opt_pcbe_cpuref(void);
987c478bd9Sstevel@tonic-gate static char *opt_pcbe_list_events(uint_t picnum);
997c478bd9Sstevel@tonic-gate static char *opt_pcbe_list_attrs(void);
1007c478bd9Sstevel@tonic-gate static uint64_t opt_pcbe_event_coverage(char *event);
1017c478bd9Sstevel@tonic-gate static uint64_t opt_pcbe_overflow_bitmap(void);
1027c478bd9Sstevel@tonic-gate static int opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset,
1037c478bd9Sstevel@tonic-gate     uint32_t flags, uint_t nattrs, kcpc_attr_t *attrs, void **data,
1047c478bd9Sstevel@tonic-gate     void *token);
1057c478bd9Sstevel@tonic-gate static void opt_pcbe_program(void *token);
1067c478bd9Sstevel@tonic-gate static void opt_pcbe_allstop(void);
1077c478bd9Sstevel@tonic-gate static void opt_pcbe_sample(void *token);
1087c478bd9Sstevel@tonic-gate static void opt_pcbe_free(void *config);
1097c478bd9Sstevel@tonic-gate 
1107c478bd9Sstevel@tonic-gate static pcbe_ops_t opt_pcbe_ops = {
1117c478bd9Sstevel@tonic-gate 	PCBE_VER_1,
1127c478bd9Sstevel@tonic-gate 	CPC_CAP_OVERFLOW_INTERRUPT,
1137c478bd9Sstevel@tonic-gate 	opt_pcbe_ncounters,
1147c478bd9Sstevel@tonic-gate 	opt_pcbe_impl_name,
1157c478bd9Sstevel@tonic-gate 	opt_pcbe_cpuref,
1167c478bd9Sstevel@tonic-gate 	opt_pcbe_list_events,
1177c478bd9Sstevel@tonic-gate 	opt_pcbe_list_attrs,
1187c478bd9Sstevel@tonic-gate 	opt_pcbe_event_coverage,
1197c478bd9Sstevel@tonic-gate 	opt_pcbe_overflow_bitmap,
1207c478bd9Sstevel@tonic-gate 	opt_pcbe_configure,
1217c478bd9Sstevel@tonic-gate 	opt_pcbe_program,
1227c478bd9Sstevel@tonic-gate 	opt_pcbe_allstop,
1237c478bd9Sstevel@tonic-gate 	opt_pcbe_sample,
1247c478bd9Sstevel@tonic-gate 	opt_pcbe_free
1257c478bd9Sstevel@tonic-gate };
1267c478bd9Sstevel@tonic-gate 
127d0e58ef5SRobert Mustacchi /*
128d0e58ef5SRobert Mustacchi  * Base MSR addresses for the PerfEvtSel registers and the counters themselves.
129d0e58ef5SRobert Mustacchi  * Add counter number to base address to get corresponding MSR address.
130d0e58ef5SRobert Mustacchi  */
131d0e58ef5SRobert Mustacchi #define	PES_BASE_ADDR	0xC0010000
132d0e58ef5SRobert Mustacchi #define	PIC_BASE_ADDR	0xC0010004
133d0e58ef5SRobert Mustacchi 
134d0e58ef5SRobert Mustacchi /*
135d0e58ef5SRobert Mustacchi  * Base MSR addresses for the PerfEvtSel registers and counters. The counter and
136d0e58ef5SRobert Mustacchi  * event select registers are interleaved, so one needs to multiply the counter
137d0e58ef5SRobert Mustacchi  * number by two to determine what they should be set to.
138d0e58ef5SRobert Mustacchi  */
139d0e58ef5SRobert Mustacchi #define	PES_EXT_BASE_ADDR	0xC0010200
140d0e58ef5SRobert Mustacchi #define	PIC_EXT_BASE_ADDR	0xC0010201
141d0e58ef5SRobert Mustacchi 
142d0e58ef5SRobert Mustacchi /*
143d0e58ef5SRobert Mustacchi  * The number of counters present depends on which CPU features are present.
144d0e58ef5SRobert Mustacchi  */
145d0e58ef5SRobert Mustacchi #define	OPT_PCBE_DEF_NCOUNTERS	4
146d0e58ef5SRobert Mustacchi #define	OPT_PCBE_EXT_NCOUNTERS	6
147d0e58ef5SRobert Mustacchi 
1487c478bd9Sstevel@tonic-gate /*
1497c478bd9Sstevel@tonic-gate  * Define offsets and masks for the fields in the Performance
1507c478bd9Sstevel@tonic-gate  * Event-Select (PES) registers.
1517c478bd9Sstevel@tonic-gate  */
15231725658Sksadhukh #define	OPT_PES_HOST_SHIFT	41
15331725658Sksadhukh #define	OPT_PES_GUEST_SHIFT	40
154d0e58ef5SRobert Mustacchi #define	OPT_PES_EVSELHI_SHIFT	32
1557c478bd9Sstevel@tonic-gate #define	OPT_PES_CMASK_SHIFT	24
1567c478bd9Sstevel@tonic-gate #define	OPT_PES_CMASK_MASK	0xFF
1577c478bd9Sstevel@tonic-gate #define	OPT_PES_INV_SHIFT	23
1587c478bd9Sstevel@tonic-gate #define	OPT_PES_ENABLE_SHIFT	22
1597c478bd9Sstevel@tonic-gate #define	OPT_PES_INT_SHIFT	20
1607c478bd9Sstevel@tonic-gate #define	OPT_PES_PC_SHIFT	19
1617c478bd9Sstevel@tonic-gate #define	OPT_PES_EDGE_SHIFT	18
1627c478bd9Sstevel@tonic-gate #define	OPT_PES_OS_SHIFT	17
1637c478bd9Sstevel@tonic-gate #define	OPT_PES_USR_SHIFT	16
1647c478bd9Sstevel@tonic-gate #define	OPT_PES_UMASK_SHIFT	8
1657c478bd9Sstevel@tonic-gate #define	OPT_PES_UMASK_MASK	0xFF
1667c478bd9Sstevel@tonic-gate 
16731725658Sksadhukh #define	OPT_PES_INV		(1ULL << OPT_PES_INV_SHIFT)
16831725658Sksadhukh #define	OPT_PES_ENABLE		(1ULL << OPT_PES_ENABLE_SHIFT)
16931725658Sksadhukh #define	OPT_PES_INT		(1ULL << OPT_PES_INT_SHIFT)
17031725658Sksadhukh #define	OPT_PES_PC		(1ULL << OPT_PES_PC_SHIFT)
17131725658Sksadhukh #define	OPT_PES_EDGE		(1ULL << OPT_PES_EDGE_SHIFT)
17231725658Sksadhukh #define	OPT_PES_OS		(1ULL << OPT_PES_OS_SHIFT)
17331725658Sksadhukh #define	OPT_PES_USR		(1ULL << OPT_PES_USR_SHIFT)
17431725658Sksadhukh #define	OPT_PES_HOST		(1ULL << OPT_PES_HOST_SHIFT)
17531725658Sksadhukh #define	OPT_PES_GUEST		(1ULL << OPT_PES_GUEST_SHIFT)
1767c478bd9Sstevel@tonic-gate 
1777c478bd9Sstevel@tonic-gate typedef struct _opt_pcbe_config {
1787c478bd9Sstevel@tonic-gate 	uint8_t		opt_picno;	/* Counter number: 0, 1, 2, or 3 */
1797c478bd9Sstevel@tonic-gate 	uint64_t	opt_evsel;	/* Event Selection register */
1807c478bd9Sstevel@tonic-gate 	uint64_t	opt_rawpic;	/* Raw counter value */
1817c478bd9Sstevel@tonic-gate } opt_pcbe_config_t;
1827c478bd9Sstevel@tonic-gate 
183d0e58ef5SRobert Mustacchi opt_pcbe_config_t nullcfgs[OPT_PCBE_EXT_NCOUNTERS] = {
1847c478bd9Sstevel@tonic-gate 	{ 0, 0, 0 },
1857c478bd9Sstevel@tonic-gate 	{ 1, 0, 0 },
1867c478bd9Sstevel@tonic-gate 	{ 2, 0, 0 },
187d0e58ef5SRobert Mustacchi 	{ 3, 0, 0 },
188d0e58ef5SRobert Mustacchi 	{ 4, 0, 0 },
189d0e58ef5SRobert Mustacchi 	{ 5, 0, 0 },
1907c478bd9Sstevel@tonic-gate };
1917c478bd9Sstevel@tonic-gate 
192d0e58ef5SRobert Mustacchi typedef uint64_t (*opt_pcbe_addr_f)(uint_t);
1937c478bd9Sstevel@tonic-gate 
194d0e58ef5SRobert Mustacchi typedef struct opt_pcbe_data {
195d0e58ef5SRobert Mustacchi 	uint_t		opd_ncounters;
196d0e58ef5SRobert Mustacchi 	uint_t		opd_cmask;
197d0e58ef5SRobert Mustacchi 	opt_pcbe_addr_f	opd_pesf;
198d0e58ef5SRobert Mustacchi 	opt_pcbe_addr_f	opd_picf;
199d0e58ef5SRobert Mustacchi } opt_pcbe_data_t;
200c7a079a8SJonathan Haslam 
201d0e58ef5SRobert Mustacchi opt_pcbe_data_t opd;
2027c478bd9Sstevel@tonic-gate 
2037c478bd9Sstevel@tonic-gate #define	MASK48		0xFFFFFFFFFFFF
2047c478bd9Sstevel@tonic-gate 
205e850fb01SKuriakose Kuruvilla #define	EV_END {NULL, 0}
206c7a079a8SJonathan Haslam #define	GEN_EV_END {NULL, NULL, 0 }
2077c478bd9Sstevel@tonic-gate 
208d0e58ef5SRobert Mustacchi /*
209d0e58ef5SRobert Mustacchi  * The following Macros are used to define tables of events that are used by
210d0e58ef5SRobert Mustacchi  * various families and some generic classes of events.
211d0e58ef5SRobert Mustacchi  *
212d0e58ef5SRobert Mustacchi  * When programming a performance counter there are two different values that we
213d0e58ef5SRobert Mustacchi  * need to set:
214d0e58ef5SRobert Mustacchi  *
215d0e58ef5SRobert Mustacchi  *   o Event - Determines the general class of event that is being used.
216d0e58ef5SRobert Mustacchi  *   o Unit  - A further breakdown that gives more specific value.
217d0e58ef5SRobert Mustacchi  *
218d0e58ef5SRobert Mustacchi  * Prior to the introduction of family 17h support, all family specific events
219d0e58ef5SRobert Mustacchi  * were programmed based on their event. The generic events, which tried to
220d0e58ef5SRobert Mustacchi  * provide PAPI mappings to events specified an additional unit mask.
221d0e58ef5SRobert Mustacchi  *
222d0e58ef5SRobert Mustacchi  * Starting with Family 17h, CPU performance counters default to using both the
223d0e58ef5SRobert Mustacchi  * unit mask and the event select. Generic events are always aliases to a
224d0e58ef5SRobert Mustacchi  * specific event/unit pair, hence why the units for them are always zero. In
225d0e58ef5SRobert Mustacchi  * addition, the naming of events in family 17h has been changed to reflect
226d0e58ef5SRobert Mustacchi  * AMD's guide. While this is a departure from what people are used to, it is
227d0e58ef5SRobert Mustacchi  * believed that matching the more detailed literature that folks are told to
228d0e58ef5SRobert Mustacchi  * reference is more valuable.
229d0e58ef5SRobert Mustacchi  */
230d0e58ef5SRobert Mustacchi 
231e850fb01SKuriakose Kuruvilla #define	AMD_cmn_events						\
232e850fb01SKuriakose Kuruvilla 	{ "FP_dispatched_fpu_ops",			0x0 },	\
233e850fb01SKuriakose Kuruvilla 	{ "FP_cycles_no_fpu_ops_retired",		0x1 },	\
234e850fb01SKuriakose Kuruvilla 	{ "FP_dispatched_fpu_ops_ff",			0x2 },	\
235e850fb01SKuriakose Kuruvilla 	{ "LS_seg_reg_load",				0x20 },	\
236e850fb01SKuriakose Kuruvilla 	{ "LS_uarch_resync_self_modify",		0x21 },	\
237e850fb01SKuriakose Kuruvilla 	{ "LS_uarch_resync_snoop",			0x22 },	\
238e850fb01SKuriakose Kuruvilla 	{ "LS_buffer_2_full",				0x23 },	\
239e850fb01SKuriakose Kuruvilla 	{ "LS_locked_operation",			0x24 },	\
240e850fb01SKuriakose Kuruvilla 	{ "LS_retired_cflush",				0x26 },	\
241e850fb01SKuriakose Kuruvilla 	{ "LS_retired_cpuid",				0x27 },	\
242e850fb01SKuriakose Kuruvilla 	{ "DC_access",					0x40 },	\
243e850fb01SKuriakose Kuruvilla 	{ "DC_miss",					0x41 },	\
244e850fb01SKuriakose Kuruvilla 	{ "DC_refill_from_L2",				0x42 },	\
245e850fb01SKuriakose Kuruvilla 	{ "DC_refill_from_system",			0x43 },	\
246e850fb01SKuriakose Kuruvilla 	{ "DC_copyback",				0x44 },	\
247e850fb01SKuriakose Kuruvilla 	{ "DC_dtlb_L1_miss_L2_hit",			0x45 },	\
248e850fb01SKuriakose Kuruvilla 	{ "DC_dtlb_L1_miss_L2_miss",			0x46 },	\
249e850fb01SKuriakose Kuruvilla 	{ "DC_misaligned_data_ref",			0x47 },	\
250e850fb01SKuriakose Kuruvilla 	{ "DC_uarch_late_cancel_access",		0x48 },	\
251e850fb01SKuriakose Kuruvilla 	{ "DC_uarch_early_cancel_access",		0x49 },	\
252e850fb01SKuriakose Kuruvilla 	{ "DC_1bit_ecc_error_found",			0x4A },	\
253e850fb01SKuriakose Kuruvilla 	{ "DC_dispatched_prefetch_instr",		0x4B },	\
254e850fb01SKuriakose Kuruvilla 	{ "DC_dcache_accesses_by_locks",		0x4C },	\
255e850fb01SKuriakose Kuruvilla 	{ "BU_memory_requests",				0x65 },	\
256e850fb01SKuriakose Kuruvilla 	{ "BU_data_prefetch",				0x67 },	\
257e850fb01SKuriakose Kuruvilla 	{ "BU_system_read_responses",			0x6C },	\
258e850fb01SKuriakose Kuruvilla 	{ "BU_cpu_clk_unhalted",			0x76 },	\
259e850fb01SKuriakose Kuruvilla 	{ "BU_internal_L2_req",				0x7D },	\
260e850fb01SKuriakose Kuruvilla 	{ "BU_fill_req_missed_L2",			0x7E },	\
261e850fb01SKuriakose Kuruvilla 	{ "BU_fill_into_L2",				0x7F },	\
262e850fb01SKuriakose Kuruvilla 	{ "IC_fetch",					0x80 },	\
263e850fb01SKuriakose Kuruvilla 	{ "IC_miss",					0x81 },	\
264e850fb01SKuriakose Kuruvilla 	{ "IC_refill_from_L2",				0x82 },	\
265e850fb01SKuriakose Kuruvilla 	{ "IC_refill_from_system",			0x83 },	\
266e850fb01SKuriakose Kuruvilla 	{ "IC_itlb_L1_miss_L2_hit",			0x84 },	\
267e850fb01SKuriakose Kuruvilla 	{ "IC_itlb_L1_miss_L2_miss",			0x85 },	\
268e850fb01SKuriakose Kuruvilla 	{ "IC_uarch_resync_snoop",			0x86 },	\
269e850fb01SKuriakose Kuruvilla 	{ "IC_instr_fetch_stall",			0x87 },	\
270e850fb01SKuriakose Kuruvilla 	{ "IC_return_stack_hit",			0x88 },	\
271e850fb01SKuriakose Kuruvilla 	{ "IC_return_stack_overflow",			0x89 },	\
272e850fb01SKuriakose Kuruvilla 	{ "FR_retired_x86_instr_w_excp_intr",		0xC0 },	\
273e850fb01SKuriakose Kuruvilla 	{ "FR_retired_uops",				0xC1 },	\
274e850fb01SKuriakose Kuruvilla 	{ "FR_retired_branches_w_excp_intr",		0xC2 },	\
275e850fb01SKuriakose Kuruvilla 	{ "FR_retired_branches_mispred",		0xC3 },	\
276e850fb01SKuriakose Kuruvilla 	{ "FR_retired_taken_branches",			0xC4 },	\
277e850fb01SKuriakose Kuruvilla 	{ "FR_retired_taken_branches_mispred",		0xC5 },	\
278e850fb01SKuriakose Kuruvilla 	{ "FR_retired_far_ctl_transfer",		0xC6 },	\
279e850fb01SKuriakose Kuruvilla 	{ "FR_retired_resyncs",				0xC7 },	\
280e850fb01SKuriakose Kuruvilla 	{ "FR_retired_near_rets",			0xC8 },	\
281e850fb01SKuriakose Kuruvilla 	{ "FR_retired_near_rets_mispred",		0xC9 },	\
282e850fb01SKuriakose Kuruvilla 	{ "FR_retired_taken_branches_mispred_addr_miscomp",	0xCA },\
283e850fb01SKuriakose Kuruvilla 	{ "FR_retired_fastpath_double_op_instr",	0xCC },	\
284e850fb01SKuriakose Kuruvilla 	{ "FR_intr_masked_cycles",			0xCD },	\
285e850fb01SKuriakose Kuruvilla 	{ "FR_intr_masked_while_pending_cycles",	0xCE },	\
286e850fb01SKuriakose Kuruvilla 	{ "FR_taken_hardware_intrs",			0xCF },	\
287e850fb01SKuriakose Kuruvilla 	{ "FR_nothing_to_dispatch",			0xD0 },	\
288e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stalls",				0xD1 },	\
289e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_branch_abort_to_retire",	0xD2 },	\
290e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_serialization",		0xD3 },	\
291e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_segment_load",		0xD4 },	\
292e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_reorder_buffer_full",	0xD5 },	\
293e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_resv_stations_full",	0xD6 },	\
294e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_fpu_full",			0xD7 },	\
295e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_ls_full",			0xD8 },	\
296e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_waiting_all_quiet",	0xD9 },	\
297e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_far_ctl_trsfr_resync_branch_pend",	0xDA },\
298e850fb01SKuriakose Kuruvilla 	{ "FR_fpu_exception",				0xDB },	\
299e850fb01SKuriakose Kuruvilla 	{ "FR_num_brkpts_dr0",				0xDC },	\
300e850fb01SKuriakose Kuruvilla 	{ "FR_num_brkpts_dr1",				0xDD },	\
301e850fb01SKuriakose Kuruvilla 	{ "FR_num_brkpts_dr2",				0xDE },	\
302e850fb01SKuriakose Kuruvilla 	{ "FR_num_brkpts_dr3",				0xDF },	\
303e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_page_access",			0xE0 },	\
304e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_turnaround",			0xE3 },	\
305e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_bypass_counter_saturation",	0xE4 },	\
306e850fb01SKuriakose Kuruvilla 	{ "NB_cpu_io_to_mem_io",			0xE9 },	\
307e850fb01SKuriakose Kuruvilla 	{ "NB_cache_block_commands",			0xEA },	\
308e850fb01SKuriakose Kuruvilla 	{ "NB_sized_commands",				0xEB },	\
309e850fb01SKuriakose Kuruvilla 	{ "NB_ht_bus0_bandwidth",			0xF6 }
310e850fb01SKuriakose Kuruvilla 
311e850fb01SKuriakose Kuruvilla #define	AMD_FAMILY_f_events					\
312e850fb01SKuriakose Kuruvilla 	{ "BU_quadwords_written_to_system",		0x6D },	\
313e850fb01SKuriakose Kuruvilla 	{ "FR_retired_fpu_instr",			0xCB },	\
314e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_page_table_overflow",		0xE1 },	\
315e850fb01SKuriakose Kuruvilla 	{ "NB_sized_blocks",				0xE5 },	\
316e850fb01SKuriakose Kuruvilla 	{ "NB_ECC_errors",				0xE8 },	\
317e850fb01SKuriakose Kuruvilla 	{ "NB_probe_result",				0xEC },	\
318e850fb01SKuriakose Kuruvilla 	{ "NB_gart_events",				0xEE },	\
319e850fb01SKuriakose Kuruvilla 	{ "NB_ht_bus1_bandwidth",			0xF7 },	\
320e850fb01SKuriakose Kuruvilla 	{ "NB_ht_bus2_bandwidth",			0xF8 }
321e850fb01SKuriakose Kuruvilla 
322e850fb01SKuriakose Kuruvilla #define	AMD_FAMILY_10h_events					\
323e850fb01SKuriakose Kuruvilla 	{ "FP_retired_sse_ops",				0x3 },	\
324e850fb01SKuriakose Kuruvilla 	{ "FP_retired_move_ops",			0x4 },	\
325e850fb01SKuriakose Kuruvilla 	{ "FP_retired_serialize_ops",			0x5 },	\
326e850fb01SKuriakose Kuruvilla 	{ "FP_serialize_ops_cycles",			0x6 },	\
327e850fb01SKuriakose Kuruvilla 	{ "LS_cancelled_store_to_load_fwd_ops",		0x2A },	\
328e850fb01SKuriakose Kuruvilla 	{ "LS_smi_received",				0x2B },	\
329e850fb01SKuriakose Kuruvilla 	{ "DC_dtlb_L1_hit",				0x4D },	\
330e850fb01SKuriakose Kuruvilla 	{ "LS_ineffective_prefetch",			0x52 },	\
331e850fb01SKuriakose Kuruvilla 	{ "LS_global_tlb_flush",			0x54 },	\
332e850fb01SKuriakose Kuruvilla 	{ "BU_octwords_written_to_system",		0x6D },	\
333e850fb01SKuriakose Kuruvilla 	{ "Page_size_mismatches",			0x165 },	\
334e850fb01SKuriakose Kuruvilla 	{ "IC_eviction",				0x8B },	\
335e850fb01SKuriakose Kuruvilla 	{ "IC_cache_lines_invalidate",			0x8C },	\
336e850fb01SKuriakose Kuruvilla 	{ "IC_itlb_reload",				0x99 },	\
337e850fb01SKuriakose Kuruvilla 	{ "IC_itlb_reload_aborted",			0x9A },	\
338e850fb01SKuriakose Kuruvilla 	{ "FR_retired_mmx_sse_fp_instr",		0xCB },	\
339e850fb01SKuriakose Kuruvilla 	{ "Retired_x87_fp_ops",				0x1C0 },	\
340e850fb01SKuriakose Kuruvilla 	{ "IBS_ops_tagged",				0x1CF },	\
341e850fb01SKuriakose Kuruvilla 	{ "LFENCE_inst_retired",			0x1D3 },	\
342e850fb01SKuriakose Kuruvilla 	{ "SFENCE_inst_retired",			0x1D4 },	\
343e850fb01SKuriakose Kuruvilla 	{ "MFENCE_inst_retired",			0x1D5 },	\
344e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_page_table_overflow",		0xE1 },	\
345e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_dram_cmd_slots_missed",		0xE2 },	\
346e850fb01SKuriakose Kuruvilla 	{ "NB_thermal_status",				0xE8 },	\
347e850fb01SKuriakose Kuruvilla 	{ "NB_probe_results_upstream_req",		0xEC },	\
348e850fb01SKuriakose Kuruvilla 	{ "NB_gart_events",				0xEE },	\
349e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_req",				0x1F0 },	\
350e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_to_dram_req_to_target",		0x1E0 },	\
351e850fb01SKuriakose Kuruvilla 	{ "CB_io_to_dram_req_to_target",		0x1E1 },	\
352e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_read_cmd_latency_to_target_0_to_3",	0x1E2 },	\
353e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_read_cmd_req_to_target_0_to_3",	0x1E3 },	\
354e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_read_cmd_latency_to_target_4_to_7",	0x1E4 },	\
355e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_read_cmd_req_to_target_4_to_7",	0x1E5 },	\
356e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_cmd_latency_to_target_0_to_7",	0x1E6 },	\
357e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_req_to_target_0_to_7",		0x1E7 },	\
358e850fb01SKuriakose Kuruvilla 	{ "NB_ht_bus1_bandwidth",			0xF7 },	\
359e850fb01SKuriakose Kuruvilla 	{ "NB_ht_bus2_bandwidth",			0xF8 },	\
360e850fb01SKuriakose Kuruvilla 	{ "NB_ht_bus3_bandwidth",			0x1F9 },	\
361e850fb01SKuriakose Kuruvilla 	{ "L3_read_req",				0x4E0 },	\
362e850fb01SKuriakose Kuruvilla 	{ "L3_miss",					0x4E1 },	\
363e850fb01SKuriakose Kuruvilla 	{ "L3_l2_eviction_l3_fill",			0x4E2 },	\
364e850fb01SKuriakose Kuruvilla 	{ "L3_eviction",				0x4E3 }
365e850fb01SKuriakose Kuruvilla 
366e850fb01SKuriakose Kuruvilla #define	AMD_FAMILY_11h_events					\
367e850fb01SKuriakose Kuruvilla 	{ "BU_quadwords_written_to_system",		0x6D },	\
368e850fb01SKuriakose Kuruvilla 	{ "FR_retired_mmx_fp_instr",			0xCB },	\
369e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_page_table_events",		0xE1 },	\
370e850fb01SKuriakose Kuruvilla 	{ "NB_thermal_status",				0xE8 },	\
371e850fb01SKuriakose Kuruvilla 	{ "NB_probe_results_upstream_req",		0xEC },	\
372e850fb01SKuriakose Kuruvilla 	{ "NB_dev_events",				0xEE },	\
373e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_req",				0x1F0 }
37431725658Sksadhukh 
375c7a079a8SJonathan Haslam #define	AMD_cmn_generic_events						\
376c7a079a8SJonathan Haslam 	{ "PAPI_br_ins",	"FR_retired_branches_w_excp_intr", 0x0 },\
377c7a079a8SJonathan Haslam 	{ "PAPI_br_msp",	"FR_retired_branches_mispred",	0x0 },	\
378c7a079a8SJonathan Haslam 	{ "PAPI_br_tkn",	"FR_retired_taken_branches",	0x0 },	\
379c7a079a8SJonathan Haslam 	{ "PAPI_fp_ops",	"FP_dispatched_fpu_ops",	0x3 },	\
380c7a079a8SJonathan Haslam 	{ "PAPI_fad_ins",	"FP_dispatched_fpu_ops",	0x1 },	\
381c7a079a8SJonathan Haslam 	{ "PAPI_fml_ins",	"FP_dispatched_fpu_ops",	0x2 },	\
382c7a079a8SJonathan Haslam 	{ "PAPI_fpu_idl",	"FP_cycles_no_fpu_ops_retired",	0x0 },	\
383c7a079a8SJonathan Haslam 	{ "PAPI_tot_cyc",	"BU_cpu_clk_unhalted",		0x0 },	\
384c7a079a8SJonathan Haslam 	{ "PAPI_tot_ins",	"FR_retired_x86_instr_w_excp_intr", 0x0 }, \
385c7a079a8SJonathan Haslam 	{ "PAPI_l1_dca",	"DC_access",			0x0 },	\
386c7a079a8SJonathan Haslam 	{ "PAPI_l1_dcm",	"DC_miss",			0x0 },	\
387c7a079a8SJonathan Haslam 	{ "PAPI_l1_ldm",	"DC_refill_from_L2",		0xe },	\
388c7a079a8SJonathan Haslam 	{ "PAPI_l1_stm",	"DC_refill_from_L2",		0x10 },	\
389c7a079a8SJonathan Haslam 	{ "PAPI_l1_ica",	"IC_fetch",			0x0 },	\
390c7a079a8SJonathan Haslam 	{ "PAPI_l1_icm",	"IC_miss",			0x0 },	\
391c7a079a8SJonathan Haslam 	{ "PAPI_l1_icr",	"IC_fetch",			0x0 },	\
392c7a079a8SJonathan Haslam 	{ "PAPI_l2_dch",	"DC_refill_from_L2",		0x1e },	\
393c7a079a8SJonathan Haslam 	{ "PAPI_l2_dcm",	"DC_refill_from_system",	0x1e },	\
394c7a079a8SJonathan Haslam 	{ "PAPI_l2_dcr",	"DC_refill_from_L2",		0xe },	\
395c7a079a8SJonathan Haslam 	{ "PAPI_l2_dcw",	"DC_refill_from_L2",		0x10 },	\
396c7a079a8SJonathan Haslam 	{ "PAPI_l2_ich",	"IC_refill_from_L2",		0x0 },	\
397c7a079a8SJonathan Haslam 	{ "PAPI_l2_icm",	"IC_refill_from_system",	0x0 },	\
398c7a079a8SJonathan Haslam 	{ "PAPI_l2_ldm",	"DC_refill_from_system",	0xe },	\
399c7a079a8SJonathan Haslam 	{ "PAPI_l2_stm",	"DC_refill_from_system",	0x10 },	\
400c7a079a8SJonathan Haslam 	{ "PAPI_res_stl",	"FR_dispatch_stalls",		0x0 },	\
401c7a079a8SJonathan Haslam 	{ "PAPI_stl_icy",	"FR_nothing_to_dispatch",	0x0 },	\
402c7a079a8SJonathan Haslam 	{ "PAPI_hw_int",	"FR_taken_hardware_intrs",	0x0 }
403c7a079a8SJonathan Haslam 
404c7a079a8SJonathan Haslam #define	OPT_cmn_generic_events						\
405c7a079a8SJonathan Haslam 	{ "PAPI_tlb_dm",	"DC_dtlb_L1_miss_L2_miss",	0x0 },	\
406c7a079a8SJonathan Haslam 	{ "PAPI_tlb_im",	"IC_itlb_L1_miss_L2_miss",	0x0 },	\
407c7a079a8SJonathan Haslam 	{ "PAPI_fp_ins",	"FR_retired_fpu_instr",		0xd },	\
408c7a079a8SJonathan Haslam 	{ "PAPI_vec_ins",	"FR_retired_fpu_instr",		0x4 }
409c7a079a8SJonathan Haslam 
410c7a079a8SJonathan Haslam #define	AMD_FAMILY_10h_generic_events					\
411c7a079a8SJonathan Haslam 	{ "PAPI_tlb_dm",	"DC_dtlb_L1_miss_L2_miss",	0x7 },	\
412c7a079a8SJonathan Haslam 	{ "PAPI_tlb_im",	"IC_itlb_L1_miss_L2_miss",	0x3 },	\
413c7a079a8SJonathan Haslam 	{ "PAPI_l3_dcr",	"L3_read_req",			0xf1 }, \
414c7a079a8SJonathan Haslam 	{ "PAPI_l3_icr",	"L3_read_req",			0xf2 }, \
415c7a079a8SJonathan Haslam 	{ "PAPI_l3_tcr",	"L3_read_req",			0xf7 }, \
416c7a079a8SJonathan Haslam 	{ "PAPI_l3_stm",	"L3_miss",			0xf4 }, \
417c7a079a8SJonathan Haslam 	{ "PAPI_l3_ldm",	"L3_miss",			0xf3 }, \
418c7a079a8SJonathan Haslam 	{ "PAPI_l3_tcm",	"L3_miss",			0xf7 }
419c7a079a8SJonathan Haslam 
420d0e58ef5SRobert Mustacchi static const amd_event_t family_f_events[] = {
42131725658Sksadhukh 	AMD_cmn_events,
422e850fb01SKuriakose Kuruvilla 	AMD_FAMILY_f_events,
423fb47e43fSjhaslam 	EV_END
424fb47e43fSjhaslam };
425fb47e43fSjhaslam 
426d0e58ef5SRobert Mustacchi static const amd_event_t family_10h_events[] = {
42731725658Sksadhukh 	AMD_cmn_events,
428e850fb01SKuriakose Kuruvilla 	AMD_FAMILY_10h_events,
4297c478bd9Sstevel@tonic-gate 	EV_END
4307c478bd9Sstevel@tonic-gate };
4317c478bd9Sstevel@tonic-gate 
432d0e58ef5SRobert Mustacchi static const amd_event_t family_11h_events[] = {
43331725658Sksadhukh 	AMD_cmn_events,
434e850fb01SKuriakose Kuruvilla 	AMD_FAMILY_11h_events,
43531725658Sksadhukh 	EV_END
43631725658Sksadhukh };
43731725658Sksadhukh 
438d0e58ef5SRobert Mustacchi static const amd_generic_event_t opt_generic_events[] = {
439c7a079a8SJonathan Haslam 	AMD_cmn_generic_events,
440c7a079a8SJonathan Haslam 	OPT_cmn_generic_events,
441c7a079a8SJonathan Haslam 	GEN_EV_END
442c7a079a8SJonathan Haslam };
443c7a079a8SJonathan Haslam 
444d0e58ef5SRobert Mustacchi static const amd_generic_event_t family_10h_generic_events[] = {
445c7a079a8SJonathan Haslam 	AMD_cmn_generic_events,
446c7a079a8SJonathan Haslam 	AMD_FAMILY_10h_generic_events,
447c7a079a8SJonathan Haslam 	GEN_EV_END
448c7a079a8SJonathan Haslam };
449c7a079a8SJonathan Haslam 
450d0e58ef5SRobert Mustacchi /*
451281939dfSRobert Mustacchi  * For Family 17h and Family 19h, the cpcgen utility generates all of our events
452281939dfSRobert Mustacchi  * including ones that need specific unit codes, therefore we leave all unit
453281939dfSRobert Mustacchi  * codes out of these. Zen 1, Zen 2, and Zen 3 have different event sets that
454281939dfSRobert Mustacchi  * they support.
455d0e58ef5SRobert Mustacchi  */
45631aa6202SRobert Mustacchi static const amd_generic_event_t family_17h_zen1_papi_events[] = {
457d0e58ef5SRobert Mustacchi 	{ "PAPI_br_cn",		"ExRetCond" },
45831aa6202SRobert Mustacchi 	{ "PAPI_br_ins",	"ExRetBrn" },
459d0e58ef5SRobert Mustacchi 	{ "PAPI_fpu_idl",	"FpSchedEmpty" },
460d0e58ef5SRobert Mustacchi 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
461d0e58ef5SRobert Mustacchi 	{ "PAPI_tot_ins",	"ExRetInstr" },
462d0e58ef5SRobert Mustacchi 	{ "PAPI_tlb_dm",	"LsL1DTlbMiss" },
463d0e58ef5SRobert Mustacchi 	{ "PAPI_tlb_im",	"BpL1TlbMissL2Miss" },
464d0e58ef5SRobert Mustacchi 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
465d0e58ef5SRobert Mustacchi 	GEN_EV_END
466d0e58ef5SRobert Mustacchi };
467d0e58ef5SRobert Mustacchi 
46831aa6202SRobert Mustacchi static const amd_generic_event_t family_17h_zen2_papi_events[] = {
46931aa6202SRobert Mustacchi 	{ "PAPI_br_cn",		"ExRetCond" },
47031aa6202SRobert Mustacchi 	{ "PAPI_br_ins",	"ExRetBrn" },
47131aa6202SRobert Mustacchi 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
47231aa6202SRobert Mustacchi 	{ "PAPI_tot_ins",	"ExRetInstr" },
47331aa6202SRobert Mustacchi 	{ "PAPI_tlb_dm",	"LsL1DTlbMiss" },
47431aa6202SRobert Mustacchi 	{ "PAPI_tlb_im",	"BpL1TlbMissL2Miss" },
47531aa6202SRobert Mustacchi 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
47631aa6202SRobert Mustacchi 	GEN_EV_END
47731aa6202SRobert Mustacchi };
47831aa6202SRobert Mustacchi 
479281939dfSRobert Mustacchi static const amd_generic_event_t family_19h_zen3_papi_events[] = {
480281939dfSRobert Mustacchi 	{ "PAPI_br_cn",		"ExRetCond" },
481281939dfSRobert Mustacchi 	{ "PAPI_br_ins",	"ExRetBrn" },
482281939dfSRobert Mustacchi 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
483281939dfSRobert Mustacchi 	{ "PAPI_tot_ins",	"ExRetInstr" },
484281939dfSRobert Mustacchi 	{ "PAPI_tlb_dm",	"LsL1DTlbMiss" },
485281939dfSRobert Mustacchi 	{ "PAPI_tlb_im",	"BpL1TlbMissL2TlbMiss" },
486281939dfSRobert Mustacchi 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
487281939dfSRobert Mustacchi 	GEN_EV_END
488281939dfSRobert Mustacchi };
489281939dfSRobert Mustacchi 
490281939dfSRobert Mustacchi 
49131aa6202SRobert Mustacchi 
4927c478bd9Sstevel@tonic-gate static char	*evlist;
4937c478bd9Sstevel@tonic-gate static size_t	evlist_sz;
494d0e58ef5SRobert Mustacchi static const amd_event_t *amd_events = NULL;
495d0e58ef5SRobert Mustacchi static uint_t amd_family, amd_model;
496d0e58ef5SRobert Mustacchi static const amd_generic_event_t *amd_generic_events = NULL;
4977c478bd9Sstevel@tonic-gate 
498d0e58ef5SRobert Mustacchi static char amd_fam_f_rev_ae_bkdg[] = "See \"BIOS and Kernel Developer's "
499e850fb01SKuriakose Kuruvilla "Guide for AMD Athlon 64 and AMD Opteron Processors\" (AMD publication 26094)";
500d0e58ef5SRobert Mustacchi static char amd_fam_f_NPT_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
501e850fb01SKuriakose Kuruvilla "for AMD NPT Family 0Fh Processors\" (AMD publication 32559)";
502d0e58ef5SRobert Mustacchi static char amd_fam_10h_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
503e850fb01SKuriakose Kuruvilla "(BKDG) For AMD Family 10h Processors\" (AMD publication 31116)";
504d0e58ef5SRobert Mustacchi static char amd_fam_11h_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
505e850fb01SKuriakose Kuruvilla "(BKDG) For AMD Family 11h Processors\" (AMD publication 41256)";
50631aa6202SRobert Mustacchi static char amd_fam_17h_zen1_reg[] = "See \"Open-Source Register Reference For "
507d0e58ef5SRobert Mustacchi "AMD Family 17h Processors Models 00h-2Fh\" (AMD publication 56255) and "
50831aa6202SRobert Mustacchi "amd_f17h_zen1_events(3CPC)";
50931aa6202SRobert Mustacchi static char amd_fam_17h_zen2_reg[] = "See \"Preliminary Processor Programming "
51031aa6202SRobert Mustacchi "Reference (PPR) for AMD Family 17h Model 31h, Revision B0 Processors\" "
51131aa6202SRobert Mustacchi "(AMD publication 55803), \"Processor Programming Reference (PPR) for AMD "
51231aa6202SRobert Mustacchi "Family 17h Model 71h, Revision B0 Processors\" (AMD publication 56176), and "
51331aa6202SRobert Mustacchi "amd_f17h_zen2_events(3CPC)";
514281939dfSRobert Mustacchi static char amd_fam_19h_zen3_reg[] = "See \"Preliminary Processor Programming "
515281939dfSRobert Mustacchi "Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors Volume "
516*8efb7381SRobert Mustacchi "1 of 2\" (AMD publication 55898), \"Processor Programming Reference (PPR) "
517*8efb7381SRobert Mustacchi "for AMD Family 19h Model 21h, Revision B0 Processors\" (AMD publication "
518*8efb7381SRobert Mustacchi "56214), and amd_f17h_zen3_events(3CPC)";
519e850fb01SKuriakose Kuruvilla 
520e850fb01SKuriakose Kuruvilla static char amd_pcbe_impl_name[64];
521e850fb01SKuriakose Kuruvilla static char *amd_pcbe_cpuref;
522e850fb01SKuriakose Kuruvilla 
523e850fb01SKuriakose Kuruvilla 
5247c478bd9Sstevel@tonic-gate #define	BITS(v, u, l)   \
5257c478bd9Sstevel@tonic-gate 	(((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1))
5267c478bd9Sstevel@tonic-gate 
527d0e58ef5SRobert Mustacchi static uint64_t
opt_pcbe_pes_addr(uint_t counter)528d0e58ef5SRobert Mustacchi opt_pcbe_pes_addr(uint_t counter)
529d0e58ef5SRobert Mustacchi {
530d0e58ef5SRobert Mustacchi 	ASSERT3U(counter, <, opd.opd_ncounters);
531d0e58ef5SRobert Mustacchi 	return (PES_BASE_ADDR + counter);
532d0e58ef5SRobert Mustacchi }
533d0e58ef5SRobert Mustacchi 
534d0e58ef5SRobert Mustacchi static uint64_t
opt_pcbe_pes_ext_addr(uint_t counter)535d0e58ef5SRobert Mustacchi opt_pcbe_pes_ext_addr(uint_t counter)
536d0e58ef5SRobert Mustacchi {
537d0e58ef5SRobert Mustacchi 	ASSERT3U(counter, <, opd.opd_ncounters);
538d0e58ef5SRobert Mustacchi 	return (PES_EXT_BASE_ADDR + 2 * counter);
539d0e58ef5SRobert Mustacchi }
540d0e58ef5SRobert Mustacchi 
541d0e58ef5SRobert Mustacchi static uint64_t
opt_pcbe_pic_addr(uint_t counter)542d0e58ef5SRobert Mustacchi opt_pcbe_pic_addr(uint_t counter)
543d0e58ef5SRobert Mustacchi {
544d0e58ef5SRobert Mustacchi 	ASSERT3U(counter, <, opd.opd_ncounters);
545d0e58ef5SRobert Mustacchi 	return (PIC_BASE_ADDR + 2 * counter);
546d0e58ef5SRobert Mustacchi }
547d0e58ef5SRobert Mustacchi 
548d0e58ef5SRobert Mustacchi static uint64_t
opt_pcbe_pic_ext_addr(uint_t counter)549d0e58ef5SRobert Mustacchi opt_pcbe_pic_ext_addr(uint_t counter)
550d0e58ef5SRobert Mustacchi {
551d0e58ef5SRobert Mustacchi 	ASSERT3U(counter, <, opd.opd_ncounters);
552d0e58ef5SRobert Mustacchi 	return (PIC_EXT_BASE_ADDR + 2 * counter);
553d0e58ef5SRobert Mustacchi }
5547c478bd9Sstevel@tonic-gate 
5557c478bd9Sstevel@tonic-gate static int
opt_pcbe_init(void)5567c478bd9Sstevel@tonic-gate opt_pcbe_init(void)
5577c478bd9Sstevel@tonic-gate {
558d0e58ef5SRobert Mustacchi 	const amd_event_t		*evp;
559d0e58ef5SRobert Mustacchi 	const amd_generic_event_t	*gevp;
5607c478bd9Sstevel@tonic-gate 
56131725658Sksadhukh 	amd_family = cpuid_getfamily(CPU);
562d0e58ef5SRobert Mustacchi 	amd_model = cpuid_getmodel(CPU);
56331725658Sksadhukh 
5647c478bd9Sstevel@tonic-gate 	/*
5657c478bd9Sstevel@tonic-gate 	 * Make sure this really _is_ an Opteron or Athlon 64 system. The kernel
5667c478bd9Sstevel@tonic-gate 	 * loads this module based on its name in the module directory, but it
5677c478bd9Sstevel@tonic-gate 	 * could have been renamed.
5687c478bd9Sstevel@tonic-gate 	 */
5699b0429a1SPu Wen 	if ((cpuid_getvendor(CPU) != X86_VENDOR_AMD || amd_family < 0xf) &&
5709b0429a1SPu Wen 	    cpuid_getvendor(CPU) != X86_VENDOR_HYGON)
5717c478bd9Sstevel@tonic-gate 		return (-1);
5727c478bd9Sstevel@tonic-gate 
573d0e58ef5SRobert Mustacchi 	if (amd_family == 0xf) {
574e850fb01SKuriakose Kuruvilla 		/* Some tools expect this string for family 0fh */
575c1374a13SSurya Prakki 		(void) snprintf(amd_pcbe_impl_name, sizeof (amd_pcbe_impl_name),
576e850fb01SKuriakose Kuruvilla 		    "AMD Opteron & Athlon64");
577d0e58ef5SRobert Mustacchi 	} else {
578c1374a13SSurya Prakki 		(void) snprintf(amd_pcbe_impl_name, sizeof (amd_pcbe_impl_name),
5799b0429a1SPu Wen 		    "%s Family %02xh",
5809b0429a1SPu Wen 		    cpuid_getvendor(CPU) == X86_VENDOR_HYGON ? "Hygon" : "AMD",
5819b0429a1SPu Wen 		    amd_family);
582d0e58ef5SRobert Mustacchi 	}
583d0e58ef5SRobert Mustacchi 
584d0e58ef5SRobert Mustacchi 	/*
585d0e58ef5SRobert Mustacchi 	 * Determine whether or not the extended counter set is supported on
586d0e58ef5SRobert Mustacchi 	 * this processor.
587d0e58ef5SRobert Mustacchi 	 */
588d0e58ef5SRobert Mustacchi 	if (is_x86_feature(x86_featureset, X86FSET_AMD_PCEC)) {
589d0e58ef5SRobert Mustacchi 		opd.opd_ncounters = OPT_PCBE_EXT_NCOUNTERS;
590d0e58ef5SRobert Mustacchi 		opd.opd_pesf = opt_pcbe_pes_ext_addr;
591d0e58ef5SRobert Mustacchi 		opd.opd_picf = opt_pcbe_pic_ext_addr;
592d0e58ef5SRobert Mustacchi 	} else {
593d0e58ef5SRobert Mustacchi 		opd.opd_ncounters = OPT_PCBE_DEF_NCOUNTERS;
594d0e58ef5SRobert Mustacchi 		opd.opd_pesf = opt_pcbe_pes_addr;
595d0e58ef5SRobert Mustacchi 		opd.opd_picf = opt_pcbe_pic_addr;
596d0e58ef5SRobert Mustacchi 	}
597d0e58ef5SRobert Mustacchi 	opd.opd_cmask = (1 << opd.opd_ncounters) - 1;
598e850fb01SKuriakose Kuruvilla 
599fb47e43fSjhaslam 	/*
600fb47e43fSjhaslam 	 * Figure out processor revision here and assign appropriate
601fb47e43fSjhaslam 	 * event configuration.
602fb47e43fSjhaslam 	 */
603fb47e43fSjhaslam 
604e850fb01SKuriakose Kuruvilla 	if (amd_family == 0xf) {
605e850fb01SKuriakose Kuruvilla 		uint32_t rev;
606e850fb01SKuriakose Kuruvilla 
607e850fb01SKuriakose Kuruvilla 		rev = cpuid_getchiprev(CPU);
608fb47e43fSjhaslam 
609e850fb01SKuriakose Kuruvilla 		if (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_F))
610e850fb01SKuriakose Kuruvilla 			amd_pcbe_cpuref = amd_fam_f_NPT_bkdg;
611e850fb01SKuriakose Kuruvilla 		else
612e850fb01SKuriakose Kuruvilla 			amd_pcbe_cpuref = amd_fam_f_rev_ae_bkdg;
613e850fb01SKuriakose Kuruvilla 		amd_events = family_f_events;
614c7a079a8SJonathan Haslam 		amd_generic_events = opt_generic_events;
615e850fb01SKuriakose Kuruvilla 	} else if (amd_family == 0x10) {
616e850fb01SKuriakose Kuruvilla 		amd_pcbe_cpuref = amd_fam_10h_bkdg;
61731725658Sksadhukh 		amd_events = family_10h_events;
618c7a079a8SJonathan Haslam 		amd_generic_events = family_10h_generic_events;
619e850fb01SKuriakose Kuruvilla 	} else if (amd_family == 0x11) {
620e850fb01SKuriakose Kuruvilla 		amd_pcbe_cpuref = amd_fam_11h_bkdg;
621e850fb01SKuriakose Kuruvilla 		amd_events = family_11h_events;
622e850fb01SKuriakose Kuruvilla 		amd_generic_events = opt_generic_events;
6239b0429a1SPu Wen 	} else if ((amd_family == 0x17 && amd_model <= 0x2f) ||
6249b0429a1SPu Wen 	    amd_family == 0x18) {
62531aa6202SRobert Mustacchi 		amd_pcbe_cpuref = amd_fam_17h_zen1_reg;
62631aa6202SRobert Mustacchi 		amd_events = opteron_pcbe_f17h_zen1_events;
62731aa6202SRobert Mustacchi 		amd_generic_events = family_17h_zen1_papi_events;
62831aa6202SRobert Mustacchi 	} else if (amd_family == 0x17 && amd_model >= 0x30 &&
62931aa6202SRobert Mustacchi 	    amd_model <= 0x7f) {
63031aa6202SRobert Mustacchi 		amd_pcbe_cpuref = amd_fam_17h_zen2_reg;
63131aa6202SRobert Mustacchi 		amd_events = opteron_pcbe_f17h_zen2_events;
63231aa6202SRobert Mustacchi 		amd_generic_events = family_17h_zen2_papi_events;
633*8efb7381SRobert Mustacchi 	} else if (amd_family == 0x19 && (amd_model <= 0xf ||
634*8efb7381SRobert Mustacchi 	    (amd_model >= 0x20 && amd_model <= 0x2f))) {
635281939dfSRobert Mustacchi 		amd_pcbe_cpuref = amd_fam_19h_zen3_reg;
636281939dfSRobert Mustacchi 		amd_events = opteron_pcbe_f19h_zen3_events;
637281939dfSRobert Mustacchi 		amd_generic_events = family_19h_zen3_papi_events;
638e850fb01SKuriakose Kuruvilla 	} else {
639e850fb01SKuriakose Kuruvilla 		/*
640d0e58ef5SRobert Mustacchi 		 * Different families have different meanings on events and even
641d0e58ef5SRobert Mustacchi 		 * worse (like family 15h), different constraints around
642d0e58ef5SRobert Mustacchi 		 * programming these values.
643e850fb01SKuriakose Kuruvilla 		 */
644d0e58ef5SRobert Mustacchi 		return (-1);
64531725658Sksadhukh 	}
646fb47e43fSjhaslam 
6477c478bd9Sstevel@tonic-gate 	/*
6487c478bd9Sstevel@tonic-gate 	 * Construct event list.
6497c478bd9Sstevel@tonic-gate 	 *
6507c478bd9Sstevel@tonic-gate 	 * First pass:  Calculate size needed. We'll need an additional byte
6517c478bd9Sstevel@tonic-gate 	 *		for the NULL pointer during the last strcat.
6527c478bd9Sstevel@tonic-gate 	 *
6537c478bd9Sstevel@tonic-gate 	 * Second pass: Copy strings.
6547c478bd9Sstevel@tonic-gate 	 */
65531725658Sksadhukh 	for (evp = amd_events; evp->name != NULL; evp++)
6567c478bd9Sstevel@tonic-gate 		evlist_sz += strlen(evp->name) + 1;
6577c478bd9Sstevel@tonic-gate 
658c7a079a8SJonathan Haslam 	for (gevp = amd_generic_events; gevp->name != NULL; gevp++)
659c7a079a8SJonathan Haslam 		evlist_sz += strlen(gevp->name) + 1;
660c7a079a8SJonathan Haslam 
6617c478bd9Sstevel@tonic-gate 	evlist = kmem_alloc(evlist_sz + 1, KM_SLEEP);
6627c478bd9Sstevel@tonic-gate 	evlist[0] = '\0';
6637c478bd9Sstevel@tonic-gate 
66431725658Sksadhukh 	for (evp = amd_events; evp->name != NULL; evp++) {
6657c478bd9Sstevel@tonic-gate 		(void) strcat(evlist, evp->name);
6667c478bd9Sstevel@tonic-gate 		(void) strcat(evlist, ",");
6677c478bd9Sstevel@tonic-gate 	}
668c7a079a8SJonathan Haslam 
669c7a079a8SJonathan Haslam 	for (gevp = amd_generic_events; gevp->name != NULL; gevp++) {
670c7a079a8SJonathan Haslam 		(void) strcat(evlist, gevp->name);
671c7a079a8SJonathan Haslam 		(void) strcat(evlist, ",");
672c7a079a8SJonathan Haslam 	}
673c7a079a8SJonathan Haslam 
6747c478bd9Sstevel@tonic-gate 	/*
6757c478bd9Sstevel@tonic-gate 	 * Remove trailing comma.
6767c478bd9Sstevel@tonic-gate 	 */
6777c478bd9Sstevel@tonic-gate 	evlist[evlist_sz - 1] = '\0';
6787c478bd9Sstevel@tonic-gate 
6797c478bd9Sstevel@tonic-gate 	return (0);
6807c478bd9Sstevel@tonic-gate }
6817c478bd9Sstevel@tonic-gate 
6827c478bd9Sstevel@tonic-gate static uint_t
opt_pcbe_ncounters(void)6837c478bd9Sstevel@tonic-gate opt_pcbe_ncounters(void)
6847c478bd9Sstevel@tonic-gate {
685d0e58ef5SRobert Mustacchi 	return (opd.opd_ncounters);
6867c478bd9Sstevel@tonic-gate }
6877c478bd9Sstevel@tonic-gate 
6887c478bd9Sstevel@tonic-gate static const char *
opt_pcbe_impl_name(void)6897c478bd9Sstevel@tonic-gate opt_pcbe_impl_name(void)
6907c478bd9Sstevel@tonic-gate {
691e850fb01SKuriakose Kuruvilla 	return (amd_pcbe_impl_name);
6927c478bd9Sstevel@tonic-gate }
6937c478bd9Sstevel@tonic-gate 
6947c478bd9Sstevel@tonic-gate static const char *
opt_pcbe_cpuref(void)6957c478bd9Sstevel@tonic-gate opt_pcbe_cpuref(void)
6967c478bd9Sstevel@tonic-gate {
697e850fb01SKuriakose Kuruvilla 
698e850fb01SKuriakose Kuruvilla 	return (amd_pcbe_cpuref);
6997c478bd9Sstevel@tonic-gate }
7007c478bd9Sstevel@tonic-gate 
7017c478bd9Sstevel@tonic-gate /*ARGSUSED*/
7027c478bd9Sstevel@tonic-gate static char *
opt_pcbe_list_events(uint_t picnum)7037c478bd9Sstevel@tonic-gate opt_pcbe_list_events(uint_t picnum)
7047c478bd9Sstevel@tonic-gate {
7057c478bd9Sstevel@tonic-gate 	return (evlist);
7067c478bd9Sstevel@tonic-gate }
7077c478bd9Sstevel@tonic-gate 
7087c478bd9Sstevel@tonic-gate static char *
opt_pcbe_list_attrs(void)7097c478bd9Sstevel@tonic-gate opt_pcbe_list_attrs(void)
7107c478bd9Sstevel@tonic-gate {
7117c478bd9Sstevel@tonic-gate 	return ("edge,pc,inv,cmask,umask");
7127c478bd9Sstevel@tonic-gate }
7137c478bd9Sstevel@tonic-gate 
714d0e58ef5SRobert Mustacchi static const amd_generic_event_t *
find_generic_event(char * name)715c7a079a8SJonathan Haslam find_generic_event(char *name)
716c7a079a8SJonathan Haslam {
717d0e58ef5SRobert Mustacchi 	const amd_generic_event_t	*gevp;
718c7a079a8SJonathan Haslam 
719c7a079a8SJonathan Haslam 	for (gevp = amd_generic_events; gevp->name != NULL; gevp++)
720c7a079a8SJonathan Haslam 		if (strcmp(name, gevp->name) == 0)
721c7a079a8SJonathan Haslam 			return (gevp);
722c7a079a8SJonathan Haslam 
723c7a079a8SJonathan Haslam 	return (NULL);
724c7a079a8SJonathan Haslam }
725c7a079a8SJonathan Haslam 
726d0e58ef5SRobert Mustacchi static const amd_event_t *
find_event(char * name)7277c478bd9Sstevel@tonic-gate find_event(char *name)
7287c478bd9Sstevel@tonic-gate {
729d0e58ef5SRobert Mustacchi 	const amd_event_t	*evp;
7307c478bd9Sstevel@tonic-gate 
73131725658Sksadhukh 	for (evp = amd_events; evp->name != NULL; evp++)
7327c478bd9Sstevel@tonic-gate 		if (strcmp(name, evp->name) == 0)
7337c478bd9Sstevel@tonic-gate 			return (evp);
7347c478bd9Sstevel@tonic-gate 
7357c478bd9Sstevel@tonic-gate 	return (NULL);
7367c478bd9Sstevel@tonic-gate }
7377c478bd9Sstevel@tonic-gate 
738b885580bSAlexander Kolbasov /*ARGSUSED*/
739b885580bSAlexander Kolbasov static uint64_t
opt_pcbe_event_coverage(char * event)740b885580bSAlexander Kolbasov opt_pcbe_event_coverage(char *event)
741b885580bSAlexander Kolbasov {
742b885580bSAlexander Kolbasov 	/*
743b885580bSAlexander Kolbasov 	 * Check whether counter event is supported
744b885580bSAlexander Kolbasov 	 */
745b885580bSAlexander Kolbasov 	if (find_event(event) == NULL && find_generic_event(event) == NULL)
746b885580bSAlexander Kolbasov 		return (0);
747b885580bSAlexander Kolbasov 
748b885580bSAlexander Kolbasov 	/*
749b885580bSAlexander Kolbasov 	 * Fortunately, all counters can count all events.
750b885580bSAlexander Kolbasov 	 */
751d0e58ef5SRobert Mustacchi 	return (opd.opd_cmask);
752b885580bSAlexander Kolbasov }
753b885580bSAlexander Kolbasov 
754b885580bSAlexander Kolbasov static uint64_t
opt_pcbe_overflow_bitmap(void)755b885580bSAlexander Kolbasov opt_pcbe_overflow_bitmap(void)
756b885580bSAlexander Kolbasov {
757b885580bSAlexander Kolbasov 	/*
758b885580bSAlexander Kolbasov 	 * Unfortunately, this chip cannot detect which counter overflowed, so
759b885580bSAlexander Kolbasov 	 * we must act as if they all did.
760b885580bSAlexander Kolbasov 	 */
761d0e58ef5SRobert Mustacchi 	return (opd.opd_cmask);
762b885580bSAlexander Kolbasov }
763b885580bSAlexander Kolbasov 
7647c478bd9Sstevel@tonic-gate /*ARGSUSED*/
7657c478bd9Sstevel@tonic-gate static int
opt_pcbe_configure(uint_t picnum,char * event,uint64_t preset,uint32_t flags,uint_t nattrs,kcpc_attr_t * attrs,void ** data,void * token)7667c478bd9Sstevel@tonic-gate opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, uint32_t flags,
7677c478bd9Sstevel@tonic-gate     uint_t nattrs, kcpc_attr_t *attrs, void **data, void *token)
7687c478bd9Sstevel@tonic-gate {
769d0e58ef5SRobert Mustacchi 	opt_pcbe_config_t		*cfg;
770d0e58ef5SRobert Mustacchi 	const amd_event_t		*evp;
771d0e58ef5SRobert Mustacchi 	amd_event_t			ev_raw = { "raw", 0};
772d0e58ef5SRobert Mustacchi 	const amd_generic_event_t	*gevp;
773d0e58ef5SRobert Mustacchi 	int				i;
774d0e58ef5SRobert Mustacchi 	uint64_t			evsel = 0, evsel_tmp = 0;
7757c478bd9Sstevel@tonic-gate 
7767c478bd9Sstevel@tonic-gate 	/*
7777c478bd9Sstevel@tonic-gate 	 * If we've been handed an existing configuration, we need only preset
7787c478bd9Sstevel@tonic-gate 	 * the counter value.
7797c478bd9Sstevel@tonic-gate 	 */
7807c478bd9Sstevel@tonic-gate 	if (*data != NULL) {
7817c478bd9Sstevel@tonic-gate 		cfg = *data;
7827c478bd9Sstevel@tonic-gate 		cfg->opt_rawpic = preset & MASK48;
7837c478bd9Sstevel@tonic-gate 		return (0);
7847c478bd9Sstevel@tonic-gate 	}
7857c478bd9Sstevel@tonic-gate 
786d0e58ef5SRobert Mustacchi 	if (picnum >= opd.opd_ncounters)
7877c478bd9Sstevel@tonic-gate 		return (CPC_INVALID_PICNUM);
7887c478bd9Sstevel@tonic-gate 
7895d3a5ad8Srab 	if ((evp = find_event(event)) == NULL) {
790c7a079a8SJonathan Haslam 		if ((gevp = find_generic_event(event)) != NULL) {
791c7a079a8SJonathan Haslam 			evp = find_event(gevp->event);
792c7a079a8SJonathan Haslam 			ASSERT(evp != NULL);
7935d3a5ad8Srab 
794c7a079a8SJonathan Haslam 			if (nattrs > 0)
795c7a079a8SJonathan Haslam 				return (CPC_ATTRIBUTE_OUT_OF_RANGE);
7965d3a5ad8Srab 
797c7a079a8SJonathan Haslam 			evsel |= gevp->umask << OPT_PES_UMASK_SHIFT;
798c7a079a8SJonathan Haslam 		} else {
799c7a079a8SJonathan Haslam 			long tmp;
800c7a079a8SJonathan Haslam 
801c7a079a8SJonathan Haslam 			/*
802c7a079a8SJonathan Haslam 			 * If ddi_strtol() likes this event, use it as a raw
803c7a079a8SJonathan Haslam 			 * event code.
804c7a079a8SJonathan Haslam 			 */
805c7a079a8SJonathan Haslam 			if (ddi_strtol(event, NULL, 0, &tmp) != 0)
806c7a079a8SJonathan Haslam 				return (CPC_INVALID_EVENT);
807c7a079a8SJonathan Haslam 
808c7a079a8SJonathan Haslam 			ev_raw.emask = tmp;
809c7a079a8SJonathan Haslam 			evp = &ev_raw;
810c7a079a8SJonathan Haslam 		}
8115d3a5ad8Srab 	}
8127c478bd9Sstevel@tonic-gate 
81331725658Sksadhukh 	/*
814e850fb01SKuriakose Kuruvilla 	 * Configuration of EventSelect register. While on some families
815e850fb01SKuriakose Kuruvilla 	 * certain bits might not be supported (e.g. Guest/Host on family
816e850fb01SKuriakose Kuruvilla 	 * 11h), setting these bits is harmless
81731725658Sksadhukh 	 */
81831725658Sksadhukh 
819e850fb01SKuriakose Kuruvilla 	/* Set GuestOnly bit to 0 and HostOnly bit to 1 */
820e850fb01SKuriakose Kuruvilla 	evsel &= ~OPT_PES_HOST;
821e850fb01SKuriakose Kuruvilla 	evsel &= ~OPT_PES_GUEST;
82231725658Sksadhukh 
823e850fb01SKuriakose Kuruvilla 	/* Set bits [35:32] for extended part of Event Select field */
824e850fb01SKuriakose Kuruvilla 	evsel_tmp = evp->emask & 0x0f00;
825d0e58ef5SRobert Mustacchi 	evsel |= evsel_tmp << OPT_PES_EVSELHI_SHIFT;
82631725658Sksadhukh 
82731725658Sksadhukh 	evsel |= evp->emask & 0x00ff;
828d0e58ef5SRobert Mustacchi 	evsel |= evp->unit << OPT_PES_UMASK_SHIFT;
8297c478bd9Sstevel@tonic-gate 
8307c478bd9Sstevel@tonic-gate 	if (flags & CPC_COUNT_USER)
8317c478bd9Sstevel@tonic-gate 		evsel |= OPT_PES_USR;
8327c478bd9Sstevel@tonic-gate 	if (flags & CPC_COUNT_SYSTEM)
8337c478bd9Sstevel@tonic-gate 		evsel |= OPT_PES_OS;
8347c478bd9Sstevel@tonic-gate 	if (flags & CPC_OVF_NOTIFY_EMT)
8357c478bd9Sstevel@tonic-gate 		evsel |= OPT_PES_INT;
8367c478bd9Sstevel@tonic-gate 
8377c478bd9Sstevel@tonic-gate 	for (i = 0; i < nattrs; i++) {
8387c478bd9Sstevel@tonic-gate 		if (strcmp(attrs[i].ka_name, "edge") == 0) {
8397c478bd9Sstevel@tonic-gate 			if (attrs[i].ka_val != 0)
8407c478bd9Sstevel@tonic-gate 				evsel |= OPT_PES_EDGE;
8417c478bd9Sstevel@tonic-gate 		} else if (strcmp(attrs[i].ka_name, "pc") == 0) {
8427c478bd9Sstevel@tonic-gate 			if (attrs[i].ka_val != 0)
8437c478bd9Sstevel@tonic-gate 				evsel |= OPT_PES_PC;
8447c478bd9Sstevel@tonic-gate 		} else if (strcmp(attrs[i].ka_name, "inv") == 0) {
8457c478bd9Sstevel@tonic-gate 			if (attrs[i].ka_val != 0)
8467c478bd9Sstevel@tonic-gate 				evsel |= OPT_PES_INV;
8477c478bd9Sstevel@tonic-gate 		} else if (strcmp(attrs[i].ka_name, "cmask") == 0) {
8487c478bd9Sstevel@tonic-gate 			if ((attrs[i].ka_val | OPT_PES_CMASK_MASK) !=
8497c478bd9Sstevel@tonic-gate 			    OPT_PES_CMASK_MASK)
8507c478bd9Sstevel@tonic-gate 				return (CPC_ATTRIBUTE_OUT_OF_RANGE);
8517c478bd9Sstevel@tonic-gate 			evsel |= attrs[i].ka_val << OPT_PES_CMASK_SHIFT;
8527c478bd9Sstevel@tonic-gate 		} else if (strcmp(attrs[i].ka_name, "umask") == 0) {
853e850fb01SKuriakose Kuruvilla 			if ((attrs[i].ka_val | OPT_PES_UMASK_MASK) !=
854e850fb01SKuriakose Kuruvilla 			    OPT_PES_UMASK_MASK)
8557c478bd9Sstevel@tonic-gate 				return (CPC_ATTRIBUTE_OUT_OF_RANGE);
8567c478bd9Sstevel@tonic-gate 			evsel |= attrs[i].ka_val << OPT_PES_UMASK_SHIFT;
8577c478bd9Sstevel@tonic-gate 		} else
8587c478bd9Sstevel@tonic-gate 			return (CPC_INVALID_ATTRIBUTE);
8597c478bd9Sstevel@tonic-gate 	}
8607c478bd9Sstevel@tonic-gate 
8617c478bd9Sstevel@tonic-gate 	cfg = kmem_alloc(sizeof (*cfg), KM_SLEEP);
8627c478bd9Sstevel@tonic-gate 
8637c478bd9Sstevel@tonic-gate 	cfg->opt_picno = picnum;
8647c478bd9Sstevel@tonic-gate 	cfg->opt_evsel = evsel;
8657c478bd9Sstevel@tonic-gate 	cfg->opt_rawpic = preset & MASK48;
8667c478bd9Sstevel@tonic-gate 
8677c478bd9Sstevel@tonic-gate 	*data = cfg;
8687c478bd9Sstevel@tonic-gate 	return (0);
8697c478bd9Sstevel@tonic-gate }
8707c478bd9Sstevel@tonic-gate 
8717c478bd9Sstevel@tonic-gate static void
opt_pcbe_program(void * token)8727c478bd9Sstevel@tonic-gate opt_pcbe_program(void *token)
8737c478bd9Sstevel@tonic-gate {
874d0e58ef5SRobert Mustacchi 	opt_pcbe_config_t	*cfgs[OPT_PCBE_EXT_NCOUNTERS] = { &nullcfgs[0],
875d0e58ef5SRobert Mustacchi 						&nullcfgs[1], &nullcfgs[2],
876d0e58ef5SRobert Mustacchi 						&nullcfgs[3], &nullcfgs[4],
877d0e58ef5SRobert Mustacchi 						&nullcfgs[5] };
8787c478bd9Sstevel@tonic-gate 	opt_pcbe_config_t	*pcfg = NULL;
8797c478bd9Sstevel@tonic-gate 	int			i;
880843e1988Sjohnlev 	ulong_t			curcr4 = getcr4();
8817c478bd9Sstevel@tonic-gate 
8827c478bd9Sstevel@tonic-gate 	/*
8837c478bd9Sstevel@tonic-gate 	 * Allow nonprivileged code to read the performance counters if desired.
8847c478bd9Sstevel@tonic-gate 	 */
8857c478bd9Sstevel@tonic-gate 	if (kcpc_allow_nonpriv(token))
8867c478bd9Sstevel@tonic-gate 		setcr4(curcr4 | CR4_PCE);
8877c478bd9Sstevel@tonic-gate 	else
8887c478bd9Sstevel@tonic-gate 		setcr4(curcr4 & ~CR4_PCE);
8897c478bd9Sstevel@tonic-gate 
8907c478bd9Sstevel@tonic-gate 	/*
8917c478bd9Sstevel@tonic-gate 	 * Query kernel for all configs which will be co-programmed.
8927c478bd9Sstevel@tonic-gate 	 */
8937c478bd9Sstevel@tonic-gate 	do {
8947c478bd9Sstevel@tonic-gate 		pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, NULL);
8957c478bd9Sstevel@tonic-gate 
8967c478bd9Sstevel@tonic-gate 		if (pcfg != NULL) {
897d0e58ef5SRobert Mustacchi 			ASSERT(pcfg->opt_picno < opd.opd_ncounters);
8987c478bd9Sstevel@tonic-gate 			cfgs[pcfg->opt_picno] = pcfg;
8997c478bd9Sstevel@tonic-gate 		}
9007c478bd9Sstevel@tonic-gate 	} while (pcfg != NULL);
9017c478bd9Sstevel@tonic-gate 
9027c478bd9Sstevel@tonic-gate 	/*
9037c478bd9Sstevel@tonic-gate 	 * Program in two loops. The first configures and presets the counter,
9047c478bd9Sstevel@tonic-gate 	 * and the second loop enables the counters. This ensures that the
9057c478bd9Sstevel@tonic-gate 	 * counters are all enabled as closely together in time as possible.
9067c478bd9Sstevel@tonic-gate 	 */
9077c478bd9Sstevel@tonic-gate 
908d0e58ef5SRobert Mustacchi 	for (i = 0; i < opd.opd_ncounters; i++) {
909d0e58ef5SRobert Mustacchi 		wrmsr(opd.opd_pesf(i), cfgs[i]->opt_evsel);
910d0e58ef5SRobert Mustacchi 		wrmsr(opd.opd_picf(i), cfgs[i]->opt_rawpic);
9117c478bd9Sstevel@tonic-gate 	}
9127c478bd9Sstevel@tonic-gate 
913d0e58ef5SRobert Mustacchi 	for (i = 0; i < opd.opd_ncounters; i++) {
914d0e58ef5SRobert Mustacchi 		wrmsr(opd.opd_pesf(i), cfgs[i]->opt_evsel |
9150ac7d7d8Skucharsk 		    (uint64_t)(uintptr_t)OPT_PES_ENABLE);
9167c478bd9Sstevel@tonic-gate 	}
9177c478bd9Sstevel@tonic-gate }
9187c478bd9Sstevel@tonic-gate 
9197c478bd9Sstevel@tonic-gate static void
opt_pcbe_allstop(void)9207c478bd9Sstevel@tonic-gate opt_pcbe_allstop(void)
9217c478bd9Sstevel@tonic-gate {
9227c478bd9Sstevel@tonic-gate 	int		i;
9237c478bd9Sstevel@tonic-gate 
924d0e58ef5SRobert Mustacchi 	for (i = 0; i < opd.opd_ncounters; i++)
925d0e58ef5SRobert Mustacchi 		wrmsr(opd.opd_pesf(i), 0ULL);
9267c478bd9Sstevel@tonic-gate 
9277c478bd9Sstevel@tonic-gate 	/*
9287c478bd9Sstevel@tonic-gate 	 * Disable non-privileged access to the counter registers.
9297c478bd9Sstevel@tonic-gate 	 */
930843e1988Sjohnlev 	setcr4(getcr4() & ~CR4_PCE);
9317c478bd9Sstevel@tonic-gate }
9327c478bd9Sstevel@tonic-gate 
9337c478bd9