1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 /*
27  * This file contains preset event names from the Performance Application
28  * Programming Interface v3.5 which included the following notice:
29  *
30  *                             Copyright (c) 2005,6
31  *                           Innovative Computing Labs
32  *                         Computer Science Department,
33  *                            University of Tennessee,
34  *                                 Knoxville, TN.
35  *                              All Rights Reserved.
36  *
37  *
38  * Redistribution and use in source and binary forms, with or without
39  * modification, are permitted provided that the following conditions are met:
40  *
41  *    * Redistributions of source code must retain the above copyright notice,
42  *      this list of conditions and the following disclaimer.
43  *    * Redistributions in binary form must reproduce the above copyright
44  *	notice, this list of conditions and the following disclaimer in the
45  *	documentation and/or other materials provided with the distribution.
46  *    * Neither the name of the University of Tennessee nor the names of its
47  *      contributors may be used to endorse or promote products derived from
48  *	this software without specific prior written permission.
49  *
50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
51  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
54  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
60  * POSSIBILITY OF SUCH DAMAGE.
61  *
62  *
63  * This open source software license conforms to the BSD License template.
64  */
65 
66 /*
67  * Portions Copyright 2009 Advanced Micro Devices, Inc.
68  * Copyright 2019 Joyent, Inc.
69  * Copyright 2021 Oxide Computer Company
70  */
71 
72 /*
73  * Performance Counter Back-End for AMD Opteron and AMD Athlon 64 processors.
74  */
75 
76 #include <sys/cpuvar.h>
77 #include <sys/param.h>
78 #include <sys/systm.h>
79 #include <sys/cpc_pcbe.h>
80 #include <sys/kmem.h>
81 #include <sys/sdt.h>
82 #include <sys/modctl.h>
83 #include <sys/errno.h>
84 #include <sys/debug.h>
85 #include <sys/archsystm.h>
86 #include <sys/x86_archext.h>
87 #include <sys/privregs.h>
88 #include <sys/ddi.h>
89 #include <sys/sunddi.h>
90 
91 #include "opteron_pcbe_table.h"
92 #include <opteron_pcbe_cpcgen.h>
93 
94 static int opt_pcbe_init(void);
95 static uint_t opt_pcbe_ncounters(void);
96 static const char *opt_pcbe_impl_name(void);
97 static const char *opt_pcbe_cpuref(void);
98 static char *opt_pcbe_list_events(uint_t picnum);
99 static char *opt_pcbe_list_attrs(void);
100 static uint64_t opt_pcbe_event_coverage(char *event);
101 static uint64_t opt_pcbe_overflow_bitmap(void);
102 static int opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset,
103     uint32_t flags, uint_t nattrs, kcpc_attr_t *attrs, void **data,
104     void *token);
105 static void opt_pcbe_program(void *token);
106 static void opt_pcbe_allstop(void);
107 static void opt_pcbe_sample(void *token);
108 static void opt_pcbe_free(void *config);
109 
110 static pcbe_ops_t opt_pcbe_ops = {
111 	PCBE_VER_1,
112 	CPC_CAP_OVERFLOW_INTERRUPT,
113 	opt_pcbe_ncounters,
114 	opt_pcbe_impl_name,
115 	opt_pcbe_cpuref,
116 	opt_pcbe_list_events,
117 	opt_pcbe_list_attrs,
118 	opt_pcbe_event_coverage,
119 	opt_pcbe_overflow_bitmap,
120 	opt_pcbe_configure,
121 	opt_pcbe_program,
122 	opt_pcbe_allstop,
123 	opt_pcbe_sample,
124 	opt_pcbe_free
125 };
126 
127 /*
128  * Base MSR addresses for the PerfEvtSel registers and the counters themselves.
129  * Add counter number to base address to get corresponding MSR address.
130  */
131 #define	PES_BASE_ADDR	0xC0010000
132 #define	PIC_BASE_ADDR	0xC0010004
133 
134 /*
135  * Base MSR addresses for the PerfEvtSel registers and counters. The counter and
136  * event select registers are interleaved, so one needs to multiply the counter
137  * number by two to determine what they should be set to.
138  */
139 #define	PES_EXT_BASE_ADDR	0xC0010200
140 #define	PIC_EXT_BASE_ADDR	0xC0010201
141 
142 /*
143  * The number of counters present depends on which CPU features are present.
144  */
145 #define	OPT_PCBE_DEF_NCOUNTERS	4
146 #define	OPT_PCBE_EXT_NCOUNTERS	6
147 
148 /*
149  * Define offsets and masks for the fields in the Performance
150  * Event-Select (PES) registers.
151  */
152 #define	OPT_PES_HOST_SHIFT	41
153 #define	OPT_PES_GUEST_SHIFT	40
154 #define	OPT_PES_EVSELHI_SHIFT	32
155 #define	OPT_PES_CMASK_SHIFT	24
156 #define	OPT_PES_CMASK_MASK	0xFF
157 #define	OPT_PES_INV_SHIFT	23
158 #define	OPT_PES_ENABLE_SHIFT	22
159 #define	OPT_PES_INT_SHIFT	20
160 #define	OPT_PES_PC_SHIFT	19
161 #define	OPT_PES_EDGE_SHIFT	18
162 #define	OPT_PES_OS_SHIFT	17
163 #define	OPT_PES_USR_SHIFT	16
164 #define	OPT_PES_UMASK_SHIFT	8
165 #define	OPT_PES_UMASK_MASK	0xFF
166 
167 #define	OPT_PES_INV		(1ULL << OPT_PES_INV_SHIFT)
168 #define	OPT_PES_ENABLE		(1ULL << OPT_PES_ENABLE_SHIFT)
169 #define	OPT_PES_INT		(1ULL << OPT_PES_INT_SHIFT)
170 #define	OPT_PES_PC		(1ULL << OPT_PES_PC_SHIFT)
171 #define	OPT_PES_EDGE		(1ULL << OPT_PES_EDGE_SHIFT)
172 #define	OPT_PES_OS		(1ULL << OPT_PES_OS_SHIFT)
173 #define	OPT_PES_USR		(1ULL << OPT_PES_USR_SHIFT)
174 #define	OPT_PES_HOST		(1ULL << OPT_PES_HOST_SHIFT)
175 #define	OPT_PES_GUEST		(1ULL << OPT_PES_GUEST_SHIFT)
176 
177 typedef struct _opt_pcbe_config {
178 	uint8_t		opt_picno;	/* Counter number: 0, 1, 2, or 3 */
179 	uint64_t	opt_evsel;	/* Event Selection register */
180 	uint64_t	opt_rawpic;	/* Raw counter value */
181 } opt_pcbe_config_t;
182 
183 opt_pcbe_config_t nullcfgs[OPT_PCBE_EXT_NCOUNTERS] = {
184 	{ 0, 0, 0 },
185 	{ 1, 0, 0 },
186 	{ 2, 0, 0 },
187 	{ 3, 0, 0 },
188 	{ 4, 0, 0 },
189 	{ 5, 0, 0 },
190 };
191 
192 typedef uint64_t (*opt_pcbe_addr_f)(uint_t);
193 
194 typedef struct opt_pcbe_data {
195 	uint_t		opd_ncounters;
196 	uint_t		opd_cmask;
197 	opt_pcbe_addr_f	opd_pesf;
198 	opt_pcbe_addr_f	opd_picf;
199 } opt_pcbe_data_t;
200 
201 opt_pcbe_data_t opd;
202 
203 #define	MASK48		0xFFFFFFFFFFFF
204 
205 #define	EV_END {NULL, 0}
206 #define	GEN_EV_END {NULL, NULL, 0 }
207 
208 /*
209  * The following Macros are used to define tables of events that are used by
210  * various families and some generic classes of events.
211  *
212  * When programming a performance counter there are two different values that we
213  * need to set:
214  *
215  *   o Event - Determines the general class of event that is being used.
216  *   o Unit  - A further breakdown that gives more specific value.
217  *
218  * Prior to the introduction of family 17h support, all family specific events
219  * were programmed based on their event. The generic events, which tried to
220  * provide PAPI mappings to events specified an additional unit mask.
221  *
222  * Starting with Family 17h, CPU performance counters default to using both the
223  * unit mask and the event select. Generic events are always aliases to a
224  * specific event/unit pair, hence why the units for them are always zero. In
225  * addition, the naming of events in family 17h has been changed to reflect
226  * AMD's guide. While this is a departure from what people are used to, it is
227  * believed that matching the more detailed literature that folks are told to
228  * reference is more valuable.
229  */
230 
231 #define	AMD_cmn_events						\
232 	{ "FP_dispatched_fpu_ops",			0x0 },	\
233 	{ "FP_cycles_no_fpu_ops_retired",		0x1 },	\
234 	{ "FP_dispatched_fpu_ops_ff",			0x2 },	\
235 	{ "LS_seg_reg_load",				0x20 },	\
236 	{ "LS_uarch_resync_self_modify",		0x21 },	\
237 	{ "LS_uarch_resync_snoop",			0x22 },	\
238 	{ "LS_buffer_2_full",				0x23 },	\
239 	{ "LS_locked_operation",			0x24 },	\
240 	{ "LS_retired_cflush",				0x26 },	\
241 	{ "LS_retired_cpuid",				0x27 },	\
242 	{ "DC_access",					0x40 },	\
243 	{ "DC_miss",					0x41 },	\
244 	{ "DC_refill_from_L2",				0x42 },	\
245 	{ "DC_refill_from_system",			0x43 },	\
246 	{ "DC_copyback",				0x44 },	\
247 	{ "DC_dtlb_L1_miss_L2_hit",			0x45 },	\
248 	{ "DC_dtlb_L1_miss_L2_miss",			0x46 },	\
249 	{ "DC_misaligned_data_ref",			0x47 },	\
250 	{ "DC_uarch_late_cancel_access",		0x48 },	\
251 	{ "DC_uarch_early_cancel_access",		0x49 },	\
252 	{ "DC_1bit_ecc_error_found",			0x4A },	\
253 	{ "DC_dispatched_prefetch_instr",		0x4B },	\
254 	{ "DC_dcache_accesses_by_locks",		0x4C },	\
255 	{ "BU_memory_requests",				0x65 },	\
256 	{ "BU_data_prefetch",				0x67 },	\
257 	{ "BU_system_read_responses",			0x6C },	\
258 	{ "BU_cpu_clk_unhalted",			0x76 },	\
259 	{ "BU_internal_L2_req",				0x7D },	\
260 	{ "BU_fill_req_missed_L2",			0x7E },	\
261 	{ "BU_fill_into_L2",				0x7F },	\
262 	{ "IC_fetch",					0x80 },	\
263 	{ "IC_miss",					0x81 },	\
264 	{ "IC_refill_from_L2",				0x82 },	\
265 	{ "IC_refill_from_system",			0x83 },	\
266 	{ "IC_itlb_L1_miss_L2_hit",			0x84 },	\
267 	{ "IC_itlb_L1_miss_L2_miss",			0x85 },	\
268 	{ "IC_uarch_resync_snoop",			0x86 },	\
269 	{ "IC_instr_fetch_stall",			0x87 },	\
270 	{ "IC_return_stack_hit",			0x88 },	\
271 	{ "IC_return_stack_overflow",			0x89 },	\
272 	{ "FR_retired_x86_instr_w_excp_intr",		0xC0 },	\
273 	{ "FR_retired_uops",				0xC1 },	\
274 	{ "FR_retired_branches_w_excp_intr",		0xC2 },	\
275 	{ "FR_retired_branches_mispred",		0xC3 },	\
276 	{ "FR_retired_taken_branches",			0xC4 },	\
277 	{ "FR_retired_taken_branches_mispred",		0xC5 },	\
278 	{ "FR_retired_far_ctl_transfer",		0xC6 },	\
279 	{ "FR_retired_resyncs",				0xC7 },	\
280 	{ "FR_retired_near_rets",			0xC8 },	\
281 	{ "FR_retired_near_rets_mispred",		0xC9 },	\
282 	{ "FR_retired_taken_branches_mispred_addr_miscomp",	0xCA },\
283 	{ "FR_retired_fastpath_double_op_instr",	0xCC },	\
284 	{ "FR_intr_masked_cycles",			0xCD },	\
285 	{ "FR_intr_masked_while_pending_cycles",	0xCE },	\
286 	{ "FR_taken_hardware_intrs",			0xCF },	\
287 	{ "FR_nothing_to_dispatch",			0xD0 },	\
288 	{ "FR_dispatch_stalls",				0xD1 },	\
289 	{ "FR_dispatch_stall_branch_abort_to_retire",	0xD2 },	\
290 	{ "FR_dispatch_stall_serialization",		0xD3 },	\
291 	{ "FR_dispatch_stall_segment_load",		0xD4 },	\
292 	{ "FR_dispatch_stall_reorder_buffer_full",	0xD5 },	\
293 	{ "FR_dispatch_stall_resv_stations_full",	0xD6 },	\
294 	{ "FR_dispatch_stall_fpu_full",			0xD7 },	\
295 	{ "FR_dispatch_stall_ls_full",			0xD8 },	\
296 	{ "FR_dispatch_stall_waiting_all_quiet",	0xD9 },	\
297 	{ "FR_dispatch_stall_far_ctl_trsfr_resync_branch_pend",	0xDA },\
298 	{ "FR_fpu_exception",				0xDB },	\
299 	{ "FR_num_brkpts_dr0",				0xDC },	\
300 	{ "FR_num_brkpts_dr1",				0xDD },	\
301 	{ "FR_num_brkpts_dr2",				0xDE },	\
302 	{ "FR_num_brkpts_dr3",				0xDF },	\
303 	{ "NB_mem_ctrlr_page_access",			0xE0 },	\
304 	{ "NB_mem_ctrlr_turnaround",			0xE3 },	\
305 	{ "NB_mem_ctrlr_bypass_counter_saturation",	0xE4 },	\
306 	{ "NB_cpu_io_to_mem_io",			0xE9 },	\
307 	{ "NB_cache_block_commands",			0xEA },	\
308 	{ "NB_sized_commands",				0xEB },	\
309 	{ "NB_ht_bus0_bandwidth",			0xF6 }
310 
311 #define	AMD_FAMILY_f_events					\
312 	{ "BU_quadwords_written_to_system",		0x6D },	\
313 	{ "FR_retired_fpu_instr",			0xCB },	\
314 	{ "NB_mem_ctrlr_page_table_overflow",		0xE1 },	\
315 	{ "NB_sized_blocks",				0xE5 },	\
316 	{ "NB_ECC_errors",				0xE8 },	\
317 	{ "NB_probe_result",				0xEC },	\
318 	{ "NB_gart_events",				0xEE },	\
319 	{ "NB_ht_bus1_bandwidth",			0xF7 },	\
320 	{ "NB_ht_bus2_bandwidth",			0xF8 }
321 
322 #define	AMD_FAMILY_10h_events					\
323 	{ "FP_retired_sse_ops",				0x3 },	\
324 	{ "FP_retired_move_ops",			0x4 },	\
325 	{ "FP_retired_serialize_ops",			0x5 },	\
326 	{ "FP_serialize_ops_cycles",			0x6 },	\
327 	{ "LS_cancelled_store_to_load_fwd_ops",		0x2A },	\
328 	{ "LS_smi_received",				0x2B },	\
329 	{ "DC_dtlb_L1_hit",				0x4D },	\
330 	{ "LS_ineffective_prefetch",			0x52 },	\
331 	{ "LS_global_tlb_flush",			0x54 },	\
332 	{ "BU_octwords_written_to_system",		0x6D },	\
333 	{ "Page_size_mismatches",			0x165 },	\
334 	{ "IC_eviction",				0x8B },	\
335 	{ "IC_cache_lines_invalidate",			0x8C },	\
336 	{ "IC_itlb_reload",				0x99 },	\
337 	{ "IC_itlb_reload_aborted",			0x9A },	\
338 	{ "FR_retired_mmx_sse_fp_instr",		0xCB },	\
339 	{ "Retired_x87_fp_ops",				0x1C0 },	\
340 	{ "IBS_ops_tagged",				0x1CF },	\
341 	{ "LFENCE_inst_retired",			0x1D3 },	\
342 	{ "SFENCE_inst_retired",			0x1D4 },	\
343 	{ "MFENCE_inst_retired",			0x1D5 },	\
344 	{ "NB_mem_ctrlr_page_table_overflow",		0xE1 },	\
345 	{ "NB_mem_ctrlr_dram_cmd_slots_missed",		0xE2 },	\
346 	{ "NB_thermal_status",				0xE8 },	\
347 	{ "NB_probe_results_upstream_req",		0xEC },	\
348 	{ "NB_gart_events",				0xEE },	\
349 	{ "NB_mem_ctrlr_req",				0x1F0 },	\
350 	{ "CB_cpu_to_dram_req_to_target",		0x1E0 },	\
351 	{ "CB_io_to_dram_req_to_target",		0x1E1 },	\
352 	{ "CB_cpu_read_cmd_latency_to_target_0_to_3",	0x1E2 },	\
353 	{ "CB_cpu_read_cmd_req_to_target_0_to_3",	0x1E3 },	\
354 	{ "CB_cpu_read_cmd_latency_to_target_4_to_7",	0x1E4 },	\
355 	{ "CB_cpu_read_cmd_req_to_target_4_to_7",	0x1E5 },	\
356 	{ "CB_cpu_cmd_latency_to_target_0_to_7",	0x1E6 },	\
357 	{ "CB_cpu_req_to_target_0_to_7",		0x1E7 },	\
358 	{ "NB_ht_bus1_bandwidth",			0xF7 },	\
359 	{ "NB_ht_bus2_bandwidth",			0xF8 },	\
360 	{ "NB_ht_bus3_bandwidth",			0x1F9 },	\
361 	{ "L3_read_req",				0x4E0 },	\
362 	{ "L3_miss",					0x4E1 },	\
363 	{ "L3_l2_eviction_l3_fill",			0x4E2 },	\
364 	{ "L3_eviction",				0x4E3 }
365 
366 #define	AMD_FAMILY_11h_events					\
367 	{ "BU_quadwords_written_to_system",		0x6D },	\
368 	{ "FR_retired_mmx_fp_instr",			0xCB },	\
369 	{ "NB_mem_ctrlr_page_table_events",		0xE1 },	\
370 	{ "NB_thermal_status",				0xE8 },	\
371 	{ "NB_probe_results_upstream_req",		0xEC },	\
372 	{ "NB_dev_events",				0xEE },	\
373 	{ "NB_mem_ctrlr_req",				0x1F0 }
374 
375 #define	AMD_cmn_generic_events						\
376 	{ "PAPI_br_ins",	"FR_retired_branches_w_excp_intr", 0x0 },\
377 	{ "PAPI_br_msp",	"FR_retired_branches_mispred",	0x0 },	\
378 	{ "PAPI_br_tkn",	"FR_retired_taken_branches",	0x0 },	\
379 	{ "PAPI_fp_ops",	"FP_dispatched_fpu_ops",	0x3 },	\
380 	{ "PAPI_fad_ins",	"FP_dispatched_fpu_ops",	0x1 },	\
381 	{ "PAPI_fml_ins",	"FP_dispatched_fpu_ops",	0x2 },	\
382 	{ "PAPI_fpu_idl",	"FP_cycles_no_fpu_ops_retired",	0x0 },	\
383 	{ "PAPI_tot_cyc",	"BU_cpu_clk_unhalted",		0x0 },	\
384 	{ "PAPI_tot_ins",	"FR_retired_x86_instr_w_excp_intr", 0x0 }, \
385 	{ "PAPI_l1_dca",	"DC_access",			0x0 },	\
386 	{ "PAPI_l1_dcm",	"DC_miss",			0x0 },	\
387 	{ "PAPI_l1_ldm",	"DC_refill_from_L2",		0xe },	\
388 	{ "PAPI_l1_stm",	"DC_refill_from_L2",		0x10 },	\
389 	{ "PAPI_l1_ica",	"IC_fetch",			0x0 },	\
390 	{ "PAPI_l1_icm",	"IC_miss",			0x0 },	\
391 	{ "PAPI_l1_icr",	"IC_fetch",			0x0 },	\
392 	{ "PAPI_l2_dch",	"DC_refill_from_L2",		0x1e },	\
393 	{ "PAPI_l2_dcm",	"DC_refill_from_system",	0x1e },	\
394 	{ "PAPI_l2_dcr",	"DC_refill_from_L2",		0xe },	\
395 	{ "PAPI_l2_dcw",	"DC_refill_from_L2",		0x10 },	\
396 	{ "PAPI_l2_ich",	"IC_refill_from_L2",		0x0 },	\
397 	{ "PAPI_l2_icm",	"IC_refill_from_system",	0x0 },	\
398 	{ "PAPI_l2_ldm",	"DC_refill_from_system",	0xe },	\
399 	{ "PAPI_l2_stm",	"DC_refill_from_system",	0x10 },	\
400 	{ "PAPI_res_stl",	"FR_dispatch_stalls",		0x0 },	\
401 	{ "PAPI_stl_icy",	"FR_nothing_to_dispatch",	0x0 },	\
402 	{ "PAPI_hw_int",	"FR_taken_hardware_intrs",	0x0 }
403 
404 #define	OPT_cmn_generic_events						\
405 	{ "PAPI_tlb_dm",	"DC_dtlb_L1_miss_L2_miss",	0x0 },	\
406 	{ "PAPI_tlb_im",	"IC_itlb_L1_miss_L2_miss",	0x0 },	\
407 	{ "PAPI_fp_ins",	"FR_retired_fpu_instr",		0xd },	\
408 	{ "PAPI_vec_ins",	"FR_retired_fpu_instr",		0x4 }
409 
410 #define	AMD_FAMILY_10h_generic_events					\
411 	{ "PAPI_tlb_dm",	"DC_dtlb_L1_miss_L2_miss",	0x7 },	\
412 	{ "PAPI_tlb_im",	"IC_itlb_L1_miss_L2_miss",	0x3 },	\
413 	{ "PAPI_l3_dcr",	"L3_read_req",			0xf1 }, \
414 	{ "PAPI_l3_icr",	"L3_read_req",			0xf2 }, \
415 	{ "PAPI_l3_tcr",	"L3_read_req",			0xf7 }, \
416 	{ "PAPI_l3_stm",	"L3_miss",			0xf4 }, \
417 	{ "PAPI_l3_ldm",	"L3_miss",			0xf3 }, \
418 	{ "PAPI_l3_tcm",	"L3_miss",			0xf7 }
419 
420 static const amd_event_t family_f_events[] = {
421 	AMD_cmn_events,
422 	AMD_FAMILY_f_events,
423 	EV_END
424 };
425 
426 static const amd_event_t family_10h_events[] = {
427 	AMD_cmn_events,
428 	AMD_FAMILY_10h_events,
429 	EV_END
430 };
431 
432 static const amd_event_t family_11h_events[] = {
433 	AMD_cmn_events,
434 	AMD_FAMILY_11h_events,
435 	EV_END
436 };
437 
438 static const amd_generic_event_t opt_generic_events[] = {
439 	AMD_cmn_generic_events,
440 	OPT_cmn_generic_events,
441 	GEN_EV_END
442 };
443 
444 static const amd_generic_event_t family_10h_generic_events[] = {
445 	AMD_cmn_generic_events,
446 	AMD_FAMILY_10h_generic_events,
447 	GEN_EV_END
448 };
449 
450 /*
451  * For Family 17h and Family 19h, the cpcgen utility generates all of our events
452  * including ones that need specific unit codes, therefore we leave all unit
453  * codes out of these. Zen 1, Zen 2, and Zen 3 have different event sets that
454  * they support.
455  */
456 static const amd_generic_event_t family_17h_zen1_papi_events[] = {
457 	{ "PAPI_br_cn",		"ExRetCond" },
458 	{ "PAPI_br_ins",	"ExRetBrn" },
459 	{ "PAPI_fpu_idl",	"FpSchedEmpty" },
460 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
461 	{ "PAPI_tot_ins",	"ExRetInstr" },
462 	{ "PAPI_tlb_dm",	"LsL1DTlbMiss" },
463 	{ "PAPI_tlb_im",	"BpL1TlbMissL2Miss" },
464 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
465 	GEN_EV_END
466 };
467 
468 static const amd_generic_event_t family_17h_zen2_papi_events[] = {
469 	{ "PAPI_br_cn",		"ExRetCond" },
470 	{ "PAPI_br_ins",	"ExRetBrn" },
471 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
472 	{ "PAPI_tot_ins",	"ExRetInstr" },
473 	{ "PAPI_tlb_dm",	"LsL1DTlbMiss" },
474 	{ "PAPI_tlb_im",	"BpL1TlbMissL2Miss" },
475 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
476 	GEN_EV_END
477 };
478 
479 static const amd_generic_event_t family_19h_zen3_papi_events[] = {
480 	{ "PAPI_br_cn",		"ExRetCond" },
481 	{ "PAPI_br_ins",	"ExRetBrn" },
482 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
483 	{ "PAPI_tot_ins",	"ExRetInstr" },
484 	{ "PAPI_tlb_dm",	"LsL1DTlbMiss" },
485 	{ "PAPI_tlb_im",	"BpL1TlbMissL2TlbMiss" },
486 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
487 	GEN_EV_END
488 };
489 
490 
491 
492 static char	*evlist;
493 static size_t	evlist_sz;
494 static const amd_event_t *amd_events = NULL;
495 static uint_t amd_family, amd_model;
496 static const amd_generic_event_t *amd_generic_events = NULL;
497 
498 static char amd_fam_f_rev_ae_bkdg[] = "See \"BIOS and Kernel Developer's "
499 "Guide for AMD Athlon 64 and AMD Opteron Processors\" (AMD publication 26094)";
500 static char amd_fam_f_NPT_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
501 "for AMD NPT Family 0Fh Processors\" (AMD publication 32559)";
502 static char amd_fam_10h_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
503 "(BKDG) For AMD Family 10h Processors\" (AMD publication 31116)";
504 static char amd_fam_11h_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
505 "(BKDG) For AMD Family 11h Processors\" (AMD publication 41256)";
506 static char amd_fam_17h_zen1_reg[] = "See \"Open-Source Register Reference For "
507 "AMD Family 17h Processors Models 00h-2Fh\" (AMD publication 56255) and "
508 "amd_f17h_zen1_events(3CPC)";
509 static char amd_fam_17h_zen2_reg[] = "See \"Preliminary Processor Programming "
510 "Reference (PPR) for AMD Family 17h Model 31h, Revision B0 Processors\" "
511 "(AMD publication 55803), \"Processor Programming Reference (PPR) for AMD "
512 "Family 17h Model 71h, Revision B0 Processors\" (AMD publication 56176), and "
513 "amd_f17h_zen2_events(3CPC)";
514 static char amd_fam_19h_zen3_reg[] = "See \"Preliminary Processor Programming "
515 "Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors Volume "
516 "1 of 2\" (AMD publication 55898), \"Processor Programming Reference (PPR) "
517 "for AMD Family 19h Model 21h, Revision B0 Processors\" (AMD publication "
518 "56214), and amd_f17h_zen3_events(3CPC)";
519 
520 static char amd_pcbe_impl_name[64];
521 static char *amd_pcbe_cpuref;
522 
523 
524 #define	BITS(v, u, l)   \
525 	(((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1))
526 
527 static uint64_t
opt_pcbe_pes_addr(uint_t counter)528 opt_pcbe_pes_addr(uint_t counter)
529 {
530 	ASSERT3U(counter, <, opd.opd_ncounters);
531 	return (PES_BASE_ADDR + counter);
532 }
533 
534 static uint64_t
opt_pcbe_pes_ext_addr(uint_t counter)535 opt_pcbe_pes_ext_addr(uint_t counter)
536 {
537 	ASSERT3U(counter, <, opd.opd_ncounters);
538 	return (PES_EXT_BASE_ADDR + 2 * counter);
539 }
540 
541 static uint64_t
opt_pcbe_pic_addr(uint_t counter)542 opt_pcbe_pic_addr(uint_t counter)
543 {
544 	ASSERT3U(counter, <, opd.opd_ncounters);
545 	return (PIC_BASE_ADDR + 2 * counter);
546 }
547 
548 static uint64_t
opt_pcbe_pic_ext_addr(uint_t counter)549 opt_pcbe_pic_ext_addr(uint_t counter)
550 {
551 	ASSERT3U(counter, <, opd.opd_ncounters);
552 	return (PIC_EXT_BASE_ADDR + 2 * counter);
553 }
554 
555 static int
opt_pcbe_init(void)556 opt_pcbe_init(void)
557 {
558 	const amd_event_t		*evp;
559 	const amd_generic_event_t	*gevp;
560 
561 	amd_family = cpuid_getfamily(CPU);
562 	amd_model = cpuid_getmodel(CPU);
563 
564 	/*
565 	 * Make sure this really _is_ an Opteron or Athlon 64 system. The kernel
566 	 * loads this module based on its name in the module directory, but it
567 	 * could have been renamed.
568 	 */
569 	if ((cpuid_getvendor(CPU) != X86_VENDOR_AMD || amd_family < 0xf) &&
570 	    cpuid_getvendor(CPU) != X86_VENDOR_HYGON)
571 		return (-1);
572 
573 	if (amd_family == 0xf) {
574 		/* Some tools expect this string for family 0fh */
575 		(void) snprintf(amd_pcbe_impl_name, sizeof (amd_pcbe_impl_name),
576 		    "AMD Opteron & Athlon64");
577 	} else {
578 		(void) snprintf(amd_pcbe_impl_name, sizeof (amd_pcbe_impl_name),
579 		    "%s Family %02xh",
580 		    cpuid_getvendor(CPU) == X86_VENDOR_HYGON ? "Hygon" : "AMD",
581 		    amd_family);
582 	}
583 
584 	/*
585 	 * Determine whether or not the extended counter set is supported on
586 	 * this processor.
587 	 */
588 	if (is_x86_feature(x86_featureset, X86FSET_AMD_PCEC)) {
589 		opd.opd_ncounters = OPT_PCBE_EXT_NCOUNTERS;
590 		opd.opd_pesf = opt_pcbe_pes_ext_addr;
591 		opd.opd_picf = opt_pcbe_pic_ext_addr;
592 	} else {
593 		opd.opd_ncounters = OPT_PCBE_DEF_NCOUNTERS;
594 		opd.opd_pesf = opt_pcbe_pes_addr;
595 		opd.opd_picf = opt_pcbe_pic_addr;
596 	}
597 	opd.opd_cmask = (1 << opd.opd_ncounters) - 1;
598 
599 	/*
600 	 * Figure out processor revision here and assign appropriate
601 	 * event configuration.
602 	 */
603 
604 	if (amd_family == 0xf) {
605 		uint32_t rev;
606 
607 		rev = cpuid_getchiprev(CPU);
608 
609 		if (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_F))
610 			amd_pcbe_cpuref = amd_fam_f_NPT_bkdg;
611 		else
612 			amd_pcbe_cpuref = amd_fam_f_rev_ae_bkdg;
613 		amd_events = family_f_events;
614 		amd_generic_events = opt_generic_events;
615 	} else if (amd_family == 0x10) {
616 		amd_pcbe_cpuref = amd_fam_10h_bkdg;
617 		amd_events = family_10h_events;
618 		amd_generic_events = family_10h_generic_events;
619 	} else if (amd_family == 0x11) {
620 		amd_pcbe_cpuref = amd_fam_11h_bkdg;
621 		amd_events = family_11h_events;
622 		amd_generic_events = opt_generic_events;
623 	} else if ((amd_family == 0x17 && amd_model <= 0x2f) ||
624 	    amd_family == 0x18) {
625 		amd_pcbe_cpuref = amd_fam_17h_zen1_reg;
626 		amd_events = opteron_pcbe_f17h_zen1_events;
627 		amd_generic_events = family_17h_zen1_papi_events;
628 	} else if (amd_family == 0x17 && amd_model >= 0x30 &&
629 	    amd_model <= 0x7f) {
630 		amd_pcbe_cpuref = amd_fam_17h_zen2_reg;
631 		amd_events = opteron_pcbe_f17h_zen2_events;
632 		amd_generic_events = family_17h_zen2_papi_events;
633 	} else if (amd_family == 0x19 && (amd_model <= 0xf ||
634 	    (amd_model >= 0x20 && amd_model <= 0x2f))) {
635 		amd_pcbe_cpuref = amd_fam_19h_zen3_reg;
636 		amd_events = opteron_pcbe_f19h_zen3_events;
637 		amd_generic_events = family_19h_zen3_papi_events;
638 	} else {
639 		/*
640 		 * Different families have different meanings on events and even
641 		 * worse (like family 15h), different constraints around
642 		 * programming these values.
643 		 */
644 		return (-1);
645 	}
646 
647 	/*
648 	 * Construct event list.
649 	 *
650 	 * First pass:  Calculate size needed. We'll need an additional byte
651 	 *		for the NULL pointer during the last strcat.
652 	 *
653 	 * Second pass: Copy strings.
654 	 */
655 	for (evp = amd_events; evp->name != NULL; evp++)
656 		evlist_sz += strlen(evp->name) + 1;
657 
658 	for (gevp = amd_generic_events; gevp->name != NULL; gevp++)
659 		evlist_sz += strlen(gevp->name) + 1;
660 
661 	evlist = kmem_alloc(evlist_sz + 1, KM_SLEEP);
662 	evlist[0] = '\0';
663 
664 	for (evp = amd_events; evp->name != NULL; evp++) {
665 		(void) strcat(evlist, evp->name);
666 		(void) strcat(evlist, ",");
667 	}
668 
669 	for (gevp = amd_generic_events; gevp->name != NULL; gevp++) {
670 		(void) strcat(evlist, gevp->name);
671 		(void) strcat(evlist, ",");
672 	}
673 
674 	/*
675 	 * Remove trailing comma.
676 	 */
677 	evlist[evlist_sz - 1] = '\0';
678 
679 	return (0);
680 }
681 
682 static uint_t
opt_pcbe_ncounters(void)683 opt_pcbe_ncounters(void)
684 {
685 	return (opd.opd_ncounters);
686 }
687 
688 static const char *
opt_pcbe_impl_name(void)689 opt_pcbe_impl_name(void)
690 {
691 	return (amd_pcbe_impl_name);
692 }
693 
694 static const char *
opt_pcbe_cpuref(void)695 opt_pcbe_cpuref(void)
696 {
697 
698 	return (amd_pcbe_cpuref);
699 }
700 
701 /*ARGSUSED*/
702 static char *
opt_pcbe_list_events(uint_t picnum)703 opt_pcbe_list_events(uint_t picnum)
704 {
705 	return (evlist);
706 }
707 
708 static char *
opt_pcbe_list_attrs(void)709 opt_pcbe_list_attrs(void)
710 {
711 	return ("edge,pc,inv,cmask,umask");
712 }
713 
714 static const amd_generic_event_t *
find_generic_event(char * name)715 find_generic_event(char *name)
716 {
717 	const amd_generic_event_t	*gevp;
718 
719 	for (gevp = amd_generic_events; gevp->name != NULL; gevp++)
720 		if (strcmp(name, gevp->name) == 0)
721 			return (gevp);
722 
723 	return (NULL);
724 }
725 
726 static const amd_event_t *
find_event(char * name)727 find_event(char *name)
728 {
729 	const amd_event_t	*evp;
730 
731 	for (evp = amd_events; evp->name != NULL; evp++)
732 		if (strcmp(name, evp->name) == 0)
733 			return (evp);
734 
735 	return (NULL);
736 }
737 
738 /*ARGSUSED*/
739 static uint64_t
opt_pcbe_event_coverage(char * event)740 opt_pcbe_event_coverage(char *event)
741 {
742 	/*
743 	 * Check whether counter event is supported
744 	 */
745 	if (find_event(event) == NULL && find_generic_event(event) == NULL)
746 		return (0);
747 
748 	/*
749 	 * Fortunately, all counters can count all events.
750 	 */
751 	return (opd.opd_cmask);
752 }
753 
754 static uint64_t
opt_pcbe_overflow_bitmap(void)755 opt_pcbe_overflow_bitmap(void)
756 {
757 	/*
758 	 * Unfortunately, this chip cannot detect which counter overflowed, so
759 	 * we must act as if they all did.
760 	 */
761 	return (opd.opd_cmask);
762 }
763 
764 /*ARGSUSED*/
765 static int
opt_pcbe_configure(uint_t picnum,char * event,uint64_t preset,uint32_t flags,uint_t nattrs,kcpc_attr_t * attrs,void ** data,void * token)766 opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, uint32_t flags,
767     uint_t nattrs, kcpc_attr_t *attrs, void **data, void *token)
768 {
769 	opt_pcbe_config_t		*cfg;
770 	const amd_event_t		*evp;
771 	amd_event_t			ev_raw = { "raw", 0};
772 	const amd_generic_event_t	*gevp;
773 	int				i;
774 	uint64_t			evsel = 0, evsel_tmp = 0;
775 
776 	/*
777 	 * If we've been handed an existing configuration, we need only preset
778 	 * the counter value.
779 	 */
780 	if (*data != NULL) {
781 		cfg = *data;
782 		cfg->opt_rawpic = preset & MASK48;
783 		return (0);
784 	}
785 
786 	if (picnum >= opd.opd_ncounters)
787 		return (CPC_INVALID_PICNUM);
788 
789 	if ((evp = find_event(event)) == NULL) {
790 		if ((gevp = find_generic_event(event)) != NULL) {
791 			evp = find_event(gevp->event);
792 			ASSERT(evp != NULL);
793 
794 			if (nattrs > 0)
795 				return (CPC_ATTRIBUTE_OUT_OF_RANGE);
796 
797 			evsel |= gevp->umask << OPT_PES_UMASK_SHIFT;
798 		} else {
799 			long tmp;
800 
801 			/*
802 			 * If ddi_strtol() likes this event, use it as a raw
803 			 * event code.
804 			 */
805 			if (ddi_strtol(event, NULL, 0, &tmp) != 0)
806 				return (CPC_INVALID_EVENT);
807 
808 			ev_raw.emask = tmp;
809 			evp = &ev_raw;
810 		}
811 	}
812 
813 	/*
814 	 * Configuration of EventSelect register. While on some families
815 	 * certain bits might not be supported (e.g. Guest/Host on family
816 	 * 11h), setting these bits is harmless
817 	 */
818 
819 	/* Set GuestOnly bit to 0 and HostOnly bit to 1 */
820 	evsel &= ~OPT_PES_HOST;
821 	evsel &= ~OPT_PES_GUEST;
822 
823 	/* Set bits [35:32] for extended part of Event Select field */
824 	evsel_tmp = evp->emask & 0x0f00;
825 	evsel |= evsel_tmp << OPT_PES_EVSELHI_SHIFT;
826 
827 	evsel |= evp->emask & 0x00ff;
828 	evsel |= evp->unit << OPT_PES_UMASK_SHIFT;
829 
830 	if (flags & CPC_COUNT_USER)
831 		evsel |= OPT_PES_USR;
832 	if (flags & CPC_COUNT_SYSTEM)
833 		evsel |= OPT_PES_OS;
834 	if (flags & CPC_OVF_NOTIFY_EMT)
835 		evsel |= OPT_PES_INT;
836 
837 	for (i = 0; i < nattrs; i++) {
838 		if (strcmp(attrs[i].ka_name, "edge") == 0) {
839 			if (attrs[i].ka_val != 0)
840 				evsel |= OPT_PES_EDGE;
841 		} else if (strcmp(attrs[i].ka_name, "pc") == 0) {
842 			if (attrs[i].ka_val != 0)
843 				evsel |= OPT_PES_PC;
844 		} else if (strcmp(attrs[i].ka_name, "inv") == 0) {
845 			if (attrs[i].ka_val != 0)
846 				evsel |= OPT_PES_INV;
847 		} else if (strcmp(attrs[i].ka_name, "cmask") == 0) {
848 			if ((attrs[i].ka_val | OPT_PES_CMASK_MASK) !=
849 			    OPT_PES_CMASK_MASK)
850 				return (CPC_ATTRIBUTE_OUT_OF_RANGE);
851 			evsel |= attrs[i].ka_val << OPT_PES_CMASK_SHIFT;
852 		} else if (strcmp(attrs[i].ka_name, "umask") == 0) {
853 			if ((attrs[i].ka_val | OPT_PES_UMASK_MASK) !=
854 			    OPT_PES_UMASK_MASK)
855 				return (CPC_ATTRIBUTE_OUT_OF_RANGE);
856 			evsel |= attrs[i].ka_val << OPT_PES_UMASK_SHIFT;
857 		} else
858 			return (CPC_INVALID_ATTRIBUTE);
859 	}
860 
861 	cfg = kmem_alloc(sizeof (*cfg), KM_SLEEP);
862 
863 	cfg->opt_picno = picnum;
864 	cfg->opt_evsel = evsel;
865 	cfg->opt_rawpic = preset & MASK48;
866 
867 	*data = cfg;
868 	return (0);
869 }
870 
871 static void
opt_pcbe_program(void * token)872 opt_pcbe_program(void *token)
873 {
874 	opt_pcbe_config_t	*cfgs[OPT_PCBE_EXT_NCOUNTERS] = { &nullcfgs[0],
875 						&nullcfgs[1], &nullcfgs[2],
876 						&nullcfgs[3], &nullcfgs[4],
877 						&nullcfgs[5] };
878 	opt_pcbe_config_t	*pcfg = NULL;
879 	int			i;
880 	ulong_t			curcr4 = getcr4();
881 
882 	/*
883 	 * Allow nonprivileged code to read the performance counters if desired.
884 	 */
885 	if (kcpc_allow_nonpriv(token))
886 		setcr4(curcr4 | CR4_PCE);
887 	else
888 		setcr4(curcr4 & ~CR4_PCE);
889 
890 	/*
891 	 * Query kernel for all configs which will be co-programmed.
892 	 */
893 	do {
894 		pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, NULL);
895 
896 		if (pcfg != NULL) {
897 			ASSERT(pcfg->opt_picno < opd.opd_ncounters);
898 			cfgs[pcfg->opt_picno] = pcfg;
899 		}
900 	} while (pcfg != NULL);
901 
902 	/*
903 	 * Program in two loops. The first configures and presets the counter,
904 	 * and the second loop enables the counters. This ensures that the
905 	 * counters are all enabled as closely together in time as possible.
906 	 */
907 
908 	for (i = 0; i < opd.opd_ncounters; i++) {
909 		wrmsr(opd.opd_pesf(i), cfgs[i]->opt_evsel);
910 		wrmsr(opd.opd_picf(i), cfgs[i]->opt_rawpic);
911 	}
912 
913 	for (i = 0; i < opd.opd_ncounters; i++) {
914 		wrmsr(opd.opd_pesf(i), cfgs[i]->opt_evsel |
915 		    (uint64_t)(uintptr_t)OPT_PES_ENABLE);
916 	}
917 }
918 
919 static void
opt_pcbe_allstop(void)920 opt_pcbe_allstop(void)
921 {
922 	int		i;
923 
924 	for (i = 0; i < opd.opd_ncounters; i++)
925 		wrmsr(opd.opd_pesf(i), 0ULL);
926 
927 	/*
928 	 * Disable non-privileged access to the counter registers.
929 	 */
930 	setcr4(getcr4() & ~CR4_PCE);
931 }
932 
933 static void
opt_pcbe_sample(void * token)934 opt_pcbe_sample(void *token)
935 {
936 	opt_pcbe_config_t	*cfgs[OPT_PCBE_EXT_NCOUNTERS] = { NULL, NULL,
937 						NULL, NULL, NULL, NULL };
938 	opt_pcbe_config_t	*pcfg = NULL;
939 	int			i;
940 	uint64_t		curpic[OPT_PCBE_EXT_NCOUNTERS];
941 	uint64_t		*addrs[OPT_PCBE_EXT_NCOUNTERS];
942 	uint64_t		*tmp;
943 	int64_t			diff;
944 
945 	for (i = 0; i < opd.opd_ncounters; i++)
946 		curpic[i] = rdmsr(opd.opd_picf(i));
947 
948 	/*
949 	 * Query kernel for all configs which are co-programmed.
950 	 */
951 	do {
952 		pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, &tmp);
953 
954 		if (pcfg != NULL) {
955 			ASSERT3U(pcfg->opt_picno, <, opd.opd_ncounters);
956 			cfgs[pcfg->opt_picno] = pcfg;
957 			addrs[pcfg->opt_picno] = tmp;
958 		}
959 	} while (pcfg != NULL);
960 
961 	for (i = 0; i < opd.opd_ncounters; i++) {
962 		if (cfgs[i] == NULL)
963 			continue;
964 
965 		diff = (curpic[i] - cfgs[i]->opt_rawpic) & MASK48;
966 		*addrs[i] += diff;
967 		DTRACE_PROBE4(opt__pcbe__sample, int, i, uint64_t, *addrs[i],
968 		    uint64_t, curpic[i], uint64_t, cfgs[i]->opt_rawpic);
969 		cfgs[i]->opt_rawpic = *addrs[i] & MASK48;
970 	}
971 }
972 
973 static void
opt_pcbe_free(void * config)974 opt_pcbe_free(void *config)
975 {
976 	kmem_free(config, sizeof (opt_pcbe_config_t));
977 }
978 
979 
980 static struct modlpcbe modlpcbe = {
981 	&mod_pcbeops,
982 	"AMD Performance Counters",
983 	&opt_pcbe_ops
984 };
985 
986 static struct modlinkage modl = {
987 	MODREV_1,
988 	&modlpcbe,
989 };
990 
991 int
_init(void)992 _init(void)
993 {
994 	int ret;
995 
996 	if (opt_pcbe_init() != 0)
997 		return (ENOTSUP);
998 
999 	if ((ret = mod_install(&modl)) != 0)
1000 		kmem_free(evlist, evlist_sz + 1);
1001 
1002 	return (ret);
1003 }
1004 
1005 int
_fini(void)1006 _fini(void)
1007 {
1008 	int ret;
1009 
1010 	if ((ret = mod_remove(&modl)) == 0)
1011 		kmem_free(evlist, evlist_sz + 1);
1012 	return (ret);
1013 }
1014 
1015 int
_info(struct modinfo * mi)1016 _info(struct modinfo *mi)
1017 {
1018 	return (mod_info(&modl, mi));
1019 }
1020