17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5346af85bScwb * Common Development and Distribution License (the "License"). 6346af85bScwb * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22820c9f58Skk * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 26*c7a079a8SJonathan Haslam /* 27*c7a079a8SJonathan Haslam * This file contains preset event names from the Performance Application 28*c7a079a8SJonathan Haslam * Programming Interface v3.5 which included the following notice: 29*c7a079a8SJonathan Haslam * 30*c7a079a8SJonathan Haslam * Copyright (c) 2005,6 31*c7a079a8SJonathan Haslam * Innovative Computing Labs 32*c7a079a8SJonathan Haslam * Computer Science Department, 33*c7a079a8SJonathan Haslam * University of Tennessee, 34*c7a079a8SJonathan Haslam * Knoxville, TN. 35*c7a079a8SJonathan Haslam * All Rights Reserved. 36*c7a079a8SJonathan Haslam * 37*c7a079a8SJonathan Haslam * 38*c7a079a8SJonathan Haslam * Redistribution and use in source and binary forms, with or without 39*c7a079a8SJonathan Haslam * modification, are permitted provided that the following conditions are met: 40*c7a079a8SJonathan Haslam * 41*c7a079a8SJonathan Haslam * * Redistributions of source code must retain the above copyright notice, 42*c7a079a8SJonathan Haslam * this list of conditions and the following disclaimer. 43*c7a079a8SJonathan Haslam * * Redistributions in binary form must reproduce the above copyright 44*c7a079a8SJonathan Haslam * notice, this list of conditions and the following disclaimer in the 45*c7a079a8SJonathan Haslam * documentation and/or other materials provided with the distribution. 46*c7a079a8SJonathan Haslam * * Neither the name of the University of Tennessee nor the names of its 47*c7a079a8SJonathan Haslam * contributors may be used to endorse or promote products derived from 48*c7a079a8SJonathan Haslam * this software without specific prior written permission. 49*c7a079a8SJonathan Haslam * 50*c7a079a8SJonathan Haslam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 51*c7a079a8SJonathan Haslam * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52*c7a079a8SJonathan Haslam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53*c7a079a8SJonathan Haslam * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 54*c7a079a8SJonathan Haslam * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55*c7a079a8SJonathan Haslam * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56*c7a079a8SJonathan Haslam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57*c7a079a8SJonathan Haslam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58*c7a079a8SJonathan Haslam * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59*c7a079a8SJonathan Haslam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60*c7a079a8SJonathan Haslam * POSSIBILITY OF SUCH DAMAGE. 61*c7a079a8SJonathan Haslam * 62*c7a079a8SJonathan Haslam * 63*c7a079a8SJonathan Haslam * This open source software license conforms to the BSD License template. 64*c7a079a8SJonathan Haslam */ 657c478bd9Sstevel@tonic-gate 667c478bd9Sstevel@tonic-gate /* 677c478bd9Sstevel@tonic-gate * Performance Counter Back-End for AMD Opteron and AMD Athlon 64 processors. 687c478bd9Sstevel@tonic-gate */ 697c478bd9Sstevel@tonic-gate 707c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 717c478bd9Sstevel@tonic-gate #include <sys/param.h> 727c478bd9Sstevel@tonic-gate #include <sys/systm.h> 737c478bd9Sstevel@tonic-gate #include <sys/cpc_pcbe.h> 747c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 757c478bd9Sstevel@tonic-gate #include <sys/sdt.h> 767c478bd9Sstevel@tonic-gate #include <sys/modctl.h> 777c478bd9Sstevel@tonic-gate #include <sys/errno.h> 787c478bd9Sstevel@tonic-gate #include <sys/debug.h> 797c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 807c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h> 817c478bd9Sstevel@tonic-gate #include <sys/privregs.h> 825d3a5ad8Srab #include <sys/ddi.h> 835d3a5ad8Srab #include <sys/sunddi.h> 847c478bd9Sstevel@tonic-gate 857c478bd9Sstevel@tonic-gate static int opt_pcbe_init(void); 867c478bd9Sstevel@tonic-gate static uint_t opt_pcbe_ncounters(void); 877c478bd9Sstevel@tonic-gate static const char *opt_pcbe_impl_name(void); 887c478bd9Sstevel@tonic-gate static const char *opt_pcbe_cpuref(void); 897c478bd9Sstevel@tonic-gate static char *opt_pcbe_list_events(uint_t picnum); 907c478bd9Sstevel@tonic-gate static char *opt_pcbe_list_attrs(void); 917c478bd9Sstevel@tonic-gate static uint64_t opt_pcbe_event_coverage(char *event); 927c478bd9Sstevel@tonic-gate static uint64_t opt_pcbe_overflow_bitmap(void); 937c478bd9Sstevel@tonic-gate static int opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, 947c478bd9Sstevel@tonic-gate uint32_t flags, uint_t nattrs, kcpc_attr_t *attrs, void **data, 957c478bd9Sstevel@tonic-gate void *token); 967c478bd9Sstevel@tonic-gate static void opt_pcbe_program(void *token); 977c478bd9Sstevel@tonic-gate static void opt_pcbe_allstop(void); 987c478bd9Sstevel@tonic-gate static void opt_pcbe_sample(void *token); 997c478bd9Sstevel@tonic-gate static void opt_pcbe_free(void *config); 1007c478bd9Sstevel@tonic-gate 1017c478bd9Sstevel@tonic-gate static pcbe_ops_t opt_pcbe_ops = { 1027c478bd9Sstevel@tonic-gate PCBE_VER_1, 1037c478bd9Sstevel@tonic-gate CPC_CAP_OVERFLOW_INTERRUPT, 1047c478bd9Sstevel@tonic-gate opt_pcbe_ncounters, 1057c478bd9Sstevel@tonic-gate opt_pcbe_impl_name, 1067c478bd9Sstevel@tonic-gate opt_pcbe_cpuref, 1077c478bd9Sstevel@tonic-gate opt_pcbe_list_events, 1087c478bd9Sstevel@tonic-gate opt_pcbe_list_attrs, 1097c478bd9Sstevel@tonic-gate opt_pcbe_event_coverage, 1107c478bd9Sstevel@tonic-gate opt_pcbe_overflow_bitmap, 1117c478bd9Sstevel@tonic-gate opt_pcbe_configure, 1127c478bd9Sstevel@tonic-gate opt_pcbe_program, 1137c478bd9Sstevel@tonic-gate opt_pcbe_allstop, 1147c478bd9Sstevel@tonic-gate opt_pcbe_sample, 1157c478bd9Sstevel@tonic-gate opt_pcbe_free 1167c478bd9Sstevel@tonic-gate }; 1177c478bd9Sstevel@tonic-gate 1187c478bd9Sstevel@tonic-gate /* 1197c478bd9Sstevel@tonic-gate * Define offsets and masks for the fields in the Performance 1207c478bd9Sstevel@tonic-gate * Event-Select (PES) registers. 1217c478bd9Sstevel@tonic-gate */ 12231725658Sksadhukh #define OPT_PES_HOST_SHIFT 41 12331725658Sksadhukh #define OPT_PES_GUEST_SHIFT 40 1247c478bd9Sstevel@tonic-gate #define OPT_PES_CMASK_SHIFT 24 1257c478bd9Sstevel@tonic-gate #define OPT_PES_CMASK_MASK 0xFF 1267c478bd9Sstevel@tonic-gate #define OPT_PES_INV_SHIFT 23 1277c478bd9Sstevel@tonic-gate #define OPT_PES_ENABLE_SHIFT 22 1287c478bd9Sstevel@tonic-gate #define OPT_PES_INT_SHIFT 20 1297c478bd9Sstevel@tonic-gate #define OPT_PES_PC_SHIFT 19 1307c478bd9Sstevel@tonic-gate #define OPT_PES_EDGE_SHIFT 18 1317c478bd9Sstevel@tonic-gate #define OPT_PES_OS_SHIFT 17 1327c478bd9Sstevel@tonic-gate #define OPT_PES_USR_SHIFT 16 1337c478bd9Sstevel@tonic-gate #define OPT_PES_UMASK_SHIFT 8 1347c478bd9Sstevel@tonic-gate #define OPT_PES_UMASK_MASK 0xFF 1357c478bd9Sstevel@tonic-gate 13631725658Sksadhukh #define OPT_PES_INV (1ULL << OPT_PES_INV_SHIFT) 13731725658Sksadhukh #define OPT_PES_ENABLE (1ULL << OPT_PES_ENABLE_SHIFT) 13831725658Sksadhukh #define OPT_PES_INT (1ULL << OPT_PES_INT_SHIFT) 13931725658Sksadhukh #define OPT_PES_PC (1ULL << OPT_PES_PC_SHIFT) 14031725658Sksadhukh #define OPT_PES_EDGE (1ULL << OPT_PES_EDGE_SHIFT) 14131725658Sksadhukh #define OPT_PES_OS (1ULL << OPT_PES_OS_SHIFT) 14231725658Sksadhukh #define OPT_PES_USR (1ULL << OPT_PES_USR_SHIFT) 14331725658Sksadhukh #define OPT_PES_HOST (1ULL << OPT_PES_HOST_SHIFT) 14431725658Sksadhukh #define OPT_PES_GUEST (1ULL << OPT_PES_GUEST_SHIFT) 1457c478bd9Sstevel@tonic-gate 1467c478bd9Sstevel@tonic-gate typedef struct _opt_pcbe_config { 1477c478bd9Sstevel@tonic-gate uint8_t opt_picno; /* Counter number: 0, 1, 2, or 3 */ 1487c478bd9Sstevel@tonic-gate uint64_t opt_evsel; /* Event Selection register */ 1497c478bd9Sstevel@tonic-gate uint64_t opt_rawpic; /* Raw counter value */ 1507c478bd9Sstevel@tonic-gate } opt_pcbe_config_t; 1517c478bd9Sstevel@tonic-gate 1527c478bd9Sstevel@tonic-gate opt_pcbe_config_t nullcfgs[4] = { 1537c478bd9Sstevel@tonic-gate { 0, 0, 0 }, 1547c478bd9Sstevel@tonic-gate { 1, 0, 0 }, 1557c478bd9Sstevel@tonic-gate { 2, 0, 0 }, 1567c478bd9Sstevel@tonic-gate { 3, 0, 0 } 1577c478bd9Sstevel@tonic-gate }; 1587c478bd9Sstevel@tonic-gate 15931725658Sksadhukh typedef struct _amd_event { 1607c478bd9Sstevel@tonic-gate char *name; 16131725658Sksadhukh uint16_t emask; /* Event mask setting */ 1627c478bd9Sstevel@tonic-gate uint8_t umask_valid; /* Mask of unreserved UNIT_MASK bits */ 16331725658Sksadhukh } amd_event_t; 1647c478bd9Sstevel@tonic-gate 165*c7a079a8SJonathan Haslam typedef struct _amd_generic_event { 166*c7a079a8SJonathan Haslam char *name; 167*c7a079a8SJonathan Haslam char *event; 168*c7a079a8SJonathan Haslam uint8_t umask; 169*c7a079a8SJonathan Haslam } amd_generic_event_t; 170*c7a079a8SJonathan Haslam 1717c478bd9Sstevel@tonic-gate /* 1727c478bd9Sstevel@tonic-gate * Base MSR addresses for the PerfEvtSel registers and the counters themselves. 1737c478bd9Sstevel@tonic-gate * Add counter number to base address to get corresponding MSR address. 1747c478bd9Sstevel@tonic-gate */ 1757c478bd9Sstevel@tonic-gate #define PES_BASE_ADDR 0xC0010000 1767c478bd9Sstevel@tonic-gate #define PIC_BASE_ADDR 0xC0010004 1777c478bd9Sstevel@tonic-gate 1787c478bd9Sstevel@tonic-gate #define MASK48 0xFFFFFFFFFFFF 1797c478bd9Sstevel@tonic-gate 1807c478bd9Sstevel@tonic-gate #define EV_END {NULL, 0, 0} 181*c7a079a8SJonathan Haslam #define GEN_EV_END {NULL, NULL, 0 } 1827c478bd9Sstevel@tonic-gate 18331725658Sksadhukh #define AMD_cmn_events \ 18431725658Sksadhukh { "FP_dispatched_fpu_ops", 0x0, 0x3F }, \ 185fb47e43fSjhaslam { "FP_cycles_no_fpu_ops_retired", 0x1, 0x0 }, \ 186fb47e43fSjhaslam { "FP_dispatched_fpu_ops_ff", 0x2, 0x0 }, \ 187fb47e43fSjhaslam { "LS_seg_reg_load", 0x20, 0x7F }, \ 188fb47e43fSjhaslam { "LS_uarch_resync_self_modify", 0x21, 0x0 }, \ 189fb47e43fSjhaslam { "LS_uarch_resync_snoop", 0x22, 0x0 }, \ 190fb47e43fSjhaslam { "LS_buffer_2_full", 0x23, 0x0 }, \ 191fb47e43fSjhaslam { "LS_retired_cflush", 0x26, 0x0 }, \ 192fb47e43fSjhaslam { "LS_retired_cpuid", 0x27, 0x0 }, \ 193fb47e43fSjhaslam { "DC_access", 0x40, 0x0 }, \ 194fb47e43fSjhaslam { "DC_miss", 0x41, 0x0 }, \ 195fb47e43fSjhaslam { "DC_refill_from_L2", 0x42, 0x1F }, \ 196fb47e43fSjhaslam { "DC_refill_from_system", 0x43, 0x1F }, \ 197fb47e43fSjhaslam { "DC_misaligned_data_ref", 0x47, 0x0 }, \ 198fb47e43fSjhaslam { "DC_uarch_late_cancel_access", 0x48, 0x0 }, \ 199fb47e43fSjhaslam { "DC_uarch_early_cancel_access", 0x49, 0x0 }, \ 200fb47e43fSjhaslam { "DC_dispatched_prefetch_instr", 0x4B, 0x7 }, \ 201fb47e43fSjhaslam { "DC_dcache_accesses_by_locks", 0x4C, 0x2 }, \ 202fb47e43fSjhaslam { "BU_memory_requests", 0x65, 0x83}, \ 203fb47e43fSjhaslam { "BU_data_prefetch", 0x67, 0x3 }, \ 204fb47e43fSjhaslam { "BU_cpu_clk_unhalted", 0x76, 0x0 }, \ 205fb47e43fSjhaslam { "IC_fetch", 0x80, 0x0 }, \ 206fb47e43fSjhaslam { "IC_miss", 0x81, 0x0 }, \ 207fb47e43fSjhaslam { "IC_refill_from_L2", 0x82, 0x0 }, \ 208fb47e43fSjhaslam { "IC_refill_from_system", 0x83, 0x0 }, \ 209fb47e43fSjhaslam { "IC_itlb_L1_miss_L2_hit", 0x84, 0x0 }, \ 210fb47e43fSjhaslam { "IC_uarch_resync_snoop", 0x86, 0x0 }, \ 211fb47e43fSjhaslam { "IC_instr_fetch_stall", 0x87, 0x0 }, \ 212fb47e43fSjhaslam { "IC_return_stack_hit", 0x88, 0x0 }, \ 213fb47e43fSjhaslam { "IC_return_stack_overflow", 0x89, 0x0 }, \ 214fb47e43fSjhaslam { "FR_retired_x86_instr_w_excp_intr", 0xC0, 0x0 }, \ 215fb47e43fSjhaslam { "FR_retired_uops", 0xC1, 0x0 }, \ 216fb47e43fSjhaslam { "FR_retired_branches_w_excp_intr", 0xC2, 0x0 }, \ 217fb47e43fSjhaslam { "FR_retired_branches_mispred", 0xC3, 0x0 }, \ 218fb47e43fSjhaslam { "FR_retired_taken_branches", 0xC4, 0x0 }, \ 219fb47e43fSjhaslam { "FR_retired_taken_branches_mispred", 0xC5, 0x0 }, \ 220fb47e43fSjhaslam { "FR_retired_far_ctl_transfer", 0xC6, 0x0 }, \ 221fb47e43fSjhaslam { "FR_retired_resyncs", 0xC7, 0x0 }, \ 222fb47e43fSjhaslam { "FR_retired_near_rets", 0xC8, 0x0 }, \ 223fb47e43fSjhaslam { "FR_retired_near_rets_mispred", 0xC9, 0x0 }, \ 22477b329feSjhaslam { "FR_retired_taken_branches_mispred_addr_miscomp", 0xCA, 0x0 },\ 225fb47e43fSjhaslam { "FR_retired_fastpath_double_op_instr", 0xCC, 0x7 }, \ 226fb47e43fSjhaslam { "FR_intr_masked_cycles", 0xCD, 0x0 }, \ 227fb47e43fSjhaslam { "FR_intr_masked_while_pending_cycles", 0xCE, 0x0 }, \ 228fb47e43fSjhaslam { "FR_taken_hardware_intrs", 0xCF, 0x0 }, \ 229fb47e43fSjhaslam { "FR_nothing_to_dispatch", 0xD0, 0x0 }, \ 230fb47e43fSjhaslam { "FR_dispatch_stalls", 0xD1, 0x0 }, \ 231fb47e43fSjhaslam { "FR_dispatch_stall_branch_abort_to_retire", 0xD2, 0x0 }, \ 232fb47e43fSjhaslam { "FR_dispatch_stall_serialization", 0xD3, 0x0 }, \ 233fb47e43fSjhaslam { "FR_dispatch_stall_segment_load", 0xD4, 0x0 }, \ 234fb47e43fSjhaslam { "FR_dispatch_stall_reorder_buffer_full", 0xD5, 0x0 }, \ 235fb47e43fSjhaslam { "FR_dispatch_stall_resv_stations_full", 0xD6, 0x0 }, \ 236fb47e43fSjhaslam { "FR_dispatch_stall_fpu_full", 0xD7, 0x0 }, \ 237fb47e43fSjhaslam { "FR_dispatch_stall_ls_full", 0xD8, 0x0 }, \ 238fb47e43fSjhaslam { "FR_dispatch_stall_waiting_all_quiet", 0xD9, 0x0 }, \ 23977b329feSjhaslam { "FR_dispatch_stall_far_ctl_trsfr_resync_branch_pend", 0xDA, 0x0 },\ 240fb47e43fSjhaslam { "FR_fpu_exception", 0xDB, 0xF }, \ 241fb47e43fSjhaslam { "FR_num_brkpts_dr0", 0xDC, 0x0 }, \ 242fb47e43fSjhaslam { "FR_num_brkpts_dr1", 0xDD, 0x0 }, \ 243fb47e43fSjhaslam { "FR_num_brkpts_dr2", 0xDE, 0x0 }, \ 244fb47e43fSjhaslam { "FR_num_brkpts_dr3", 0xDF, 0x0 }, \ 24531725658Sksadhukh { "NB_mem_ctrlr_bypass_counter_saturation", 0xE4, 0xF } 24631725658Sksadhukh 24731725658Sksadhukh #define OPT_events \ 24831725658Sksadhukh { "LS_locked_operation", 0x24, 0x7 }, \ 24931725658Sksadhukh { "DC_copyback", 0x44, 0x1F }, \ 25031725658Sksadhukh { "DC_dtlb_L1_miss_L2_hit", 0x45, 0x0 }, \ 25131725658Sksadhukh { "DC_dtlb_L1_miss_L2_miss", 0x46, 0x0 }, \ 25231725658Sksadhukh { "DC_1bit_ecc_error_found", 0x4A, 0x3 }, \ 25331725658Sksadhukh { "BU_system_read_responses", 0x6C, 0x7 }, \ 25431725658Sksadhukh { "BU_quadwords_written_to_system", 0x6D, 0x1 }, \ 25531725658Sksadhukh { "BU_internal_L2_req", 0x7D, 0x1F }, \ 25631725658Sksadhukh { "BU_fill_req_missed_L2", 0x7E, 0x7 }, \ 25731725658Sksadhukh { "BU_fill_into_L2", 0x7F, 0x1 }, \ 25831725658Sksadhukh { "IC_itlb_L1_miss_L2_miss", 0x85, 0x0 }, \ 25931725658Sksadhukh { "FR_retired_fpu_instr", 0xCB, 0xF }, \ 260fb47e43fSjhaslam { "NB_mem_ctrlr_page_access", 0xE0, 0x7 }, \ 261fb47e43fSjhaslam { "NB_mem_ctrlr_page_table_overflow", 0xE1, 0x0 }, \ 262fb47e43fSjhaslam { "NB_mem_ctrlr_turnaround", 0xE3, 0x7 }, \ 263fb47e43fSjhaslam { "NB_ECC_errors", 0xE8, 0x80}, \ 264fb47e43fSjhaslam { "NB_sized_commands", 0xEB, 0x7F }, \ 265fb47e43fSjhaslam { "NB_probe_result", 0xEC, 0x7F}, \ 266fb47e43fSjhaslam { "NB_gart_events", 0xEE, 0x7 }, \ 267fb47e43fSjhaslam { "NB_ht_bus0_bandwidth", 0xF6, 0xF }, \ 268fb47e43fSjhaslam { "NB_ht_bus1_bandwidth", 0xF7, 0xF }, \ 269fb47e43fSjhaslam { "NB_ht_bus2_bandwidth", 0xF8, 0xF } 270fb47e43fSjhaslam 271fb47e43fSjhaslam #define OPT_RevD_events \ 272fb47e43fSjhaslam { "NB_sized_blocks", 0xE5, 0x3C } 273fb47e43fSjhaslam 274fb47e43fSjhaslam #define OPT_RevE_events \ 275fb47e43fSjhaslam { "NB_cpu_io_to_mem_io", 0xE9, 0xFF}, \ 276fb47e43fSjhaslam { "NB_cache_block_commands", 0xEA, 0x3D} 277fb47e43fSjhaslam 27831725658Sksadhukh #define AMD_FAMILY_10h_cmn_events \ 27931725658Sksadhukh { "FP_retired_sse_ops", 0x3, 0x7F}, \ 28031725658Sksadhukh { "FP_retired_move_ops", 0x4, 0xF}, \ 28131725658Sksadhukh { "FP_retired_serialize_ops", 0x5, 0xF}, \ 28231725658Sksadhukh { "FP_serialize_ops_cycles", 0x6, 0x3}, \ 28331725658Sksadhukh { "DC_copyback", 0x44, 0x7F }, \ 28431725658Sksadhukh { "DC_dtlb_L1_miss_L2_hit", 0x45, 0x3 }, \ 28531725658Sksadhukh { "DC_dtlb_L1_miss_L2_miss", 0x46, 0x7 }, \ 28631725658Sksadhukh { "DC_1bit_ecc_error_found", 0x4A, 0xF }, \ 28731725658Sksadhukh { "DC_dtlb_L1_hit", 0x4D, 0x7 }, \ 28831725658Sksadhukh { "BU_system_read_responses", 0x6C, 0x17 }, \ 28931725658Sksadhukh { "BU_octwords_written_to_system", 0x6D, 0x1 }, \ 29031725658Sksadhukh { "BU_internal_L2_req", 0x7D, 0x3F }, \ 29131725658Sksadhukh { "BU_fill_req_missed_L2", 0x7E, 0xF }, \ 29231725658Sksadhukh { "BU_fill_into_L2", 0x7F, 0x3 }, \ 29331725658Sksadhukh { "IC_itlb_L1_miss_L2_miss", 0x85, 0x3 }, \ 29431725658Sksadhukh { "IC_eviction", 0x8B, 0x0 }, \ 29531725658Sksadhukh { "IC_cache_lines_invalidate", 0x8C, 0xF }, \ 29631725658Sksadhukh { "IC_itlb_reload", 0x99, 0x0 }, \ 29731725658Sksadhukh { "IC_itlb_reload_aborted", 0x9A, 0x0 }, \ 29831725658Sksadhukh { "FR_retired_mmx_sse_fp_instr", 0xCB, 0x7 }, \ 29931725658Sksadhukh { "NB_mem_ctrlr_page_access", 0xE0, 0xFF }, \ 30031725658Sksadhukh { "NB_mem_ctrlr_page_table_overflow", 0xE1, 0x3 }, \ 30131725658Sksadhukh { "NB_mem_ctrlr_turnaround", 0xE3, 0x3F }, \ 30231725658Sksadhukh { "NB_thermal_status", 0xE8, 0x7C}, \ 30331725658Sksadhukh { "NB_sized_commands", 0xEB, 0x3F }, \ 30431725658Sksadhukh { "NB_probe_results_upstream_req", 0xEC, 0xFF}, \ 30531725658Sksadhukh { "NB_gart_events", 0xEE, 0xFF }, \ 30631725658Sksadhukh { "NB_ht_bus0_bandwidth", 0xF6, 0xBF }, \ 30731725658Sksadhukh { "NB_ht_bus1_bandwidth", 0xF7, 0xBF }, \ 30831725658Sksadhukh { "NB_ht_bus2_bandwidth", 0xF8, 0xBF }, \ 30931725658Sksadhukh { "NB_ht_bus3_bandwidth", 0x1F9, 0xBF }, \ 31031725658Sksadhukh { "LS_locked_operation", 0x24, 0xF }, \ 31131725658Sksadhukh { "LS_cancelled_store_to_load_fwd_ops", 0x2A, 0x7 }, \ 31231725658Sksadhukh { "LS_smi_received", 0x2B, 0x0 }, \ 31331725658Sksadhukh { "LS_ineffective_prefetch", 0x52, 0x9 }, \ 31431725658Sksadhukh { "LS_global_tlb_flush", 0x54, 0x0 }, \ 31531725658Sksadhukh { "NB_mem_ctrlr_dram_cmd_slots_missed", 0xE2, 0x3 }, \ 31631725658Sksadhukh { "NB_mem_ctrlr_req", 0x1F0, 0xFF }, \ 31731725658Sksadhukh { "CB_cpu_to_dram_req_to_target", 0x1E0, 0xFF }, \ 31831725658Sksadhukh { "CB_io_to_dram_req_to_target", 0x1E1, 0xFF }, \ 31931725658Sksadhukh { "CB_cpu_read_cmd_latency_to_target_0_to_3", 0x1E2, 0xFF }, \ 32031725658Sksadhukh { "CB_cpu_read_cmd_req_to_target_0_to_3", 0x1E3, 0xFF }, \ 32131725658Sksadhukh { "CB_cpu_read_cmd_latency_to_target_4_to_7", 0x1E4, 0xFF }, \ 32231725658Sksadhukh { "CB_cpu_read_cmd_req_to_target_4_to_7", 0x1E5, 0xFF }, \ 32331725658Sksadhukh { "CB_cpu_cmd_latency_to_target_0_to_7", 0x1E6, 0xFF }, \ 32431725658Sksadhukh { "CB_cpu_req_to_target_0_to_7", 0x1E7, 0xFF }, \ 32531725658Sksadhukh { "L3_read_req", 0x4E0, 0xF7 }, \ 32631725658Sksadhukh { "L3_miss", 0x4E1, 0xF7 }, \ 32731725658Sksadhukh { "L3_l2_eviction_l3_fill", 0x4E2, 0xFF }, \ 32831725658Sksadhukh { "L3_eviction", 0x4E3, 0xF } 32931725658Sksadhukh 330*c7a079a8SJonathan Haslam #define AMD_cmn_generic_events \ 331*c7a079a8SJonathan Haslam { "PAPI_br_ins", "FR_retired_branches_w_excp_intr", 0x0 },\ 332*c7a079a8SJonathan Haslam { "PAPI_br_msp", "FR_retired_branches_mispred", 0x0 }, \ 333*c7a079a8SJonathan Haslam { "PAPI_br_tkn", "FR_retired_taken_branches", 0x0 }, \ 334*c7a079a8SJonathan Haslam { "PAPI_fp_ops", "FP_dispatched_fpu_ops", 0x3 }, \ 335*c7a079a8SJonathan Haslam { "PAPI_fad_ins", "FP_dispatched_fpu_ops", 0x1 }, \ 336*c7a079a8SJonathan Haslam { "PAPI_fml_ins", "FP_dispatched_fpu_ops", 0x2 }, \ 337*c7a079a8SJonathan Haslam { "PAPI_fpu_idl", "FP_cycles_no_fpu_ops_retired", 0x0 }, \ 338*c7a079a8SJonathan Haslam { "PAPI_tot_cyc", "BU_cpu_clk_unhalted", 0x0 }, \ 339*c7a079a8SJonathan Haslam { "PAPI_tot_ins", "FR_retired_x86_instr_w_excp_intr", 0x0 }, \ 340*c7a079a8SJonathan Haslam { "PAPI_l1_dca", "DC_access", 0x0 }, \ 341*c7a079a8SJonathan Haslam { "PAPI_l1_dcm", "DC_miss", 0x0 }, \ 342*c7a079a8SJonathan Haslam { "PAPI_l1_ldm", "DC_refill_from_L2", 0xe }, \ 343*c7a079a8SJonathan Haslam { "PAPI_l1_stm", "DC_refill_from_L2", 0x10 }, \ 344*c7a079a8SJonathan Haslam { "PAPI_l1_ica", "IC_fetch", 0x0 }, \ 345*c7a079a8SJonathan Haslam { "PAPI_l1_icm", "IC_miss", 0x0 }, \ 346*c7a079a8SJonathan Haslam { "PAPI_l1_icr", "IC_fetch", 0x0 }, \ 347*c7a079a8SJonathan Haslam { "PAPI_l2_dch", "DC_refill_from_L2", 0x1e }, \ 348*c7a079a8SJonathan Haslam { "PAPI_l2_dcm", "DC_refill_from_system", 0x1e }, \ 349*c7a079a8SJonathan Haslam { "PAPI_l2_dcr", "DC_refill_from_L2", 0xe }, \ 350*c7a079a8SJonathan Haslam { "PAPI_l2_dcw", "DC_refill_from_L2", 0x10 }, \ 351*c7a079a8SJonathan Haslam { "PAPI_l2_ich", "IC_refill_from_L2", 0x0 }, \ 352*c7a079a8SJonathan Haslam { "PAPI_l2_icm", "IC_refill_from_system", 0x0 }, \ 353*c7a079a8SJonathan Haslam { "PAPI_l2_ldm", "DC_refill_from_system", 0xe }, \ 354*c7a079a8SJonathan Haslam { "PAPI_l2_stm", "DC_refill_from_system", 0x10 }, \ 355*c7a079a8SJonathan Haslam { "PAPI_res_stl", "FR_dispatch_stalls", 0x0 }, \ 356*c7a079a8SJonathan Haslam { "PAPI_stl_icy", "FR_nothing_to_dispatch", 0x0 }, \ 357*c7a079a8SJonathan Haslam { "PAPI_hw_int", "FR_taken_hardware_intrs", 0x0 } 358*c7a079a8SJonathan Haslam 359*c7a079a8SJonathan Haslam #define OPT_cmn_generic_events \ 360*c7a079a8SJonathan Haslam { "PAPI_tlb_dm", "DC_dtlb_L1_miss_L2_miss", 0x0 }, \ 361*c7a079a8SJonathan Haslam { "PAPI_tlb_im", "IC_itlb_L1_miss_L2_miss", 0x0 }, \ 362*c7a079a8SJonathan Haslam { "PAPI_fp_ins", "FR_retired_fpu_instr", 0xd }, \ 363*c7a079a8SJonathan Haslam { "PAPI_vec_ins", "FR_retired_fpu_instr", 0x4 } 364*c7a079a8SJonathan Haslam 365*c7a079a8SJonathan Haslam #define AMD_FAMILY_10h_generic_events \ 366*c7a079a8SJonathan Haslam { "PAPI_tlb_dm", "DC_dtlb_L1_miss_L2_miss", 0x7 }, \ 367*c7a079a8SJonathan Haslam { "PAPI_tlb_im", "IC_itlb_L1_miss_L2_miss", 0x3 }, \ 368*c7a079a8SJonathan Haslam { "PAPI_l3_dcr", "L3_read_req", 0xf1 }, \ 369*c7a079a8SJonathan Haslam { "PAPI_l3_icr", "L3_read_req", 0xf2 }, \ 370*c7a079a8SJonathan Haslam { "PAPI_l3_tcr", "L3_read_req", 0xf7 }, \ 371*c7a079a8SJonathan Haslam { "PAPI_l3_stm", "L3_miss", 0xf4 }, \ 372*c7a079a8SJonathan Haslam { "PAPI_l3_ldm", "L3_miss", 0xf3 }, \ 373*c7a079a8SJonathan Haslam { "PAPI_l3_tcm", "L3_miss", 0xf7 } 374*c7a079a8SJonathan Haslam 37531725658Sksadhukh static amd_event_t opt_events[] = { 37631725658Sksadhukh AMD_cmn_events, 37731725658Sksadhukh OPT_events, 378fb47e43fSjhaslam EV_END 379fb47e43fSjhaslam }; 380fb47e43fSjhaslam 38131725658Sksadhukh static amd_event_t opt_events_rev_D[] = { 38231725658Sksadhukh AMD_cmn_events, 38331725658Sksadhukh OPT_events, 384fb47e43fSjhaslam OPT_RevD_events, 385fb47e43fSjhaslam EV_END 386fb47e43fSjhaslam }; 387fb47e43fSjhaslam 38831725658Sksadhukh static amd_event_t opt_events_rev_E[] = { 38931725658Sksadhukh AMD_cmn_events, 39031725658Sksadhukh OPT_events, 391fb47e43fSjhaslam OPT_RevD_events, 392fb47e43fSjhaslam OPT_RevE_events, 3937c478bd9Sstevel@tonic-gate EV_END 3947c478bd9Sstevel@tonic-gate }; 3957c478bd9Sstevel@tonic-gate 39631725658Sksadhukh static amd_event_t family_10h_events[] = { 39731725658Sksadhukh AMD_cmn_events, 39831725658Sksadhukh OPT_RevE_events, 39931725658Sksadhukh AMD_FAMILY_10h_cmn_events, 40031725658Sksadhukh EV_END 40131725658Sksadhukh }; 40231725658Sksadhukh 403*c7a079a8SJonathan Haslam static amd_generic_event_t opt_generic_events[] = { 404*c7a079a8SJonathan Haslam AMD_cmn_generic_events, 405*c7a079a8SJonathan Haslam OPT_cmn_generic_events, 406*c7a079a8SJonathan Haslam GEN_EV_END 407*c7a079a8SJonathan Haslam }; 408*c7a079a8SJonathan Haslam 409*c7a079a8SJonathan Haslam static amd_generic_event_t family_10h_generic_events[] = { 410*c7a079a8SJonathan Haslam AMD_cmn_generic_events, 411*c7a079a8SJonathan Haslam AMD_FAMILY_10h_generic_events, 412*c7a079a8SJonathan Haslam GEN_EV_END 413*c7a079a8SJonathan Haslam }; 414*c7a079a8SJonathan Haslam 4157c478bd9Sstevel@tonic-gate static char *evlist; 4167c478bd9Sstevel@tonic-gate static size_t evlist_sz; 41731725658Sksadhukh static amd_event_t *amd_events = NULL; 41831725658Sksadhukh static uint_t amd_family; 419*c7a079a8SJonathan Haslam static amd_generic_event_t *amd_generic_events = NULL; 4207c478bd9Sstevel@tonic-gate 4217c478bd9Sstevel@tonic-gate #define BITS(v, u, l) \ 4227c478bd9Sstevel@tonic-gate (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1)) 4237c478bd9Sstevel@tonic-gate 42431725658Sksadhukh #define OPTERON_FAMILY 0xf 42531725658Sksadhukh #define AMD_FAMILY_10H 0x10 4267c478bd9Sstevel@tonic-gate 4277c478bd9Sstevel@tonic-gate static int 4287c478bd9Sstevel@tonic-gate opt_pcbe_init(void) 4297c478bd9Sstevel@tonic-gate { 43031725658Sksadhukh amd_event_t *evp; 431*c7a079a8SJonathan Haslam amd_generic_event_t *gevp; 432fb47e43fSjhaslam uint32_t rev; 4337c478bd9Sstevel@tonic-gate 43431725658Sksadhukh amd_family = cpuid_getfamily(CPU); 43531725658Sksadhukh 4367c478bd9Sstevel@tonic-gate /* 4377c478bd9Sstevel@tonic-gate * Make sure this really _is_ an Opteron or Athlon 64 system. The kernel 4387c478bd9Sstevel@tonic-gate * loads this module based on its name in the module directory, but it 4397c478bd9Sstevel@tonic-gate * could have been renamed. 4407c478bd9Sstevel@tonic-gate */ 4417c478bd9Sstevel@tonic-gate if (cpuid_getvendor(CPU) != X86_VENDOR_AMD || 44231725658Sksadhukh (amd_family != OPTERON_FAMILY && amd_family != AMD_FAMILY_10H)) 4437c478bd9Sstevel@tonic-gate return (-1); 4447c478bd9Sstevel@tonic-gate 445fb47e43fSjhaslam /* 446fb47e43fSjhaslam * Figure out processor revision here and assign appropriate 447fb47e43fSjhaslam * event configuration. 448fb47e43fSjhaslam */ 449fb47e43fSjhaslam 450fb47e43fSjhaslam rev = cpuid_getchiprev(CPU); 451fb47e43fSjhaslam 45231725658Sksadhukh if (amd_family == OPTERON_FAMILY) { 453*c7a079a8SJonathan Haslam amd_generic_events = opt_generic_events; 45431725658Sksadhukh if (!X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_D)) { 45531725658Sksadhukh amd_events = opt_events; 45631725658Sksadhukh } else if X86_CHIPREV_MATCH(rev, X86_CHIPREV_AMD_F_REV_D) { 45731725658Sksadhukh amd_events = opt_events_rev_D; 45831725658Sksadhukh } else if (X86_CHIPREV_MATCH(rev, X86_CHIPREV_AMD_F_REV_E) || 45931725658Sksadhukh X86_CHIPREV_MATCH(rev, X86_CHIPREV_AMD_F_REV_F) || 46031725658Sksadhukh X86_CHIPREV_MATCH(rev, X86_CHIPREV_AMD_F_REV_G)) { 46131725658Sksadhukh amd_events = opt_events_rev_E; 46231725658Sksadhukh } else { 46331725658Sksadhukh amd_events = opt_events; 46431725658Sksadhukh } 46531725658Sksadhukh } else { 46631725658Sksadhukh amd_events = family_10h_events; 467*c7a079a8SJonathan Haslam amd_generic_events = family_10h_generic_events; 46831725658Sksadhukh } 469fb47e43fSjhaslam 4707c478bd9Sstevel@tonic-gate /* 4717c478bd9Sstevel@tonic-gate * Construct event list. 4727c478bd9Sstevel@tonic-gate * 4737c478bd9Sstevel@tonic-gate * First pass: Calculate size needed. We'll need an additional byte 4747c478bd9Sstevel@tonic-gate * for the NULL pointer during the last strcat. 4757c478bd9Sstevel@tonic-gate * 4767c478bd9Sstevel@tonic-gate * Second pass: Copy strings. 4777c478bd9Sstevel@tonic-gate */ 47831725658Sksadhukh for (evp = amd_events; evp->name != NULL; evp++) 4797c478bd9Sstevel@tonic-gate evlist_sz += strlen(evp->name) + 1; 4807c478bd9Sstevel@tonic-gate 481*c7a079a8SJonathan Haslam for (gevp = amd_generic_events; gevp->name != NULL; gevp++) 482*c7a079a8SJonathan Haslam evlist_sz += strlen(gevp->name) + 1; 483*c7a079a8SJonathan Haslam 4847c478bd9Sstevel@tonic-gate evlist = kmem_alloc(evlist_sz + 1, KM_SLEEP); 4857c478bd9Sstevel@tonic-gate evlist[0] = '\0'; 4867c478bd9Sstevel@tonic-gate 48731725658Sksadhukh for (evp = amd_events; evp->name != NULL; evp++) { 4887c478bd9Sstevel@tonic-gate (void) strcat(evlist, evp->name); 4897c478bd9Sstevel@tonic-gate (void) strcat(evlist, ","); 4907c478bd9Sstevel@tonic-gate } 491*c7a079a8SJonathan Haslam 492*c7a079a8SJonathan Haslam for (gevp = amd_generic_events; gevp->name != NULL; gevp++) { 493*c7a079a8SJonathan Haslam (void) strcat(evlist, gevp->name); 494*c7a079a8SJonathan Haslam (void) strcat(evlist, ","); 495*c7a079a8SJonathan Haslam } 496*c7a079a8SJonathan Haslam 4977c478bd9Sstevel@tonic-gate /* 4987c478bd9Sstevel@tonic-gate * Remove trailing comma. 4997c478bd9Sstevel@tonic-gate */ 5007c478bd9Sstevel@tonic-gate evlist[evlist_sz - 1] = '\0'; 5017c478bd9Sstevel@tonic-gate 5027c478bd9Sstevel@tonic-gate return (0); 5037c478bd9Sstevel@tonic-gate } 5047c478bd9Sstevel@tonic-gate 5057c478bd9Sstevel@tonic-gate static uint_t 5067c478bd9Sstevel@tonic-gate opt_pcbe_ncounters(void) 5077c478bd9Sstevel@tonic-gate { 5087c478bd9Sstevel@tonic-gate return (4); 5097c478bd9Sstevel@tonic-gate } 5107c478bd9Sstevel@tonic-gate 5117c478bd9Sstevel@tonic-gate static const char * 5127c478bd9Sstevel@tonic-gate opt_pcbe_impl_name(void) 5137c478bd9Sstevel@tonic-gate { 51431725658Sksadhukh if (amd_family == OPTERON_FAMILY) { 51531725658Sksadhukh return ("AMD Opteron & Athlon64"); 51631725658Sksadhukh } else if (amd_family == AMD_FAMILY_10H) { 51731725658Sksadhukh return ("AMD Family 10h"); 51831725658Sksadhukh } else { 51931725658Sksadhukh return ("Unknown AMD processor"); 52031725658Sksadhukh } 5217c478bd9Sstevel@tonic-gate } 5227c478bd9Sstevel@tonic-gate 5237c478bd9Sstevel@tonic-gate static const char * 5247c478bd9Sstevel@tonic-gate opt_pcbe_cpuref(void) 5257c478bd9Sstevel@tonic-gate { 52631725658Sksadhukh if (amd_family == OPTERON_FAMILY) { 52731725658Sksadhukh return ("See Chapter 10 of the \"BIOS and Kernel Developer's" 52831725658Sksadhukh " Guide for the AMD Athlon 64 and AMD Opteron Processors,\" " 52931725658Sksadhukh "AMD publication #26094"); 53031725658Sksadhukh } else if (amd_family == AMD_FAMILY_10H) { 53131725658Sksadhukh return ("See section 3.15 of the \"BIOS and Kernel " 53231725658Sksadhukh "Developer's Guide (BKDG) For AMD Family 10h Processors,\" " 53331725658Sksadhukh "AMD publication #31116"); 53431725658Sksadhukh } else { 53531725658Sksadhukh return ("Unknown AMD processor"); 53631725658Sksadhukh } 5377c478bd9Sstevel@tonic-gate } 5387c478bd9Sstevel@tonic-gate 5397c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 5407c478bd9Sstevel@tonic-gate static char * 5417c478bd9Sstevel@tonic-gate opt_pcbe_list_events(uint_t picnum) 5427c478bd9Sstevel@tonic-gate { 5437c478bd9Sstevel@tonic-gate return (evlist); 5447c478bd9Sstevel@tonic-gate } 5457c478bd9Sstevel@tonic-gate 5467c478bd9Sstevel@tonic-gate static char * 5477c478bd9Sstevel@tonic-gate opt_pcbe_list_attrs(void) 5487c478bd9Sstevel@tonic-gate { 5497c478bd9Sstevel@tonic-gate return ("edge,pc,inv,cmask,umask"); 5507c478bd9Sstevel@tonic-gate } 5517c478bd9Sstevel@tonic-gate 5527c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 5537c478bd9Sstevel@tonic-gate static uint64_t 5547c478bd9Sstevel@tonic-gate opt_pcbe_event_coverage(char *event) 5557c478bd9Sstevel@tonic-gate { 5567c478bd9Sstevel@tonic-gate /* 5577c478bd9Sstevel@tonic-gate * Fortunately, all counters can count all events. 5587c478bd9Sstevel@tonic-gate */ 5597c478bd9Sstevel@tonic-gate return (0xF); 5607c478bd9Sstevel@tonic-gate } 5617c478bd9Sstevel@tonic-gate 5627c478bd9Sstevel@tonic-gate static uint64_t 5637c478bd9Sstevel@tonic-gate opt_pcbe_overflow_bitmap(void) 5647c478bd9Sstevel@tonic-gate { 5657c478bd9Sstevel@tonic-gate /* 5667c478bd9Sstevel@tonic-gate * Unfortunately, this chip cannot detect which counter overflowed, so 5677c478bd9Sstevel@tonic-gate * we must act as if they all did. 5687c478bd9Sstevel@tonic-gate */ 5697c478bd9Sstevel@tonic-gate return (0xF); 5707c478bd9Sstevel@tonic-gate } 5717c478bd9Sstevel@tonic-gate 572*c7a079a8SJonathan Haslam static amd_generic_event_t * 573*c7a079a8SJonathan Haslam find_generic_event(char *name) 574*c7a079a8SJonathan Haslam { 575*c7a079a8SJonathan Haslam amd_generic_event_t *gevp; 576*c7a079a8SJonathan Haslam 577*c7a079a8SJonathan Haslam for (gevp = amd_generic_events; gevp->name != NULL; gevp++) 578*c7a079a8SJonathan Haslam if (strcmp(name, gevp->name) == 0) 579*c7a079a8SJonathan Haslam return (gevp); 580*c7a079a8SJonathan Haslam 581*c7a079a8SJonathan Haslam return (NULL); 582*c7a079a8SJonathan Haslam } 583*c7a079a8SJonathan Haslam 58431725658Sksadhukh static amd_event_t * 5857c478bd9Sstevel@tonic-gate find_event(char *name) 5867c478bd9Sstevel@tonic-gate { 587*c7a079a8SJonathan Haslam amd_event_t *evp; 5887c478bd9Sstevel@tonic-gate 58931725658Sksadhukh for (evp = amd_events; evp->name != NULL; evp++) 5907c478bd9Sstevel@tonic-gate if (strcmp(name, evp->name) == 0) 5917c478bd9Sstevel@tonic-gate return (evp); 5927c478bd9Sstevel@tonic-gate 5937c478bd9Sstevel@tonic-gate return (NULL); 5947c478bd9Sstevel@tonic-gate } 5957c478bd9Sstevel@tonic-gate 5967c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 5977c478bd9Sstevel@tonic-gate static int 5987c478bd9Sstevel@tonic-gate opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, uint32_t flags, 5997c478bd9Sstevel@tonic-gate uint_t nattrs, kcpc_attr_t *attrs, void **data, void *token) 6007c478bd9Sstevel@tonic-gate { 6017c478bd9Sstevel@tonic-gate opt_pcbe_config_t *cfg; 60231725658Sksadhukh amd_event_t *evp; 60331725658Sksadhukh amd_event_t ev_raw = { "raw", 0, 0xFF }; 604*c7a079a8SJonathan Haslam amd_generic_event_t *gevp; 6057c478bd9Sstevel@tonic-gate int i; 60631725658Sksadhukh uint64_t evsel = 0, evsel_tmp = 0; 6077c478bd9Sstevel@tonic-gate 6087c478bd9Sstevel@tonic-gate /* 6097c478bd9Sstevel@tonic-gate * If we've been handed an existing configuration, we need only preset 6107c478bd9Sstevel@tonic-gate * the counter value. 6117c478bd9Sstevel@tonic-gate */ 6127c478bd9Sstevel@tonic-gate if (*data != NULL) { 6137c478bd9Sstevel@tonic-gate cfg = *data; 6147c478bd9Sstevel@tonic-gate cfg->opt_rawpic = preset & MASK48; 6157c478bd9Sstevel@tonic-gate return (0); 6167c478bd9Sstevel@tonic-gate } 6177c478bd9Sstevel@tonic-gate 6187c478bd9Sstevel@tonic-gate if (picnum >= 4) 6197c478bd9Sstevel@tonic-gate return (CPC_INVALID_PICNUM); 6207c478bd9Sstevel@tonic-gate 6215d3a5ad8Srab if ((evp = find_event(event)) == NULL) { 622*c7a079a8SJonathan Haslam if ((gevp = find_generic_event(event)) != NULL) { 623*c7a079a8SJonathan Haslam evp = find_event(gevp->event); 624*c7a079a8SJonathan Haslam ASSERT(evp != NULL); 6255d3a5ad8Srab 626*c7a079a8SJonathan Haslam if (nattrs > 0) 627*c7a079a8SJonathan Haslam return (CPC_ATTRIBUTE_OUT_OF_RANGE); 6285d3a5ad8Srab 629*c7a079a8SJonathan Haslam evsel |= gevp->umask << OPT_PES_UMASK_SHIFT; 630*c7a079a8SJonathan Haslam } else { 631*c7a079a8SJonathan Haslam long tmp; 632*c7a079a8SJonathan Haslam 633*c7a079a8SJonathan Haslam /* 634*c7a079a8SJonathan Haslam * If ddi_strtol() likes this event, use it as a raw 635*c7a079a8SJonathan Haslam * event code. 636*c7a079a8SJonathan Haslam */ 637*c7a079a8SJonathan Haslam if (ddi_strtol(event, NULL, 0, &tmp) != 0) 638*c7a079a8SJonathan Haslam return (CPC_INVALID_EVENT); 639*c7a079a8SJonathan Haslam 640*c7a079a8SJonathan Haslam ev_raw.emask = tmp; 641*c7a079a8SJonathan Haslam evp = &ev_raw; 642*c7a079a8SJonathan Haslam } 6435d3a5ad8Srab } 6447c478bd9Sstevel@tonic-gate 64531725658Sksadhukh /* 64631725658Sksadhukh * Configuration of EventSelect register for family 10h processors. 64731725658Sksadhukh */ 64831725658Sksadhukh if (amd_family == AMD_FAMILY_10H) { 64931725658Sksadhukh 65031725658Sksadhukh /* Set GuestOnly bit to 0 and HostOnly bit to 1 */ 65131725658Sksadhukh evsel &= ~OPT_PES_HOST; 65231725658Sksadhukh evsel &= ~OPT_PES_GUEST; 65331725658Sksadhukh 65431725658Sksadhukh /* Set bits [35:32] for extended part of Event Select field */ 65531725658Sksadhukh evsel_tmp = evp->emask & 0x0f00; 65631725658Sksadhukh evsel |= evsel_tmp << 24; 65731725658Sksadhukh } 65831725658Sksadhukh 65931725658Sksadhukh evsel |= evp->emask & 0x00ff; 6607c478bd9Sstevel@tonic-gate 6617c478bd9Sstevel@tonic-gate if (flags & CPC_COUNT_USER) 6627c478bd9Sstevel@tonic-gate evsel |= OPT_PES_USR; 6637c478bd9Sstevel@tonic-gate if (flags & CPC_COUNT_SYSTEM) 6647c478bd9Sstevel@tonic-gate evsel |= OPT_PES_OS; 6657c478bd9Sstevel@tonic-gate if (flags & CPC_OVF_NOTIFY_EMT) 6667c478bd9Sstevel@tonic-gate evsel |= OPT_PES_INT; 6677c478bd9Sstevel@tonic-gate 6687c478bd9Sstevel@tonic-gate for (i = 0; i < nattrs; i++) { 6697c478bd9Sstevel@tonic-gate if (strcmp(attrs[i].ka_name, "edge") == 0) { 6707c478bd9Sstevel@tonic-gate if (attrs[i].ka_val != 0) 6717c478bd9Sstevel@tonic-gate evsel |= OPT_PES_EDGE; 6727c478bd9Sstevel@tonic-gate } else if (strcmp(attrs[i].ka_name, "pc") == 0) { 6737c478bd9Sstevel@tonic-gate if (attrs[i].ka_val != 0) 6747c478bd9Sstevel@tonic-gate evsel |= OPT_PES_PC; 6757c478bd9Sstevel@tonic-gate } else if (strcmp(attrs[i].ka_name, "inv") == 0) { 6767c478bd9Sstevel@tonic-gate if (attrs[i].ka_val != 0) 6777c478bd9Sstevel@tonic-gate evsel |= OPT_PES_INV; 6787c478bd9Sstevel@tonic-gate } else if (strcmp(attrs[i].ka_name, "cmask") == 0) { 6797c478bd9Sstevel@tonic-gate if ((attrs[i].ka_val | OPT_PES_CMASK_MASK) != 6807c478bd9Sstevel@tonic-gate OPT_PES_CMASK_MASK) 6817c478bd9Sstevel@tonic-gate return (CPC_ATTRIBUTE_OUT_OF_RANGE); 6827c478bd9Sstevel@tonic-gate evsel |= attrs[i].ka_val << OPT_PES_CMASK_SHIFT; 6837c478bd9Sstevel@tonic-gate } else if (strcmp(attrs[i].ka_name, "umask") == 0) { 6847c478bd9Sstevel@tonic-gate if ((attrs[i].ka_val | evp->umask_valid) != 6857c478bd9Sstevel@tonic-gate evp->umask_valid) 6867c478bd9Sstevel@tonic-gate return (CPC_ATTRIBUTE_OUT_OF_RANGE); 6877c478bd9Sstevel@tonic-gate evsel |= attrs[i].ka_val << OPT_PES_UMASK_SHIFT; 6887c478bd9Sstevel@tonic-gate } else 6897c478bd9Sstevel@tonic-gate return (CPC_INVALID_ATTRIBUTE); 6907c478bd9Sstevel@tonic-gate } 6917c478bd9Sstevel@tonic-gate 6927c478bd9Sstevel@tonic-gate cfg = kmem_alloc(sizeof (*cfg), KM_SLEEP); 6937c478bd9Sstevel@tonic-gate 6947c478bd9Sstevel@tonic-gate cfg->opt_picno = picnum; 6957c478bd9Sstevel@tonic-gate cfg->opt_evsel = evsel; 6967c478bd9Sstevel@tonic-gate cfg->opt_rawpic = preset & MASK48; 6977c478bd9Sstevel@tonic-gate 6987c478bd9Sstevel@tonic-gate *data = cfg; 6997c478bd9Sstevel@tonic-gate return (0); 7007c478bd9Sstevel@tonic-gate } 7017c478bd9Sstevel@tonic-gate 7027c478bd9Sstevel@tonic-gate static void 7037c478bd9Sstevel@tonic-gate opt_pcbe_program(void *token) 7047c478bd9Sstevel@tonic-gate { 7057c478bd9Sstevel@tonic-gate opt_pcbe_config_t *cfgs[4] = { &nullcfgs[0], &nullcfgs[1], 7067c478bd9Sstevel@tonic-gate &nullcfgs[2], &nullcfgs[3] }; 7077c478bd9Sstevel@tonic-gate opt_pcbe_config_t *pcfg = NULL; 7087c478bd9Sstevel@tonic-gate int i; 709843e1988Sjohnlev ulong_t curcr4 = getcr4(); 7107c478bd9Sstevel@tonic-gate 7117c478bd9Sstevel@tonic-gate /* 7127c478bd9Sstevel@tonic-gate * Allow nonprivileged code to read the performance counters if desired. 7137c478bd9Sstevel@tonic-gate */ 7147c478bd9Sstevel@tonic-gate if (kcpc_allow_nonpriv(token)) 7157c478bd9Sstevel@tonic-gate setcr4(curcr4 | CR4_PCE); 7167c478bd9Sstevel@tonic-gate else 7177c478bd9Sstevel@tonic-gate setcr4(curcr4 & ~CR4_PCE); 7187c478bd9Sstevel@tonic-gate 7197c478bd9Sstevel@tonic-gate /* 7207c478bd9Sstevel@tonic-gate * Query kernel for all configs which will be co-programmed. 7217c478bd9Sstevel@tonic-gate */ 7227c478bd9Sstevel@tonic-gate do { 7237c478bd9Sstevel@tonic-gate pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, NULL); 7247c478bd9Sstevel@tonic-gate 7257c478bd9Sstevel@tonic-gate if (pcfg != NULL) { 7267c478bd9Sstevel@tonic-gate ASSERT(pcfg->opt_picno < 4); 7277c478bd9Sstevel@tonic-gate cfgs[pcfg->opt_picno] = pcfg; 7287c478bd9Sstevel@tonic-gate } 7297c478bd9Sstevel@tonic-gate } while (pcfg != NULL); 7307c478bd9Sstevel@tonic-gate 7317c478bd9Sstevel@tonic-gate /* 7327c478bd9Sstevel@tonic-gate * Program in two loops. The first configures and presets the counter, 7337c478bd9Sstevel@tonic-gate * and the second loop enables the counters. This ensures that the 7347c478bd9Sstevel@tonic-gate * counters are all enabled as closely together in time as possible. 7357c478bd9Sstevel@tonic-gate */ 7367c478bd9Sstevel@tonic-gate 7377c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) { 7380ac7d7d8Skucharsk wrmsr(PES_BASE_ADDR + i, cfgs[i]->opt_evsel); 7390ac7d7d8Skucharsk wrmsr(PIC_BASE_ADDR + i, cfgs[i]->opt_rawpic); 7407c478bd9Sstevel@tonic-gate } 7417c478bd9Sstevel@tonic-gate 7427c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) { 7430ac7d7d8Skucharsk wrmsr(PES_BASE_ADDR + i, cfgs[i]->opt_evsel | 7440ac7d7d8Skucharsk (uint64_t)(uintptr_t)OPT_PES_ENABLE); 7457c478bd9Sstevel@tonic-gate } 7467c478bd9Sstevel@tonic-gate } 7477c478bd9Sstevel@tonic-gate 7487c478bd9Sstevel@tonic-gate static void 7497c478bd9Sstevel@tonic-gate opt_pcbe_allstop(void) 7507c478bd9Sstevel@tonic-gate { 7517c478bd9Sstevel@tonic-gate int i; 7527c478bd9Sstevel@tonic-gate 7537c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) 7540ac7d7d8Skucharsk wrmsr(PES_BASE_ADDR + i, 0ULL); 7557c478bd9Sstevel@tonic-gate 7567c478bd9Sstevel@tonic-gate /* 7577c478bd9Sstevel@tonic-gate * Disable non-privileged access to the counter registers. 7587c478bd9Sstevel@tonic-gate */ 759843e1988Sjohnlev setcr4(getcr4() & ~CR4_PCE); 7607c478bd9Sstevel@tonic-gate } 7617c478bd9Sstevel@tonic-gate 7627c478bd9Sstevel@tonic-gate static void 7637c478bd9Sstevel@tonic-gate opt_pcbe_sample(void *token) 7647c478bd9Sstevel@tonic-gate { 7657c478bd9Sstevel@tonic-gate opt_pcbe_config_t *cfgs[4] = { NULL, NULL, NULL, NULL }; 7667c478bd9Sstevel@tonic-gate opt_pcbe_config_t *pcfg = NULL; 7677c478bd9Sstevel@tonic-gate int i; 7687c478bd9Sstevel@tonic-gate uint64_t curpic[4]; 7697c478bd9Sstevel@tonic-gate uint64_t *addrs[4]; 7707c478bd9Sstevel@tonic-gate uint64_t *tmp; 7717c478bd9Sstevel@tonic-gate int64_t diff; 7727c478bd9Sstevel@tonic-gate 7737c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) 77493d449f8Skucharsk curpic[i] = rdmsr(PIC_BASE_ADDR + i); 7757c478bd9Sstevel@tonic-gate 7767c478bd9Sstevel@tonic-gate /* 7777c478bd9Sstevel@tonic-gate * Query kernel for all configs which are co-programmed. 7787c478bd9Sstevel@tonic-gate */ 7797c478bd9Sstevel@tonic-gate do { 7807c478bd9Sstevel@tonic-gate pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, &tmp); 7817c478bd9Sstevel@tonic-gate 7827c478bd9Sstevel@tonic-gate if (pcfg != NULL) { 7837c478bd9Sstevel@tonic-gate ASSERT(pcfg->opt_picno < 4); 7847c478bd9Sstevel@tonic-gate cfgs[pcfg->opt_picno] = pcfg; 7857c478bd9Sstevel@tonic-gate addrs[pcfg->opt_picno] = tmp; 7867c478bd9Sstevel@tonic-gate } 7877c478bd9Sstevel@tonic-gate } while (pcfg != NULL); 7887c478bd9Sstevel@tonic-gate 7897c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) { 7907c478bd9Sstevel@tonic-gate if (cfgs[i] == NULL) 7917c478bd9Sstevel@tonic-gate continue; 7927c478bd9Sstevel@tonic-gate 7937c478bd9Sstevel@tonic-gate diff = (curpic[i] - cfgs[i]->opt_rawpic) & MASK48; 7947c478bd9Sstevel@tonic-gate *addrs[i] += diff; 7957c478bd9Sstevel@tonic-gate DTRACE_PROBE4(opt__pcbe__sample, int, i, uint64_t, *addrs[i], 7967c478bd9Sstevel@tonic-gate uint64_t, curpic[i], uint64_t, cfgs[i]->opt_rawpic); 7977c478bd9Sstevel@tonic-gate cfgs[i]->opt_rawpic = *addrs[i] & MASK48; 7987c478bd9Sstevel@tonic-gate } 7997c478bd9Sstevel@tonic-gate } 8007c478bd9Sstevel@tonic-gate 8017c478bd9Sstevel@tonic-gate static void 8027c478bd9Sstevel@tonic-gate opt_pcbe_free(void *config) 8037c478bd9Sstevel@tonic-gate { 8047c478bd9Sstevel@tonic-gate kmem_free(config, sizeof (opt_pcbe_config_t)); 8057c478bd9Sstevel@tonic-gate } 8067c478bd9Sstevel@tonic-gate 8077c478bd9Sstevel@tonic-gate 8087c478bd9Sstevel@tonic-gate static struct modlpcbe modlpcbe = { 8097c478bd9Sstevel@tonic-gate &mod_pcbeops, 810820c9f58Skk "AMD Performance Counters", 8117c478bd9Sstevel@tonic-gate &opt_pcbe_ops 8127c478bd9Sstevel@tonic-gate }; 8137c478bd9Sstevel@tonic-gate 8147c478bd9Sstevel@tonic-gate static struct modlinkage modl = { 8157c478bd9Sstevel@tonic-gate MODREV_1, 8167c478bd9Sstevel@tonic-gate &modlpcbe, 8177c478bd9Sstevel@tonic-gate }; 8187c478bd9Sstevel@tonic-gate 8197c478bd9Sstevel@tonic-gate int 8207c478bd9Sstevel@tonic-gate _init(void) 8217c478bd9Sstevel@tonic-gate { 8227c478bd9Sstevel@tonic-gate int ret; 8237c478bd9Sstevel@tonic-gate 8247c478bd9Sstevel@tonic-gate if (opt_pcbe_init() != 0) 8257c478bd9Sstevel@tonic-gate return (ENOTSUP); 8267c478bd9Sstevel@tonic-gate 8277c478bd9Sstevel@tonic-gate if ((ret = mod_install(&modl)) != 0) 8287c478bd9Sstevel@tonic-gate kmem_free(evlist, evlist_sz + 1); 8297c478bd9Sstevel@tonic-gate 8307c478bd9Sstevel@tonic-gate return (ret); 8317c478bd9Sstevel@tonic-gate } 8327c478bd9Sstevel@tonic-gate 8337c478bd9Sstevel@tonic-gate int 8347c478bd9Sstevel@tonic-gate _fini(void) 8357c478bd9Sstevel@tonic-gate { 8367c478bd9Sstevel@tonic-gate int ret; 8377c478bd9Sstevel@tonic-gate 8387c478bd9Sstevel@tonic-gate if ((ret = mod_remove(&modl)) == 0) 8397c478bd9Sstevel@tonic-gate kmem_free(evlist, evlist_sz + 1); 8407c478bd9Sstevel@tonic-gate return (ret); 8417c478bd9Sstevel@tonic-gate } 8427c478bd9Sstevel@tonic-gate 8437c478bd9Sstevel@tonic-gate int 8447c478bd9Sstevel@tonic-gate _info(struct modinfo *mi) 8457c478bd9Sstevel@tonic-gate { 8467c478bd9Sstevel@tonic-gate return (mod_info(&modl, mi)); 8477c478bd9Sstevel@tonic-gate } 848