17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5346af85bScwb  * Common Development and Distribution License (the "License").
6346af85bScwb  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
22e850fb01SKuriakose Kuruvilla  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
237c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
247c478bd9Sstevel@tonic-gate  */
257c478bd9Sstevel@tonic-gate 
26c7a079a8SJonathan Haslam /*
27c7a079a8SJonathan Haslam  * This file contains preset event names from the Performance Application
28c7a079a8SJonathan Haslam  * Programming Interface v3.5 which included the following notice:
29c7a079a8SJonathan Haslam  *
30c7a079a8SJonathan Haslam  *                             Copyright (c) 2005,6
31c7a079a8SJonathan Haslam  *                           Innovative Computing Labs
32c7a079a8SJonathan Haslam  *                         Computer Science Department,
33c7a079a8SJonathan Haslam  *                            University of Tennessee,
34c7a079a8SJonathan Haslam  *                                 Knoxville, TN.
35c7a079a8SJonathan Haslam  *                              All Rights Reserved.
36c7a079a8SJonathan Haslam  *
37c7a079a8SJonathan Haslam  *
38c7a079a8SJonathan Haslam  * Redistribution and use in source and binary forms, with or without
39c7a079a8SJonathan Haslam  * modification, are permitted provided that the following conditions are met:
40c7a079a8SJonathan Haslam  *
41c7a079a8SJonathan Haslam  *    * Redistributions of source code must retain the above copyright notice,
42c7a079a8SJonathan Haslam  *      this list of conditions and the following disclaimer.
43c7a079a8SJonathan Haslam  *    * Redistributions in binary form must reproduce the above copyright
44c7a079a8SJonathan Haslam  *	notice, this list of conditions and the following disclaimer in the
45c7a079a8SJonathan Haslam  *	documentation and/or other materials provided with the distribution.
46c7a079a8SJonathan Haslam  *    * Neither the name of the University of Tennessee nor the names of its
47c7a079a8SJonathan Haslam  *      contributors may be used to endorse or promote products derived from
48c7a079a8SJonathan Haslam  *	this software without specific prior written permission.
49c7a079a8SJonathan Haslam  *
50c7a079a8SJonathan Haslam  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
51c7a079a8SJonathan Haslam  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52c7a079a8SJonathan Haslam  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53c7a079a8SJonathan Haslam  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
54c7a079a8SJonathan Haslam  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55c7a079a8SJonathan Haslam  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56c7a079a8SJonathan Haslam  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57c7a079a8SJonathan Haslam  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58c7a079a8SJonathan Haslam  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59c7a079a8SJonathan Haslam  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
60c7a079a8SJonathan Haslam  * POSSIBILITY OF SUCH DAMAGE.
61c7a079a8SJonathan Haslam  *
62c7a079a8SJonathan Haslam  *
63c7a079a8SJonathan Haslam  * This open source software license conforms to the BSD License template.
64c7a079a8SJonathan Haslam  */
657c478bd9Sstevel@tonic-gate 
66e850fb01SKuriakose Kuruvilla /*
67e850fb01SKuriakose Kuruvilla  * Portions Copyright 2009 Advanced Micro Devices, Inc.
68e850fb01SKuriakose Kuruvilla  */
69e850fb01SKuriakose Kuruvilla 
707c478bd9Sstevel@tonic-gate /*
717c478bd9Sstevel@tonic-gate  * Performance Counter Back-End for AMD Opteron and AMD Athlon 64 processors.
727c478bd9Sstevel@tonic-gate  */
737c478bd9Sstevel@tonic-gate 
747c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h>
757c478bd9Sstevel@tonic-gate #include <sys/param.h>
767c478bd9Sstevel@tonic-gate #include <sys/systm.h>
777c478bd9Sstevel@tonic-gate #include <sys/cpc_pcbe.h>
787c478bd9Sstevel@tonic-gate #include <sys/kmem.h>
797c478bd9Sstevel@tonic-gate #include <sys/sdt.h>
807c478bd9Sstevel@tonic-gate #include <sys/modctl.h>
817c478bd9Sstevel@tonic-gate #include <sys/errno.h>
827c478bd9Sstevel@tonic-gate #include <sys/debug.h>
837c478bd9Sstevel@tonic-gate #include <sys/archsystm.h>
847c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h>
857c478bd9Sstevel@tonic-gate #include <sys/privregs.h>
865d3a5ad8Srab #include <sys/ddi.h>
875d3a5ad8Srab #include <sys/sunddi.h>
887c478bd9Sstevel@tonic-gate 
897c478bd9Sstevel@tonic-gate static int opt_pcbe_init(void);
907c478bd9Sstevel@tonic-gate static uint_t opt_pcbe_ncounters(void);
917c478bd9Sstevel@tonic-gate static const char *opt_pcbe_impl_name(void);
927c478bd9Sstevel@tonic-gate static const char *opt_pcbe_cpuref(void);
937c478bd9Sstevel@tonic-gate static char *opt_pcbe_list_events(uint_t picnum);
947c478bd9Sstevel@tonic-gate static char *opt_pcbe_list_attrs(void);
957c478bd9Sstevel@tonic-gate static uint64_t opt_pcbe_event_coverage(char *event);
967c478bd9Sstevel@tonic-gate static uint64_t opt_pcbe_overflow_bitmap(void);
977c478bd9Sstevel@tonic-gate static int opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset,
987c478bd9Sstevel@tonic-gate     uint32_t flags, uint_t nattrs, kcpc_attr_t *attrs, void **data,
997c478bd9Sstevel@tonic-gate     void *token);
1007c478bd9Sstevel@tonic-gate static void opt_pcbe_program(void *token);
1017c478bd9Sstevel@tonic-gate static void opt_pcbe_allstop(void);
1027c478bd9Sstevel@tonic-gate static void opt_pcbe_sample(void *token);
1037c478bd9Sstevel@tonic-gate static void opt_pcbe_free(void *config);
1047c478bd9Sstevel@tonic-gate 
1057c478bd9Sstevel@tonic-gate static pcbe_ops_t opt_pcbe_ops = {
1067c478bd9Sstevel@tonic-gate 	PCBE_VER_1,
1077c478bd9Sstevel@tonic-gate 	CPC_CAP_OVERFLOW_INTERRUPT,
1087c478bd9Sstevel@tonic-gate 	opt_pcbe_ncounters,
1097c478bd9Sstevel@tonic-gate 	opt_pcbe_impl_name,
1107c478bd9Sstevel@tonic-gate 	opt_pcbe_cpuref,
1117c478bd9Sstevel@tonic-gate 	opt_pcbe_list_events,
1127c478bd9Sstevel@tonic-gate 	opt_pcbe_list_attrs,
1137c478bd9Sstevel@tonic-gate 	opt_pcbe_event_coverage,
1147c478bd9Sstevel@tonic-gate 	opt_pcbe_overflow_bitmap,
1157c478bd9Sstevel@tonic-gate 	opt_pcbe_configure,
1167c478bd9Sstevel@tonic-gate 	opt_pcbe_program,
1177c478bd9Sstevel@tonic-gate 	opt_pcbe_allstop,
1187c478bd9Sstevel@tonic-gate 	opt_pcbe_sample,
1197c478bd9Sstevel@tonic-gate 	opt_pcbe_free
1207c478bd9Sstevel@tonic-gate };
1217c478bd9Sstevel@tonic-gate 
1227c478bd9Sstevel@tonic-gate /*
1237c478bd9Sstevel@tonic-gate  * Define offsets and masks for the fields in the Performance
1247c478bd9Sstevel@tonic-gate  * Event-Select (PES) registers.
1257c478bd9Sstevel@tonic-gate  */
12631725658Sksadhukh #define	OPT_PES_HOST_SHIFT	41
12731725658Sksadhukh #define	OPT_PES_GUEST_SHIFT	40
1287c478bd9Sstevel@tonic-gate #define	OPT_PES_CMASK_SHIFT	24
1297c478bd9Sstevel@tonic-gate #define	OPT_PES_CMASK_MASK	0xFF
1307c478bd9Sstevel@tonic-gate #define	OPT_PES_INV_SHIFT	23
1317c478bd9Sstevel@tonic-gate #define	OPT_PES_ENABLE_SHIFT	22
1327c478bd9Sstevel@tonic-gate #define	OPT_PES_INT_SHIFT	20
1337c478bd9Sstevel@tonic-gate #define	OPT_PES_PC_SHIFT	19
1347c478bd9Sstevel@tonic-gate #define	OPT_PES_EDGE_SHIFT	18
1357c478bd9Sstevel@tonic-gate #define	OPT_PES_OS_SHIFT	17
1367c478bd9Sstevel@tonic-gate #define	OPT_PES_USR_SHIFT	16
1377c478bd9Sstevel@tonic-gate #define	OPT_PES_UMASK_SHIFT	8
1387c478bd9Sstevel@tonic-gate #define	OPT_PES_UMASK_MASK	0xFF
1397c478bd9Sstevel@tonic-gate 
14031725658Sksadhukh #define	OPT_PES_INV		(1ULL << OPT_PES_INV_SHIFT)
14131725658Sksadhukh #define	OPT_PES_ENABLE		(1ULL << OPT_PES_ENABLE_SHIFT)
14231725658Sksadhukh #define	OPT_PES_INT		(1ULL << OPT_PES_INT_SHIFT)
14331725658Sksadhukh #define	OPT_PES_PC		(1ULL << OPT_PES_PC_SHIFT)
14431725658Sksadhukh #define	OPT_PES_EDGE		(1ULL << OPT_PES_EDGE_SHIFT)
14531725658Sksadhukh #define	OPT_PES_OS		(1ULL << OPT_PES_OS_SHIFT)
14631725658Sksadhukh #define	OPT_PES_USR		(1ULL << OPT_PES_USR_SHIFT)
14731725658Sksadhukh #define	OPT_PES_HOST		(1ULL << OPT_PES_HOST_SHIFT)
14831725658Sksadhukh #define	OPT_PES_GUEST		(1ULL << OPT_PES_GUEST_SHIFT)
1497c478bd9Sstevel@tonic-gate 
1507c478bd9Sstevel@tonic-gate typedef struct _opt_pcbe_config {
1517c478bd9Sstevel@tonic-gate 	uint8_t		opt_picno;	/* Counter number: 0, 1, 2, or 3 */
1527c478bd9Sstevel@tonic-gate 	uint64_t	opt_evsel;	/* Event Selection register */
1537c478bd9Sstevel@tonic-gate 	uint64_t	opt_rawpic;	/* Raw counter value */
1547c478bd9Sstevel@tonic-gate } opt_pcbe_config_t;
1557c478bd9Sstevel@tonic-gate 
1567c478bd9Sstevel@tonic-gate opt_pcbe_config_t nullcfgs[4] = {
1577c478bd9Sstevel@tonic-gate 	{ 0, 0, 0 },
1587c478bd9Sstevel@tonic-gate 	{ 1, 0, 0 },
1597c478bd9Sstevel@tonic-gate 	{ 2, 0, 0 },
1607c478bd9Sstevel@tonic-gate 	{ 3, 0, 0 }
1617c478bd9Sstevel@tonic-gate };
1627c478bd9Sstevel@tonic-gate 
16331725658Sksadhukh typedef struct _amd_event {
1647c478bd9Sstevel@tonic-gate 	char		*name;
16531725658Sksadhukh 	uint16_t	emask;		/* Event mask setting */
16631725658Sksadhukh } amd_event_t;
1677c478bd9Sstevel@tonic-gate 
168c7a079a8SJonathan Haslam typedef struct _amd_generic_event {
169c7a079a8SJonathan Haslam 	char *name;
170c7a079a8SJonathan Haslam 	char *event;
171c7a079a8SJonathan Haslam 	uint8_t umask;
172c7a079a8SJonathan Haslam } amd_generic_event_t;
173c7a079a8SJonathan Haslam 
1747c478bd9Sstevel@tonic-gate /*
1757c478bd9Sstevel@tonic-gate  * Base MSR addresses for the PerfEvtSel registers and the counters themselves.
1767c478bd9Sstevel@tonic-gate  * Add counter number to base address to get corresponding MSR address.
1777c478bd9Sstevel@tonic-gate  */
1787c478bd9Sstevel@tonic-gate #define	PES_BASE_ADDR	0xC0010000
1797c478bd9Sstevel@tonic-gate #define	PIC_BASE_ADDR	0xC0010004
1807c478bd9Sstevel@tonic-gate 
1817c478bd9Sstevel@tonic-gate #define	MASK48		0xFFFFFFFFFFFF
1827c478bd9Sstevel@tonic-gate 
183e850fb01SKuriakose Kuruvilla #define	EV_END {NULL, 0}
184c7a079a8SJonathan Haslam #define	GEN_EV_END {NULL, NULL, 0 }
1857c478bd9Sstevel@tonic-gate 
186e850fb01SKuriakose Kuruvilla #define	AMD_cmn_events						\
187e850fb01SKuriakose Kuruvilla 	{ "FP_dispatched_fpu_ops",			0x0 },	\
188e850fb01SKuriakose Kuruvilla 	{ "FP_cycles_no_fpu_ops_retired",		0x1 },	\
189e850fb01SKuriakose Kuruvilla 	{ "FP_dispatched_fpu_ops_ff",			0x2 },	\
190e850fb01SKuriakose Kuruvilla 	{ "LS_seg_reg_load",				0x20 },	\
191e850fb01SKuriakose Kuruvilla 	{ "LS_uarch_resync_self_modify",		0x21 },	\
192e850fb01SKuriakose Kuruvilla 	{ "LS_uarch_resync_snoop",			0x22 },	\
193e850fb01SKuriakose Kuruvilla 	{ "LS_buffer_2_full",				0x23 },	\
194e850fb01SKuriakose Kuruvilla 	{ "LS_locked_operation",			0x24 },	\
195e850fb01SKuriakose Kuruvilla 	{ "LS_retired_cflush",				0x26 },	\
196e850fb01SKuriakose Kuruvilla 	{ "LS_retired_cpuid",				0x27 },	\
197e850fb01SKuriakose Kuruvilla 	{ "DC_access",					0x40 },	\
198e850fb01SKuriakose Kuruvilla 	{ "DC_miss",					0x41 },	\
199e850fb01SKuriakose Kuruvilla 	{ "DC_refill_from_L2",				0x42 },	\
200e850fb01SKuriakose Kuruvilla 	{ "DC_refill_from_system",			0x43 },	\
201e850fb01SKuriakose Kuruvilla 	{ "DC_copyback",				0x44 },	\
202e850fb01SKuriakose Kuruvilla 	{ "DC_dtlb_L1_miss_L2_hit",			0x45 },	\
203e850fb01SKuriakose Kuruvilla 	{ "DC_dtlb_L1_miss_L2_miss",			0x46 },	\
204e850fb01SKuriakose Kuruvilla 	{ "DC_misaligned_data_ref",			0x47 },	\
205e850fb01SKuriakose Kuruvilla 	{ "DC_uarch_late_cancel_access",		0x48 },	\
206e850fb01SKuriakose Kuruvilla 	{ "DC_uarch_early_cancel_access",		0x49 },	\
207e850fb01SKuriakose Kuruvilla 	{ "DC_1bit_ecc_error_found",			0x4A },	\
208e850fb01SKuriakose Kuruvilla 	{ "DC_dispatched_prefetch_instr",		0x4B },	\
209e850fb01SKuriakose Kuruvilla 	{ "DC_dcache_accesses_by_locks",		0x4C },	\
210e850fb01SKuriakose Kuruvilla 	{ "BU_memory_requests",				0x65 },	\
211e850fb01SKuriakose Kuruvilla 	{ "BU_data_prefetch",				0x67 },	\
212e850fb01SKuriakose Kuruvilla 	{ "BU_system_read_responses",			0x6C },	\
213e850fb01SKuriakose Kuruvilla 	{ "BU_cpu_clk_unhalted",			0x76 },	\
214e850fb01SKuriakose Kuruvilla 	{ "BU_internal_L2_req",				0x7D },	\
215e850fb01SKuriakose Kuruvilla 	{ "BU_fill_req_missed_L2",			0x7E },	\
216e850fb01SKuriakose Kuruvilla 	{ "BU_fill_into_L2",				0x7F },	\
217e850fb01SKuriakose Kuruvilla 	{ "IC_fetch",					0x80 },	\
218e850fb01SKuriakose Kuruvilla 	{ "IC_miss",					0x81 },	\
219e850fb01SKuriakose Kuruvilla 	{ "IC_refill_from_L2",				0x82 },	\
220e850fb01SKuriakose Kuruvilla 	{ "IC_refill_from_system",			0x83 },	\
221e850fb01SKuriakose Kuruvilla 	{ "IC_itlb_L1_miss_L2_hit",			0x84 },	\
222e850fb01SKuriakose Kuruvilla 	{ "IC_itlb_L1_miss_L2_miss",			0x85 },	\
223e850fb01SKuriakose Kuruvilla 	{ "IC_uarch_resync_snoop",			0x86 },	\
224e850fb01SKuriakose Kuruvilla 	{ "IC_instr_fetch_stall",			0x87 },	\
225e850fb01SKuriakose Kuruvilla 	{ "IC_return_stack_hit",			0x88 },	\
226e850fb01SKuriakose Kuruvilla 	{ "IC_return_stack_overflow",			0x89 },	\
227e850fb01SKuriakose Kuruvilla 	{ "FR_retired_x86_instr_w_excp_intr",		0xC0 },	\
228e850fb01SKuriakose Kuruvilla 	{ "FR_retired_uops",				0xC1 },	\
229e850fb01SKuriakose Kuruvilla 	{ "FR_retired_branches_w_excp_intr",		0xC2 },	\
230e850fb01SKuriakose Kuruvilla 	{ "FR_retired_branches_mispred",		0xC3 },	\
231e850fb01SKuriakose Kuruvilla 	{ "FR_retired_taken_branches",			0xC4 },	\
232e850fb01SKuriakose Kuruvilla 	{ "FR_retired_taken_branches_mispred",		0xC5 },	\
233e850fb01SKuriakose Kuruvilla 	{ "FR_retired_far_ctl_transfer",		0xC6 },	\
234e850fb01SKuriakose Kuruvilla 	{ "FR_retired_resyncs",				0xC7 },	\
235e850fb01SKuriakose Kuruvilla 	{ "FR_retired_near_rets",			0xC8 },	\
236e850fb01SKuriakose Kuruvilla 	{ "FR_retired_near_rets_mispred",		0xC9 },	\
237e850fb01SKuriakose Kuruvilla 	{ "FR_retired_taken_branches_mispred_addr_miscomp",	0xCA },\
238e850fb01SKuriakose Kuruvilla 	{ "FR_retired_fastpath_double_op_instr",	0xCC },	\
239e850fb01SKuriakose Kuruvilla 	{ "FR_intr_masked_cycles",			0xCD },	\
240e850fb01SKuriakose Kuruvilla 	{ "FR_intr_masked_while_pending_cycles",	0xCE },	\
241e850fb01SKuriakose Kuruvilla 	{ "FR_taken_hardware_intrs",			0xCF },	\
242e850fb01SKuriakose Kuruvilla 	{ "FR_nothing_to_dispatch",			0xD0 },	\
243e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stalls",				0xD1 },	\
244e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_branch_abort_to_retire",	0xD2 },	\
245e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_serialization",		0xD3 },	\
246e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_segment_load",		0xD4 },	\
247e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_reorder_buffer_full",	0xD5 },	\
248e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_resv_stations_full",	0xD6 },	\
249e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_fpu_full",			0xD7 },	\
250e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_ls_full",			0xD8 },	\
251e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_waiting_all_quiet",	0xD9 },	\
252e850fb01SKuriakose Kuruvilla 	{ "FR_dispatch_stall_far_ctl_trsfr_resync_branch_pend",	0xDA },\
253e850fb01SKuriakose Kuruvilla 	{ "FR_fpu_exception",				0xDB },	\
254e850fb01SKuriakose Kuruvilla 	{ "FR_num_brkpts_dr0",				0xDC },	\
255e850fb01SKuriakose Kuruvilla 	{ "FR_num_brkpts_dr1",				0xDD },	\
256e850fb01SKuriakose Kuruvilla 	{ "FR_num_brkpts_dr2",				0xDE },	\
257e850fb01SKuriakose Kuruvilla 	{ "FR_num_brkpts_dr3",				0xDF },	\
258e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_page_access",			0xE0 },	\
259e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_turnaround",			0xE3 },	\
260e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_bypass_counter_saturation",	0xE4 },	\
261e850fb01SKuriakose Kuruvilla 	{ "NB_cpu_io_to_mem_io",			0xE9 },	\
262e850fb01SKuriakose Kuruvilla 	{ "NB_cache_block_commands",			0xEA },	\
263e850fb01SKuriakose Kuruvilla 	{ "NB_sized_commands",				0xEB },	\
264e850fb01SKuriakose Kuruvilla 	{ "NB_ht_bus0_bandwidth",			0xF6 }
265e850fb01SKuriakose Kuruvilla 
266e850fb01SKuriakose Kuruvilla #define	AMD_FAMILY_f_events					\
267e850fb01SKuriakose Kuruvilla 	{ "BU_quadwords_written_to_system",		0x6D },	\
268e850fb01SKuriakose Kuruvilla 	{ "FR_retired_fpu_instr",			0xCB },	\
269e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_page_table_overflow",		0xE1 },	\
270e850fb01SKuriakose Kuruvilla 	{ "NB_sized_blocks",				0xE5 },	\
271e850fb01SKuriakose Kuruvilla 	{ "NB_ECC_errors",				0xE8 },	\
272e850fb01SKuriakose Kuruvilla 	{ "NB_probe_result",				0xEC },	\
273e850fb01SKuriakose Kuruvilla 	{ "NB_gart_events",				0xEE },	\
274e850fb01SKuriakose Kuruvilla 	{ "NB_ht_bus1_bandwidth",			0xF7 },	\
275e850fb01SKuriakose Kuruvilla 	{ "NB_ht_bus2_bandwidth",			0xF8 }
276e850fb01SKuriakose Kuruvilla 
277e850fb01SKuriakose Kuruvilla #define	AMD_FAMILY_10h_events					\
278e850fb01SKuriakose Kuruvilla 	{ "FP_retired_sse_ops",				0x3 },	\
279e850fb01SKuriakose Kuruvilla 	{ "FP_retired_move_ops",			0x4 },	\
280e850fb01SKuriakose Kuruvilla 	{ "FP_retired_serialize_ops",			0x5 },	\
281e850fb01SKuriakose Kuruvilla 	{ "FP_serialize_ops_cycles",			0x6 },	\
282e850fb01SKuriakose Kuruvilla 	{ "LS_cancelled_store_to_load_fwd_ops",		0x2A },	\
283e850fb01SKuriakose Kuruvilla 	{ "LS_smi_received",				0x2B },	\
284e850fb01SKuriakose Kuruvilla 	{ "DC_dtlb_L1_hit",				0x4D },	\
285e850fb01SKuriakose Kuruvilla 	{ "LS_ineffective_prefetch",			0x52 },	\
286e850fb01SKuriakose Kuruvilla 	{ "LS_global_tlb_flush",			0x54 },	\
287e850fb01SKuriakose Kuruvilla 	{ "BU_octwords_written_to_system",		0x6D },	\
288e850fb01SKuriakose Kuruvilla 	{ "Page_size_mismatches",			0x165 },	\
289e850fb01SKuriakose Kuruvilla 	{ "IC_eviction",				0x8B },	\
290e850fb01SKuriakose Kuruvilla 	{ "IC_cache_lines_invalidate",			0x8C },	\
291e850fb01SKuriakose Kuruvilla 	{ "IC_itlb_reload",				0x99 },	\
292e850fb01SKuriakose Kuruvilla 	{ "IC_itlb_reload_aborted",			0x9A },	\
293e850fb01SKuriakose Kuruvilla 	{ "FR_retired_mmx_sse_fp_instr",		0xCB },	\
294e850fb01SKuriakose Kuruvilla 	{ "Retired_x87_fp_ops",				0x1C0 },	\
295e850fb01SKuriakose Kuruvilla 	{ "IBS_ops_tagged",				0x1CF },	\
296e850fb01SKuriakose Kuruvilla 	{ "LFENCE_inst_retired",			0x1D3 },	\
297e850fb01SKuriakose Kuruvilla 	{ "SFENCE_inst_retired",			0x1D4 },	\
298e850fb01SKuriakose Kuruvilla 	{ "MFENCE_inst_retired",			0x1D5 },	\
299e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_page_table_overflow",		0xE1 },	\
300e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_dram_cmd_slots_missed",		0xE2 },	\
301e850fb01SKuriakose Kuruvilla 	{ "NB_thermal_status",				0xE8 },	\
302e850fb01SKuriakose Kuruvilla 	{ "NB_probe_results_upstream_req",		0xEC },	\
303e850fb01SKuriakose Kuruvilla 	{ "NB_gart_events",				0xEE },	\
304e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_req",				0x1F0 },	\
305e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_to_dram_req_to_target",		0x1E0 },	\
306e850fb01SKuriakose Kuruvilla 	{ "CB_io_to_dram_req_to_target",		0x1E1 },	\
307e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_read_cmd_latency_to_target_0_to_3",	0x1E2 },	\
308e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_read_cmd_req_to_target_0_to_3",	0x1E3 },	\
309e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_read_cmd_latency_to_target_4_to_7",	0x1E4 },	\
310e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_read_cmd_req_to_target_4_to_7",	0x1E5 },	\
311e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_cmd_latency_to_target_0_to_7",	0x1E6 },	\
312e850fb01SKuriakose Kuruvilla 	{ "CB_cpu_req_to_target_0_to_7",		0x1E7 },	\
313e850fb01SKuriakose Kuruvilla 	{ "NB_ht_bus1_bandwidth",			0xF7 },	\
314e850fb01SKuriakose Kuruvilla 	{ "NB_ht_bus2_bandwidth",			0xF8 },	\
315e850fb01SKuriakose Kuruvilla 	{ "NB_ht_bus3_bandwidth",			0x1F9 },	\
316e850fb01SKuriakose Kuruvilla 	{ "L3_read_req",				0x4E0 },	\
317e850fb01SKuriakose Kuruvilla 	{ "L3_miss",					0x4E1 },	\
318e850fb01SKuriakose Kuruvilla 	{ "L3_l2_eviction_l3_fill",			0x4E2 },	\
319e850fb01SKuriakose Kuruvilla 	{ "L3_eviction",				0x4E3 }
320e850fb01SKuriakose Kuruvilla 
321e850fb01SKuriakose Kuruvilla #define	AMD_FAMILY_11h_events					\
322e850fb01SKuriakose Kuruvilla 	{ "BU_quadwords_written_to_system",		0x6D },	\
323e850fb01SKuriakose Kuruvilla 	{ "FR_retired_mmx_fp_instr",			0xCB },	\
324e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_page_table_events",		0xE1 },	\
325e850fb01SKuriakose Kuruvilla 	{ "NB_thermal_status",				0xE8 },	\
326e850fb01SKuriakose Kuruvilla 	{ "NB_probe_results_upstream_req",		0xEC },	\
327e850fb01SKuriakose Kuruvilla 	{ "NB_dev_events",				0xEE },	\
328e850fb01SKuriakose Kuruvilla 	{ "NB_mem_ctrlr_req",				0x1F0 }
32931725658Sksadhukh 
330c7a079a8SJonathan Haslam #define	AMD_cmn_generic_events						\
331c7a079a8SJonathan Haslam 	{ "PAPI_br_ins",	"FR_retired_branches_w_excp_intr", 0x0 },\
332c7a079a8SJonathan Haslam 	{ "PAPI_br_msp",	"FR_retired_branches_mispred",	0x0 },	\
333c7a079a8SJonathan Haslam 	{ "PAPI_br_tkn",	"FR_retired_taken_branches",	0x0 },	\
334c7a079a8SJonathan Haslam 	{ "PAPI_fp_ops",	"FP_dispatched_fpu_ops",	0x3 },	\
335c7a079a8SJonathan Haslam 	{ "PAPI_fad_ins",	"FP_dispatched_fpu_ops",	0x1 },	\
336c7a079a8SJonathan Haslam 	{ "PAPI_fml_ins",	"FP_dispatched_fpu_ops",	0x2 },	\
337c7a079a8SJonathan Haslam 	{ "PAPI_fpu_idl",	"FP_cycles_no_fpu_ops_retired",	0x0 },	\
338c7a079a8SJonathan Haslam 	{ "PAPI_tot_cyc",	"BU_cpu_clk_unhalted",		0x0 },	\
339c7a079a8SJonathan Haslam 	{ "PAPI_tot_ins",	"FR_retired_x86_instr_w_excp_intr", 0x0 }, \
340c7a079a8SJonathan Haslam 	{ "PAPI_l1_dca",	"DC_access",			0x0 },	\
341c7a079a8SJonathan Haslam 	{ "PAPI_l1_dcm",	"DC_miss",			0x0 },	\
342c7a079a8SJonathan Haslam 	{ "PAPI_l1_ldm",	"DC_refill_from_L2",		0xe },	\
343c7a079a8SJonathan Haslam 	{ "PAPI_l1_stm",	"DC_refill_from_L2",		0x10 },	\
344c7a079a8SJonathan Haslam 	{ "PAPI_l1_ica",	"IC_fetch",			0x0 },	\
345c7a079a8SJonathan Haslam 	{ "PAPI_l1_icm",	"IC_miss",			0x0 },	\
346c7a079a8SJonathan Haslam 	{ "PAPI_l1_icr",	"IC_fetch",			0x0 },	\
347c7a079a8SJonathan Haslam 	{ "PAPI_l2_dch",	"DC_refill_from_L2",		0x1e },	\
348c7a079a8SJonathan Haslam 	{ "PAPI_l2_dcm",	"DC_refill_from_system",	0x1e },	\
349c7a079a8SJonathan Haslam 	{ "PAPI_l2_dcr",	"DC_refill_from_L2",		0xe },	\
350c7a079a8SJonathan Haslam 	{ "PAPI_l2_dcw",	"DC_refill_from_L2",		0x10 },	\
351c7a079a8SJonathan Haslam 	{ "PAPI_l2_ich",	"IC_refill_from_L2",		0x0 },	\
352c7a079a8SJonathan Haslam 	{ "PAPI_l2_icm",	"IC_refill_from_system",	0x0 },	\
353c7a079a8SJonathan Haslam 	{ "PAPI_l2_ldm",	"DC_refill_from_system",	0xe },	\
354c7a079a8SJonathan Haslam 	{ "PAPI_l2_stm",	"DC_refill_from_system",	0x10 },	\
355c7a079a8SJonathan Haslam 	{ "PAPI_res_stl",	"FR_dispatch_stalls",		0x0 },	\
356c7a079a8SJonathan Haslam 	{ "PAPI_stl_icy",	"FR_nothing_to_dispatch",	0x0 },	\
357c7a079a8SJonathan Haslam 	{ "PAPI_hw_int",	"FR_taken_hardware_intrs",	0x0 }
358c7a079a8SJonathan Haslam 
359c7a079a8SJonathan Haslam #define	OPT_cmn_generic_events						\
360c7a079a8SJonathan Haslam 	{ "PAPI_tlb_dm",	"DC_dtlb_L1_miss_L2_miss",	0x0 },	\
361c7a079a8SJonathan Haslam 	{ "PAPI_tlb_im",	"IC_itlb_L1_miss_L2_miss",	0x0 },	\
362c7a079a8SJonathan Haslam 	{ "PAPI_fp_ins",	"FR_retired_fpu_instr",		0xd },	\
363c7a079a8SJonathan Haslam 	{ "PAPI_vec_ins",	"FR_retired_fpu_instr",		0x4 }
364c7a079a8SJonathan Haslam 
365c7a079a8SJonathan Haslam #define	AMD_FAMILY_10h_generic_events					\
366c7a079a8SJonathan Haslam 	{ "PAPI_tlb_dm",	"DC_dtlb_L1_miss_L2_miss",	0x7 },	\
367c7a079a8SJonathan Haslam 	{ "PAPI_tlb_im",	"IC_itlb_L1_miss_L2_miss",	0x3 },	\
368c7a079a8SJonathan Haslam 	{ "PAPI_l3_dcr",	"L3_read_req",			0xf1 }, \
369c7a079a8SJonathan Haslam 	{ "PAPI_l3_icr",	"L3_read_req",			0xf2 }, \
370c7a079a8SJonathan Haslam 	{ "PAPI_l3_tcr",	"L3_read_req",			0xf7 }, \
371c7a079a8SJonathan Haslam 	{ "PAPI_l3_stm",	"L3_miss",			0xf4 }, \
372c7a079a8SJonathan Haslam 	{ "PAPI_l3_ldm",	"L3_miss",			0xf3 }, \
373c7a079a8SJonathan Haslam 	{ "PAPI_l3_tcm",	"L3_miss",			0xf7 }
374c7a079a8SJonathan Haslam 
375e850fb01SKuriakose Kuruvilla #define	AMD_PCBE_SUPPORTED(family) (((family) >= 0xf) && ((family) <= 0x11))
376fb47e43fSjhaslam 
377e850fb01SKuriakose Kuruvilla static amd_event_t family_f_events[] = {
37831725658Sksadhukh 	AMD_cmn_events,
379e850fb01SKuriakose Kuruvilla 	AMD_FAMILY_f_events,
380fb47e43fSjhaslam 	EV_END
381fb47e43fSjhaslam };
382fb47e43fSjhaslam 
383e850fb01SKuriakose Kuruvilla static amd_event_t family_10h_events[] = {
38431725658Sksadhukh 	AMD_cmn_events,
385e850fb01SKuriakose Kuruvilla 	AMD_FAMILY_10h_events,
3867c478bd9Sstevel@tonic-gate 	EV_END
3877c478bd9Sstevel@tonic-gate };
3887c478bd9Sstevel@tonic-gate 
389e850fb01SKuriakose Kuruvilla static amd_event_t family_11h_events[] = {
39031725658Sksadhukh 	AMD_cmn_events,
391e850fb01SKuriakose Kuruvilla 	AMD_FAMILY_11h_events,
39231725658Sksadhukh 	EV_END
39331725658Sksadhukh };
39431725658Sksadhukh 
395c7a079a8SJonathan Haslam static amd_generic_event_t opt_generic_events[] = {
396c7a079a8SJonathan Haslam 	AMD_cmn_generic_events,
397c7a079a8SJonathan Haslam 	OPT_cmn_generic_events,
398c7a079a8SJonathan Haslam 	GEN_EV_END
399c7a079a8SJonathan Haslam };
400c7a079a8SJonathan Haslam 
401c7a079a8SJonathan Haslam static amd_generic_event_t family_10h_generic_events[] = {
402c7a079a8SJonathan Haslam 	AMD_cmn_generic_events,
403c7a079a8SJonathan Haslam 	AMD_FAMILY_10h_generic_events,
404c7a079a8SJonathan Haslam 	GEN_EV_END
405c7a079a8SJonathan Haslam };
406c7a079a8SJonathan Haslam 
4077c478bd9Sstevel@tonic-gate static char	*evlist;
4087c478bd9Sstevel@tonic-gate static size_t	evlist_sz;
40931725658Sksadhukh static amd_event_t *amd_events = NULL;
41031725658Sksadhukh static uint_t amd_family;
411c7a079a8SJonathan Haslam static amd_generic_event_t *amd_generic_events = NULL;
4127c478bd9Sstevel@tonic-gate 
413e850fb01SKuriakose Kuruvilla #define	AMD_CPUREF_SIZE	256
414e850fb01SKuriakose Kuruvilla static char amd_generic_bkdg[AMD_CPUREF_SIZE];
415e850fb01SKuriakose Kuruvilla static char amd_fam_f_rev_ae_bkdg[] = "See \"BIOS and Kernel Developer's " \
416e850fb01SKuriakose Kuruvilla "Guide for AMD Athlon 64 and AMD Opteron Processors\" (AMD publication 26094)";
417e850fb01SKuriakose Kuruvilla static char amd_fam_f_NPT_bkdg[] = "See \"BIOS and Kernel Developer's Guide " \
418e850fb01SKuriakose Kuruvilla "for AMD NPT Family 0Fh Processors\" (AMD publication 32559)";
419e850fb01SKuriakose Kuruvilla static char amd_fam_10h_bkdg[] = "See \"BIOS and Kernel Developer's Guide " \
420e850fb01SKuriakose Kuruvilla "(BKDG) For AMD Family 10h Processors\" (AMD publication 31116)";
421e850fb01SKuriakose Kuruvilla static char amd_fam_11h_bkdg[] = "See \"BIOS and Kernel Developer's Guide " \
422e850fb01SKuriakose Kuruvilla "(BKDG) For AMD Family 11h Processors\" (AMD publication 41256)";
423e850fb01SKuriakose Kuruvilla 
424e850fb01SKuriakose Kuruvilla static char amd_pcbe_impl_name[64];
425e850fb01SKuriakose Kuruvilla static char *amd_pcbe_cpuref;
426e850fb01SKuriakose Kuruvilla 
427e850fb01SKuriakose Kuruvilla 
4287c478bd9Sstevel@tonic-gate #define	BITS(v, u, l)   \
4297c478bd9Sstevel@tonic-gate 	(((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1))
4307c478bd9Sstevel@tonic-gate 
4317c478bd9Sstevel@tonic-gate 
4327c478bd9Sstevel@tonic-gate static int
4337c478bd9Sstevel@tonic-gate opt_pcbe_init(void)
4347c478bd9Sstevel@tonic-gate {
43531725658Sksadhukh 	amd_event_t		*evp;
436c7a079a8SJonathan Haslam 	amd_generic_event_t	*gevp;
4377c478bd9Sstevel@tonic-gate 
43831725658Sksadhukh 	amd_family = cpuid_getfamily(CPU);
43931725658Sksadhukh 
4407c478bd9Sstevel@tonic-gate 	/*
4417c478bd9Sstevel@tonic-gate 	 * Make sure this really _is_ an Opteron or Athlon 64 system. The kernel
4427c478bd9Sstevel@tonic-gate 	 * loads this module based on its name in the module directory, but it
4437c478bd9Sstevel@tonic-gate 	 * could have been renamed.
4447c478bd9Sstevel@tonic-gate 	 */
445e850fb01SKuriakose Kuruvilla 	if (cpuid_getvendor(CPU) != X86_VENDOR_AMD || amd_family < 0xf)
4467c478bd9Sstevel@tonic-gate 		return (-1);
4477c478bd9Sstevel@tonic-gate 
448e850fb01SKuriakose Kuruvilla 	if (amd_family == 0xf)
449e850fb01SKuriakose Kuruvilla 		/* Some tools expect this string for family 0fh */
450*c1374a13SSurya Prakki 		(void) snprintf(amd_pcbe_impl_name, sizeof (amd_pcbe_impl_name),
451e850fb01SKuriakose Kuruvilla 		    "AMD Opteron & Athlon64");
452e850fb01SKuriakose Kuruvilla 	else
453*c1374a13SSurya Prakki 		(void) snprintf(amd_pcbe_impl_name, sizeof (amd_pcbe_impl_name),
454e850fb01SKuriakose Kuruvilla 		    "AMD Family %02xh%s", amd_family,
455e850fb01SKuriakose Kuruvilla 		    AMD_PCBE_SUPPORTED(amd_family) ? "" :" (unsupported)");
456e850fb01SKuriakose Kuruvilla 
457fb47e43fSjhaslam 	/*
458fb47e43fSjhaslam 	 * Figure out processor revision here and assign appropriate
459fb47e43fSjhaslam 	 * event configuration.
460fb47e43fSjhaslam 	 */
461fb47e43fSjhaslam 
462e850fb01SKuriakose Kuruvilla 	if (amd_family == 0xf) {
463e850fb01SKuriakose Kuruvilla 		uint32_t rev;
464e850fb01SKuriakose Kuruvilla 
465e850fb01SKuriakose Kuruvilla 		rev = cpuid_getchiprev(CPU);
466fb47e43fSjhaslam 
467e850fb01SKuriakose Kuruvilla 		if (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_F))
468e850fb01SKuriakose Kuruvilla 			amd_pcbe_cpuref = amd_fam_f_NPT_bkdg;
469e850fb01SKuriakose Kuruvilla 		else
470e850fb01SKuriakose Kuruvilla 			amd_pcbe_cpuref = amd_fam_f_rev_ae_bkdg;
471e850fb01SKuriakose Kuruvilla 		amd_events = family_f_events;
472c7a079a8SJonathan Haslam 		amd_generic_events = opt_generic_events;
473e850fb01SKuriakose Kuruvilla 	} else if (amd_family == 0x10) {
474e850fb01SKuriakose Kuruvilla 		amd_pcbe_cpuref = amd_fam_10h_bkdg;
47531725658Sksadhukh 		amd_events = family_10h_events;
476c7a079a8SJonathan Haslam 		amd_generic_events = family_10h_generic_events;
477e850fb01SKuriakose Kuruvilla 	} else if (amd_family == 0x11) {
478e850fb01SKuriakose Kuruvilla 		amd_pcbe_cpuref = amd_fam_11h_bkdg;
479e850fb01SKuriakose Kuruvilla 		amd_events = family_11h_events;
480e850fb01SKuriakose Kuruvilla 		amd_generic_events = opt_generic_events;
481e850fb01SKuriakose Kuruvilla 	} else {
482e850fb01SKuriakose Kuruvilla 
483e850fb01SKuriakose Kuruvilla 		amd_pcbe_cpuref = amd_generic_bkdg;
484*c1374a13SSurya Prakki 		(void) snprintf(amd_pcbe_cpuref, AMD_CPUREF_SIZE,
485e850fb01SKuriakose Kuruvilla 		    "See BIOS and Kernel Developer's Guide "    \
486e850fb01SKuriakose Kuruvilla 		    "(BKDG) For AMD Family %02xh Processors. "  \
487e850fb01SKuriakose Kuruvilla 		    "(Note that this pcbe does not explicitly " \
488e850fb01SKuriakose Kuruvilla 		    "support this family)", amd_family);
489e850fb01SKuriakose Kuruvilla 
490e850fb01SKuriakose Kuruvilla 		/*
491e850fb01SKuriakose Kuruvilla 		 * For families that are not explicitly supported we'll use
492e850fb01SKuriakose Kuruvilla 		 * events for family 0xf. Even if they are not quite right,
493e850fb01SKuriakose Kuruvilla 		 * it's OK --- we state that pcbe is unsupported.
494e850fb01SKuriakose Kuruvilla 		 */
495e850fb01SKuriakose Kuruvilla 		amd_events = family_f_events;
496e850fb01SKuriakose Kuruvilla 		amd_generic_events = opt_generic_events;
49731725658Sksadhukh 	}
498fb47e43fSjhaslam 
4997c478bd9Sstevel@tonic-gate 	/*
5007c478bd9Sstevel@tonic-gate 	 * Construct event list.
5017c478bd9Sstevel@tonic-gate 	 *
5027c478bd9Sstevel@tonic-gate 	 * First pass:  Calculate size needed. We'll need an additional byte
5037c478bd9Sstevel@tonic-gate 	 *		for the NULL pointer during the last strcat.
5047c478bd9Sstevel@tonic-gate 	 *
5057c478bd9Sstevel@tonic-gate 	 * Second pass: Copy strings.
5067c478bd9Sstevel@tonic-gate 	 */
50731725658Sksadhukh 	for (evp = amd_events; evp->name != NULL; evp++)
5087c478bd9Sstevel@tonic-gate 		evlist_sz += strlen(evp->name) + 1;
5097c478bd9Sstevel@tonic-gate 
510c7a079a8SJonathan Haslam 	for (gevp = amd_generic_events; gevp->name != NULL; gevp++)
511c7a079a8SJonathan Haslam 		evlist_sz += strlen(gevp->name) + 1;
512c7a079a8SJonathan Haslam 
5137c478bd9Sstevel@tonic-gate 	evlist = kmem_alloc(evlist_sz + 1, KM_SLEEP);
5147c478bd9Sstevel@tonic-gate 	evlist[0] = '\0';
5157c478bd9Sstevel@tonic-gate 
51631725658Sksadhukh 	for (evp = amd_events; evp->name != NULL; evp++) {
5177c478bd9Sstevel@tonic-gate 		(void) strcat(evlist, evp->name);
5187c478bd9Sstevel@tonic-gate 		(void) strcat(evlist, ",");
5197c478bd9Sstevel@tonic-gate 	}
520c7a079a8SJonathan Haslam 
521c7a079a8SJonathan Haslam 	for (gevp = amd_generic_events; gevp->name != NULL; gevp++) {
522c7a079a8SJonathan Haslam 		(void) strcat(evlist, gevp->name);
523c7a079a8SJonathan Haslam 		(void) strcat(evlist, ",");
524c7a079a8SJonathan Haslam 	}
525c7a079a8SJonathan Haslam 
5267c478bd9Sstevel@tonic-gate 	/*
5277c478bd9Sstevel@tonic-gate 	 * Remove trailing comma.
5287c478bd9Sstevel@tonic-gate 	 */
5297c478bd9Sstevel@tonic-gate 	evlist[evlist_sz - 1] = '\0';
5307c478bd9Sstevel@tonic-gate 
5317c478bd9Sstevel@tonic-gate 	return (0);
5327c478bd9Sstevel@tonic-gate }
5337c478bd9Sstevel@tonic-gate 
5347c478bd9Sstevel@tonic-gate static uint_t
5357c478bd9Sstevel@tonic-gate opt_pcbe_ncounters(void)
5367c478bd9Sstevel@tonic-gate {
5377c478bd9Sstevel@tonic-gate 	return (4);
5387c478bd9Sstevel@tonic-gate }
5397c478bd9Sstevel@tonic-gate 
5407c478bd9Sstevel@tonic-gate static const char *
5417c478bd9Sstevel@tonic-gate opt_pcbe_impl_name(void)
5427c478bd9Sstevel@tonic-gate {
543e850fb01SKuriakose Kuruvilla 	return (amd_pcbe_impl_name);
5447c478bd9Sstevel@tonic-gate }
5457c478bd9Sstevel@tonic-gate 
5467c478bd9Sstevel@tonic-gate static const char *
5477c478bd9Sstevel@tonic-gate opt_pcbe_cpuref(void)
5487c478bd9Sstevel@tonic-gate {
549e850fb01SKuriakose Kuruvilla 
550e850fb01SKuriakose Kuruvilla 	return (amd_pcbe_cpuref);
5517c478bd9Sstevel@tonic-gate }
5527c478bd9Sstevel@tonic-gate 
5537c478bd9Sstevel@tonic-gate /*ARGSUSED*/
5547c478bd9Sstevel@tonic-gate static char *
5557c478bd9Sstevel@tonic-gate opt_pcbe_list_events(uint_t picnum)
5567c478bd9Sstevel@tonic-gate {
5577c478bd9Sstevel@tonic-gate 	return (evlist);
5587c478bd9Sstevel@tonic-gate }
5597c478bd9Sstevel@tonic-gate 
5607c478bd9Sstevel@tonic-gate static char *
5617c478bd9Sstevel@tonic-gate opt_pcbe_list_attrs(void)
5627c478bd9Sstevel@tonic-gate {
5637c478bd9Sstevel@tonic-gate 	return ("edge,pc,inv,cmask,umask");
5647c478bd9Sstevel@tonic-gate }
5657c478bd9Sstevel@tonic-gate 
5667c478bd9Sstevel@tonic-gate /*ARGSUSED*/
5677c478bd9Sstevel@tonic-gate static uint64_t
5687c478bd9Sstevel@tonic-gate opt_pcbe_event_coverage(char *event)
5697c478bd9Sstevel@tonic-gate {
5707c478bd9Sstevel@tonic-gate 	/*
5717c478bd9Sstevel@tonic-gate 	 * Fortunately, all counters can count all events.
5727c478bd9Sstevel@tonic-gate 	 */
5737c478bd9Sstevel@tonic-gate 	return (0xF);
5747c478bd9Sstevel@tonic-gate }
5757c478bd9Sstevel@tonic-gate 
5767c478bd9Sstevel@tonic-gate static uint64_t
5777c478bd9Sstevel@tonic-gate opt_pcbe_overflow_bitmap(void)
5787c478bd9Sstevel@tonic-gate {
5797c478bd9Sstevel@tonic-gate 	/*
5807c478bd9Sstevel@tonic-gate 	 * Unfortunately, this chip cannot detect which counter overflowed, so
5817c478bd9Sstevel@tonic-gate 	 * we must act as if they all did.
5827c478bd9Sstevel@tonic-gate 	 */
5837c478bd9Sstevel@tonic-gate 	return (0xF);
5847c478bd9Sstevel@tonic-gate }
5857c478bd9Sstevel@tonic-gate 
586c7a079a8SJonathan Haslam static amd_generic_event_t *
587c7a079a8SJonathan Haslam find_generic_event(char *name)
588c7a079a8SJonathan Haslam {
589c7a079a8SJonathan Haslam 	amd_generic_event_t	*gevp;
590c7a079a8SJonathan Haslam 
591c7a079a8SJonathan Haslam 	for (gevp = amd_generic_events; gevp->name != NULL; gevp++)
592c7a079a8SJonathan Haslam 		if (strcmp(name, gevp->name) == 0)
593c7a079a8SJonathan Haslam 			return (gevp);
594c7a079a8SJonathan Haslam 
595c7a079a8SJonathan Haslam 	return (NULL);
596c7a079a8SJonathan Haslam }
597c7a079a8SJonathan Haslam 
59831725658Sksadhukh static amd_event_t *
5997c478bd9Sstevel@tonic-gate find_event(char *name)
6007c478bd9Sstevel@tonic-gate {
601c7a079a8SJonathan Haslam 	amd_event_t		*evp;
6027c478bd9Sstevel@tonic-gate 
60331725658Sksadhukh 	for (evp = amd_events; evp->name != NULL; evp++)
6047c478bd9Sstevel@tonic-gate 		if (strcmp(name, evp->name) == 0)
6057c478bd9Sstevel@tonic-gate 			return (evp);
6067c478bd9Sstevel@tonic-gate 
6077c478bd9Sstevel@tonic-gate 	return (NULL);
6087c478bd9Sstevel@tonic-gate }
6097c478bd9Sstevel@tonic-gate 
6107c478bd9Sstevel@tonic-gate /*ARGSUSED*/
6117c478bd9Sstevel@tonic-gate static int
6127c478bd9Sstevel@tonic-gate opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, uint32_t flags,
6137c478bd9Sstevel@tonic-gate     uint_t nattrs, kcpc_attr_t *attrs, void **data, void *token)
6147c478bd9Sstevel@tonic-gate {
6157c478bd9Sstevel@tonic-gate 	opt_pcbe_config_t	*cfg;
61631725658Sksadhukh 	amd_event_t		*evp;
617e850fb01SKuriakose Kuruvilla 	amd_event_t		ev_raw = { "raw", 0};
618c7a079a8SJonathan Haslam 	amd_generic_event_t	*gevp;
6197c478bd9Sstevel@tonic-gate 	int			i;
62031725658Sksadhukh 	uint64_t		evsel = 0, evsel_tmp = 0;
6217c478bd9Sstevel@tonic-gate 
6227c478bd9Sstevel@tonic-gate 	/*
6237c478bd9Sstevel@tonic-gate 	 * If we've been handed an existing configuration, we need only preset
6247c478bd9Sstevel@tonic-gate 	 * the counter value.
6257c478bd9Sstevel@tonic-gate 	 */
6267c478bd9Sstevel@tonic-gate 	if (*data != NULL) {
6277c478bd9Sstevel@tonic-gate 		cfg = *data;
6287c478bd9Sstevel@tonic-gate 		cfg->opt_rawpic = preset & MASK48;
6297c478bd9Sstevel@tonic-gate 		return (0);
6307c478bd9Sstevel@tonic-gate 	}
6317c478bd9Sstevel@tonic-gate 
6327c478bd9Sstevel@tonic-gate 	if (picnum >= 4)
6337c478bd9Sstevel@tonic-gate 		return (CPC_INVALID_PICNUM);
6347c478bd9Sstevel@tonic-gate 
6355d3a5ad8Srab 	if ((evp = find_event(event)) == NULL) {
636c7a079a8SJonathan Haslam 		if ((gevp = find_generic_event(event)) != NULL) {
637c7a079a8SJonathan Haslam 			evp = find_event(gevp->event);
638c7a079a8SJonathan Haslam 			ASSERT(evp != NULL);
6395d3a5ad8Srab 
640c7a079a8SJonathan Haslam 			if (nattrs > 0)
641c7a079a8SJonathan Haslam 				return (CPC_ATTRIBUTE_OUT_OF_RANGE);
6425d3a5ad8Srab 
643c7a079a8SJonathan Haslam 			evsel |= gevp->umask << OPT_PES_UMASK_SHIFT;
644c7a079a8SJonathan Haslam 		} else {
645c7a079a8SJonathan Haslam 			long tmp;
646c7a079a8SJonathan Haslam 
647c7a079a8SJonathan Haslam 			/*
648c7a079a8SJonathan Haslam 			 * If ddi_strtol() likes this event, use it as a raw
649c7a079a8SJonathan Haslam 			 * event code.
650c7a079a8SJonathan Haslam 			 */
651c7a079a8SJonathan Haslam 			if (ddi_strtol(event, NULL, 0, &tmp) != 0)
652c7a079a8SJonathan Haslam 				return (CPC_INVALID_EVENT);
653c7a079a8SJonathan Haslam 
654c7a079a8SJonathan Haslam 			ev_raw.emask = tmp;
655c7a079a8SJonathan Haslam 			evp = &ev_raw;
656c7a079a8SJonathan Haslam 		}
6575d3a5ad8Srab 	}
6587c478bd9Sstevel@tonic-gate 
65931725658Sksadhukh 	/*
660e850fb01SKuriakose Kuruvilla 	 * Configuration of EventSelect register. While on some families
661e850fb01SKuriakose Kuruvilla 	 * certain bits might not be supported (e.g. Guest/Host on family
662e850fb01SKuriakose Kuruvilla 	 * 11h), setting these bits is harmless
66331725658Sksadhukh 	 */
66431725658Sksadhukh 
665e850fb01SKuriakose Kuruvilla 	/* Set GuestOnly bit to 0 and HostOnly bit to 1 */
666e850fb01SKuriakose Kuruvilla 	evsel &= ~OPT_PES_HOST;
667e850fb01SKuriakose Kuruvilla 	evsel &= ~OPT_PES_GUEST;
66831725658Sksadhukh 
669e850fb01SKuriakose Kuruvilla 	/* Set bits [35:32] for extended part of Event Select field */
670e850fb01SKuriakose Kuruvilla 	evsel_tmp = evp->emask & 0x0f00;
671e850fb01SKuriakose Kuruvilla 	evsel |= evsel_tmp << 24;
67231725658Sksadhukh 
67331725658Sksadhukh 	evsel |= evp->emask & 0x00ff;
6747c478bd9Sstevel@tonic-gate 
6757c478bd9Sstevel@tonic-gate 	if (flags & CPC_COUNT_USER)
6767c478bd9Sstevel@tonic-gate 		evsel |= OPT_PES_USR;
6777c478bd9Sstevel@tonic-gate 	if (flags & CPC_COUNT_SYSTEM)
6787c478bd9Sstevel@tonic-gate 		evsel |= OPT_PES_OS;
6797c478bd9Sstevel@tonic-gate 	if (flags & CPC_OVF_NOTIFY_EMT)
6807c478bd9Sstevel@tonic-gate 		evsel |= OPT_PES_INT;
6817c478bd9Sstevel@tonic-gate 
6827c478bd9Sstevel@tonic-gate 	for (i = 0; i < nattrs; i++) {
6837c478bd9Sstevel@tonic-gate 		if (strcmp(attrs[i].ka_name, "edge") == 0) {
6847c478bd9Sstevel@tonic-gate 			if (attrs[i].ka_val != 0)
6857c478bd9Sstevel@tonic-gate 				evsel |= OPT_PES_EDGE;
6867c478bd9Sstevel@tonic-gate 		} else if (strcmp(attrs[i].ka_name, "pc") == 0) {
6877c478bd9Sstevel@tonic-gate 			if (attrs[i].ka_val != 0)
6887c478bd9Sstevel@tonic-gate 				evsel |= OPT_PES_PC;
6897c478bd9Sstevel@tonic-gate 		} else if (strcmp(attrs[i].ka_name, "inv") == 0) {
6907c478bd9Sstevel@tonic-gate 			if (attrs[i].ka_val != 0)
6917c478bd9Sstevel@tonic-gate 				evsel |= OPT_PES_INV;
6927c478bd9Sstevel@tonic-gate 		} else if (strcmp(attrs[i].ka_name, "cmask") == 0) {
6937c478bd9Sstevel@tonic-gate 			if ((attrs[i].ka_val | OPT_PES_CMASK_MASK) !=
6947c478bd9Sstevel@tonic-gate 			    OPT_PES_CMASK_MASK)
6957c478bd9Sstevel@tonic-gate 				return (CPC_ATTRIBUTE_OUT_OF_RANGE);
6967c478bd9Sstevel@tonic-gate 			evsel |= attrs[i].ka_val << OPT_PES_CMASK_SHIFT;
6977c478bd9Sstevel@tonic-gate 		} else if (strcmp(attrs[i].ka_name, "umask") == 0) {
698e850fb01SKuriakose Kuruvilla 			if ((attrs[i].ka_val | OPT_PES_UMASK_MASK) !=
699e850fb01SKuriakose Kuruvilla 			    OPT_PES_UMASK_MASK)
7007c478bd9Sstevel@tonic-gate 				return (CPC_ATTRIBUTE_OUT_OF_RANGE);
7017c478bd9Sstevel@tonic-gate 			evsel |= attrs[i].ka_val << OPT_PES_UMASK_SHIFT;
7027c478bd9Sstevel@tonic-gate 		} else
7037c478bd9Sstevel@tonic-gate 			return (CPC_INVALID_ATTRIBUTE);
7047c478bd9Sstevel@tonic-gate 	}
7057c478bd9Sstevel@tonic-gate 
7067c478bd9Sstevel@tonic-gate 	cfg = kmem_alloc(sizeof (*cfg), KM_SLEEP);
7077c478bd9Sstevel@tonic-gate 
7087c478bd9Sstevel@tonic-gate 	cfg->opt_picno = picnum;
7097c478bd9Sstevel@tonic-gate 	cfg->opt_evsel = evsel;
7107c478bd9Sstevel@tonic-gate 	cfg->opt_rawpic = preset & MASK48;
7117c478bd9Sstevel@tonic-gate 
7127c478bd9Sstevel@tonic-gate 	*data = cfg;
7137c478bd9Sstevel@tonic-gate 	return (0);
7147c478bd9Sstevel@tonic-gate }
7157c478bd9Sstevel@tonic-gate 
7167c478bd9Sstevel@tonic-gate static void
7177c478bd9Sstevel@tonic-gate opt_pcbe_program(void *token)
7187c478bd9Sstevel@tonic-gate {
7197c478bd9Sstevel@tonic-gate 	opt_pcbe_config_t	*cfgs[4] = { &nullcfgs[0], &nullcfgs[1],
7207c478bd9Sstevel@tonic-gate 						&nullcfgs[2], &nullcfgs[3] };
7217c478bd9Sstevel@tonic-gate 	opt_pcbe_config_t	*pcfg = NULL;
7227c478bd9Sstevel@tonic-gate 	int			i;
723843e1988Sjohnlev 	ulong_t			curcr4 = getcr4();
7247c478bd9Sstevel@tonic-gate 
7257c478bd9Sstevel@tonic-gate 	/*
7267c478bd9Sstevel@tonic-gate 	 * Allow nonprivileged code to read the performance counters if desired.
7277c478bd9Sstevel@tonic-gate 	 */
7287c478bd9Sstevel@tonic-gate 	if (kcpc_allow_nonpriv(token))
7297c478bd9Sstevel@tonic-gate 		setcr4(curcr4 | CR4_PCE);
7307c478bd9Sstevel@tonic-gate 	else
7317c478bd9Sstevel@tonic-gate 		setcr4(curcr4 & ~CR4_PCE);
7327c478bd9Sstevel@tonic-gate 
7337c478bd9Sstevel@tonic-gate 	/*
7347c478bd9Sstevel@tonic-gate 	 * Query kernel for all configs which will be co-programmed.
7357c478bd9Sstevel@tonic-gate 	 */
7367c478bd9Sstevel@tonic-gate 	do {
7377c478bd9Sstevel@tonic-gate 		pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, NULL);
7387c478bd9Sstevel@tonic-gate 
7397c478bd9Sstevel@tonic-gate 		if (pcfg != NULL) {
7407c478bd9Sstevel@tonic-gate 			ASSERT(pcfg->opt_picno < 4);
7417c478bd9Sstevel@tonic-gate 			cfgs[pcfg->opt_picno] = pcfg;
7427c478bd9Sstevel@tonic-gate 		}
7437c478bd9Sstevel@tonic-gate 	} while (pcfg != NULL);
7447c478bd9Sstevel@tonic-gate 
7457c478bd9Sstevel@tonic-gate 	/*
7467c478bd9Sstevel@tonic-gate 	 * Program in two loops. The first configures and presets the counter,
7477c478bd9Sstevel@tonic-gate 	 * and the second loop enables the counters. This ensures that the
7487c478bd9Sstevel@tonic-gate 	 * counters are all enabled as closely together in time as possible.
7497c478bd9Sstevel@tonic-gate 	 */
7507c478bd9Sstevel@tonic-gate 
7517c478bd9Sstevel@tonic-gate 	for (i = 0; i < 4; i++) {
7520ac7d7d8Skucharsk 		wrmsr(PES_BASE_ADDR + i, cfgs[i]->opt_evsel);
7530ac7d7d8Skucharsk 		wrmsr(PIC_BASE_ADDR + i, cfgs[i]->opt_rawpic);
7547c478bd9Sstevel@tonic-gate 	}
7557c478bd9Sstevel@tonic-gate 
7567c478bd9Sstevel@tonic-gate 	for (i = 0; i < 4; i++) {
7570ac7d7d8Skucharsk 		wrmsr(PES_BASE_ADDR + i, cfgs[i]->opt_evsel |
7580ac7d7d8Skucharsk 		    (uint64_t)(uintptr_t)OPT_PES_ENABLE);
7597c478bd9Sstevel@tonic-gate 	}
7607c478bd9Sstevel@tonic-gate }
7617c478bd9Sstevel@tonic-gate 
7627c478bd9Sstevel@tonic-gate static void
7637c478bd9Sstevel@tonic-gate opt_pcbe_allstop(void)
7647c478bd9Sstevel@tonic-gate {
7657c478bd9Sstevel@tonic-gate 	int		i;
7667c478bd9Sstevel@tonic-gate 
7677c478bd9Sstevel@tonic-gate 	for (i = 0; i < 4; i++)
7680ac7d7d8Skucharsk 		wrmsr(PES_BASE_ADDR + i, 0ULL);
7697c478bd9Sstevel@tonic-gate 
7707c478bd9Sstevel@tonic-gate 	/*
7717c478bd9Sstevel@tonic-gate 	 * Disable non-privileged access to the counter registers.
7727c478bd9Sstevel@tonic-gate 	 */
773843e1988Sjohnlev 	setcr4(getcr4() & ~CR4_PCE);
7747c478bd9Sstevel@tonic-gate }
7757c478bd9Sstevel@tonic-gate 
7767c478bd9Sstevel@tonic-gate static void
7777c478bd9Sstevel@tonic-gate opt_pcbe_sample(void *token)
7787c478bd9Sstevel@tonic-gate {
7797c478bd9Sstevel@tonic-gate 	opt_pcbe_config_t	*cfgs[4] = { NULL, NULL, NULL, NULL };
7807c478bd9Sstevel@tonic-gate 	opt_pcbe_config_t	*pcfg = NULL;
7817c478bd9Sstevel@tonic-gate 	int			i;
7827c478bd9Sstevel@tonic-gate 	uint64_t		curpic[4];
7837c478bd9Sstevel@tonic-gate 	uint64_t		*addrs[4];
7847c478bd9Sstevel@tonic-gate 	uint64_t		*tmp;
7857c478bd9Sstevel@tonic-gate 	int64_t			diff;
7867c478bd9Sstevel@tonic-gate 
7877c478bd9Sstevel@tonic-gate 	for (i = 0; i < 4; i++)
78893d449f8Skucharsk 		curpic[i] = rdmsr(PIC_BASE_ADDR + i);
7897c478bd9Sstevel@tonic-gate 
7907c478bd9Sstevel@tonic-gate 	/*
7917c478bd9Sstevel@tonic-gate 	 * Query kernel for all configs which are co-programmed.
7927c478bd9Sstevel@tonic-gate 	 */
7937c478bd9Sstevel@tonic-gate 	do {
7947c478bd9Sstevel@tonic-gate 		pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, &tmp);
7957c478bd9Sstevel@tonic-gate 
7967c478bd9Sstevel@tonic-gate 		if (pcfg != NULL) {
7977c478bd9Sstevel@tonic-gate 			ASSERT(pcfg->opt_picno < 4);
7987c478bd9Sstevel@tonic-gate 			cfgs[pcfg->opt_picno] = pcfg;
7997c478bd9Sstevel@tonic-gate 			addrs[pcfg->opt_picno] = tmp;
8007c478bd9Sstevel@tonic-gate 		}
8017c478bd9Sstevel@tonic-gate 	} while (pcfg != NULL);
8027c478bd9Sstevel@tonic-gate 
8037c478bd9Sstevel@tonic-gate 	for (i = 0; i < 4; i++) {
8047c478bd9Sstevel@tonic-gate 		if (cfgs[i] == NULL)
8057c478bd9Sstevel@tonic-gate 			continue;
8067c478bd9Sstevel@tonic-gate 
8077c478bd9Sstevel@tonic-gate 		diff = (curpic[i] - cfgs[i]->opt_rawpic) & MASK48;
8087c478bd9Sstevel@tonic-gate 		*addrs[i] += diff;
8097c478bd9Sstevel@tonic-gate 		DTRACE_PROBE4(opt__pcbe__sample, int, i, uint64_t, *addrs[i],
8107c478bd9Sstevel@tonic-gate 		    uint64_t, curpic[i], uint64_t, cfgs[i]->opt_rawpic);
8117c478bd9Sstevel@tonic-gate 		cfgs[i]->opt_rawpic = *addrs[i] & MASK48;
8127c478bd9Sstevel@tonic-gate 	}
8137c478bd9Sstevel@tonic-gate }
8147c478bd9Sstevel@tonic-gate 
8157c478bd9Sstevel@tonic-gate static void
8167c478bd9Sstevel@tonic-gate opt_pcbe_free(void *config)
8177c478bd9Sstevel@tonic-gate {
8187c478bd9Sstevel@tonic-gate 	kmem_free(config, sizeof (opt_pcbe_config_t));
8197c478bd9Sstevel@tonic-gate }
8207c478bd9Sstevel@tonic-gate 
8217c478bd9Sstevel@tonic-gate 
8227c478bd9Sstevel@tonic-gate static struct modlpcbe modlpcbe = {
8237c478bd9Sstevel@tonic-gate 	&mod_pcbeops,
824820c9f58Skk 	"AMD Performance Counters",
8257c478bd9Sstevel@tonic-gate 	&opt_pcbe_ops
8267c478bd9Sstevel@tonic-gate };
8277c478bd9Sstevel@tonic-gate 
8287c478bd9Sstevel@tonic-gate static struct modlinkage modl = {
8297c478bd9Sstevel@tonic-gate 	MODREV_1,
8307c478bd9Sstevel@tonic-gate 	&modlpcbe,
8317c478bd9Sstevel@tonic-gate };
8327c478bd9Sstevel@tonic-gate 
8337c478bd9Sstevel@tonic-gate int
8347c478bd9Sstevel@tonic-gate _init(void)
8357c478bd9Sstevel@tonic-gate {
8367c478bd9Sstevel@tonic-gate 	int ret;
8377c478bd9Sstevel@tonic-gate 
8387c478bd9Sstevel@tonic-gate 	if (opt_pcbe_init() != 0)
8397c478bd9Sstevel@tonic-gate 		return (ENOTSUP);
8407c478bd9Sstevel@tonic-gate 
8417c478bd9Sstevel@tonic-gate 	if ((ret = mod_install(&modl)) != 0)
8427c478bd9Sstevel@tonic-gate 		kmem_free(evlist, evlist_sz + 1);
8437c478bd9Sstevel@tonic-gate 
8447c478bd9Sstevel@tonic-gate 	return (ret);
8457c478bd9Sstevel@tonic-gate }
8467c478bd9Sstevel@tonic-gate 
8477c478bd9Sstevel@tonic-gate int
8487c478bd9Sstevel@tonic-gate _fini(void)
8497c478bd9Sstevel@tonic-gate {
8507c478bd9Sstevel@tonic-gate 	int ret;
8517c478bd9Sstevel@tonic-gate 
8527c478bd9Sstevel@tonic-gate 	if ((ret = mod_remove(&modl)) == 0)
8537c478bd9Sstevel@tonic-gate 		kmem_free(evlist, evlist_sz + 1);
8547c478bd9Sstevel@tonic-gate 	return (ret);
8557c478bd9Sstevel@tonic-gate }
8567c478bd9Sstevel@tonic-gate 
8577c478bd9Sstevel@tonic-gate int
8587c478bd9Sstevel@tonic-gate _info(struct modinfo *mi)
8597c478bd9Sstevel@tonic-gate {
8607c478bd9Sstevel@tonic-gate 	return (mod_info(&modl, mi));
8617c478bd9Sstevel@tonic-gate }
862