17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5346af85bScwb * Common Development and Distribution License (the "License"). 6346af85bScwb * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22346af85bScwb * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 277c478bd9Sstevel@tonic-gate 287c478bd9Sstevel@tonic-gate /* 297c478bd9Sstevel@tonic-gate * Performance Counter Back-End for AMD Opteron and AMD Athlon 64 processors. 307c478bd9Sstevel@tonic-gate */ 317c478bd9Sstevel@tonic-gate 327c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 337c478bd9Sstevel@tonic-gate #include <sys/param.h> 347c478bd9Sstevel@tonic-gate #include <sys/systm.h> 357c478bd9Sstevel@tonic-gate #include <sys/cpc_pcbe.h> 367c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 377c478bd9Sstevel@tonic-gate #include <sys/sdt.h> 387c478bd9Sstevel@tonic-gate #include <sys/modctl.h> 397c478bd9Sstevel@tonic-gate #include <sys/errno.h> 407c478bd9Sstevel@tonic-gate #include <sys/debug.h> 417c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 427c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h> 437c478bd9Sstevel@tonic-gate #include <sys/privregs.h> 44*5d3a5ad8Srab #include <sys/ddi.h> 45*5d3a5ad8Srab #include <sys/sunddi.h> 467c478bd9Sstevel@tonic-gate 477c478bd9Sstevel@tonic-gate static int opt_pcbe_init(void); 487c478bd9Sstevel@tonic-gate static uint_t opt_pcbe_ncounters(void); 497c478bd9Sstevel@tonic-gate static const char *opt_pcbe_impl_name(void); 507c478bd9Sstevel@tonic-gate static const char *opt_pcbe_cpuref(void); 517c478bd9Sstevel@tonic-gate static char *opt_pcbe_list_events(uint_t picnum); 527c478bd9Sstevel@tonic-gate static char *opt_pcbe_list_attrs(void); 537c478bd9Sstevel@tonic-gate static uint64_t opt_pcbe_event_coverage(char *event); 547c478bd9Sstevel@tonic-gate static uint64_t opt_pcbe_overflow_bitmap(void); 557c478bd9Sstevel@tonic-gate static int opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, 567c478bd9Sstevel@tonic-gate uint32_t flags, uint_t nattrs, kcpc_attr_t *attrs, void **data, 577c478bd9Sstevel@tonic-gate void *token); 587c478bd9Sstevel@tonic-gate static void opt_pcbe_program(void *token); 597c478bd9Sstevel@tonic-gate static void opt_pcbe_allstop(void); 607c478bd9Sstevel@tonic-gate static void opt_pcbe_sample(void *token); 617c478bd9Sstevel@tonic-gate static void opt_pcbe_free(void *config); 627c478bd9Sstevel@tonic-gate 637c478bd9Sstevel@tonic-gate static pcbe_ops_t opt_pcbe_ops = { 647c478bd9Sstevel@tonic-gate PCBE_VER_1, 657c478bd9Sstevel@tonic-gate CPC_CAP_OVERFLOW_INTERRUPT, 667c478bd9Sstevel@tonic-gate opt_pcbe_ncounters, 677c478bd9Sstevel@tonic-gate opt_pcbe_impl_name, 687c478bd9Sstevel@tonic-gate opt_pcbe_cpuref, 697c478bd9Sstevel@tonic-gate opt_pcbe_list_events, 707c478bd9Sstevel@tonic-gate opt_pcbe_list_attrs, 717c478bd9Sstevel@tonic-gate opt_pcbe_event_coverage, 727c478bd9Sstevel@tonic-gate opt_pcbe_overflow_bitmap, 737c478bd9Sstevel@tonic-gate opt_pcbe_configure, 747c478bd9Sstevel@tonic-gate opt_pcbe_program, 757c478bd9Sstevel@tonic-gate opt_pcbe_allstop, 767c478bd9Sstevel@tonic-gate opt_pcbe_sample, 777c478bd9Sstevel@tonic-gate opt_pcbe_free 787c478bd9Sstevel@tonic-gate }; 797c478bd9Sstevel@tonic-gate 807c478bd9Sstevel@tonic-gate /* 817c478bd9Sstevel@tonic-gate * Define offsets and masks for the fields in the Performance 827c478bd9Sstevel@tonic-gate * Event-Select (PES) registers. 837c478bd9Sstevel@tonic-gate */ 847c478bd9Sstevel@tonic-gate #define OPT_PES_CMASK_SHIFT 24 857c478bd9Sstevel@tonic-gate #define OPT_PES_CMASK_MASK 0xFF 867c478bd9Sstevel@tonic-gate #define OPT_PES_INV_SHIFT 23 877c478bd9Sstevel@tonic-gate #define OPT_PES_ENABLE_SHIFT 22 887c478bd9Sstevel@tonic-gate #define OPT_PES_INT_SHIFT 20 897c478bd9Sstevel@tonic-gate #define OPT_PES_PC_SHIFT 19 907c478bd9Sstevel@tonic-gate #define OPT_PES_EDGE_SHIFT 18 917c478bd9Sstevel@tonic-gate #define OPT_PES_OS_SHIFT 17 927c478bd9Sstevel@tonic-gate #define OPT_PES_USR_SHIFT 16 937c478bd9Sstevel@tonic-gate #define OPT_PES_UMASK_SHIFT 8 947c478bd9Sstevel@tonic-gate #define OPT_PES_UMASK_MASK 0xFF 957c478bd9Sstevel@tonic-gate 967c478bd9Sstevel@tonic-gate #define OPT_PES_INV (1 << OPT_PES_INV_SHIFT) 977c478bd9Sstevel@tonic-gate #define OPT_PES_ENABLE (1 << OPT_PES_ENABLE_SHIFT) 987c478bd9Sstevel@tonic-gate #define OPT_PES_INT (1 << OPT_PES_INT_SHIFT) 997c478bd9Sstevel@tonic-gate #define OPT_PES_PC (1 << OPT_PES_PC_SHIFT) 1007c478bd9Sstevel@tonic-gate #define OPT_PES_EDGE (1 << OPT_PES_EDGE_SHIFT) 1017c478bd9Sstevel@tonic-gate #define OPT_PES_OS (1 << OPT_PES_OS_SHIFT) 1027c478bd9Sstevel@tonic-gate #define OPT_PES_USR (1 << OPT_PES_USR_SHIFT) 1037c478bd9Sstevel@tonic-gate 1047c478bd9Sstevel@tonic-gate typedef struct _opt_pcbe_config { 1057c478bd9Sstevel@tonic-gate uint8_t opt_picno; /* Counter number: 0, 1, 2, or 3 */ 1067c478bd9Sstevel@tonic-gate uint64_t opt_evsel; /* Event Selection register */ 1077c478bd9Sstevel@tonic-gate uint64_t opt_rawpic; /* Raw counter value */ 1087c478bd9Sstevel@tonic-gate } opt_pcbe_config_t; 1097c478bd9Sstevel@tonic-gate 1107c478bd9Sstevel@tonic-gate opt_pcbe_config_t nullcfgs[4] = { 1117c478bd9Sstevel@tonic-gate { 0, 0, 0 }, 1127c478bd9Sstevel@tonic-gate { 1, 0, 0 }, 1137c478bd9Sstevel@tonic-gate { 2, 0, 0 }, 1147c478bd9Sstevel@tonic-gate { 3, 0, 0 } 1157c478bd9Sstevel@tonic-gate }; 1167c478bd9Sstevel@tonic-gate 1177c478bd9Sstevel@tonic-gate typedef struct _opt_event { 1187c478bd9Sstevel@tonic-gate char *name; 1197c478bd9Sstevel@tonic-gate uint8_t emask; /* Event mask setting */ 1207c478bd9Sstevel@tonic-gate uint8_t umask_valid; /* Mask of unreserved UNIT_MASK bits */ 1217c478bd9Sstevel@tonic-gate } opt_event_t; 1227c478bd9Sstevel@tonic-gate 1237c478bd9Sstevel@tonic-gate /* 1247c478bd9Sstevel@tonic-gate * Base MSR addresses for the PerfEvtSel registers and the counters themselves. 1257c478bd9Sstevel@tonic-gate * Add counter number to base address to get corresponding MSR address. 1267c478bd9Sstevel@tonic-gate */ 1277c478bd9Sstevel@tonic-gate #define PES_BASE_ADDR 0xC0010000 1287c478bd9Sstevel@tonic-gate #define PIC_BASE_ADDR 0xC0010004 1297c478bd9Sstevel@tonic-gate 1307c478bd9Sstevel@tonic-gate #define MASK48 0xFFFFFFFFFFFF 1317c478bd9Sstevel@tonic-gate 1327c478bd9Sstevel@tonic-gate #define EV_END {NULL, 0, 0} 1337c478bd9Sstevel@tonic-gate 1347c478bd9Sstevel@tonic-gate static opt_event_t opt_events[] = { 1357c478bd9Sstevel@tonic-gate { "FP_dispatched_fpu_ops", 0x0, 0x1F }, 1367c478bd9Sstevel@tonic-gate { "FP_cycles_no_fpu_ops_retired", 0x1, 0x0 }, 1377c478bd9Sstevel@tonic-gate { "FP_dispatched_fpu_ops_ff", 0x2, 0x0 }, 1387c478bd9Sstevel@tonic-gate { "LS_seg_reg_load", 0x20, 0x7F }, 1397c478bd9Sstevel@tonic-gate { "LS_uarch_resync_self_modify", 0x21, 0x0 }, 1407c478bd9Sstevel@tonic-gate { "LS_uarch_resync_snoop", 0x22, 0x0 }, 1417c478bd9Sstevel@tonic-gate { "LS_buffer_2_full", 0x23, 0x0 }, 1427c478bd9Sstevel@tonic-gate { "LS_locked_operation", 0x24, 0x7 }, 1437c478bd9Sstevel@tonic-gate { "LS_uarch_late_cancel_op", 0x25, 0x0 }, 1447c478bd9Sstevel@tonic-gate { "LS_retired_cflush", 0x26, 0x0 }, 1457c478bd9Sstevel@tonic-gate { "LS_retired_cpuid", 0x27, 0x0 }, 1467c478bd9Sstevel@tonic-gate { "DC_access", 0x40, 0x0 }, 1477c478bd9Sstevel@tonic-gate { "DC_miss", 0x41, 0x0 }, 1487c478bd9Sstevel@tonic-gate { "DC_refill_from_L2", 0x42, 0x1F }, 1497c478bd9Sstevel@tonic-gate { "DC_refill_from_system", 0x43, 0x1F }, 1507c478bd9Sstevel@tonic-gate { "DC_copyback", 0x44, 0x1F }, 1517c478bd9Sstevel@tonic-gate { "DC_dtlb_L1_miss_L2_hit", 0x45, 0x0 }, 1527c478bd9Sstevel@tonic-gate { "DC_dtlb_L1_miss_L2_miss", 0x46, 0x0 }, 1537c478bd9Sstevel@tonic-gate { "DC_misaligned_data_ref", 0x47, 0x0 }, 1547c478bd9Sstevel@tonic-gate { "DC_uarch_late_cancel_access", 0x48, 0x0 }, 1557c478bd9Sstevel@tonic-gate { "DC_uarch_early_cancel_access", 0x49, 0x0 }, 1567c478bd9Sstevel@tonic-gate { "DC_1bit_ecc_error_found", 0x4A, 0x3 }, 1577c478bd9Sstevel@tonic-gate { "DC_dispatched_prefetch_instr", 0x4B, 0x7 }, 1587c478bd9Sstevel@tonic-gate { "DC_dcache_accesses_by_locks", 0x4C, 0x3 }, 159346af85bScwb { "BU_memory_requests", 0x65, 0x83}, 160346af85bScwb { "BU_data_prefetch", 0x67, 0x3 }, 161346af85bScwb { "BU_system_read_responses", 0x6C, 0x7 }, 162346af85bScwb { "BU_quadwords_written_to_system", 0x6D, 0x1 }, 1637c478bd9Sstevel@tonic-gate { "BU_cpu_clk_unhalted", 0x76, 0x0 }, 1647c478bd9Sstevel@tonic-gate { "BU_internal_L2_req", 0x7D, 0x1F }, 1657c478bd9Sstevel@tonic-gate { "BU_fill_req_missed_L2", 0x7E, 0x7 }, 1667c478bd9Sstevel@tonic-gate { "BU_fill_into_L2", 0x7F, 0x3 }, 1677c478bd9Sstevel@tonic-gate { "IC_fetch", 0x80, 0x0 }, 1687c478bd9Sstevel@tonic-gate { "IC_miss", 0x81, 0x0 }, 1697c478bd9Sstevel@tonic-gate { "IC_refill_from_L2", 0x82, 0x0 }, 1707c478bd9Sstevel@tonic-gate { "IC_refill_from_system", 0x83, 0x0 }, 1717c478bd9Sstevel@tonic-gate { "IC_itlb_L1_miss_L2_hit", 0x84, 0x0 }, 1727c478bd9Sstevel@tonic-gate { "IC_itlb_L1_miss_L2_miss", 0x85, 0x0 }, 1737c478bd9Sstevel@tonic-gate { "IC_uarch_resync_snoop", 0x86, 0x0 }, 1747c478bd9Sstevel@tonic-gate { "IC_instr_fetch_stall", 0x87, 0x0 }, 1757c478bd9Sstevel@tonic-gate { "IC_return_stack_hit", 0x88, 0x0 }, 1767c478bd9Sstevel@tonic-gate { "IC_return_stack_overflow", 0x89, 0x0 }, 1777c478bd9Sstevel@tonic-gate { "FR_retired_x86_instr_w_excp_intr", 0xC0, 0x0 }, 1787c478bd9Sstevel@tonic-gate { "FR_retired_uops", 0xC1, 0x0 }, 1797c478bd9Sstevel@tonic-gate { "FR_retired_branches_w_excp_intr", 0xC2, 0x0 }, 1807c478bd9Sstevel@tonic-gate { "FR_retired_branches_mispred", 0xC3, 0x0 }, 1817c478bd9Sstevel@tonic-gate { "FR_retired_taken_branches", 0xC4, 0x0 }, 1827c478bd9Sstevel@tonic-gate { "FR_retired_taken_branches_mispred", 0xC5, 0x0 }, 1837c478bd9Sstevel@tonic-gate { "FR_retired_far_ctl_transfer", 0xC6, 0x0 }, 1847c478bd9Sstevel@tonic-gate { "FR_retired_resyncs", 0xC7, 0x0 }, 1857c478bd9Sstevel@tonic-gate { "FR_retired_near_rets", 0xC8, 0x0 }, 1867c478bd9Sstevel@tonic-gate { "FR_retired_near_rets_mispred", 0xC9, 0x0 }, 1877c478bd9Sstevel@tonic-gate { "FR_retired_taken_branches_mispred_addr_miscomp", 0xCA, 0x0 }, 1887c478bd9Sstevel@tonic-gate { "FR_retired_fpu_instr", 0xCB, 0xF }, 1897c478bd9Sstevel@tonic-gate { "FR_retired_fastpath_double_op_instr", 0xCC, 0x7 }, 1907c478bd9Sstevel@tonic-gate { "FR_intr_masked_cycles", 0xCD, 0x0 }, 1917c478bd9Sstevel@tonic-gate { "FR_intr_masked_while_pending_cycles", 0xCE, 0x0 }, 1927c478bd9Sstevel@tonic-gate { "FR_taken_hardware_intrs", 0xCF, 0x0 }, 1937c478bd9Sstevel@tonic-gate { "FR_nothing_to_dispatch", 0xD0, 0x0 }, 1947c478bd9Sstevel@tonic-gate { "FR_dispatch_stalls", 0xD1, 0x0 }, 1957c478bd9Sstevel@tonic-gate { "FR_dispatch_stall_branch_abort_to_retire", 0xD2, 0x0 }, 1967c478bd9Sstevel@tonic-gate { "FR_dispatch_stall_serialization", 0xD3, 0x0 }, 1977c478bd9Sstevel@tonic-gate { "FR_dispatch_stall_segment_load", 0xD4, 0x0 }, 1987c478bd9Sstevel@tonic-gate { "FR_dispatch_stall_reorder_buffer_full", 0xD5, 0x0 }, 1997c478bd9Sstevel@tonic-gate { "FR_dispatch_stall_resv_stations_full", 0xD6, 0x0 }, 2007c478bd9Sstevel@tonic-gate { "FR_dispatch_stall_fpu_full", 0xD7, 0x0 }, 2017c478bd9Sstevel@tonic-gate { "FR_dispatch_stall_ls_full", 0xD8, 0x0 }, 2027c478bd9Sstevel@tonic-gate { "FR_dispatch_stall_waiting_all_quiet", 0xD9, 0x0 }, 2037c478bd9Sstevel@tonic-gate { "FR_dispatch_stall_far_ctl_trsfr_resync_branch_pend", 0xDA, 0x0 }, 2047c478bd9Sstevel@tonic-gate { "FR_fpu_exception", 0xDB, 0xF }, 2057c478bd9Sstevel@tonic-gate { "FR_num_brkpts_dr0", 0xDC, 0x0 }, 2067c478bd9Sstevel@tonic-gate { "FR_num_brkpts_dr1", 0xDD, 0x0 }, 2077c478bd9Sstevel@tonic-gate { "FR_num_brkpts_dr2", 0xDE, 0x0 }, 2087c478bd9Sstevel@tonic-gate { "FR_num_brkpts_dr3", 0xDF, 0x0 }, 2097c478bd9Sstevel@tonic-gate { "NB_mem_ctrlr_page_access", 0xE0, 0x7 }, 2107c478bd9Sstevel@tonic-gate { "NB_mem_ctrlr_page_table_overflow", 0xE1, 0x0 }, 2117c478bd9Sstevel@tonic-gate { "NB_mem_ctrlr_dram_cmd_slots_missed", 0xE2, 0x0 }, 2127c478bd9Sstevel@tonic-gate { "NB_mem_ctrlr_turnaround", 0xE3, 0x7 }, 2137c478bd9Sstevel@tonic-gate { "NB_mem_ctrlr_bypass_counter_saturation", 0xE4, 0xF }, 214346af85bScwb { "NB_sized_blocks_Rev_D", 0xE5, 0x3C}, 215346af85bScwb { "NB_ECC_errors", 0xE8, 0x80}, 216346af85bScwb { "NB_cpu_io_to_mem_io_Rev_E", 0xE9, 0xFF}, 217346af85bScwb { "NB_cache_block_commands_Rev_E", 0xEA, 0x3D}, 2187c478bd9Sstevel@tonic-gate { "NB_sized_commands", 0xEB, 0x7F }, 219346af85bScwb { "NB_probe_result", 0xEC, 0x7F}, 220346af85bScwb { "NB_gart_events", 0xEE, 0x7 }, 2217c478bd9Sstevel@tonic-gate { "NB_ht_bus0_bandwidth", 0xF6, 0xF }, 2227c478bd9Sstevel@tonic-gate { "NB_ht_bus1_bandwidth", 0xF7, 0xF }, 2237c478bd9Sstevel@tonic-gate { "NB_ht_bus2_bandwidth", 0xF8, 0xF }, 2247c478bd9Sstevel@tonic-gate EV_END 2257c478bd9Sstevel@tonic-gate }; 2267c478bd9Sstevel@tonic-gate 2277c478bd9Sstevel@tonic-gate static char *evlist; 2287c478bd9Sstevel@tonic-gate static size_t evlist_sz; 2297c478bd9Sstevel@tonic-gate 2307c478bd9Sstevel@tonic-gate #define BITS(v, u, l) \ 2317c478bd9Sstevel@tonic-gate (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1)) 2327c478bd9Sstevel@tonic-gate 2337c478bd9Sstevel@tonic-gate #define OPTERON_FAMILY 15 2347c478bd9Sstevel@tonic-gate 2357c478bd9Sstevel@tonic-gate static int 2367c478bd9Sstevel@tonic-gate opt_pcbe_init(void) 2377c478bd9Sstevel@tonic-gate { 2387c478bd9Sstevel@tonic-gate opt_event_t *evp; 2397c478bd9Sstevel@tonic-gate 2407c478bd9Sstevel@tonic-gate /* 2417c478bd9Sstevel@tonic-gate * Make sure this really _is_ an Opteron or Athlon 64 system. The kernel 2427c478bd9Sstevel@tonic-gate * loads this module based on its name in the module directory, but it 2437c478bd9Sstevel@tonic-gate * could have been renamed. 2447c478bd9Sstevel@tonic-gate */ 2457c478bd9Sstevel@tonic-gate if (cpuid_getvendor(CPU) != X86_VENDOR_AMD || 2467c478bd9Sstevel@tonic-gate cpuid_getfamily(CPU) != OPTERON_FAMILY) 2477c478bd9Sstevel@tonic-gate return (-1); 2487c478bd9Sstevel@tonic-gate 2497c478bd9Sstevel@tonic-gate /* 2507c478bd9Sstevel@tonic-gate * Construct event list. 2517c478bd9Sstevel@tonic-gate * 2527c478bd9Sstevel@tonic-gate * First pass: Calculate size needed. We'll need an additional byte 2537c478bd9Sstevel@tonic-gate * for the NULL pointer during the last strcat. 2547c478bd9Sstevel@tonic-gate * 2557c478bd9Sstevel@tonic-gate * Second pass: Copy strings. 2567c478bd9Sstevel@tonic-gate */ 2577c478bd9Sstevel@tonic-gate for (evp = opt_events; evp->name != NULL; evp++) 2587c478bd9Sstevel@tonic-gate evlist_sz += strlen(evp->name) + 1; 2597c478bd9Sstevel@tonic-gate 2607c478bd9Sstevel@tonic-gate evlist = kmem_alloc(evlist_sz + 1, KM_SLEEP); 2617c478bd9Sstevel@tonic-gate evlist[0] = '\0'; 2627c478bd9Sstevel@tonic-gate 2637c478bd9Sstevel@tonic-gate for (evp = opt_events; evp->name != NULL; evp++) { 2647c478bd9Sstevel@tonic-gate (void) strcat(evlist, evp->name); 2657c478bd9Sstevel@tonic-gate (void) strcat(evlist, ","); 2667c478bd9Sstevel@tonic-gate } 2677c478bd9Sstevel@tonic-gate /* 2687c478bd9Sstevel@tonic-gate * Remove trailing comma. 2697c478bd9Sstevel@tonic-gate */ 2707c478bd9Sstevel@tonic-gate evlist[evlist_sz - 1] = '\0'; 2717c478bd9Sstevel@tonic-gate 2727c478bd9Sstevel@tonic-gate return (0); 2737c478bd9Sstevel@tonic-gate } 2747c478bd9Sstevel@tonic-gate 2757c478bd9Sstevel@tonic-gate static uint_t 2767c478bd9Sstevel@tonic-gate opt_pcbe_ncounters(void) 2777c478bd9Sstevel@tonic-gate { 2787c478bd9Sstevel@tonic-gate return (4); 2797c478bd9Sstevel@tonic-gate } 2807c478bd9Sstevel@tonic-gate 2817c478bd9Sstevel@tonic-gate static const char * 2827c478bd9Sstevel@tonic-gate opt_pcbe_impl_name(void) 2837c478bd9Sstevel@tonic-gate { 2847c478bd9Sstevel@tonic-gate return ("AMD Opteron & Athlon64"); 2857c478bd9Sstevel@tonic-gate } 2867c478bd9Sstevel@tonic-gate 2877c478bd9Sstevel@tonic-gate static const char * 2887c478bd9Sstevel@tonic-gate opt_pcbe_cpuref(void) 2897c478bd9Sstevel@tonic-gate { 2907c478bd9Sstevel@tonic-gate return ("See Chapter 10 of the \"BIOS and Kernel Developer's Guide " 2917c478bd9Sstevel@tonic-gate "for the AMD Athlon 64 and AMD Opteron Processors,\" " 2927c478bd9Sstevel@tonic-gate "AMD publication #26094"); 2937c478bd9Sstevel@tonic-gate } 2947c478bd9Sstevel@tonic-gate 2957c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 2967c478bd9Sstevel@tonic-gate static char * 2977c478bd9Sstevel@tonic-gate opt_pcbe_list_events(uint_t picnum) 2987c478bd9Sstevel@tonic-gate { 2997c478bd9Sstevel@tonic-gate return (evlist); 3007c478bd9Sstevel@tonic-gate } 3017c478bd9Sstevel@tonic-gate 3027c478bd9Sstevel@tonic-gate static char * 3037c478bd9Sstevel@tonic-gate opt_pcbe_list_attrs(void) 3047c478bd9Sstevel@tonic-gate { 3057c478bd9Sstevel@tonic-gate return ("edge,pc,inv,cmask,umask"); 3067c478bd9Sstevel@tonic-gate } 3077c478bd9Sstevel@tonic-gate 3087c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 3097c478bd9Sstevel@tonic-gate static uint64_t 3107c478bd9Sstevel@tonic-gate opt_pcbe_event_coverage(char *event) 3117c478bd9Sstevel@tonic-gate { 3127c478bd9Sstevel@tonic-gate /* 3137c478bd9Sstevel@tonic-gate * Fortunately, all counters can count all events. 3147c478bd9Sstevel@tonic-gate */ 3157c478bd9Sstevel@tonic-gate return (0xF); 3167c478bd9Sstevel@tonic-gate } 3177c478bd9Sstevel@tonic-gate 3187c478bd9Sstevel@tonic-gate static uint64_t 3197c478bd9Sstevel@tonic-gate opt_pcbe_overflow_bitmap(void) 3207c478bd9Sstevel@tonic-gate { 3217c478bd9Sstevel@tonic-gate /* 3227c478bd9Sstevel@tonic-gate * Unfortunately, this chip cannot detect which counter overflowed, so 3237c478bd9Sstevel@tonic-gate * we must act as if they all did. 3247c478bd9Sstevel@tonic-gate */ 3257c478bd9Sstevel@tonic-gate return (0xF); 3267c478bd9Sstevel@tonic-gate } 3277c478bd9Sstevel@tonic-gate 3287c478bd9Sstevel@tonic-gate static opt_event_t * 3297c478bd9Sstevel@tonic-gate find_event(char *name) 3307c478bd9Sstevel@tonic-gate { 3317c478bd9Sstevel@tonic-gate opt_event_t *evp; 3327c478bd9Sstevel@tonic-gate 3337c478bd9Sstevel@tonic-gate for (evp = opt_events; evp->name != NULL; evp++) 3347c478bd9Sstevel@tonic-gate if (strcmp(name, evp->name) == 0) 3357c478bd9Sstevel@tonic-gate return (evp); 3367c478bd9Sstevel@tonic-gate 3377c478bd9Sstevel@tonic-gate return (NULL); 3387c478bd9Sstevel@tonic-gate } 3397c478bd9Sstevel@tonic-gate 3407c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 3417c478bd9Sstevel@tonic-gate static int 3427c478bd9Sstevel@tonic-gate opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, uint32_t flags, 3437c478bd9Sstevel@tonic-gate uint_t nattrs, kcpc_attr_t *attrs, void **data, void *token) 3447c478bd9Sstevel@tonic-gate { 3457c478bd9Sstevel@tonic-gate opt_pcbe_config_t *cfg; 3467c478bd9Sstevel@tonic-gate opt_event_t *evp; 347*5d3a5ad8Srab opt_event_t ev_raw = { "raw", 0, 0xFF }; 3487c478bd9Sstevel@tonic-gate int i; 3497c478bd9Sstevel@tonic-gate uint32_t evsel = 0; 3507c478bd9Sstevel@tonic-gate 3517c478bd9Sstevel@tonic-gate /* 3527c478bd9Sstevel@tonic-gate * If we've been handed an existing configuration, we need only preset 3537c478bd9Sstevel@tonic-gate * the counter value. 3547c478bd9Sstevel@tonic-gate */ 3557c478bd9Sstevel@tonic-gate if (*data != NULL) { 3567c478bd9Sstevel@tonic-gate cfg = *data; 3577c478bd9Sstevel@tonic-gate cfg->opt_rawpic = preset & MASK48; 3587c478bd9Sstevel@tonic-gate return (0); 3597c478bd9Sstevel@tonic-gate } 3607c478bd9Sstevel@tonic-gate 3617c478bd9Sstevel@tonic-gate if (picnum >= 4) 3627c478bd9Sstevel@tonic-gate return (CPC_INVALID_PICNUM); 3637c478bd9Sstevel@tonic-gate 364*5d3a5ad8Srab if ((evp = find_event(event)) == NULL) { 365*5d3a5ad8Srab long tmp; 366*5d3a5ad8Srab 367*5d3a5ad8Srab /* 368*5d3a5ad8Srab * If ddi_strtol() likes this event, use it as a raw event code. 369*5d3a5ad8Srab */ 370*5d3a5ad8Srab if (ddi_strtol(event, NULL, 0, &tmp) != 0) 371*5d3a5ad8Srab return (CPC_INVALID_EVENT); 372*5d3a5ad8Srab 373*5d3a5ad8Srab ev_raw.emask = tmp; 374*5d3a5ad8Srab evp = &ev_raw; 375*5d3a5ad8Srab } 3767c478bd9Sstevel@tonic-gate 3777c478bd9Sstevel@tonic-gate evsel |= evp->emask; 3787c478bd9Sstevel@tonic-gate 3797c478bd9Sstevel@tonic-gate if (flags & CPC_COUNT_USER) 3807c478bd9Sstevel@tonic-gate evsel |= OPT_PES_USR; 3817c478bd9Sstevel@tonic-gate if (flags & CPC_COUNT_SYSTEM) 3827c478bd9Sstevel@tonic-gate evsel |= OPT_PES_OS; 3837c478bd9Sstevel@tonic-gate if (flags & CPC_OVF_NOTIFY_EMT) 3847c478bd9Sstevel@tonic-gate evsel |= OPT_PES_INT; 3857c478bd9Sstevel@tonic-gate 3867c478bd9Sstevel@tonic-gate for (i = 0; i < nattrs; i++) { 3877c478bd9Sstevel@tonic-gate if (strcmp(attrs[i].ka_name, "edge") == 0) { 3887c478bd9Sstevel@tonic-gate if (attrs[i].ka_val != 0) 3897c478bd9Sstevel@tonic-gate evsel |= OPT_PES_EDGE; 3907c478bd9Sstevel@tonic-gate } else if (strcmp(attrs[i].ka_name, "pc") == 0) { 3917c478bd9Sstevel@tonic-gate if (attrs[i].ka_val != 0) 3927c478bd9Sstevel@tonic-gate evsel |= OPT_PES_PC; 3937c478bd9Sstevel@tonic-gate } else if (strcmp(attrs[i].ka_name, "inv") == 0) { 3947c478bd9Sstevel@tonic-gate if (attrs[i].ka_val != 0) 3957c478bd9Sstevel@tonic-gate evsel |= OPT_PES_INV; 3967c478bd9Sstevel@tonic-gate } else if (strcmp(attrs[i].ka_name, "cmask") == 0) { 3977c478bd9Sstevel@tonic-gate if ((attrs[i].ka_val | OPT_PES_CMASK_MASK) != 3987c478bd9Sstevel@tonic-gate OPT_PES_CMASK_MASK) 3997c478bd9Sstevel@tonic-gate return (CPC_ATTRIBUTE_OUT_OF_RANGE); 4007c478bd9Sstevel@tonic-gate evsel |= attrs[i].ka_val << OPT_PES_CMASK_SHIFT; 4017c478bd9Sstevel@tonic-gate } else if (strcmp(attrs[i].ka_name, "umask") == 0) { 4027c478bd9Sstevel@tonic-gate if ((attrs[i].ka_val | evp->umask_valid) != 4037c478bd9Sstevel@tonic-gate evp->umask_valid) 4047c478bd9Sstevel@tonic-gate return (CPC_ATTRIBUTE_OUT_OF_RANGE); 4057c478bd9Sstevel@tonic-gate evsel |= attrs[i].ka_val << OPT_PES_UMASK_SHIFT; 4067c478bd9Sstevel@tonic-gate } else 4077c478bd9Sstevel@tonic-gate return (CPC_INVALID_ATTRIBUTE); 4087c478bd9Sstevel@tonic-gate } 4097c478bd9Sstevel@tonic-gate 4107c478bd9Sstevel@tonic-gate cfg = kmem_alloc(sizeof (*cfg), KM_SLEEP); 4117c478bd9Sstevel@tonic-gate 4127c478bd9Sstevel@tonic-gate cfg->opt_picno = picnum; 4137c478bd9Sstevel@tonic-gate cfg->opt_evsel = evsel; 4147c478bd9Sstevel@tonic-gate cfg->opt_rawpic = preset & MASK48; 4157c478bd9Sstevel@tonic-gate 4167c478bd9Sstevel@tonic-gate *data = cfg; 4177c478bd9Sstevel@tonic-gate return (0); 4187c478bd9Sstevel@tonic-gate } 4197c478bd9Sstevel@tonic-gate 4207c478bd9Sstevel@tonic-gate static void 4217c478bd9Sstevel@tonic-gate opt_pcbe_program(void *token) 4227c478bd9Sstevel@tonic-gate { 4237c478bd9Sstevel@tonic-gate opt_pcbe_config_t *cfgs[4] = { &nullcfgs[0], &nullcfgs[1], 4247c478bd9Sstevel@tonic-gate &nullcfgs[2], &nullcfgs[3] }; 4257c478bd9Sstevel@tonic-gate opt_pcbe_config_t *pcfg = NULL; 4267c478bd9Sstevel@tonic-gate int i; 4277c478bd9Sstevel@tonic-gate uint32_t curcr4 = getcr4(); 4287c478bd9Sstevel@tonic-gate 4297c478bd9Sstevel@tonic-gate /* 4307c478bd9Sstevel@tonic-gate * Allow nonprivileged code to read the performance counters if desired. 4317c478bd9Sstevel@tonic-gate */ 4327c478bd9Sstevel@tonic-gate if (kcpc_allow_nonpriv(token)) 4337c478bd9Sstevel@tonic-gate setcr4(curcr4 | CR4_PCE); 4347c478bd9Sstevel@tonic-gate else 4357c478bd9Sstevel@tonic-gate setcr4(curcr4 & ~CR4_PCE); 4367c478bd9Sstevel@tonic-gate 4377c478bd9Sstevel@tonic-gate /* 4387c478bd9Sstevel@tonic-gate * Query kernel for all configs which will be co-programmed. 4397c478bd9Sstevel@tonic-gate */ 4407c478bd9Sstevel@tonic-gate do { 4417c478bd9Sstevel@tonic-gate pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, NULL); 4427c478bd9Sstevel@tonic-gate 4437c478bd9Sstevel@tonic-gate if (pcfg != NULL) { 4447c478bd9Sstevel@tonic-gate ASSERT(pcfg->opt_picno < 4); 4457c478bd9Sstevel@tonic-gate cfgs[pcfg->opt_picno] = pcfg; 4467c478bd9Sstevel@tonic-gate } 4477c478bd9Sstevel@tonic-gate } while (pcfg != NULL); 4487c478bd9Sstevel@tonic-gate 4497c478bd9Sstevel@tonic-gate /* 4507c478bd9Sstevel@tonic-gate * Program in two loops. The first configures and presets the counter, 4517c478bd9Sstevel@tonic-gate * and the second loop enables the counters. This ensures that the 4527c478bd9Sstevel@tonic-gate * counters are all enabled as closely together in time as possible. 4537c478bd9Sstevel@tonic-gate */ 4547c478bd9Sstevel@tonic-gate 4557c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) { 4560ac7d7d8Skucharsk wrmsr(PES_BASE_ADDR + i, cfgs[i]->opt_evsel); 4570ac7d7d8Skucharsk wrmsr(PIC_BASE_ADDR + i, cfgs[i]->opt_rawpic); 4587c478bd9Sstevel@tonic-gate } 4597c478bd9Sstevel@tonic-gate 4607c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) { 4610ac7d7d8Skucharsk wrmsr(PES_BASE_ADDR + i, cfgs[i]->opt_evsel | 4620ac7d7d8Skucharsk (uint64_t)(uintptr_t)OPT_PES_ENABLE); 4637c478bd9Sstevel@tonic-gate } 4647c478bd9Sstevel@tonic-gate } 4657c478bd9Sstevel@tonic-gate 4667c478bd9Sstevel@tonic-gate static void 4677c478bd9Sstevel@tonic-gate opt_pcbe_allstop(void) 4687c478bd9Sstevel@tonic-gate { 4697c478bd9Sstevel@tonic-gate int i; 4707c478bd9Sstevel@tonic-gate 4717c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) 4720ac7d7d8Skucharsk wrmsr(PES_BASE_ADDR + i, 0ULL); 4737c478bd9Sstevel@tonic-gate 4747c478bd9Sstevel@tonic-gate /* 4757c478bd9Sstevel@tonic-gate * Disable non-privileged access to the counter registers. 4767c478bd9Sstevel@tonic-gate */ 4777c478bd9Sstevel@tonic-gate setcr4((uint32_t)getcr4() & ~CR4_PCE); 4787c478bd9Sstevel@tonic-gate } 4797c478bd9Sstevel@tonic-gate 4807c478bd9Sstevel@tonic-gate static void 4817c478bd9Sstevel@tonic-gate opt_pcbe_sample(void *token) 4827c478bd9Sstevel@tonic-gate { 4837c478bd9Sstevel@tonic-gate opt_pcbe_config_t *cfgs[4] = { NULL, NULL, NULL, NULL }; 4847c478bd9Sstevel@tonic-gate opt_pcbe_config_t *pcfg = NULL; 4857c478bd9Sstevel@tonic-gate int i; 4867c478bd9Sstevel@tonic-gate uint64_t curpic[4]; 4877c478bd9Sstevel@tonic-gate uint64_t *addrs[4]; 4887c478bd9Sstevel@tonic-gate uint64_t *tmp; 4897c478bd9Sstevel@tonic-gate int64_t diff; 4907c478bd9Sstevel@tonic-gate 4917c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) 49293d449f8Skucharsk curpic[i] = rdmsr(PIC_BASE_ADDR + i); 4937c478bd9Sstevel@tonic-gate 4947c478bd9Sstevel@tonic-gate /* 4957c478bd9Sstevel@tonic-gate * Query kernel for all configs which are co-programmed. 4967c478bd9Sstevel@tonic-gate */ 4977c478bd9Sstevel@tonic-gate do { 4987c478bd9Sstevel@tonic-gate pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, &tmp); 4997c478bd9Sstevel@tonic-gate 5007c478bd9Sstevel@tonic-gate if (pcfg != NULL) { 5017c478bd9Sstevel@tonic-gate ASSERT(pcfg->opt_picno < 4); 5027c478bd9Sstevel@tonic-gate cfgs[pcfg->opt_picno] = pcfg; 5037c478bd9Sstevel@tonic-gate addrs[pcfg->opt_picno] = tmp; 5047c478bd9Sstevel@tonic-gate } 5057c478bd9Sstevel@tonic-gate } while (pcfg != NULL); 5067c478bd9Sstevel@tonic-gate 5077c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) { 5087c478bd9Sstevel@tonic-gate if (cfgs[i] == NULL) 5097c478bd9Sstevel@tonic-gate continue; 5107c478bd9Sstevel@tonic-gate 5117c478bd9Sstevel@tonic-gate diff = (curpic[i] - cfgs[i]->opt_rawpic) & MASK48; 5127c478bd9Sstevel@tonic-gate *addrs[i] += diff; 5137c478bd9Sstevel@tonic-gate DTRACE_PROBE4(opt__pcbe__sample, int, i, uint64_t, *addrs[i], 5147c478bd9Sstevel@tonic-gate uint64_t, curpic[i], uint64_t, cfgs[i]->opt_rawpic); 5157c478bd9Sstevel@tonic-gate cfgs[i]->opt_rawpic = *addrs[i] & MASK48; 5167c478bd9Sstevel@tonic-gate } 5177c478bd9Sstevel@tonic-gate } 5187c478bd9Sstevel@tonic-gate 5197c478bd9Sstevel@tonic-gate static void 5207c478bd9Sstevel@tonic-gate opt_pcbe_free(void *config) 5217c478bd9Sstevel@tonic-gate { 5227c478bd9Sstevel@tonic-gate kmem_free(config, sizeof (opt_pcbe_config_t)); 5237c478bd9Sstevel@tonic-gate } 5247c478bd9Sstevel@tonic-gate 5257c478bd9Sstevel@tonic-gate 5267c478bd9Sstevel@tonic-gate static struct modlpcbe modlpcbe = { 5277c478bd9Sstevel@tonic-gate &mod_pcbeops, 5287c478bd9Sstevel@tonic-gate "AMD Performance Counters v%I%", 5297c478bd9Sstevel@tonic-gate &opt_pcbe_ops 5307c478bd9Sstevel@tonic-gate }; 5317c478bd9Sstevel@tonic-gate 5327c478bd9Sstevel@tonic-gate static struct modlinkage modl = { 5337c478bd9Sstevel@tonic-gate MODREV_1, 5347c478bd9Sstevel@tonic-gate &modlpcbe, 5357c478bd9Sstevel@tonic-gate }; 5367c478bd9Sstevel@tonic-gate 5377c478bd9Sstevel@tonic-gate int 5387c478bd9Sstevel@tonic-gate _init(void) 5397c478bd9Sstevel@tonic-gate { 5407c478bd9Sstevel@tonic-gate int ret; 5417c478bd9Sstevel@tonic-gate 5427c478bd9Sstevel@tonic-gate if (opt_pcbe_init() != 0) 5437c478bd9Sstevel@tonic-gate return (ENOTSUP); 5447c478bd9Sstevel@tonic-gate 5457c478bd9Sstevel@tonic-gate if ((ret = mod_install(&modl)) != 0) 5467c478bd9Sstevel@tonic-gate kmem_free(evlist, evlist_sz + 1); 5477c478bd9Sstevel@tonic-gate 5487c478bd9Sstevel@tonic-gate return (ret); 5497c478bd9Sstevel@tonic-gate } 5507c478bd9Sstevel@tonic-gate 5517c478bd9Sstevel@tonic-gate int 5527c478bd9Sstevel@tonic-gate _fini(void) 5537c478bd9Sstevel@tonic-gate { 5547c478bd9Sstevel@tonic-gate int ret; 5557c478bd9Sstevel@tonic-gate 5567c478bd9Sstevel@tonic-gate if ((ret = mod_remove(&modl)) == 0) 5577c478bd9Sstevel@tonic-gate kmem_free(evlist, evlist_sz + 1); 5587c478bd9Sstevel@tonic-gate return (ret); 5597c478bd9Sstevel@tonic-gate } 5607c478bd9Sstevel@tonic-gate 5617c478bd9Sstevel@tonic-gate int 5627c478bd9Sstevel@tonic-gate _info(struct modinfo *mi) 5637c478bd9Sstevel@tonic-gate { 5647c478bd9Sstevel@tonic-gate return (mod_info(&modl, mi)); 5657c478bd9Sstevel@tonic-gate } 566