17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 575bcd456Sjg * Common Development and Distribution License (the "License"). 675bcd456Sjg * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22ec0c94e7SDana Myers * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #include <sys/types.h> 277c478bd9Sstevel@tonic-gate #include <sys/stat.h> 28*ffa17327SGuoli Shu #include <sys/sysmacros.h> 297c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 307c478bd9Sstevel@tonic-gate #include <sys/pci.h> 317c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h> 327c478bd9Sstevel@tonic-gate #include <sys/pci_cfgspace.h> 337c478bd9Sstevel@tonic-gate #include <sys/memlist.h> 347c478bd9Sstevel@tonic-gate #include <sys/bootconf.h> 3570025d76Sjohnny #include <io/pci/mps_table.h> 36c88420b3Sdmick #include <sys/pci_cfgspace.h> 37c88420b3Sdmick #include <sys/pci_cfgspace_impl.h> 38c88420b3Sdmick #include <sys/psw.h> 3909f67678Sanish #include "../../../../common/pci/pci_strings.h" 40c8589f13Ssethg #include <sys/apic.h> 418a5a0d1eSanish #include <io/pciex/pcie_nvidia.h> 425af4ae46Sjveta #include <io/hotplug/pciehpc/pciehpc_acpi.h> 4325145214Smyers #include <sys/acpi/acpi.h> 4425145214Smyers #include <sys/acpica.h> 4586c1f4dcSVikram Hegde #include <sys/intel_iommu.h> 4694f1124eSVikram Hegde #include <sys/iommulib.h> 477c478bd9Sstevel@tonic-gate 487c478bd9Sstevel@tonic-gate #define pci_getb (*pci_getb_func) 497c478bd9Sstevel@tonic-gate #define pci_getw (*pci_getw_func) 507c478bd9Sstevel@tonic-gate #define pci_getl (*pci_getl_func) 517c478bd9Sstevel@tonic-gate #define pci_putb (*pci_putb_func) 527c478bd9Sstevel@tonic-gate #define pci_putw (*pci_putw_func) 537c478bd9Sstevel@tonic-gate #define pci_putl (*pci_putl_func) 547c478bd9Sstevel@tonic-gate #define dcmn_err if (pci_boot_debug) cmn_err 557c478bd9Sstevel@tonic-gate 567c478bd9Sstevel@tonic-gate #define CONFIG_INFO 0 577c478bd9Sstevel@tonic-gate #define CONFIG_UPDATE 1 587c478bd9Sstevel@tonic-gate #define CONFIG_NEW 2 59bd87be88Ssethg #define CONFIG_FIX 3 6070025d76Sjohnny #define COMPAT_BUFSIZE 512 617c478bd9Sstevel@tonic-gate 6205f867c3Sgs #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 6305f867c3Sgs #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 64*ffa17327SGuoli Shu /* round down to nearest power of two */ 65*ffa17327SGuoli Shu #define P2LE(align) \ 66*ffa17327SGuoli Shu { \ 67*ffa17327SGuoli Shu int i = 0; \ 68*ffa17327SGuoli Shu while (align >>= 1) \ 69*ffa17327SGuoli Shu i ++; \ 70*ffa17327SGuoli Shu align = 1 << i; \ 71*ffa17327SGuoli Shu } \ 7205f867c3Sgs 73bd87be88Ssethg /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 74bd87be88Ssethg #define LPC_IO_CONTROL_REG_1 0x40 75bd87be88Ssethg #define AMD8111_ENABLENMI (uint8_t)0x80 76bd87be88Ssethg #define DEVID_AMD8111_LPC 0x7468 77bd87be88Ssethg 78bd87be88Ssethg struct pci_fixundo { 79bd87be88Ssethg uint8_t bus; 80bd87be88Ssethg uint8_t dev; 81bd87be88Ssethg uint8_t fn; 82bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t); 83bd87be88Ssethg struct pci_fixundo *next; 84bd87be88Ssethg }; 85bd87be88Ssethg 8605f867c3Sgs struct pci_devfunc { 8705f867c3Sgs struct pci_devfunc *next; 8805f867c3Sgs dev_info_t *dip; 8905f867c3Sgs uchar_t dev; 9005f867c3Sgs uchar_t func; 9105f867c3Sgs boolean_t reprogram; /* this device needs to be reprogrammed */ 9205f867c3Sgs }; 9305f867c3Sgs 9478323854SJudy Chen extern int pseudo_isa; 957c478bd9Sstevel@tonic-gate extern int pci_bios_nbus; 967c478bd9Sstevel@tonic-gate static uchar_t max_dev_pci = 32; /* PCI standard */ 977c478bd9Sstevel@tonic-gate int pci_boot_debug = 0; 987c478bd9Sstevel@tonic-gate extern struct memlist *find_bus_res(int, int); 99bd87be88Ssethg static struct pci_fixundo *undolist = NULL; 10005f867c3Sgs static int num_root_bus = 0; /* count of root buses */ 1018fc7923fSDana Myers extern volatile int acpi_resource_discovery; 1027c478bd9Sstevel@tonic-gate 1037c478bd9Sstevel@tonic-gate /* 1047c478bd9Sstevel@tonic-gate * Module prototypes 1057c478bd9Sstevel@tonic-gate */ 1067c478bd9Sstevel@tonic-gate static void enumerate_bus_devs(uchar_t bus, int config_op); 1077c478bd9Sstevel@tonic-gate static void create_root_bus_dip(uchar_t bus); 10805f867c3Sgs static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 1097c478bd9Sstevel@tonic-gate ushort_t, int); 1107c478bd9Sstevel@tonic-gate static void add_compatible(dev_info_t *, ushort_t, ushort_t, 11170025d76Sjohnny ushort_t, ushort_t, uchar_t, uint_t, int); 1127c478bd9Sstevel@tonic-gate static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 11349fbdd30SErwin T Tsaur static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 11449fbdd30SErwin T Tsaur ushort_t); 1157c478bd9Sstevel@tonic-gate static void add_model_prop(dev_info_t *, uint_t); 1167c478bd9Sstevel@tonic-gate static void add_bus_range_prop(int); 117b1f176e8Sjg static void add_bus_slot_names_prop(int); 1188fc7923fSDana Myers static void add_ranges_prop(int, int); 1197c478bd9Sstevel@tonic-gate static void add_bus_available_prop(int); 12049fbdd30SErwin T Tsaur static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 12105f867c3Sgs static void fix_ppb_res(uchar_t, boolean_t); 122f55ce205Sszhou static void alloc_res_array(); 123c8589f13Ssethg static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 124c8589f13Ssethg ushort_t deviceid); 125d57b3b3dSprasad static void pciex_slot_names_prop(dev_info_t *, ushort_t); 1268fc7923fSDana Myers static void populate_bus_res(uchar_t bus); 1278fc7923fSDana Myers static void memlist_remove_list(struct memlist **list, 1288fc7923fSDana Myers struct memlist *remove_list); 1297c478bd9Sstevel@tonic-gate 13075bcd456Sjg extern int pci_slot_names_prop(int, char *, int); 13175bcd456Sjg 132ee8c1d4aSdm /* set non-zero to force PCI peer-bus renumbering */ 13325145214Smyers int pci_bus_always_renumber = 0; 13425145214Smyers 1351d6b7b34SJudy Chen /* 1361d6b7b34SJudy Chen * used to register ISA resource usage which must not be made 1371d6b7b34SJudy Chen * "available" from other PCI node' resource maps 1381d6b7b34SJudy Chen */ 1391d6b7b34SJudy Chen static struct { 1401d6b7b34SJudy Chen struct memlist *io_ports_used; 1411d6b7b34SJudy Chen struct memlist *mem_space_used; 1421d6b7b34SJudy Chen } isa_res; 1431d6b7b34SJudy Chen 1447c478bd9Sstevel@tonic-gate /* 1457c478bd9Sstevel@tonic-gate * Enumerate all PCI devices 1467c478bd9Sstevel@tonic-gate */ 1477c478bd9Sstevel@tonic-gate void 1487c478bd9Sstevel@tonic-gate pci_setup_tree() 1497c478bd9Sstevel@tonic-gate { 15005043691Sjames north - Sun Microsystems - Austin United States uint_t i, root_bus_addr = 0; 1517c478bd9Sstevel@tonic-gate 152f55ce205Sszhou alloc_res_array(); 1537c478bd9Sstevel@tonic-gate for (i = 0; i <= pci_bios_nbus; i++) { 1547c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = (uchar_t)-1; 1557c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = (uchar_t)-1; 1567c478bd9Sstevel@tonic-gate pci_bus_res[i].sub_bus = i; 1577c478bd9Sstevel@tonic-gate } 1587c478bd9Sstevel@tonic-gate 1597c478bd9Sstevel@tonic-gate pci_bus_res[0].root_addr = root_bus_addr++; 1607c478bd9Sstevel@tonic-gate create_root_bus_dip(0); 1617c478bd9Sstevel@tonic-gate enumerate_bus_devs(0, CONFIG_INFO); 1627c478bd9Sstevel@tonic-gate 1637c478bd9Sstevel@tonic-gate /* 1647c478bd9Sstevel@tonic-gate * Now enumerate peer busses 1657c478bd9Sstevel@tonic-gate * 1667c478bd9Sstevel@tonic-gate * We loop till pci_bios_nbus. On most systems, there is 1677c478bd9Sstevel@tonic-gate * one more bus at the high end, which implements the ISA 1687c478bd9Sstevel@tonic-gate * compatibility bus. We don't care about that. 1697c478bd9Sstevel@tonic-gate * 1707c478bd9Sstevel@tonic-gate * Note: In the old (bootconf) enumeration, the peer bus 1717c478bd9Sstevel@tonic-gate * address did not use the bus number, and there were 1727c478bd9Sstevel@tonic-gate * too many peer busses created. The root_bus_addr is 1737c478bd9Sstevel@tonic-gate * used to maintain the old peer bus address assignment. 1747c478bd9Sstevel@tonic-gate * However, we stop enumerating phantom peers with no 1757c478bd9Sstevel@tonic-gate * device below. 1767c478bd9Sstevel@tonic-gate */ 1777c478bd9Sstevel@tonic-gate for (i = 1; i <= pci_bios_nbus; i++) { 1787c478bd9Sstevel@tonic-gate if (pci_bus_res[i].dip == NULL) { 1797c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = root_bus_addr++; 1807c478bd9Sstevel@tonic-gate } 1817c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_INFO); 182b1f176e8Sjg 183b1f176e8Sjg /* add slot-names property for named pci hot-plug slots */ 184b1f176e8Sjg add_bus_slot_names_prop(i); 1857c478bd9Sstevel@tonic-gate } 1867c478bd9Sstevel@tonic-gate 1877c478bd9Sstevel@tonic-gate } 1887c478bd9Sstevel@tonic-gate 18925145214Smyers /* 19025145214Smyers * >0 = present, 0 = not present, <0 = error 19125145214Smyers */ 19225145214Smyers static int 19325145214Smyers pci_bbn_present(int bus) 19425145214Smyers { 19525145214Smyers ACPI_HANDLE hdl; 19625145214Smyers int rv; 19725145214Smyers 19825145214Smyers /* no dip means no _BBN */ 19925145214Smyers if (pci_bus_res[bus].dip == NULL) 20025145214Smyers return (0); 20125145214Smyers 202db2bae30SDana Myers rv = -1; /* default return value in case of error below */ 203db2bae30SDana Myers if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { 204db2bae30SDana Myers switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { 205db2bae30SDana Myers case AE_OK: 206db2bae30SDana Myers rv = 1; 207db2bae30SDana Myers break; 208db2bae30SDana Myers case AE_NOT_FOUND: 209db2bae30SDana Myers rv = 0; 210db2bae30SDana Myers break; 211db2bae30SDana Myers default: 212db2bae30SDana Myers break; 213db2bae30SDana Myers } 214db2bae30SDana Myers } 21525145214Smyers 216db2bae30SDana Myers return (rv); 21725145214Smyers } 21825145214Smyers 21925145214Smyers /* 22025145214Smyers * Return non-zero if any PCI bus in the system has an associated 22125145214Smyers * _BBN object, 0 otherwise. 22225145214Smyers */ 22325145214Smyers static int 22425145214Smyers pci_roots_have_bbn(void) 22525145214Smyers { 22625145214Smyers int i; 22725145214Smyers 22825145214Smyers /* 22925145214Smyers * Scan the PCI busses and look for at least 1 _BBN 23025145214Smyers */ 23125145214Smyers for (i = 0; i <= pci_bios_nbus; i++) { 23225145214Smyers /* skip non-root (peer) PCI busses */ 23325145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 23425145214Smyers continue; 23525145214Smyers 23625145214Smyers if (pci_bbn_present(i) > 0) 23725145214Smyers return (1); 23825145214Smyers } 23925145214Smyers return (0); 24025145214Smyers 24125145214Smyers } 24225145214Smyers 24325145214Smyers /* 24425145214Smyers * return non-zero if the machine is one on which we renumber 24525145214Smyers * the internal pci unit-addresses 24625145214Smyers */ 24725145214Smyers static int 24825145214Smyers pci_bus_renumber() 24925145214Smyers { 250ee8c1d4aSdm ACPI_TABLE_HEADER *fadt; 25125145214Smyers 252ee8c1d4aSdm if (pci_bus_always_renumber) 25325145214Smyers return (1); 254ee8c1d4aSdm 255ee8c1d4aSdm /* get the FADT */ 256db2bae30SDana Myers if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != 257db2bae30SDana Myers AE_OK) 25825145214Smyers return (0); 25925145214Smyers 260ee8c1d4aSdm /* compare OEM Table ID to "SUNm31" */ 261ee8c1d4aSdm if (strncmp("SUNm31", fadt->OemId, 6)) 262ee8c1d4aSdm return (0); 263ee8c1d4aSdm else 264ee8c1d4aSdm return (1); 26525145214Smyers } 26625145214Smyers 26725145214Smyers /* 26825145214Smyers * Initial enumeration of the physical PCI bus hierarchy can 26925145214Smyers * leave 'gaps' in the order of peer PCI bus unit-addresses. 27025145214Smyers * Systems with more than one peer PCI bus *must* have an ACPI 27125145214Smyers * _BBN object associated with each peer bus; use the presence 27225145214Smyers * of this object to remove gaps in the numbering of the peer 27325145214Smyers * PCI bus unit-addresses - only peer busses with an associated 27425145214Smyers * _BBN are counted. 27525145214Smyers */ 27625145214Smyers static void 27725145214Smyers pci_renumber_root_busses(void) 27825145214Smyers { 27925145214Smyers int pci_regs[] = {0, 0, 0}; 28025145214Smyers int i, root_addr = 0; 28125145214Smyers 282ee8c1d4aSdm /* 283ee8c1d4aSdm * Currently, we only enable the re-numbering on specific 284ee8c1d4aSdm * Sun machines; this is a work-around for the more complicated 285ee8c1d4aSdm * issue of upgrade changing physical device paths 286ee8c1d4aSdm */ 28725145214Smyers if (!pci_bus_renumber()) 28825145214Smyers return; 28925145214Smyers 29025145214Smyers /* 29125145214Smyers * If we find no _BBN objects at all, we either don't need 29225145214Smyers * to do anything or can't do anything anyway 29325145214Smyers */ 29425145214Smyers if (!pci_roots_have_bbn()) 29525145214Smyers return; 29625145214Smyers 29725145214Smyers for (i = 0; i <= pci_bios_nbus; i++) { 29825145214Smyers /* skip non-root (peer) PCI busses */ 29925145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 30025145214Smyers continue; 30125145214Smyers 30225145214Smyers if (pci_bbn_present(i) < 1) { 30325145214Smyers pci_bus_res[i].root_addr = (uchar_t)-1; 30425145214Smyers continue; 30525145214Smyers } 30625145214Smyers 30725145214Smyers ASSERT(pci_bus_res[i].dip != NULL); 30825145214Smyers if (pci_bus_res[i].root_addr != root_addr) { 30925145214Smyers /* update reg property for node */ 31025145214Smyers pci_bus_res[i].root_addr = root_addr; 31125145214Smyers pci_regs[0] = pci_bus_res[i].root_addr; 31225145214Smyers (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 31325145214Smyers pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 31425145214Smyers } 31525145214Smyers root_addr++; 31625145214Smyers } 31725145214Smyers } 31825145214Smyers 31978323854SJudy Chen void 3201d6b7b34SJudy Chen pci_register_isa_resources(int type, uint32_t base, uint32_t size) 321aaba6dfeSmyers { 3221d6b7b34SJudy Chen (void) memlist_insert( 3231d6b7b34SJudy Chen (type == 1) ? &isa_res.io_ports_used : &isa_res.mem_space_used, 3241d6b7b34SJudy Chen base, size); 325aaba6dfeSmyers } 326aaba6dfeSmyers 3275af4ae46Sjveta /* 32805f867c3Sgs * Remove the resources which are already used by devices under a subtractive 32905f867c3Sgs * bridge from the bus's resources lists, because they're not available, and 33005f867c3Sgs * shouldn't be allocated to other buses. This is necessary because tracking 33105f867c3Sgs * resources for subtractive bridges is not complete. (Subtractive bridges only 33205f867c3Sgs * track some of their claimed resources, not "the rest of the address space" as 33305f867c3Sgs * they should, so that allocation to peer non-subtractive PPBs is easier. We 33405f867c3Sgs * need a fully-capable global resource allocator). 3355af4ae46Sjveta */ 33605f867c3Sgs static void 33705f867c3Sgs remove_subtractive_res() 3385af4ae46Sjveta { 33905f867c3Sgs int i, j; 34005f867c3Sgs struct memlist *list; 3415af4ae46Sjveta 34205f867c3Sgs for (i = 0; i <= pci_bios_nbus; i++) { 34305f867c3Sgs if (pci_bus_res[i].subtractive) { 34405f867c3Sgs /* remove used io ports */ 34505f867c3Sgs list = pci_bus_res[i].io_ports_used; 34605f867c3Sgs while (list) { 3478fc7923fSDana Myers for (j = 0; j <= pci_bios_nbus; j++) 3488fc7923fSDana Myers (void) memlist_remove( 3498fc7923fSDana Myers &pci_bus_res[j].io_ports, 3508fc7923fSDana Myers list->address, list->size); 35105f867c3Sgs list = list->next; 35205f867c3Sgs } 35305f867c3Sgs /* remove used mem resource */ 35405f867c3Sgs list = pci_bus_res[i].mem_space_used; 35505f867c3Sgs while (list) { 35605f867c3Sgs for (j = 0; j <= pci_bios_nbus; j++) { 3578fc7923fSDana Myers (void) memlist_remove( 3588fc7923fSDana Myers &pci_bus_res[j].mem_space, 3598fc7923fSDana Myers list->address, list->size); 3608fc7923fSDana Myers (void) memlist_remove( 3618fc7923fSDana Myers &pci_bus_res[j].pmem_space, 3628fc7923fSDana Myers list->address, list->size); 36305f867c3Sgs } 36405f867c3Sgs list = list->next; 36505f867c3Sgs } 36605f867c3Sgs /* remove used prefetchable mem resource */ 36705f867c3Sgs list = pci_bus_res[i].pmem_space_used; 36805f867c3Sgs while (list) { 36905f867c3Sgs for (j = 0; j <= pci_bios_nbus; j++) { 3708fc7923fSDana Myers (void) memlist_remove( 3718fc7923fSDana Myers &pci_bus_res[j].pmem_space, 3728fc7923fSDana Myers list->address, list->size); 3738fc7923fSDana Myers (void) memlist_remove( 3748fc7923fSDana Myers &pci_bus_res[j].mem_space, 3758fc7923fSDana Myers list->address, list->size); 37605f867c3Sgs } 37705f867c3Sgs list = list->next; 37805f867c3Sgs } 3795af4ae46Sjveta } 38005f867c3Sgs } 38105f867c3Sgs } 38205f867c3Sgs 3838fc7923fSDana Myers /* 3848fc7923fSDana Myers * Set-up (or complete the set-up) of the bus_space resource list 3858fc7923fSDana Myers */ 38605f867c3Sgs static void 38705f867c3Sgs setup_bus_res(int bus) 38805f867c3Sgs { 38905f867c3Sgs uchar_t par_bus; 39005f867c3Sgs 39105f867c3Sgs if (pci_bus_res[bus].dip == NULL) /* unused bus */ 39205f867c3Sgs return; 39305f867c3Sgs 3948fc7923fSDana Myers /* 3958fc7923fSDana Myers * Setup bus_space if not already filled-in by populate_bus_res(); 3968fc7923fSDana Myers */ 3978fc7923fSDana Myers if (pci_bus_res[bus].bus_space == NULL) { 3988fc7923fSDana Myers ASSERT(pci_bus_res[bus].sub_bus >= bus); 3998fc7923fSDana Myers memlist_insert(&pci_bus_res[bus].bus_space, bus, 4008fc7923fSDana Myers pci_bus_res[bus].sub_bus - bus + 1); 40105f867c3Sgs } 4025af4ae46Sjveta 4038fc7923fSDana Myers ASSERT(pci_bus_res[bus].bus_space != NULL); 4048fc7923fSDana Myers 40505f867c3Sgs /* 40605f867c3Sgs * Remove resources from parent bus node if this is not a 40705f867c3Sgs * root bus. 40805f867c3Sgs */ 40905f867c3Sgs par_bus = pci_bus_res[bus].par_bus; 41005f867c3Sgs if (par_bus != (uchar_t)-1) { 41105f867c3Sgs ASSERT(pci_bus_res[par_bus].bus_space != NULL); 4128fc7923fSDana Myers memlist_remove_list(&pci_bus_res[par_bus].bus_space, 4138fc7923fSDana Myers pci_bus_res[bus].bus_space); 41405f867c3Sgs } 4158fc7923fSDana Myers 4168fc7923fSDana Myers /* remove self from bus_space */; 4178fc7923fSDana Myers (void) memlist_remove(&pci_bus_res[bus].bus_space, bus, 1); 4185af4ae46Sjveta } 4195af4ae46Sjveta 42005f867c3Sgs static uint64_t 42105f867c3Sgs get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 4225af4ae46Sjveta { 42305f867c3Sgs uint64_t addr = 0; 42405f867c3Sgs uchar_t res_bus; 4255af4ae46Sjveta 42605f867c3Sgs /* 4278fc7923fSDana Myers * Skip root(peer) buses in multiple-root-bus systems when 4288fc7923fSDana Myers * ACPI resource discovery was not successfully done. 42905f867c3Sgs */ 43005f867c3Sgs if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 4318fc7923fSDana Myers (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 4325af4ae46Sjveta return (0); 4335af4ae46Sjveta 43405f867c3Sgs res_bus = parbus; 43505f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 43605f867c3Sgs if (pci_bus_res[res_bus].io_ports) 43705f867c3Sgs break; 43805f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 43905f867c3Sgs if (res_bus == (uchar_t)-1) 44005f867c3Sgs break; /* root bus already */ 44105f867c3Sgs } 4425af4ae46Sjveta 44305f867c3Sgs if (pci_bus_res[res_bus].io_ports) { 44405f867c3Sgs addr = memlist_find(&pci_bus_res[res_bus].io_ports, 44505f867c3Sgs size, align); 44605f867c3Sgs if (addr) { 44705f867c3Sgs memlist_insert(&pci_bus_res[res_bus].io_ports_used, 44805f867c3Sgs addr, size); 4498fc7923fSDana Myers 45005f867c3Sgs /* free the old resource */ 45105f867c3Sgs memlist_free_all(&pci_bus_res[bus].io_ports); 4528fc7923fSDana Myers memlist_free_all(&pci_bus_res[bus].io_ports_used); 4538fc7923fSDana Myers 45405f867c3Sgs /* add the new resource */ 45505f867c3Sgs memlist_insert(&pci_bus_res[bus].io_ports, addr, size); 45605f867c3Sgs } 4575af4ae46Sjveta } 4585af4ae46Sjveta 45905f867c3Sgs return (addr); 46005f867c3Sgs } 46105f867c3Sgs 46205f867c3Sgs static uint64_t 46305f867c3Sgs get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 46405f867c3Sgs { 46505f867c3Sgs uint64_t addr = 0; 46605f867c3Sgs uchar_t res_bus; 4675af4ae46Sjveta 4685af4ae46Sjveta /* 4698fc7923fSDana Myers * Skip root(peer) buses in multiple-root-bus systems when 4708fc7923fSDana Myers * ACPI resource discovery was not successfully done. 4715af4ae46Sjveta */ 47205f867c3Sgs if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 4738fc7923fSDana Myers (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 4745af4ae46Sjveta return (0); 4755af4ae46Sjveta 47605f867c3Sgs res_bus = parbus; 47705f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 47805f867c3Sgs if (pci_bus_res[res_bus].mem_space) 47905f867c3Sgs break; 48005f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 48105f867c3Sgs if (res_bus == (uchar_t)-1) 48205f867c3Sgs break; /* root bus already */ 48305f867c3Sgs } 48405f867c3Sgs 48505f867c3Sgs if (pci_bus_res[res_bus].mem_space) { 48605f867c3Sgs addr = memlist_find(&pci_bus_res[res_bus].mem_space, 48705f867c3Sgs size, align); 48805f867c3Sgs if (addr) { 48905f867c3Sgs memlist_insert(&pci_bus_res[res_bus].mem_space_used, 49005f867c3Sgs addr, size); 4918fc7923fSDana Myers (void) memlist_remove(&pci_bus_res[res_bus].pmem_space, 4928fc7923fSDana Myers addr, size); 4938fc7923fSDana Myers 49405f867c3Sgs /* free the old resource */ 49505f867c3Sgs memlist_free_all(&pci_bus_res[bus].mem_space); 4968fc7923fSDana Myers memlist_free_all(&pci_bus_res[bus].mem_space_used); 4978fc7923fSDana Myers 49805f867c3Sgs /* add the new resource */ 49905f867c3Sgs memlist_insert(&pci_bus_res[bus].mem_space, addr, size); 50005f867c3Sgs } 50105f867c3Sgs } 50205f867c3Sgs 50305f867c3Sgs return (addr); 5045af4ae46Sjveta } 5055af4ae46Sjveta 50649fbdd30SErwin T Tsaur /* 50749fbdd30SErwin T Tsaur * given a cap_id, return its cap_id location in config space 50849fbdd30SErwin T Tsaur */ 50949fbdd30SErwin T Tsaur static int 51049fbdd30SErwin T Tsaur get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 51149fbdd30SErwin T Tsaur { 51249fbdd30SErwin T Tsaur uint8_t curcap, cap_id_loc; 51349fbdd30SErwin T Tsaur uint16_t status; 51449fbdd30SErwin T Tsaur int location = -1; 51549fbdd30SErwin T Tsaur 51649fbdd30SErwin T Tsaur /* 51749fbdd30SErwin T Tsaur * Need to check the Status register for ECP support first. 51849fbdd30SErwin T Tsaur * Also please note that for type 1 devices, the 51949fbdd30SErwin T Tsaur * offset could change. Should support type 1 next. 52049fbdd30SErwin T Tsaur */ 52149fbdd30SErwin T Tsaur status = pci_getw(bus, dev, func, PCI_CONF_STAT); 52249fbdd30SErwin T Tsaur if (!(status & PCI_STAT_CAP)) { 52349fbdd30SErwin T Tsaur return (-1); 52449fbdd30SErwin T Tsaur } 52549fbdd30SErwin T Tsaur cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 52649fbdd30SErwin T Tsaur 52749fbdd30SErwin T Tsaur /* Walk the list of capabilities */ 52849fbdd30SErwin T Tsaur while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 52949fbdd30SErwin T Tsaur curcap = pci_getb(bus, dev, func, cap_id_loc); 53049fbdd30SErwin T Tsaur 53149fbdd30SErwin T Tsaur if (curcap == cap_id) { 53249fbdd30SErwin T Tsaur location = cap_id_loc; 53349fbdd30SErwin T Tsaur break; 53449fbdd30SErwin T Tsaur } 53549fbdd30SErwin T Tsaur cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 53649fbdd30SErwin T Tsaur } 53749fbdd30SErwin T Tsaur return (location); 53849fbdd30SErwin T Tsaur } 53949fbdd30SErwin T Tsaur 5409896aa55Sjveta /* 54105f867c3Sgs * Assign valid resources to unconfigured pci(e) bridges. We are trying 54205f867c3Sgs * to reprogram the bridge when its 54305f867c3Sgs * i) SECBUS == SUBBUS || 54405f867c3Sgs * ii) IOBASE > IOLIM || 54505f867c3Sgs * iii) MEMBASE > MEMLIM 54605f867c3Sgs * This must be done after one full pass through the PCI tree to collect 54705f867c3Sgs * all BIOS-configured resources, so that we know what resources are 54805f867c3Sgs * free and available to assign to the unconfigured PPBs. 5499896aa55Sjveta */ 5509896aa55Sjveta static void 55105f867c3Sgs fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 5529896aa55Sjveta { 5539896aa55Sjveta uchar_t bus, dev, func; 55405f867c3Sgs uchar_t parbus, subbus; 55505f867c3Sgs uint_t io_base, io_limit, mem_base, mem_limit; 556*ffa17327SGuoli Shu uint_t io_size, mem_size, io_align, mem_align; 55705f867c3Sgs uint64_t addr = 0; 5585af4ae46Sjveta int *regp = NULL; 5599896aa55Sjveta uint_t reglen; 5605af4ae46Sjveta int rv, cap_ptr, physhi; 5619896aa55Sjveta dev_info_t *dip; 56205f867c3Sgs uint16_t cmd_reg; 56305f867c3Sgs struct memlist *list; 56405f867c3Sgs 56505f867c3Sgs /* skip root (peer) PCI busses */ 56605f867c3Sgs if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 56705f867c3Sgs return; 56805f867c3Sgs 56905f867c3Sgs /* skip subtractive PPB when prog_sub is not TRUE */ 57005f867c3Sgs if (pci_bus_res[secbus].subtractive && !prog_sub) 57105f867c3Sgs return; 5729896aa55Sjveta 5739896aa55Sjveta /* some entries may be empty due to discontiguous bus numbering */ 5745af4ae46Sjveta dip = pci_bus_res[secbus].dip; 5759896aa55Sjveta if (dip == NULL) 5769896aa55Sjveta return; 5779896aa55Sjveta 5789896aa55Sjveta rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5799896aa55Sjveta "reg", ®p, ®len); 5805af4ae46Sjveta ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0); 5815af4ae46Sjveta physhi = regp[0]; 5825af4ae46Sjveta ddi_prop_free(regp); 5839896aa55Sjveta 5845af4ae46Sjveta func = (uchar_t)PCI_REG_FUNC_G(physhi); 5855af4ae46Sjveta dev = (uchar_t)PCI_REG_DEV_G(physhi); 5865af4ae46Sjveta bus = (uchar_t)PCI_REG_BUS_G(physhi); 5879896aa55Sjveta 5889896aa55Sjveta /* 58905f867c3Sgs * If pcie bridge, check to see if link is enabled 5909896aa55Sjveta */ 59149fbdd30SErwin T Tsaur cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 59249fbdd30SErwin T Tsaur if (cap_ptr != -1) { 59305f867c3Sgs cmd_reg = pci_getw(bus, dev, func, 59405f867c3Sgs (uint16_t)cap_ptr + PCIE_LINKCTL); 59505f867c3Sgs if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 59605f867c3Sgs dcmn_err(CE_NOTE, 59705f867c3Sgs "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 59805f867c3Sgs bus, dev, func); 59905f867c3Sgs return; 60005f867c3Sgs } 60105f867c3Sgs } 6029896aa55Sjveta 60305f867c3Sgs subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 60405f867c3Sgs parbus = pci_bus_res[secbus].par_bus; 60505f867c3Sgs ASSERT(parbus == bus); 606707a5600Sgs cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 6079896aa55Sjveta 6085af4ae46Sjveta /* 60905f867c3Sgs * If we have a Cardbus bridge, but no bus space 6105af4ae46Sjveta */ 61105f867c3Sgs if (pci_bus_res[secbus].num_cbb != 0 && 61205f867c3Sgs pci_bus_res[secbus].bus_space == NULL) { 61305f867c3Sgs uchar_t range; 6145af4ae46Sjveta 61505f867c3Sgs /* normally there are 2 buses under a cardbus bridge */ 61605f867c3Sgs range = pci_bus_res[secbus].num_cbb * 2; 61705f867c3Sgs 61805f867c3Sgs /* 61905f867c3Sgs * Try to find and allocate a bus-range starting at subbus+1 62005f867c3Sgs * from the parent of the PPB. 62105f867c3Sgs */ 62205f867c3Sgs for (; range != 0; range--) { 62305f867c3Sgs if (memlist_find_with_startaddr( 62405f867c3Sgs &pci_bus_res[parbus].bus_space, 62505f867c3Sgs subbus + 1, range, 1) != NULL) 62605f867c3Sgs break; /* find bus range resource at parent */ 62705f867c3Sgs } 62805f867c3Sgs if (range != 0) { 62905f867c3Sgs memlist_insert(&pci_bus_res[secbus].bus_space, 63005f867c3Sgs subbus + 1, range); 63105f867c3Sgs subbus = subbus + range; 63205f867c3Sgs pci_bus_res[secbus].sub_bus = subbus; 63305f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 63405f867c3Sgs add_bus_range_prop(secbus); 63505f867c3Sgs 63605f867c3Sgs cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 63705f867c3Sgs "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 63805f867c3Sgs secbus, subbus); 63905f867c3Sgs } 64005f867c3Sgs } 64105f867c3Sgs 64205f867c3Sgs /* 643*ffa17327SGuoli Shu * Calculate required IO size and alignment 644*ffa17327SGuoli Shu * If bus io_size is zero, we are going to assign 512 bytes per bus, 645*ffa17327SGuoli Shu * otherwise, we'll choose the maximum value of such calculation and 646*ffa17327SGuoli Shu * bus io_size. The size needs to be 4K aligned. 647*ffa17327SGuoli Shu * 648*ffa17327SGuoli Shu * We calculate alignment as the largest power of two less than the 649*ffa17327SGuoli Shu * the sum of all children's IO size requirements, because this will 650*ffa17327SGuoli Shu * align to the size of the largest child request within that size 651*ffa17327SGuoli Shu * (which is always a power of two). 65205f867c3Sgs */ 65305f867c3Sgs io_size = (subbus - secbus + 1) * 0x200; 654*ffa17327SGuoli Shu if (io_size < pci_bus_res[secbus].io_size) 655*ffa17327SGuoli Shu io_size = pci_bus_res[secbus].io_size; 656*ffa17327SGuoli Shu io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT); 657*ffa17327SGuoli Shu io_align = io_size; 658*ffa17327SGuoli Shu P2LE(io_align); 659*ffa17327SGuoli Shu 6605af4ae46Sjveta /* 661*ffa17327SGuoli Shu * Calculate required MEM size and alignment 662*ffa17327SGuoli Shu * If bus mem_size is zero, we are going to assign 1M bytes per bus, 663*ffa17327SGuoli Shu * otherwise, we'll choose the maximum value of such calculation and 664*ffa17327SGuoli Shu * bus mem_size. The size needs to be 1M aligned. 665*ffa17327SGuoli Shu * 666*ffa17327SGuoli Shu * For the alignment, refer to the I/O comment above. 6675af4ae46Sjveta */ 66805f867c3Sgs mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 669*ffa17327SGuoli Shu if (mem_size < pci_bus_res[secbus].mem_size) { 670*ffa17327SGuoli Shu mem_size = pci_bus_res[secbus].mem_size; 671*ffa17327SGuoli Shu mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT); 672*ffa17327SGuoli Shu } 673*ffa17327SGuoli Shu mem_align = mem_size; 674*ffa17327SGuoli Shu P2LE(mem_align); 67505f867c3Sgs 67605f867c3Sgs /* Subtractive bridge */ 67705f867c3Sgs if (pci_bus_res[secbus].subtractive && prog_sub) { 67805f867c3Sgs /* 67905f867c3Sgs * We program an arbitrary amount of I/O and memory resource 68005f867c3Sgs * for the subtractive bridge so that child dynamic-resource- 68105f867c3Sgs * allocating devices (such as Cardbus bridges) have a chance 68205f867c3Sgs * of success. Until we have full-tree resource rebalancing, 68305f867c3Sgs * dynamic resource allocation (thru busra) only looks at the 68405f867c3Sgs * parent bridge, so all PPBs must have some allocatable 68505f867c3Sgs * resource. For non-subtractive bridges, the resources come 68605f867c3Sgs * from the base/limit register "windows", but subtractive 68705f867c3Sgs * bridges often don't program those (since they don't need to). 68805f867c3Sgs * If we put all the remaining resources on the subtractive 68905f867c3Sgs * bridge, then peer non-subtractive bridges can't allocate 69005f867c3Sgs * more space (even though this is probably most correct). 69105f867c3Sgs * If we put the resources only on the parent, then allocations 69205f867c3Sgs * from children of subtractive bridges will fail without 69305f867c3Sgs * special-case code for bypassing the subtractive bridge. 69405f867c3Sgs * This solution is the middle-ground temporary solution until 69505f867c3Sgs * we have fully-capable resource allocation. 69605f867c3Sgs */ 69705f867c3Sgs 69805f867c3Sgs /* 69905f867c3Sgs * Add an arbitrary I/O resource to the subtractive PPB 70005f867c3Sgs */ 70105f867c3Sgs if (pci_bus_res[secbus].io_ports == NULL) { 70205f867c3Sgs addr = get_parbus_io_res(parbus, secbus, io_size, 703*ffa17327SGuoli Shu io_align); 70405f867c3Sgs if (addr) { 7058fc7923fSDana Myers add_ranges_prop(secbus, 1); 70605f867c3Sgs pci_bus_res[secbus].io_reprogram = 70705f867c3Sgs pci_bus_res[parbus].io_reprogram; 70805f867c3Sgs 70905f867c3Sgs cmn_err(CE_NOTE, "!add io-range on subtractive" 71005f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 71105f867c3Sgs bus, dev, func, (uint32_t)addr, 71205f867c3Sgs (uint32_t)addr + io_size - 1); 71305f867c3Sgs } 71405f867c3Sgs } 71505f867c3Sgs /* 71605f867c3Sgs * Add an arbitrary memory resource to the subtractive PPB 71705f867c3Sgs */ 71805f867c3Sgs if (pci_bus_res[secbus].mem_space == NULL) { 71905f867c3Sgs addr = get_parbus_mem_res(parbus, secbus, mem_size, 720*ffa17327SGuoli Shu mem_align); 72105f867c3Sgs if (addr) { 7228fc7923fSDana Myers add_ranges_prop(secbus, 1); 72305f867c3Sgs pci_bus_res[secbus].mem_reprogram = 72405f867c3Sgs pci_bus_res[parbus].mem_reprogram; 72505f867c3Sgs 72605f867c3Sgs cmn_err(CE_NOTE, "!add mem-range on " 72705f867c3Sgs "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 72805f867c3Sgs bus, dev, func, (uint32_t)addr, 72905f867c3Sgs (uint32_t)addr + mem_size - 1); 73005f867c3Sgs } 73105f867c3Sgs } 73205f867c3Sgs 73305f867c3Sgs goto cmd_enable; 7345af4ae46Sjveta } 73505f867c3Sgs 73605f867c3Sgs /* 737707a5600Sgs * Check to see if we need to reprogram I/O space, either because the 738707a5600Sgs * parent bus needed reprogramming and so do we, or because I/O space is 739707a5600Sgs * disabled in base/limit or command register. 74005f867c3Sgs */ 74105f867c3Sgs io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 74205f867c3Sgs io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 74305f867c3Sgs io_base = (io_base & 0xf0) << 8; 74405f867c3Sgs io_limit = ((io_limit & 0xf0) << 8) | 0xfff; 74505f867c3Sgs 746707a5600Sgs if (pci_bus_res[parbus].io_reprogram || (io_base > io_limit) || 747707a5600Sgs (!(cmd_reg & PCI_COMM_IO))) { 74805f867c3Sgs if (pci_bus_res[secbus].io_ports_used) { 74905f867c3Sgs memlist_merge(&pci_bus_res[secbus].io_ports_used, 75005f867c3Sgs &pci_bus_res[secbus].io_ports); 75105f867c3Sgs } 75205f867c3Sgs if (pci_bus_res[secbus].io_ports && 75305f867c3Sgs (!pci_bus_res[parbus].io_reprogram) && 75405f867c3Sgs (!pci_bus_res[parbus].subtractive)) { 75505f867c3Sgs /* rechoose old io ports info */ 75605f867c3Sgs list = pci_bus_res[secbus].io_ports; 75705f867c3Sgs io_base = (uint_t)list->address; 75805f867c3Sgs /* 4K aligned */ 75905f867c3Sgs io_base = io_base & (~(PPB_IO_ALIGNMENT - 1)); 76005f867c3Sgs io_limit = (uint_t)(list->address + list->size); 76105f867c3Sgs while (list->next) { 76205f867c3Sgs list = list->next; 76305f867c3Sgs if ((list->address + list->size) > io_limit) 76405f867c3Sgs io_limit = (uint_t) 76505f867c3Sgs (list->address + list->size); 76605f867c3Sgs } 76705f867c3Sgs io_limit = io_limit - 1; 76805f867c3Sgs /* 4K aligned */ 76905f867c3Sgs io_limit = (io_limit + PPB_IO_ALIGNMENT) & 77005f867c3Sgs (~(PPB_IO_ALIGNMENT - 1)); 77105f867c3Sgs io_size = io_limit - io_base; 77205f867c3Sgs io_limit = io_limit - 1; 77305f867c3Sgs ASSERT(io_base <= io_limit); 77405f867c3Sgs memlist_free_all(&pci_bus_res[secbus].io_ports); 77505f867c3Sgs memlist_insert(&pci_bus_res[secbus].io_ports, 77605f867c3Sgs io_base, io_size); 77705f867c3Sgs memlist_insert(&pci_bus_res[parbus].io_ports_used, 77805f867c3Sgs io_base, io_size); 7798fc7923fSDana Myers (void) memlist_remove(&pci_bus_res[parbus].io_ports, 7808fc7923fSDana Myers io_base, io_size); 78105f867c3Sgs pci_bus_res[secbus].io_reprogram = B_TRUE; 78205f867c3Sgs } else { 78305f867c3Sgs /* get new io ports from parent bus */ 78405f867c3Sgs addr = get_parbus_io_res(parbus, secbus, io_size, 785*ffa17327SGuoli Shu io_align); 78605f867c3Sgs if (addr) { 78705f867c3Sgs io_base = addr; 78805f867c3Sgs io_limit = addr + io_size - 1; 78905f867c3Sgs pci_bus_res[secbus].io_reprogram = B_TRUE; 79005f867c3Sgs } 79105f867c3Sgs } 79205f867c3Sgs if (pci_bus_res[secbus].io_reprogram) { 79305f867c3Sgs /* reprogram PPB regs */ 79405f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 79505f867c3Sgs (uchar_t)((io_base>>8) & 0xf0)); 79605f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 79705f867c3Sgs (uchar_t)((io_limit>>8) & 0xf0)); 79805f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 79905f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 8008fc7923fSDana Myers add_ranges_prop(secbus, 1); 80105f867c3Sgs 80205f867c3Sgs cmn_err(CE_NOTE, "!reprogram io-range on" 80305f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 80405f867c3Sgs bus, dev, func, io_base, io_limit); 80505f867c3Sgs } 8069896aa55Sjveta } 8079896aa55Sjveta 8085af4ae46Sjveta /* 809707a5600Sgs * Check memory space as we did I/O space. 8105af4ae46Sjveta */ 81105f867c3Sgs mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 81205f867c3Sgs mem_base = (mem_base & 0xfff0) << 16; 81305f867c3Sgs mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 814707a5600Sgs mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 815707a5600Sgs 816707a5600Sgs if (pci_bus_res[parbus].mem_reprogram || (mem_base > mem_limit) || 817707a5600Sgs (!(cmd_reg & PCI_COMM_MAE))) { 81805f867c3Sgs if (pci_bus_res[secbus].mem_space_used) { 81905f867c3Sgs memlist_merge(&pci_bus_res[secbus].mem_space_used, 82005f867c3Sgs &pci_bus_res[secbus].mem_space); 82105f867c3Sgs } 82205f867c3Sgs if (pci_bus_res[secbus].mem_space && 82305f867c3Sgs (!pci_bus_res[parbus].mem_reprogram) && 82405f867c3Sgs (!pci_bus_res[parbus].subtractive)) { 82505f867c3Sgs /* rechoose old mem resource */ 82605f867c3Sgs list = pci_bus_res[secbus].mem_space; 82705f867c3Sgs mem_base = (uint_t)list->address; 82805f867c3Sgs /* 1M aligned */ 82905f867c3Sgs mem_base = mem_base & (~0xfffff); 83005f867c3Sgs mem_limit = (uint_t)(list->address + list->size); 83105f867c3Sgs while (list->next) { 83205f867c3Sgs list = list->next; 83305f867c3Sgs if ((list->address + list->size) > mem_limit) 83405f867c3Sgs mem_limit = (uint_t) 83505f867c3Sgs (list->address + list->size); 83605f867c3Sgs } 83705f867c3Sgs mem_limit = mem_limit - 1; 83805f867c3Sgs /* 1M aligned */ 83905f867c3Sgs mem_limit = (mem_limit + PPB_MEM_ALIGNMENT) & 84005f867c3Sgs (~(PPB_MEM_ALIGNMENT - 1)); 84105f867c3Sgs mem_size = mem_limit - mem_base; 84205f867c3Sgs mem_limit = mem_limit - 1; 84305f867c3Sgs ASSERT(mem_base <= mem_limit); 84405f867c3Sgs memlist_free_all(&pci_bus_res[secbus].mem_space); 84505f867c3Sgs memlist_insert(&pci_bus_res[secbus].mem_space, 84605f867c3Sgs mem_base, mem_size); 84705f867c3Sgs memlist_insert(&pci_bus_res[parbus].mem_space_used, 84805f867c3Sgs mem_base, mem_size); 8498fc7923fSDana Myers (void) memlist_remove(&pci_bus_res[parbus].mem_space, 8508fc7923fSDana Myers mem_base, mem_size); 85105f867c3Sgs pci_bus_res[secbus].mem_reprogram = B_TRUE; 85205f867c3Sgs } else { 85305f867c3Sgs /* get new mem resource from parent bus */ 85405f867c3Sgs addr = get_parbus_mem_res(parbus, secbus, mem_size, 855*ffa17327SGuoli Shu mem_align); 85605f867c3Sgs if (addr) { 85705f867c3Sgs mem_base = addr; 85805f867c3Sgs mem_limit = addr + mem_size - 1; 85905f867c3Sgs pci_bus_res[secbus].mem_reprogram = B_TRUE; 86005f867c3Sgs } 86105f867c3Sgs } 86205f867c3Sgs 86305f867c3Sgs if (pci_bus_res[secbus].mem_reprogram) { 86402c2c4edSGuoli Shu /* reprogram PPB MEM regs */ 86505f867c3Sgs pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 86605f867c3Sgs (uint16_t)((mem_base>>16) & 0xfff0)); 86705f867c3Sgs pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 86805f867c3Sgs (uint16_t)((mem_limit>>16) & 0xfff0)); 86902c2c4edSGuoli Shu /* 87002c2c4edSGuoli Shu * Disable PMEM window by setting base > limit. 87102c2c4edSGuoli Shu * We currently don't reprogram the PMEM like we've 87202c2c4edSGuoli Shu * done for I/O and MEM. (Devices that support prefetch 87302c2c4edSGuoli Shu * can use non-prefetch MEM.) Anyway, if the MEM access 87402c2c4edSGuoli Shu * bit is initially disabled by BIOS, we disable the 87502c2c4edSGuoli Shu * PMEM window manually by setting PMEM base > PMEM 87602c2c4edSGuoli Shu * limit here, in case there are incorrect values in 87702c2c4edSGuoli Shu * them from BIOS, so that we won't get in trouble once 87802c2c4edSGuoli Shu * the MEM access bit is enabled at the end of this 87902c2c4edSGuoli Shu * function. 88002c2c4edSGuoli Shu */ 88102c2c4edSGuoli Shu if (!(cmd_reg & PCI_COMM_MAE)) { 88202c2c4edSGuoli Shu pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 88302c2c4edSGuoli Shu 0xfff0); 88402c2c4edSGuoli Shu pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 88502c2c4edSGuoli Shu 0x0); 88602c2c4edSGuoli Shu pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 88702c2c4edSGuoli Shu 0xffffffff); 88802c2c4edSGuoli Shu pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 88902c2c4edSGuoli Shu 0x0); 89002c2c4edSGuoli Shu } 89102c2c4edSGuoli Shu 8928fc7923fSDana Myers add_ranges_prop(secbus, 1); 89305f867c3Sgs 89405f867c3Sgs cmn_err(CE_NOTE, "!reprogram mem-range on" 89505f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 89605f867c3Sgs bus, dev, func, mem_base, mem_limit); 89705f867c3Sgs } 89805f867c3Sgs } 89905f867c3Sgs 90005f867c3Sgs cmd_enable: 90105f867c3Sgs if (pci_bus_res[secbus].io_ports) 90205f867c3Sgs cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 90305f867c3Sgs if (pci_bus_res[secbus].mem_space) 90405f867c3Sgs cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 90505f867c3Sgs pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 9069896aa55Sjveta } 9079896aa55Sjveta 9087c478bd9Sstevel@tonic-gate void 9097c478bd9Sstevel@tonic-gate pci_reprogram(void) 9107c478bd9Sstevel@tonic-gate { 9117c478bd9Sstevel@tonic-gate int i, pci_reconfig = 1; 9127c478bd9Sstevel@tonic-gate char *onoff; 9138fc7923fSDana Myers int bus; 9147c478bd9Sstevel@tonic-gate 91525145214Smyers /* 91625145214Smyers * Excise phantom roots if possible 91725145214Smyers */ 91825145214Smyers pci_renumber_root_busses(); 91925145214Smyers 9208fc7923fSDana Myers /* 9218fc7923fSDana Myers * Do root-bus resource discovery 9228fc7923fSDana Myers */ 9238fc7923fSDana Myers for (bus = 0; bus <= pci_bios_nbus; bus++) { 9248fc7923fSDana Myers /* skip non-root (peer) PCI busses */ 9258fc7923fSDana Myers if (pci_bus_res[bus].par_bus != (uchar_t)-1) 9268fc7923fSDana Myers continue; 9278fc7923fSDana Myers 9288fc7923fSDana Myers /* 9298fc7923fSDana Myers * 1. find resources associated with this root bus 9308fc7923fSDana Myers */ 9318fc7923fSDana Myers populate_bus_res(bus); 9328fc7923fSDana Myers 9338fc7923fSDana Myers 9348fc7923fSDana Myers /* 9351d6b7b34SJudy Chen * 2. Remove used PCI and ISA resources from bus resource map 9368fc7923fSDana Myers */ 9378fc7923fSDana Myers 9388fc7923fSDana Myers memlist_remove_list(&pci_bus_res[bus].io_ports, 9398fc7923fSDana Myers pci_bus_res[bus].io_ports_used); 9408fc7923fSDana Myers memlist_remove_list(&pci_bus_res[bus].mem_space, 9418fc7923fSDana Myers pci_bus_res[bus].mem_space_used); 9428fc7923fSDana Myers memlist_remove_list(&pci_bus_res[bus].pmem_space, 9438fc7923fSDana Myers pci_bus_res[bus].pmem_space_used); 9448fc7923fSDana Myers memlist_remove_list(&pci_bus_res[bus].mem_space, 9458fc7923fSDana Myers pci_bus_res[bus].pmem_space_used); 9468fc7923fSDana Myers memlist_remove_list(&pci_bus_res[bus].pmem_space, 9478fc7923fSDana Myers pci_bus_res[bus].mem_space_used); 9481d6b7b34SJudy Chen 9491d6b7b34SJudy Chen memlist_remove_list(&pci_bus_res[bus].io_ports, 9501d6b7b34SJudy Chen isa_res.io_ports_used); 9511d6b7b34SJudy Chen memlist_remove_list(&pci_bus_res[bus].mem_space, 9521d6b7b34SJudy Chen isa_res.mem_space_used); 9538fc7923fSDana Myers } 9548fc7923fSDana Myers 9551d6b7b34SJudy Chen memlist_free_all(&isa_res.io_ports_used); 9561d6b7b34SJudy Chen memlist_free_all(&isa_res.mem_space_used); 9578fc7923fSDana Myers 958fc396574Srw /* add bus-range property for root/peer bus nodes */ 959fc396574Srw for (i = 0; i <= pci_bios_nbus; i++) { 9608fc7923fSDana Myers /* create bus-range property on root/peer buses */ 9618fc7923fSDana Myers if (pci_bus_res[i].par_bus == (uchar_t)-1) 962fc396574Srw add_bus_range_prop(i); 9638fc7923fSDana Myers 96405f867c3Sgs /* setup bus range resource on each bus */ 96505f867c3Sgs setup_bus_res(i); 966fc396574Srw } 967fc396574Srw 9687c478bd9Sstevel@tonic-gate if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 9697c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 9707c478bd9Sstevel@tonic-gate if (strcmp(onoff, "off") == 0) { 9717c478bd9Sstevel@tonic-gate pci_reconfig = 0; 9727c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, "pci device reprogramming disabled"); 9737c478bd9Sstevel@tonic-gate } 9747c478bd9Sstevel@tonic-gate ddi_prop_free(onoff); 9757c478bd9Sstevel@tonic-gate } 9767c478bd9Sstevel@tonic-gate 97705f867c3Sgs remove_subtractive_res(); 97805f867c3Sgs 97905f867c3Sgs /* reprogram the non-subtractive PPB */ 98005f867c3Sgs if (pci_reconfig) 98105f867c3Sgs for (i = 0; i <= pci_bios_nbus; i++) 98205f867c3Sgs fix_ppb_res(i, B_FALSE); 983aaba6dfeSmyers 9847c478bd9Sstevel@tonic-gate for (i = 0; i <= pci_bios_nbus; i++) { 98505f867c3Sgs /* configure devices not configured by BIOS */ 9869896aa55Sjveta if (pci_reconfig) { 98705f867c3Sgs /* 98805f867c3Sgs * Reprogram the subtractive PPB. At this time, all its 98905f867c3Sgs * siblings should have got their resources already. 99005f867c3Sgs */ 99105f867c3Sgs if (pci_bus_res[i].subtractive) 99205f867c3Sgs fix_ppb_res(i, B_TRUE); 9937c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_NEW); 9949896aa55Sjveta } 9958fc7923fSDana Myers } 9968fc7923fSDana Myers 9978fc7923fSDana Myers /* All dev programmed, so we can create available prop */ 9988fc7923fSDana Myers for (i = 0; i <= pci_bios_nbus; i++) 9997c478bd9Sstevel@tonic-gate add_bus_available_prop(i); 10008fc7923fSDana Myers } 10018fc7923fSDana Myers 10028fc7923fSDana Myers /* 10038fc7923fSDana Myers * populate bus resources 10048fc7923fSDana Myers */ 10058fc7923fSDana Myers static void 10068fc7923fSDana Myers populate_bus_res(uchar_t bus) 10078fc7923fSDana Myers { 10088fc7923fSDana Myers 10098fc7923fSDana Myers /* scan BIOS structures */ 10108fc7923fSDana Myers pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 10118fc7923fSDana Myers pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 10128fc7923fSDana Myers pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 10138fc7923fSDana Myers pci_bus_res[bus].bus_space = find_bus_res(bus, BUSRANGE_TYPE); 10148fc7923fSDana Myers 10156b57bdc9SDana Myers /* 10166b57bdc9SDana Myers * attempt to initialize sub_bus from the largest range-end 10176b57bdc9SDana Myers * in the bus_space list 10186b57bdc9SDana Myers */ 10196b57bdc9SDana Myers if (pci_bus_res[bus].bus_space != NULL) { 10206b57bdc9SDana Myers struct memlist *entry; 10216b57bdc9SDana Myers int current; 10226b57bdc9SDana Myers 10236b57bdc9SDana Myers entry = pci_bus_res[bus].bus_space; 10246b57bdc9SDana Myers while (entry != NULL) { 10256b57bdc9SDana Myers current = entry->address + entry->size - 1; 10266b57bdc9SDana Myers if (current > pci_bus_res[bus].sub_bus) 10276b57bdc9SDana Myers pci_bus_res[bus].sub_bus = current; 10286b57bdc9SDana Myers entry = entry->next; 10296b57bdc9SDana Myers } 10306b57bdc9SDana Myers } 10316b57bdc9SDana Myers 10328fc7923fSDana Myers if (bus == 0) { 10338fc7923fSDana Myers /* 10348fc7923fSDana Myers * Special treatment of bus 0: 10358fc7923fSDana Myers * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy 10368fc7923fSDana Myers * pcimem from boot and make I/O space the entire range 10376b57bdc9SDana Myers * starting at 0x100. 10388fc7923fSDana Myers */ 10398fc7923fSDana Myers if (pci_bus_res[0].mem_space == NULL) 10408fc7923fSDana Myers pci_bus_res[0].mem_space = 10418fc7923fSDana Myers memlist_dup(bootops->boot_mem->pcimem); 10428fc7923fSDana Myers /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 10438fc7923fSDana Myers if (pci_bus_res[0].io_ports == NULL) 10448fc7923fSDana Myers memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff); 10457c478bd9Sstevel@tonic-gate } 10468fc7923fSDana Myers 10478fc7923fSDana Myers /* 10488fc7923fSDana Myers * Create 'ranges' property here before any resources are 10498fc7923fSDana Myers * removed from the resource lists 10508fc7923fSDana Myers */ 10518fc7923fSDana Myers add_ranges_prop(bus, 0); 10527c478bd9Sstevel@tonic-gate } 10537c478bd9Sstevel@tonic-gate 10548fc7923fSDana Myers 10557c478bd9Sstevel@tonic-gate /* 10567c478bd9Sstevel@tonic-gate * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 10577c478bd9Sstevel@tonic-gate */ 10587c478bd9Sstevel@tonic-gate static void 10597c478bd9Sstevel@tonic-gate create_root_bus_dip(uchar_t bus) 10607c478bd9Sstevel@tonic-gate { 10617c478bd9Sstevel@tonic-gate int pci_regs[] = {0, 0, 0}; 10627c478bd9Sstevel@tonic-gate dev_info_t *dip; 10637c478bd9Sstevel@tonic-gate 10647c478bd9Sstevel@tonic-gate ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 10657c478bd9Sstevel@tonic-gate 106605f867c3Sgs num_root_bus++; 10677c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1068fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &dip); 10697c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 10707c478bd9Sstevel@tonic-gate "#address-cells", 3); 10717c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 10727c478bd9Sstevel@tonic-gate "#size-cells", 2); 10737c478bd9Sstevel@tonic-gate pci_regs[0] = pci_bus_res[bus].root_addr; 10747c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 10757c478bd9Sstevel@tonic-gate "reg", (int *)pci_regs, 3); 10767c478bd9Sstevel@tonic-gate 107770025d76Sjohnny /* 107870025d76Sjohnny * If system has PCIe bus, then create different properties 107970025d76Sjohnny */ 108070025d76Sjohnny if (create_pcie_root_bus(bus, dip) == B_FALSE) 108170025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 108270025d76Sjohnny "device_type", "pci"); 108370025d76Sjohnny 10847c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 10857c478bd9Sstevel@tonic-gate pci_bus_res[bus].dip = dip; 10867c478bd9Sstevel@tonic-gate } 10877c478bd9Sstevel@tonic-gate 10887c478bd9Sstevel@tonic-gate /* 10897c478bd9Sstevel@tonic-gate * For any fixed configuration (often compatability) pci devices 10907c478bd9Sstevel@tonic-gate * and those with their own expansion rom, create device nodes 10917c478bd9Sstevel@tonic-gate * to hold the already configured device details. 10927c478bd9Sstevel@tonic-gate */ 10937c478bd9Sstevel@tonic-gate void 10947c478bd9Sstevel@tonic-gate enumerate_bus_devs(uchar_t bus, int config_op) 10957c478bd9Sstevel@tonic-gate { 10967c478bd9Sstevel@tonic-gate uchar_t dev, func, nfunc, header; 10977c478bd9Sstevel@tonic-gate ushort_t venid; 109805f867c3Sgs struct pci_devfunc *devlist = NULL, *entry; 10997c478bd9Sstevel@tonic-gate 11007c478bd9Sstevel@tonic-gate if (config_op == CONFIG_NEW) { 11017c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1102bd87be88Ssethg } else if (config_op == CONFIG_FIX) { 1103bd87be88Ssethg dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 11047c478bd9Sstevel@tonic-gate } else 11057c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 11067c478bd9Sstevel@tonic-gate 11078fc7923fSDana Myers if (config_op == CONFIG_NEW) { 11088fc7923fSDana Myers devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 11098fc7923fSDana Myers while (devlist) { 11108fc7923fSDana Myers entry = devlist; 11118fc7923fSDana Myers devlist = entry->next; 11128fc7923fSDana Myers if (entry->reprogram || 11138fc7923fSDana Myers pci_bus_res[bus].io_reprogram || 11148fc7923fSDana Myers pci_bus_res[bus].mem_reprogram) { 11158fc7923fSDana Myers /* reprogram device(s) */ 11168fc7923fSDana Myers (void) add_reg_props(entry->dip, bus, 11178fc7923fSDana Myers entry->dev, entry->func, CONFIG_NEW, 0); 11188fc7923fSDana Myers } 11198fc7923fSDana Myers kmem_free(entry, sizeof (*entry)); 11208fc7923fSDana Myers } 11218fc7923fSDana Myers pci_bus_res[bus].privdata = NULL; 11228fc7923fSDana Myers return; 11238fc7923fSDana Myers } 11248fc7923fSDana Myers 11257c478bd9Sstevel@tonic-gate for (dev = 0; dev < max_dev_pci; dev++) { 11267c478bd9Sstevel@tonic-gate nfunc = 1; 11277c478bd9Sstevel@tonic-gate for (func = 0; func < nfunc; func++) { 11287c478bd9Sstevel@tonic-gate 11297c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 11307c478bd9Sstevel@tonic-gate dev, func); 11317c478bd9Sstevel@tonic-gate 11327c478bd9Sstevel@tonic-gate venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1133bd87be88Ssethg 11347c478bd9Sstevel@tonic-gate if ((venid == 0xffff) || (venid == 0)) { 11357c478bd9Sstevel@tonic-gate /* no function at this address */ 11367c478bd9Sstevel@tonic-gate continue; 11377c478bd9Sstevel@tonic-gate } 11387c478bd9Sstevel@tonic-gate 11397c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 11407c478bd9Sstevel@tonic-gate if (header == 0xff) { 11417c478bd9Sstevel@tonic-gate continue; /* illegal value */ 11427c478bd9Sstevel@tonic-gate } 11437c478bd9Sstevel@tonic-gate 11447c478bd9Sstevel@tonic-gate /* 11457c478bd9Sstevel@tonic-gate * according to some mail from Microsoft posted 11467c478bd9Sstevel@tonic-gate * to the pci-drivers alias, their only requirement 11477c478bd9Sstevel@tonic-gate * for a multifunction device is for the 1st 11487c478bd9Sstevel@tonic-gate * function to have to PCI_HEADER_MULTI bit set. 11497c478bd9Sstevel@tonic-gate */ 11507c478bd9Sstevel@tonic-gate if ((func == 0) && (header & PCI_HEADER_MULTI)) { 11517c478bd9Sstevel@tonic-gate nfunc = 8; 11527c478bd9Sstevel@tonic-gate } 115346e9e839Smyers 115405f867c3Sgs if (config_op == CONFIG_FIX || 115505f867c3Sgs config_op == CONFIG_INFO) { 1156ebf3afa8Sdmick /* 1157ebf3afa8Sdmick * Create the node, unconditionally, on the 1158ebf3afa8Sdmick * first pass only. It may still need 1159ebf3afa8Sdmick * resource assignment, which will be 1160ebf3afa8Sdmick * done on the second, CONFIG_NEW, pass. 1161ebf3afa8Sdmick */ 116205f867c3Sgs process_devfunc(bus, dev, func, header, 1163ebf3afa8Sdmick venid, config_op); 1164db063408Sdmick 11657c478bd9Sstevel@tonic-gate } 11667c478bd9Sstevel@tonic-gate } 11677c478bd9Sstevel@tonic-gate } 11687c478bd9Sstevel@tonic-gate 11698fc7923fSDana Myers /* percolate bus used resources up through parents to root */ 11708fc7923fSDana Myers if (config_op == CONFIG_INFO) { 11718fc7923fSDana Myers int par_bus; 11728fc7923fSDana Myers 11738fc7923fSDana Myers par_bus = pci_bus_res[bus].par_bus; 11748fc7923fSDana Myers while (par_bus != (uchar_t)-1) { 1175*ffa17327SGuoli Shu pci_bus_res[par_bus].io_size += 1176*ffa17327SGuoli Shu pci_bus_res[bus].io_size; 1177*ffa17327SGuoli Shu pci_bus_res[par_bus].mem_size += 1178*ffa17327SGuoli Shu pci_bus_res[bus].mem_size; 11798fc7923fSDana Myers 11808fc7923fSDana Myers if (pci_bus_res[bus].io_ports_used) 11818fc7923fSDana Myers memlist_merge(&pci_bus_res[bus].io_ports_used, 11828fc7923fSDana Myers &pci_bus_res[par_bus].io_ports_used); 11838fc7923fSDana Myers 11848fc7923fSDana Myers if (pci_bus_res[bus].mem_space_used) 11858fc7923fSDana Myers memlist_merge(&pci_bus_res[bus].mem_space_used, 11868fc7923fSDana Myers &pci_bus_res[par_bus].mem_space_used); 11878fc7923fSDana Myers 11888fc7923fSDana Myers if (pci_bus_res[bus].pmem_space_used) 11898fc7923fSDana Myers memlist_merge(&pci_bus_res[bus].pmem_space_used, 11908fc7923fSDana Myers &pci_bus_res[par_bus].pmem_space_used); 11918fc7923fSDana Myers 11928fc7923fSDana Myers par_bus = pci_bus_res[par_bus].par_bus; 11937c478bd9Sstevel@tonic-gate } 11947c478bd9Sstevel@tonic-gate } 11957c478bd9Sstevel@tonic-gate } 11967c478bd9Sstevel@tonic-gate 11977c478bd9Sstevel@tonic-gate static int 11987c478bd9Sstevel@tonic-gate check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 11997c478bd9Sstevel@tonic-gate ushort_t subvenid, ushort_t subdevid) 12007c478bd9Sstevel@tonic-gate { 12017c478bd9Sstevel@tonic-gate static int prop_exist = -1; 12027c478bd9Sstevel@tonic-gate static char *pciide_str; 12037c478bd9Sstevel@tonic-gate char compat[32]; 12047c478bd9Sstevel@tonic-gate 12057c478bd9Sstevel@tonic-gate if (prop_exist == -1) { 12067c478bd9Sstevel@tonic-gate prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 12077c478bd9Sstevel@tonic-gate ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 12087c478bd9Sstevel@tonic-gate &pciide_str) == DDI_SUCCESS); 12097c478bd9Sstevel@tonic-gate } 12107c478bd9Sstevel@tonic-gate 12117c478bd9Sstevel@tonic-gate if (!prop_exist) 12127c478bd9Sstevel@tonic-gate return (0); 12137c478bd9Sstevel@tonic-gate 12147c478bd9Sstevel@tonic-gate /* compare property value against various forms of compatible */ 12157c478bd9Sstevel@tonic-gate if (subvenid) { 12167c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 12177c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid, revid); 12187c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 12197c478bd9Sstevel@tonic-gate return (1); 12207c478bd9Sstevel@tonic-gate 12217c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 12227c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid); 12237c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 12247c478bd9Sstevel@tonic-gate return (1); 12257c478bd9Sstevel@tonic-gate 12267c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", 12277c478bd9Sstevel@tonic-gate subvenid, subdevid); 12287c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 12297c478bd9Sstevel@tonic-gate return (1); 12307c478bd9Sstevel@tonic-gate } 12317c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 12327c478bd9Sstevel@tonic-gate venid, devid, revid); 12337c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 12347c478bd9Sstevel@tonic-gate return (1); 12357c478bd9Sstevel@tonic-gate 12367c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 12377c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 12387c478bd9Sstevel@tonic-gate return (1); 12397c478bd9Sstevel@tonic-gate 12407c478bd9Sstevel@tonic-gate return (0); 12417c478bd9Sstevel@tonic-gate } 12427c478bd9Sstevel@tonic-gate 12437c478bd9Sstevel@tonic-gate static int 12447c478bd9Sstevel@tonic-gate is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 12457c478bd9Sstevel@tonic-gate ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 12467c478bd9Sstevel@tonic-gate { 12477c478bd9Sstevel@tonic-gate struct ide_table { /* table for PCI_MASS_OTHER */ 12487c478bd9Sstevel@tonic-gate ushort_t venid; 12497c478bd9Sstevel@tonic-gate ushort_t devid; 12507c478bd9Sstevel@tonic-gate } *entry; 12517c478bd9Sstevel@tonic-gate 1252334edc48Sml /* XXX SATA and other devices: need a way to add dynamically */ 12537c478bd9Sstevel@tonic-gate static struct ide_table ide_other[] = { 12547c478bd9Sstevel@tonic-gate {0x1095, 0x3112}, 12557c478bd9Sstevel@tonic-gate {0x1095, 0x3114}, 12567c478bd9Sstevel@tonic-gate {0x1095, 0x3512}, 1257d01a0451Stt {0x1095, 0x680}, /* Sil0680 */ 1258334edc48Sml {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 12597c478bd9Sstevel@tonic-gate {0, 0} 12607c478bd9Sstevel@tonic-gate }; 12617c478bd9Sstevel@tonic-gate 12627c478bd9Sstevel@tonic-gate if (basecl != PCI_CLASS_MASS) 12637c478bd9Sstevel@tonic-gate return (0); 12647c478bd9Sstevel@tonic-gate 12657c478bd9Sstevel@tonic-gate if (subcl == PCI_MASS_IDE) { 12667c478bd9Sstevel@tonic-gate return (1); 12677c478bd9Sstevel@tonic-gate } 12687c478bd9Sstevel@tonic-gate 1269d01a0451Stt if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1270d01a0451Stt return (1); 1271d01a0451Stt 12727c478bd9Sstevel@tonic-gate if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 12737c478bd9Sstevel@tonic-gate return (0); 12747c478bd9Sstevel@tonic-gate } 12757c478bd9Sstevel@tonic-gate 12767c478bd9Sstevel@tonic-gate entry = &ide_other[0]; 12777c478bd9Sstevel@tonic-gate while (entry->venid) { 12787c478bd9Sstevel@tonic-gate if (entry->venid == venid && entry->devid == devid) 12797c478bd9Sstevel@tonic-gate return (1); 12807c478bd9Sstevel@tonic-gate entry++; 12817c478bd9Sstevel@tonic-gate } 1282d01a0451Stt return (0); 12837c478bd9Sstevel@tonic-gate } 12847c478bd9Sstevel@tonic-gate 12857c478bd9Sstevel@tonic-gate static int 12867c478bd9Sstevel@tonic-gate is_display(uint_t classcode) 12877c478bd9Sstevel@tonic-gate { 12887c478bd9Sstevel@tonic-gate static uint_t disp_classes[] = { 12897c478bd9Sstevel@tonic-gate 0x000100, 12907c478bd9Sstevel@tonic-gate 0x030000, 12917c478bd9Sstevel@tonic-gate 0x030001 12927c478bd9Sstevel@tonic-gate }; 12937c478bd9Sstevel@tonic-gate int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 12947c478bd9Sstevel@tonic-gate 12957c478bd9Sstevel@tonic-gate for (i = 0; i < nclasses; i++) { 12967c478bd9Sstevel@tonic-gate if (classcode == disp_classes[i]) 12977c478bd9Sstevel@tonic-gate return (1); 12987c478bd9Sstevel@tonic-gate } 12997c478bd9Sstevel@tonic-gate return (0); 13007c478bd9Sstevel@tonic-gate } 13017c478bd9Sstevel@tonic-gate 1302bd87be88Ssethg static void 1303bd87be88Ssethg add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1304bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t)) 1305bd87be88Ssethg { 1306bd87be88Ssethg struct pci_fixundo *newundo; 1307bd87be88Ssethg 1308bd87be88Ssethg newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1309bd87be88Ssethg 1310bd87be88Ssethg /* 1311bd87be88Ssethg * Adding an item to this list means that we must turn its NMIENABLE 1312bd87be88Ssethg * bit back on at a later time. 1313bd87be88Ssethg */ 1314bd87be88Ssethg newundo->bus = bus; 1315bd87be88Ssethg newundo->dev = dev; 1316bd87be88Ssethg newundo->fn = fn; 1317bd87be88Ssethg newundo->undofn = undofn; 1318bd87be88Ssethg newundo->next = undolist; 1319bd87be88Ssethg 1320bd87be88Ssethg /* add to the undo list in LIFO order */ 1321bd87be88Ssethg undolist = newundo; 1322bd87be88Ssethg } 1323bd87be88Ssethg 1324bd87be88Ssethg void 1325bd87be88Ssethg add_pci_fixes(void) 1326bd87be88Ssethg { 1327bd87be88Ssethg int i; 1328bd87be88Ssethg 1329bd87be88Ssethg for (i = 0; i <= pci_bios_nbus; i++) { 1330bd87be88Ssethg /* 1331bd87be88Ssethg * For each bus, apply needed fixes to the appropriate devices. 1332bd87be88Ssethg * This must be done before the main enumeration loop because 1333bd87be88Ssethg * some fixes must be applied to devices normally encountered 1334bd87be88Ssethg * later in the pci scan (e.g. if a fix to device 7 must be 1335bd87be88Ssethg * applied before scanning device 6, applying fixes in the 1336bd87be88Ssethg * normal enumeration loop would obviously be too late). 1337bd87be88Ssethg */ 1338bd87be88Ssethg enumerate_bus_devs(i, CONFIG_FIX); 1339bd87be88Ssethg } 1340bd87be88Ssethg } 1341bd87be88Ssethg 1342bd87be88Ssethg void 1343bd87be88Ssethg undo_pci_fixes(void) 1344bd87be88Ssethg { 1345bd87be88Ssethg struct pci_fixundo *nextundo; 1346bd87be88Ssethg uint8_t bus, dev, fn; 1347bd87be88Ssethg 1348bd87be88Ssethg /* 1349bd87be88Ssethg * All fixes in the undo list are performed unconditionally. Future 1350bd87be88Ssethg * fixes may require selective undo. 1351bd87be88Ssethg */ 1352bd87be88Ssethg while (undolist != NULL) { 1353bd87be88Ssethg 1354bd87be88Ssethg bus = undolist->bus; 1355bd87be88Ssethg dev = undolist->dev; 1356bd87be88Ssethg fn = undolist->fn; 1357bd87be88Ssethg 1358bd87be88Ssethg (*(undolist->undofn))(bus, dev, fn); 1359bd87be88Ssethg 1360bd87be88Ssethg nextundo = undolist->next; 1361bd87be88Ssethg kmem_free(undolist, sizeof (struct pci_fixundo)); 1362bd87be88Ssethg undolist = nextundo; 1363bd87be88Ssethg } 1364bd87be88Ssethg } 1365bd87be88Ssethg 1366bd87be88Ssethg static void 1367bd87be88Ssethg undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1368bd87be88Ssethg { 1369bd87be88Ssethg uint8_t val8; 1370bd87be88Ssethg 1371bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1372bd87be88Ssethg /* 1373bd87be88Ssethg * The NMIONERR bit is turned back on to allow the SMM BIOS 1374bd87be88Ssethg * to handle more critical PCI errors (e.g. PERR#). 1375bd87be88Ssethg */ 1376bd87be88Ssethg val8 |= AMD8111_ENABLENMI; 1377bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1378bd87be88Ssethg } 1379bd87be88Ssethg 1380bd87be88Ssethg static void 1381bd87be88Ssethg pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1382bd87be88Ssethg { 1383bd87be88Ssethg uint8_t val8; 1384bd87be88Ssethg 1385bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1386bd87be88Ssethg 1387bd87be88Ssethg if ((val8 & AMD8111_ENABLENMI) == 0) 1388bd87be88Ssethg return; 1389bd87be88Ssethg 1390bd87be88Ssethg /* 1391bd87be88Ssethg * We reset NMIONERR in the LPC because master-abort on the PCI 1392bd87be88Ssethg * bridge side of the 8111 will cause NMI, which might cause SMI, 1393bd87be88Ssethg * which sometimes prevents all devices from being enumerated. 1394bd87be88Ssethg */ 1395bd87be88Ssethg val8 &= ~AMD8111_ENABLENMI; 1396bd87be88Ssethg 1397bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1398bd87be88Ssethg 1399bd87be88Ssethg add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1400bd87be88Ssethg } 1401bd87be88Ssethg 1402c8711d4dSgs static void 1403c8711d4dSgs set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1404c8711d4dSgs { 1405c8711d4dSgs uint16_t status; 1406c8711d4dSgs uint8_t header; 1407c8711d4dSgs uint8_t cap_ptr; 1408c8711d4dSgs uint8_t cap_id; 1409c8711d4dSgs uint16_t pmcsr; 1410c8711d4dSgs 1411c8711d4dSgs status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1412c8711d4dSgs if (!(status & PCI_STAT_CAP)) 1413c8711d4dSgs return; /* No capabilities list */ 1414c8711d4dSgs 1415c8711d4dSgs header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1416c8711d4dSgs if (header == PCI_HEADER_CARDBUS) 1417fb66942fSCasper H.S. Dik cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); 1418c8711d4dSgs else 1419c8711d4dSgs cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1420c8711d4dSgs /* 1421c8711d4dSgs * Walk the capabilities list searching for a PM entry. 1422c8711d4dSgs */ 1423c8711d4dSgs while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1424c8711d4dSgs cap_ptr &= PCI_CAP_PTR_MASK; 1425c8711d4dSgs cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1426c8711d4dSgs if (cap_id == PCI_CAP_ID_PM) { 1427c8711d4dSgs pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1428c8711d4dSgs pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1429c8711d4dSgs pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1430c8711d4dSgs pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1431c8711d4dSgs break; 1432c8711d4dSgs } 1433c8711d4dSgs cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1434c8711d4dSgs } 1435c8711d4dSgs 1436c8711d4dSgs } 1437c8711d4dSgs 143878323854SJudy Chen #define is_isa(bc, sc) \ 143978323854SJudy Chen (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) 144078323854SJudy Chen 144105f867c3Sgs static void 1442bd87be88Ssethg process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 14437c478bd9Sstevel@tonic-gate ushort_t vendorid, int config_op) 14447c478bd9Sstevel@tonic-gate { 14457c478bd9Sstevel@tonic-gate char nodename[32], unitaddr[5]; 14467c478bd9Sstevel@tonic-gate dev_info_t *dip; 1447c8589f13Ssethg uchar_t basecl, subcl, progcl, intr, revid; 14487c478bd9Sstevel@tonic-gate ushort_t subvenid, subdevid, status; 144970025d76Sjohnny ushort_t slot_num; 14507c478bd9Sstevel@tonic-gate uint_t classcode, revclass; 14518d483882Smlf int reprogram = 0, pciide = 0; 14527c478bd9Sstevel@tonic-gate int power[2] = {1, 1}; 145370025d76Sjohnny int pciex = 0; 145470025d76Sjohnny ushort_t is_pci_bridge = 0; 145505f867c3Sgs struct pci_devfunc *devlist = NULL, *entry = NULL; 145686c1f4dcSVikram Hegde iommu_private_t *private; 145794f1124eSVikram Hegde gfx_entry_t *gfxp; 14587c478bd9Sstevel@tonic-gate 14597c478bd9Sstevel@tonic-gate ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 14607c478bd9Sstevel@tonic-gate 14617c478bd9Sstevel@tonic-gate switch (header & PCI_HEADER_TYPE_M) { 14627c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 14637c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 14647c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 14657c478bd9Sstevel@tonic-gate break; 14667c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 14677c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 14687c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 146905f867c3Sgs /* Record the # of cardbus bridges found on the bus */ 147005f867c3Sgs if (config_op == CONFIG_INFO) 147105f867c3Sgs pci_bus_res[bus].num_cbb++; 14727c478bd9Sstevel@tonic-gate break; 14737c478bd9Sstevel@tonic-gate default: 14747c478bd9Sstevel@tonic-gate subvenid = 0; 14757c478bd9Sstevel@tonic-gate subdevid = 0; 14767c478bd9Sstevel@tonic-gate break; 14777c478bd9Sstevel@tonic-gate } 14787c478bd9Sstevel@tonic-gate 1479bd87be88Ssethg if (config_op == CONFIG_FIX) { 1480bd87be88Ssethg if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1481bd87be88Ssethg pci_fix_amd8111(bus, dev, func); 1482bd87be88Ssethg } 148305f867c3Sgs return; 1484bd87be88Ssethg } 1485bd87be88Ssethg 14867c478bd9Sstevel@tonic-gate /* XXX should be use generic names? derive from class? */ 14877c478bd9Sstevel@tonic-gate revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 14887c478bd9Sstevel@tonic-gate classcode = revclass >> 8; 14897c478bd9Sstevel@tonic-gate revid = revclass & 0xff; 14907c478bd9Sstevel@tonic-gate 14917c478bd9Sstevel@tonic-gate /* figure out if this is pci-ide */ 14927c478bd9Sstevel@tonic-gate basecl = classcode >> 16; 14937c478bd9Sstevel@tonic-gate subcl = (classcode >> 8) & 0xff; 1494c8589f13Ssethg progcl = classcode & 0xff; 14957c478bd9Sstevel@tonic-gate 14968d483882Smlf 14978d483882Smlf if (is_display(classcode)) 14987c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), "display"); 149978323854SJudy Chen else if (!pseudo_isa && is_isa(basecl, subcl)) 150078323854SJudy Chen (void) snprintf(nodename, sizeof (nodename), "isa"); 15017c478bd9Sstevel@tonic-gate else if (subvenid != 0) 15027c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 15037c478bd9Sstevel@tonic-gate "pci%x,%x", subvenid, subdevid); 15047c478bd9Sstevel@tonic-gate else 15057c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 15067c478bd9Sstevel@tonic-gate "pci%x,%x", vendorid, deviceid); 15077c478bd9Sstevel@tonic-gate 15087c478bd9Sstevel@tonic-gate /* make sure parent bus dip has been created */ 15098fc7923fSDana Myers if (pci_bus_res[bus].dip == NULL) 15107c478bd9Sstevel@tonic-gate create_root_bus_dip(bus); 15117c478bd9Sstevel@tonic-gate 15127c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 15137c478bd9Sstevel@tonic-gate DEVI_SID_NODEID, &dip); 15147c478bd9Sstevel@tonic-gate 151500d0963fSdilpreet if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 151600d0963fSdilpreet &is_pci_bridge) == B_TRUE) 151700d0963fSdilpreet pciex = 1; 151800d0963fSdilpreet 15197c478bd9Sstevel@tonic-gate /* add properties */ 15207c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 15217c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 15227c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 15237c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 15247c478bd9Sstevel@tonic-gate "class-code", classcode); 15257c478bd9Sstevel@tonic-gate if (func == 0) 15267c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 15277c478bd9Sstevel@tonic-gate else 15287c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), 15297c478bd9Sstevel@tonic-gate "%x,%x", dev, func); 15307c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 15317c478bd9Sstevel@tonic-gate "unit-address", unitaddr); 15327c478bd9Sstevel@tonic-gate 1533ebf3afa8Sdmick /* add device_type for display nodes */ 1534ebf3afa8Sdmick if (is_display(classcode)) { 1535ebf3afa8Sdmick (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1536ebf3afa8Sdmick "device_type", "display"); 1537ebf3afa8Sdmick } 15387c478bd9Sstevel@tonic-gate /* add special stuff for header type */ 15397c478bd9Sstevel@tonic-gate if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 15407c478bd9Sstevel@tonic-gate uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 15417c478bd9Sstevel@tonic-gate uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 15427c478bd9Sstevel@tonic-gate 15437c478bd9Sstevel@tonic-gate if (subvenid != 0) { 15447c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 15457c478bd9Sstevel@tonic-gate "subsystem-id", subdevid); 15467c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 15477c478bd9Sstevel@tonic-gate "subsystem-vendor-id", subvenid); 15487c478bd9Sstevel@tonic-gate } 154970025d76Sjohnny if (!pciex) 155070025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 155170025d76Sjohnny "min-grant", mingrant); 155270025d76Sjohnny if (!pciex) 155370025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 155470025d76Sjohnny "max-latency", maxlatency); 15557c478bd9Sstevel@tonic-gate } 15567c478bd9Sstevel@tonic-gate 15577c478bd9Sstevel@tonic-gate /* interrupt, record if not 0 */ 15587c478bd9Sstevel@tonic-gate intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 15597c478bd9Sstevel@tonic-gate if (intr != 0) 15607c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 15617c478bd9Sstevel@tonic-gate "interrupts", intr); 15627c478bd9Sstevel@tonic-gate 15637c478bd9Sstevel@tonic-gate /* 15647c478bd9Sstevel@tonic-gate * Add support for 133 mhz pci eventually 15657c478bd9Sstevel@tonic-gate */ 15667c478bd9Sstevel@tonic-gate status = pci_getw(bus, dev, func, PCI_CONF_STAT); 15677c478bd9Sstevel@tonic-gate 15687c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 15697c478bd9Sstevel@tonic-gate "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 157070025d76Sjohnny if (!pciex && (status & PCI_STAT_FBBC)) 15717c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 15727c478bd9Sstevel@tonic-gate "fast-back-to-back"); 157370025d76Sjohnny if (!pciex && (status & PCI_STAT_66MHZ)) 15747c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 15757c478bd9Sstevel@tonic-gate "66mhz-capable"); 15767c478bd9Sstevel@tonic-gate if (status & PCI_STAT_UDF) 15777c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 15787c478bd9Sstevel@tonic-gate "udf-supported"); 1579d57b3b3dSprasad if (pciex && slot_num) { 158070025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 158170025d76Sjohnny "physical-slot#", slot_num); 1582d57b3b3dSprasad if (!is_pci_bridge) 1583d57b3b3dSprasad pciex_slot_names_prop(dip, slot_num); 1584d57b3b3dSprasad } 15857c478bd9Sstevel@tonic-gate 15867c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 15877c478bd9Sstevel@tonic-gate "power-consumption", power, 2); 15887c478bd9Sstevel@tonic-gate 1589c8711d4dSgs /* Set the device PM state to D0 */ 1590c8711d4dSgs set_devpm_d0(bus, dev, func); 1591c8711d4dSgs 159270025d76Sjohnny if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 159349fbdd30SErwin T Tsaur add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 159405f867c3Sgs else { 159505f867c3Sgs /* 159605f867c3Sgs * Record the non-PPB devices on the bus for possible 159705f867c3Sgs * reprogramming at 2nd bus enumeration. 159805f867c3Sgs * Note: PPB reprogramming is done in fix_ppb_res() 159905f867c3Sgs */ 160005f867c3Sgs devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 160105f867c3Sgs entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 160205f867c3Sgs entry->dip = dip; 160305f867c3Sgs entry->dev = dev; 160405f867c3Sgs entry->func = func; 160505f867c3Sgs entry->next = devlist; 160605f867c3Sgs pci_bus_res[bus].privdata = entry; 160705f867c3Sgs } 160870025d76Sjohnny 1609c8589f13Ssethg if (config_op == CONFIG_INFO && 1610c8589f13Ssethg IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1611c8589f13Ssethg create_ioapic_node(bus, dev, func, vendorid, deviceid); 1612c8589f13Ssethg } 1613c8589f13Ssethg 161470025d76Sjohnny /* check for ck8-04 based PCI ISA bridge only */ 161570025d76Sjohnny if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 161670025d76Sjohnny (func == 0)) 16178a5a0d1eSanish add_nvidia_isa_bridge_props(dip, bus, dev, func); 161870025d76Sjohnny 161970025d76Sjohnny if (pciex && is_pci_bridge) 162070025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 162170025d76Sjohnny (char *)"PCIe-PCI bridge"); 162270025d76Sjohnny else 162370025d76Sjohnny add_model_prop(dip, classcode); 16247c478bd9Sstevel@tonic-gate 16257c478bd9Sstevel@tonic-gate add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 162670025d76Sjohnny revid, classcode, pciex); 16278d483882Smlf 16288d483882Smlf /* 16298d483882Smlf * See if this device is a controller that advertises 16308d483882Smlf * itself to be a standard ATA task file controller, or one that 16318d483882Smlf * has been hard coded. 16328d483882Smlf * 16338d483882Smlf * If it is, check if any other higher precedence driver listed in 16348d483882Smlf * driver_aliases will claim the node by calling 16358d483882Smlf * ddi_compatibile_driver_major. If so, clear pciide and do not 16368d483882Smlf * create a pci-ide node or any other special handling. 16378d483882Smlf * 16388d483882Smlf * If another driver does not bind, set the node name to pci-ide 16398d483882Smlf * and then let the special pci-ide handling for registers and 16408d483882Smlf * child pci-ide nodes proceed below. 16418d483882Smlf */ 16428d483882Smlf if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 16438d483882Smlf subvenid, subdevid) == 1) { 16448d483882Smlf if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 16458d483882Smlf (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 16468d483882Smlf pciide = 1; 16478d483882Smlf } 16488d483882Smlf } 16498d483882Smlf 16507c478bd9Sstevel@tonic-gate reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 16517c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 16527c478bd9Sstevel@tonic-gate 16537c478bd9Sstevel@tonic-gate /* special handling for pci-ide */ 16547c478bd9Sstevel@tonic-gate if (pciide) { 16557c478bd9Sstevel@tonic-gate dev_info_t *cdip; 16567c478bd9Sstevel@tonic-gate 16577c478bd9Sstevel@tonic-gate /* 16587c478bd9Sstevel@tonic-gate * Create properties specified by P1275 Working Group 16597c478bd9Sstevel@tonic-gate * Proposal #414 Version 1 16607c478bd9Sstevel@tonic-gate */ 16617c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 16627c478bd9Sstevel@tonic-gate "device_type", "pci-ide"); 16637c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 16647c478bd9Sstevel@tonic-gate "#address-cells", 1); 16657c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 16667c478bd9Sstevel@tonic-gate "#size-cells", 0); 16677c478bd9Sstevel@tonic-gate 16687c478bd9Sstevel@tonic-gate /* allocate two child nodes */ 16697c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 1670fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 16717c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 16727c478bd9Sstevel@tonic-gate "reg", 0); 16737c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 16747c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 1675fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 16767c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 16777c478bd9Sstevel@tonic-gate "reg", 1); 16787c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 16797c478bd9Sstevel@tonic-gate 16807c478bd9Sstevel@tonic-gate reprogram = 0; /* don't reprogram pci-ide bridge */ 16817c478bd9Sstevel@tonic-gate } 16827c478bd9Sstevel@tonic-gate 168386c1f4dcSVikram Hegde /* allocate and set up iommu private */ 168486c1f4dcSVikram Hegde private = kmem_alloc(sizeof (iommu_private_t), KM_SLEEP); 168586c1f4dcSVikram Hegde private->idp_seg = 0; 168686c1f4dcSVikram Hegde private->idp_bus = bus; 168786c1f4dcSVikram Hegde private->idp_devfn = (dev << 3) | func; 168886c1f4dcSVikram Hegde private->idp_sec = 0; 168986c1f4dcSVikram Hegde private->idp_sub = 0; 169086c1f4dcSVikram Hegde private->idp_bbp_type = IOMMU_PPB_NONE; 169186c1f4dcSVikram Hegde /* record the bridge */ 169286c1f4dcSVikram Hegde private->idp_is_bridge = ((basecl == PCI_CLASS_BRIDGE) && 169386c1f4dcSVikram Hegde (subcl == PCI_BRIDGE_PCI)); 169486c1f4dcSVikram Hegde if (private->idp_is_bridge) { 169586c1f4dcSVikram Hegde private->idp_sec = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 169686c1f4dcSVikram Hegde private->idp_sub = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 169786c1f4dcSVikram Hegde if (pciex && is_pci_bridge) 169886c1f4dcSVikram Hegde private->idp_bbp_type = IOMMU_PPB_PCIE_PCI; 169986c1f4dcSVikram Hegde else if (pciex) 170086c1f4dcSVikram Hegde private->idp_bbp_type = IOMMU_PPB_PCIE_PCIE; 170186c1f4dcSVikram Hegde else 170286c1f4dcSVikram Hegde private->idp_bbp_type = IOMMU_PPB_PCI_PCI; 170386c1f4dcSVikram Hegde } 170486c1f4dcSVikram Hegde /* record the special devices */ 170586c1f4dcSVikram Hegde private->idp_is_display = (is_display(classcode) ? B_TRUE : B_FALSE); 170686c1f4dcSVikram Hegde private->idp_is_lpc = ((basecl == PCI_CLASS_BRIDGE) && 170786c1f4dcSVikram Hegde (subcl == PCI_BRIDGE_ISA)); 170894f1124eSVikram Hegde private->idp_intel_domain = NULL; 170986c1f4dcSVikram Hegde /* hook the private to dip */ 171086c1f4dcSVikram Hegde DEVI(dip)->devi_iommu_private = private; 171186c1f4dcSVikram Hegde 171294f1124eSVikram Hegde if (private->idp_is_display == B_TRUE) { 171394f1124eSVikram Hegde gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 171494f1124eSVikram Hegde gfxp->g_dip = dip; 171594f1124eSVikram Hegde gfxp->g_prev = NULL; 171694f1124eSVikram Hegde gfxp->g_next = gfx_devinfo_list; 171794f1124eSVikram Hegde gfx_devinfo_list = gfxp; 171894f1124eSVikram Hegde if (gfxp->g_next) 171994f1124eSVikram Hegde gfxp->g_next->g_prev = gfxp; 172094f1124eSVikram Hegde } 172194f1124eSVikram Hegde 172278323854SJudy Chen /* special handling for isa */ 172378323854SJudy Chen if (!pseudo_isa && is_isa(basecl, subcl)) { 172478323854SJudy Chen /* add device_type */ 172578323854SJudy Chen (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 172678323854SJudy Chen "device_type", "isa"); 172778323854SJudy Chen } 172878323854SJudy Chen 172905f867c3Sgs if (reprogram && (entry != NULL)) 173005f867c3Sgs entry->reprogram = B_TRUE; 17317c478bd9Sstevel@tonic-gate } 17327c478bd9Sstevel@tonic-gate 1733c2de8625SScott Carter, SD IOSW /* 1734c2de8625SScott Carter, SD IOSW * Some vendors do not use unique subsystem IDs in their products, which 1735c2de8625SScott Carter, SD IOSW * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate. 1736c2de8625SScott Carter, SD IOSW * Allow for these compatible forms to be excluded on a per-device basis. 1737c2de8625SScott Carter, SD IOSW */ 1738c2de8625SScott Carter, SD IOSW /*ARGSUSED*/ 1739c2de8625SScott Carter, SD IOSW static boolean_t 1740c2de8625SScott Carter, SD IOSW subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid, 1741c2de8625SScott Carter, SD IOSW ushort_t subdevid, uchar_t revid, uint_t classcode) 1742c2de8625SScott Carter, SD IOSW { 1743c2de8625SScott Carter, SD IOSW /* Nvidia display adapters */ 1744c2de8625SScott Carter, SD IOSW if ((venid == 0x10de) && (is_display(classcode))) 1745c2de8625SScott Carter, SD IOSW return (B_TRUE); 1746c2de8625SScott Carter, SD IOSW 1747c2de8625SScott Carter, SD IOSW return (B_FALSE); 1748c2de8625SScott Carter, SD IOSW } 1749c2de8625SScott Carter, SD IOSW 17507c478bd9Sstevel@tonic-gate /* 17517c478bd9Sstevel@tonic-gate * Set the compatible property to a value compliant with 17527c478bd9Sstevel@tonic-gate * rev 2.1 of the IEEE1275 PCI binding. 175370025d76Sjohnny * (Also used for PCI-Express devices). 17547c478bd9Sstevel@tonic-gate * 17557c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss.RR (0) 17567c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss (1) 17577c478bd9Sstevel@tonic-gate * pciSSSS,ssss (2) 17587c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.RR (3) 17597c478bd9Sstevel@tonic-gate * pciVVVV,DDDD (4) 17607c478bd9Sstevel@tonic-gate * pciclass,CCSSPP (5) 17617c478bd9Sstevel@tonic-gate * pciclass,CCSS (6) 17627c478bd9Sstevel@tonic-gate * 17637c478bd9Sstevel@tonic-gate * The Subsystem (SSSS) forms are not inserted if 17647c478bd9Sstevel@tonic-gate * subsystem-vendor-id is 0. 17657c478bd9Sstevel@tonic-gate * 176670025d76Sjohnny * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 176770025d76Sjohnny * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 176870025d76Sjohnny * 17697c478bd9Sstevel@tonic-gate * Set with setprop and \x00 between each 17707c478bd9Sstevel@tonic-gate * to generate the encoded string array form. 17717c478bd9Sstevel@tonic-gate */ 17727c478bd9Sstevel@tonic-gate void 17737c478bd9Sstevel@tonic-gate add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 177470025d76Sjohnny ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 177570025d76Sjohnny int pciex) 17767c478bd9Sstevel@tonic-gate { 177770025d76Sjohnny int i = 0; 177870025d76Sjohnny int size = COMPAT_BUFSIZE; 177970025d76Sjohnny char *compat[13]; 17807c478bd9Sstevel@tonic-gate char *buf, *curr; 17817c478bd9Sstevel@tonic-gate 17827c478bd9Sstevel@tonic-gate curr = buf = kmem_alloc(size, KM_SLEEP); 17837c478bd9Sstevel@tonic-gate 178470025d76Sjohnny if (pciex) { 178570025d76Sjohnny if (subvenid) { 178670025d76Sjohnny compat[i++] = curr; /* form 0 */ 178770025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 178870025d76Sjohnny vendorid, deviceid, subvenid, subdevid, revid); 178970025d76Sjohnny size -= strlen(curr) + 1; 179070025d76Sjohnny curr += strlen(curr) + 1; 179170025d76Sjohnny 179270025d76Sjohnny compat[i++] = curr; /* form 1 */ 179370025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 179470025d76Sjohnny vendorid, deviceid, subvenid, subdevid); 179570025d76Sjohnny size -= strlen(curr) + 1; 179670025d76Sjohnny curr += strlen(curr) + 1; 179770025d76Sjohnny 179870025d76Sjohnny } 179970025d76Sjohnny compat[i++] = curr; /* form 3 */ 180070025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x", 180170025d76Sjohnny vendorid, deviceid, revid); 180270025d76Sjohnny size -= strlen(curr) + 1; 180370025d76Sjohnny curr += strlen(curr) + 1; 180470025d76Sjohnny 180570025d76Sjohnny compat[i++] = curr; /* form 4 */ 180670025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 180770025d76Sjohnny size -= strlen(curr) + 1; 180870025d76Sjohnny curr += strlen(curr) + 1; 180970025d76Sjohnny 181070025d76Sjohnny compat[i++] = curr; /* form 5 */ 181170025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%06x", classcode); 181270025d76Sjohnny size -= strlen(curr) + 1; 181370025d76Sjohnny curr += strlen(curr) + 1; 181470025d76Sjohnny 181570025d76Sjohnny compat[i++] = curr; /* form 6 */ 181670025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%04x", 181770025d76Sjohnny (classcode >> 8)); 181870025d76Sjohnny size -= strlen(curr) + 1; 181970025d76Sjohnny curr += strlen(curr) + 1; 182070025d76Sjohnny } 182170025d76Sjohnny 18227c478bd9Sstevel@tonic-gate if (subvenid) { 18237c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 0 */ 18247c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 18257c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid, revid); 18267c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 18277c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 18287c478bd9Sstevel@tonic-gate 18297c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 1 */ 18307c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x", 18317c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid); 18327c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 18337c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 18347c478bd9Sstevel@tonic-gate 1835c2de8625SScott Carter, SD IOSW if (subsys_compat_exclude(vendorid, deviceid, subvenid, 1836c2de8625SScott Carter, SD IOSW subdevid, revid, classcode) == B_FALSE) { 1837c2de8625SScott Carter, SD IOSW compat[i++] = curr; /* form 2 */ 1838c2de8625SScott Carter, SD IOSW (void) snprintf(curr, size, "pci%x,%x", subvenid, 1839c2de8625SScott Carter, SD IOSW subdevid); 1840c2de8625SScott Carter, SD IOSW size -= strlen(curr) + 1; 1841c2de8625SScott Carter, SD IOSW curr += strlen(curr) + 1; 1842c2de8625SScott Carter, SD IOSW } 18437c478bd9Sstevel@tonic-gate } 18447c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 3 */ 18457c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 18467c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 18477c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 18487c478bd9Sstevel@tonic-gate 18497c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 4 */ 18507c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 18517c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 18527c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 18537c478bd9Sstevel@tonic-gate 18547c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 5 */ 18557c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%06x", classcode); 18567c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 18577c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 18587c478bd9Sstevel@tonic-gate 18597c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 6 */ 18607c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 186170025d76Sjohnny size -= strlen(curr) + 1; 186270025d76Sjohnny curr += strlen(curr) + 1; 18637c478bd9Sstevel@tonic-gate 18647c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 18657c478bd9Sstevel@tonic-gate "compatible", compat, i); 18667c478bd9Sstevel@tonic-gate kmem_free(buf, COMPAT_BUFSIZE); 18677c478bd9Sstevel@tonic-gate } 18687c478bd9Sstevel@tonic-gate 18697c478bd9Sstevel@tonic-gate /* 18707c478bd9Sstevel@tonic-gate * Adjust the reg properties for a dual channel PCI-IDE device. 18717c478bd9Sstevel@tonic-gate * 18727c478bd9Sstevel@tonic-gate * NOTE: don't do anything that changes the order of the hard-decodes 18737c478bd9Sstevel@tonic-gate * and programmed BARs. The kernel driver depends on these values 18747c478bd9Sstevel@tonic-gate * being in this order regardless of whether they're for a 'native' 18757c478bd9Sstevel@tonic-gate * mode BAR or not. 18767c478bd9Sstevel@tonic-gate */ 18777c478bd9Sstevel@tonic-gate /* 18787c478bd9Sstevel@tonic-gate * config info for pci-ide devices 18797c478bd9Sstevel@tonic-gate */ 18807c478bd9Sstevel@tonic-gate static struct { 18817c478bd9Sstevel@tonic-gate uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 18827c478bd9Sstevel@tonic-gate uchar_t bar_offset; /* offset for alt status register */ 18837c478bd9Sstevel@tonic-gate ushort_t addr; /* compatibility mode base address */ 18847c478bd9Sstevel@tonic-gate ushort_t length; /* number of ports for this BAR */ 18857c478bd9Sstevel@tonic-gate } pciide_bar[] = { 18867c478bd9Sstevel@tonic-gate { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 18877c478bd9Sstevel@tonic-gate { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 18887c478bd9Sstevel@tonic-gate { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 18897c478bd9Sstevel@tonic-gate { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 18907c478bd9Sstevel@tonic-gate }; 18917c478bd9Sstevel@tonic-gate 18927c478bd9Sstevel@tonic-gate static int 18937c478bd9Sstevel@tonic-gate pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 18947c478bd9Sstevel@tonic-gate { 18957c478bd9Sstevel@tonic-gate int hard_decode = 0; 18967c478bd9Sstevel@tonic-gate 18977c478bd9Sstevel@tonic-gate /* 18987c478bd9Sstevel@tonic-gate * Adjust the base and len for the BARs of the PCI-IDE 18997c478bd9Sstevel@tonic-gate * device's primary and secondary controllers. The first 19007c478bd9Sstevel@tonic-gate * two BARs are for the primary controller and the next 19017c478bd9Sstevel@tonic-gate * two BARs are for the secondary controller. The fifth 19027c478bd9Sstevel@tonic-gate * and sixth bars are never adjusted. 19037c478bd9Sstevel@tonic-gate */ 19047c478bd9Sstevel@tonic-gate if (index >= 0 && index <= 3) { 19057c478bd9Sstevel@tonic-gate *lenp = pciide_bar[index].length; 19067c478bd9Sstevel@tonic-gate 19077c478bd9Sstevel@tonic-gate if (progcl & pciide_bar[index].native_mask) { 19087c478bd9Sstevel@tonic-gate *basep += pciide_bar[index].bar_offset; 19097c478bd9Sstevel@tonic-gate } else { 19107c478bd9Sstevel@tonic-gate *basep = pciide_bar[index].addr; 19117c478bd9Sstevel@tonic-gate hard_decode = 1; 19127c478bd9Sstevel@tonic-gate } 19137c478bd9Sstevel@tonic-gate } 19147c478bd9Sstevel@tonic-gate 19157c478bd9Sstevel@tonic-gate /* 19167c478bd9Sstevel@tonic-gate * if either base or len is zero make certain both are zero 19177c478bd9Sstevel@tonic-gate */ 19187c478bd9Sstevel@tonic-gate if (*basep == 0 || *lenp == 0) { 19197c478bd9Sstevel@tonic-gate *basep = 0; 19207c478bd9Sstevel@tonic-gate *lenp = 0; 19217c478bd9Sstevel@tonic-gate hard_decode = 0; 19227c478bd9Sstevel@tonic-gate } 19237c478bd9Sstevel@tonic-gate 19247c478bd9Sstevel@tonic-gate return (hard_decode); 19257c478bd9Sstevel@tonic-gate } 19267c478bd9Sstevel@tonic-gate 19277c478bd9Sstevel@tonic-gate 19287c478bd9Sstevel@tonic-gate /* 19297c478bd9Sstevel@tonic-gate * Add the "reg" and "assigned-addresses" property 19307c478bd9Sstevel@tonic-gate */ 19317c478bd9Sstevel@tonic-gate static int 19327c478bd9Sstevel@tonic-gate add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 19337c478bd9Sstevel@tonic-gate int config_op, int pciide) 19347c478bd9Sstevel@tonic-gate { 19357c478bd9Sstevel@tonic-gate uchar_t baseclass, subclass, progclass, header; 19367c478bd9Sstevel@tonic-gate ushort_t bar_sz; 19377c478bd9Sstevel@tonic-gate uint_t value = 0, len, devloc; 19387c478bd9Sstevel@tonic-gate uint_t base, base_hi, type; 19397c478bd9Sstevel@tonic-gate ushort_t offset, end; 19407c478bd9Sstevel@tonic-gate int max_basereg, j, reprogram = 0; 19417c478bd9Sstevel@tonic-gate uint_t phys_hi; 19428fc7923fSDana Myers struct memlist **io_res, **io_res_used; 19438fc7923fSDana Myers struct memlist **mem_res, **mem_res_used; 19448fc7923fSDana Myers struct memlist **pmem_res, **pmem_res_used; 194505f867c3Sgs uchar_t res_bus; 19467c478bd9Sstevel@tonic-gate 19477c478bd9Sstevel@tonic-gate pci_regspec_t regs[16] = {{0}}; 19487c478bd9Sstevel@tonic-gate pci_regspec_t assigned[15] = {{0}}; 1949c8711d4dSgs int nreg, nasgn; 19507c478bd9Sstevel@tonic-gate 19517c478bd9Sstevel@tonic-gate io_res = &pci_bus_res[bus].io_ports; 195205f867c3Sgs io_res_used = &pci_bus_res[bus].io_ports_used; 19537c478bd9Sstevel@tonic-gate mem_res = &pci_bus_res[bus].mem_space; 195405f867c3Sgs mem_res_used = &pci_bus_res[bus].mem_space_used; 19558fc7923fSDana Myers pmem_res = &pci_bus_res[bus].pmem_space; 19568fc7923fSDana Myers pmem_res_used = &pci_bus_res[bus].pmem_space_used; 19577c478bd9Sstevel@tonic-gate 19587c478bd9Sstevel@tonic-gate devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 19597c478bd9Sstevel@tonic-gate regs[0].pci_phys_hi = devloc; 19607c478bd9Sstevel@tonic-gate nreg = 1; /* rest of regs[0] is all zero */ 19617c478bd9Sstevel@tonic-gate nasgn = 0; 19627c478bd9Sstevel@tonic-gate 19637c478bd9Sstevel@tonic-gate baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 19647c478bd9Sstevel@tonic-gate subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 19657c478bd9Sstevel@tonic-gate progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 19667c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 19677c478bd9Sstevel@tonic-gate 19687c478bd9Sstevel@tonic-gate switch (header) { 19697c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 19707c478bd9Sstevel@tonic-gate max_basereg = PCI_BASE_NUM; 19717c478bd9Sstevel@tonic-gate break; 19727c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 19737c478bd9Sstevel@tonic-gate max_basereg = PCI_BCNF_BASE_NUM; 19747c478bd9Sstevel@tonic-gate break; 19757c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 19767c478bd9Sstevel@tonic-gate max_basereg = PCI_CBUS_BASE_NUM; 1977*ffa17327SGuoli Shu reprogram = 1; 19787c478bd9Sstevel@tonic-gate break; 19797c478bd9Sstevel@tonic-gate default: 19807c478bd9Sstevel@tonic-gate max_basereg = 0; 19817c478bd9Sstevel@tonic-gate break; 19827c478bd9Sstevel@tonic-gate } 19837c478bd9Sstevel@tonic-gate 19847c478bd9Sstevel@tonic-gate /* 19857c478bd9Sstevel@tonic-gate * Create the register property by saving the current 19868d34f104Smyers * value of the base register. Write 0xffffffff to the 19878d34f104Smyers * base register. Read the value back to determine the 19888d34f104Smyers * required size of the address space. Restore the base 19898d34f104Smyers * register contents. 19908d34f104Smyers * 19918d34f104Smyers * Do not disable I/O and memory access; this isn't necessary 19928d34f104Smyers * since no driver is yet attached to this device, and disabling 19938d34f104Smyers * I/O and memory access has the side-effect of disabling PCI-PCI 19948d34f104Smyers * bridge mappings, which makes the bridge transparent to secondary- 19958d34f104Smyers * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 19968d34f104Smyers * Spec V1.2). 19977c478bd9Sstevel@tonic-gate */ 19987c478bd9Sstevel@tonic-gate end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 19997c478bd9Sstevel@tonic-gate for (j = 0, offset = PCI_CONF_BASE0; offset < end; 20007c478bd9Sstevel@tonic-gate j++, offset += bar_sz) { 20017c478bd9Sstevel@tonic-gate /* determine the size of the address space */ 20027c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 20037c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 0xffffffff); 20047c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 20057c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 20067c478bd9Sstevel@tonic-gate 20077c478bd9Sstevel@tonic-gate /* construct phys hi,med.lo, size hi, lo */ 20087c478bd9Sstevel@tonic-gate if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 20093e98767bSMax zhen int hard_decode = 0; 20103e98767bSMax zhen 20117c478bd9Sstevel@tonic-gate /* i/o space */ 20127c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 20137c478bd9Sstevel@tonic-gate value &= PCI_BASE_IO_ADDR_M; 20147c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 20157c478bd9Sstevel@tonic-gate 20167c478bd9Sstevel@tonic-gate /* XXX Adjust first 4 IDE registers */ 20177c478bd9Sstevel@tonic-gate if (pciide) { 2018f088817aSyt if (subclass != PCI_MASS_IDE) 20197c478bd9Sstevel@tonic-gate progclass = (PCI_IDE_IF_NATIVE_PRI | 20207c478bd9Sstevel@tonic-gate PCI_IDE_IF_NATIVE_SEC); 20217c478bd9Sstevel@tonic-gate hard_decode = pciIdeAdjustBAR(progclass, j, 20227c478bd9Sstevel@tonic-gate &base, &len); 20237c478bd9Sstevel@tonic-gate } else if (value == 0) { 20247c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 20257c478bd9Sstevel@tonic-gate continue; 20267c478bd9Sstevel@tonic-gate } 20277c478bd9Sstevel@tonic-gate 20283e98767bSMax zhen regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc | 20293e98767bSMax zhen (hard_decode ? PCI_RELOCAT_B : offset); 20303e98767bSMax zhen regs[nreg].pci_phys_low = hard_decode ? 20313e98767bSMax zhen base & PCI_BASE_IO_ADDR_M : 0; 20323e98767bSMax zhen assigned[nasgn].pci_phys_hi = 20333e98767bSMax zhen PCI_RELOCAT_B | regs[nreg].pci_phys_hi; 20347c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 20357c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 20367c478bd9Sstevel@tonic-gate type = base & (~PCI_BASE_IO_ADDR_M); 20377c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 203805f867c3Sgs /* 203905f867c3Sgs * A device under a subtractive PPB can allocate 204005f867c3Sgs * resources from its parent bus if there is no resource 204105f867c3Sgs * available on its own bus. 204205f867c3Sgs */ 204305f867c3Sgs if ((config_op == CONFIG_NEW) && (*io_res == NULL)) { 204405f867c3Sgs res_bus = bus; 204505f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 204605f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 204705f867c3Sgs if (res_bus == (uchar_t)-1) 204805f867c3Sgs break; /* root bus already */ 204905f867c3Sgs if (pci_bus_res[res_bus].io_ports) { 205005f867c3Sgs io_res = &pci_bus_res 205105f867c3Sgs [res_bus].io_ports; 205205f867c3Sgs break; 205305f867c3Sgs } 205405f867c3Sgs } 205505f867c3Sgs } 20567c478bd9Sstevel@tonic-gate 20577c478bd9Sstevel@tonic-gate /* 20587c478bd9Sstevel@tonic-gate * first pass - gather what's there 20597c478bd9Sstevel@tonic-gate * update/second pass - adjust/allocate regions 20607c478bd9Sstevel@tonic-gate * config - allocate regions 20617c478bd9Sstevel@tonic-gate */ 20627c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { /* first pass */ 20637c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 206405f867c3Sgs if (base != 0) { 20658fc7923fSDana Myers (void) memlist_remove(io_res, base, 20668fc7923fSDana Myers len); 206705f867c3Sgs memlist_insert(io_res_used, base, len); 2068*ffa17327SGuoli Shu } else { 20697c478bd9Sstevel@tonic-gate reprogram = 1; 2070*ffa17327SGuoli Shu } 2071*ffa17327SGuoli Shu pci_bus_res[bus].io_size += len; 207205f867c3Sgs } else if ((*io_res && base == 0) || 207305f867c3Sgs pci_bus_res[bus].io_reprogram) { 2074c8711d4dSgs base = (uint_t)memlist_find(io_res, len, len); 20757c478bd9Sstevel@tonic-gate if (base != 0) { 207605f867c3Sgs memlist_insert(io_res_used, base, len); 20777c478bd9Sstevel@tonic-gate /* XXX need to worry about 64-bit? */ 20787c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 20797c478bd9Sstevel@tonic-gate base | type); 20807c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 20817c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 20827c478bd9Sstevel@tonic-gate } 20837c478bd9Sstevel@tonic-gate if (base == 0) { 20847c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program" 2085db063408Sdmick " IO space [%d/%d/%d] BAR@0x%x" 2086db063408Sdmick " length 0x%x", 2087ebf3afa8Sdmick bus, dev, func, offset, len); 2088c8711d4dSgs } 20897c478bd9Sstevel@tonic-gate } 20907c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 20917c478bd9Sstevel@tonic-gate nreg++, nasgn++; 20927c478bd9Sstevel@tonic-gate 20937c478bd9Sstevel@tonic-gate } else { 20947c478bd9Sstevel@tonic-gate /* memory space */ 20957c478bd9Sstevel@tonic-gate if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 20967c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_64; 20977c478bd9Sstevel@tonic-gate base_hi = pci_getl(bus, dev, func, offset + 4); 20987c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM64; 20997c478bd9Sstevel@tonic-gate } else { 21007c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 21017c478bd9Sstevel@tonic-gate base_hi = 0; 21027c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM32; 21037c478bd9Sstevel@tonic-gate } 21047c478bd9Sstevel@tonic-gate 21057c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 21067c478bd9Sstevel@tonic-gate value &= PCI_BASE_M_ADDR_M; 21077c478bd9Sstevel@tonic-gate 21088fc7923fSDana Myers if (value == 0) 21097c478bd9Sstevel@tonic-gate continue; 21108fc7923fSDana Myers 21117c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 21127c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 21137c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 21147c478bd9Sstevel@tonic-gate 21157c478bd9Sstevel@tonic-gate phys_hi |= (devloc | offset); 21168fc7923fSDana Myers if (base & PCI_BASE_PREF_M) 21177c478bd9Sstevel@tonic-gate phys_hi |= PCI_PREFETCH_B; 21188fc7923fSDana Myers 211905f867c3Sgs /* 212005f867c3Sgs * A device under a subtractive PPB can allocate 212105f867c3Sgs * resources from its parent bus if there is no resource 212205f867c3Sgs * available on its own bus. 212305f867c3Sgs */ 21248fc7923fSDana Myers if ((config_op == CONFIG_NEW) && (*mem_res == NULL)) { 212505f867c3Sgs res_bus = bus; 212605f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 212705f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 212805f867c3Sgs if (res_bus == (uchar_t)-1) 212905f867c3Sgs break; /* root bus already */ 213086ce93f0SGuoli Shu mem_res = 213186ce93f0SGuoli Shu &pci_bus_res[res_bus].mem_space; 21328fc7923fSDana Myers pmem_res = 21338fc7923fSDana Myers &pci_bus_res [res_bus].pmem_space; 21348fc7923fSDana Myers /* 21358fc7923fSDana Myers * Break out as long as at least 21368fc7923fSDana Myers * mem_res is available 21378fc7923fSDana Myers */ 21388fc7923fSDana Myers if ((*pmem_res && 21398fc7923fSDana Myers (phys_hi & PCI_PREFETCH_B)) || 21408fc7923fSDana Myers *mem_res) 214105f867c3Sgs break; 214205f867c3Sgs } 214305f867c3Sgs } 214405f867c3Sgs 21457c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = 21467c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = phys_hi; 21477c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 21487c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_mid = base_hi; 21497c478bd9Sstevel@tonic-gate type = base & ~PCI_BASE_M_ADDR_M; 21507c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 21517c478bd9Sstevel@tonic-gate 21527c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { 21537c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 21548fc7923fSDana Myers if (base != NULL) { 21558fc7923fSDana Myers /* remove from PMEM and MEM space */ 21568fc7923fSDana Myers (void) memlist_remove(mem_res, 21578fc7923fSDana Myers base, len); 21588fc7923fSDana Myers (void) memlist_remove(pmem_res, 21598fc7923fSDana Myers base, len); 21608fc7923fSDana Myers /* only note as used in correct map */ 21618fc7923fSDana Myers if (phys_hi & PCI_PREFETCH_B) 21628fc7923fSDana Myers memlist_insert(pmem_res_used, 216305f867c3Sgs base, len); 21648fc7923fSDana Myers else 21658fc7923fSDana Myers memlist_insert(mem_res_used, 216686ce93f0SGuoli Shu base, len); 2167*ffa17327SGuoli Shu } else { 21687c478bd9Sstevel@tonic-gate reprogram = 1; 2169*ffa17327SGuoli Shu } 2170*ffa17327SGuoli Shu pci_bus_res[bus].mem_size += len; 21718fc7923fSDana Myers } else if ((*mem_res && base == NULL) || 217205f867c3Sgs pci_bus_res[bus].mem_reprogram) { 21738fc7923fSDana Myers /* 21748fc7923fSDana Myers * When desired, attempt a prefetchable 21758fc7923fSDana Myers * allocation first 21768fc7923fSDana Myers */ 21778fc7923fSDana Myers if (phys_hi & PCI_PREFETCH_B) { 21788fc7923fSDana Myers base = (uint_t)memlist_find(pmem_res, 21798fc7923fSDana Myers len, len); 21808fc7923fSDana Myers if (base != NULL) { 21818fc7923fSDana Myers memlist_insert(pmem_res_used, 21828fc7923fSDana Myers base, len); 218386ce93f0SGuoli Shu (void) memlist_remove(mem_res, 218486ce93f0SGuoli Shu base, len); 21858fc7923fSDana Myers } 21868fc7923fSDana Myers } 21878fc7923fSDana Myers /* 21888fc7923fSDana Myers * If prefetchable allocation was not 21898fc7923fSDana Myers * desired, or failed, attempt ordinary 21908fc7923fSDana Myers * memory allocation 21918fc7923fSDana Myers */ 21928fc7923fSDana Myers if (base == NULL) { 21938fc7923fSDana Myers base = (uint_t)memlist_find(mem_res, 21948fc7923fSDana Myers len, len); 21958fc7923fSDana Myers if (base != NULL) { 21968fc7923fSDana Myers memlist_insert(mem_res_used, 21978fc7923fSDana Myers base, len); 219886ce93f0SGuoli Shu (void) memlist_remove(pmem_res, 219986ce93f0SGuoli Shu base, len); 220086ce93f0SGuoli Shu } 22018fc7923fSDana Myers } 22028fc7923fSDana Myers if (base != NULL) { 22037c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 22047c478bd9Sstevel@tonic-gate base | type); 22057c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 22067c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 22078fc7923fSDana Myers } else 22087c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program " 2209ebf3afa8Sdmick "mem space [%d/%d/%d] BAR@0x%x" 2210db063408Sdmick " length 0x%x", 2211ebf3afa8Sdmick bus, dev, func, offset, len); 22127c478bd9Sstevel@tonic-gate } 22137c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 22147c478bd9Sstevel@tonic-gate nreg++, nasgn++; 22157c478bd9Sstevel@tonic-gate } 22167c478bd9Sstevel@tonic-gate } 22177c478bd9Sstevel@tonic-gate switch (header) { 22187c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 22197c478bd9Sstevel@tonic-gate offset = PCI_CONF_ROM; 22207c478bd9Sstevel@tonic-gate break; 22217c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 22227c478bd9Sstevel@tonic-gate offset = PCI_BCNF_ROM; 22237c478bd9Sstevel@tonic-gate break; 22247c478bd9Sstevel@tonic-gate default: /* including PCI_HEADER_CARDBUS */ 22257c478bd9Sstevel@tonic-gate goto done; 22267c478bd9Sstevel@tonic-gate } 22277c478bd9Sstevel@tonic-gate 22287c478bd9Sstevel@tonic-gate /* 22297c478bd9Sstevel@tonic-gate * Add the expansion rom memory space 22307c478bd9Sstevel@tonic-gate * Determine the size of the ROM base reg; don't write reserved bits 22317c478bd9Sstevel@tonic-gate * ROM isn't in the PCI memory space. 22327c478bd9Sstevel@tonic-gate */ 22337c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 22347c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 22357c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 22367c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 223770025d76Sjohnny if (value & PCI_BASE_ROM_ENABLE) 223870025d76Sjohnny value &= PCI_BASE_ROM_ADDR_M; 223970025d76Sjohnny else 224070025d76Sjohnny value = 0; 22417c478bd9Sstevel@tonic-gate 22427c478bd9Sstevel@tonic-gate if (value != 0) { 22437c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 22447c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 22457c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | devloc) + offset; 22467c478bd9Sstevel@tonic-gate base &= PCI_BASE_ROM_ADDR_M; 22477c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 22487c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 22497c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 22507c478bd9Sstevel@tonic-gate nreg++, nasgn++; 225199ed6083Sszhou /* take it out of the memory resource */ 22528fc7923fSDana Myers if (base != NULL) { 225305f867c3Sgs (void) memlist_remove(mem_res, base, len); 22548fc7923fSDana Myers memlist_insert(mem_res_used, base, len); 22558fc7923fSDana Myers } 22567c478bd9Sstevel@tonic-gate } 22577c478bd9Sstevel@tonic-gate 22587c478bd9Sstevel@tonic-gate /* 22598fc7923fSDana Myers * Account for "legacy" (alias) video adapter resources 22607c478bd9Sstevel@tonic-gate */ 22617c478bd9Sstevel@tonic-gate 22627c478bd9Sstevel@tonic-gate /* add the three hard-decode, aliased address spaces for VGA */ 22637c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 22647c478bd9Sstevel@tonic-gate (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 22657c478bd9Sstevel@tonic-gate 22667c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3b0-0x3bb */ 22677c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 22687c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 22697c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 22707c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 22717c478bd9Sstevel@tonic-gate nreg++, nasgn++; 22728fc7923fSDana Myers (void) memlist_remove(io_res, 0x3b0, 0xc); 22738fc7923fSDana Myers memlist_insert(io_res_used, 0x3b0, 0xc); 22747c478bd9Sstevel@tonic-gate 22757c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3c0-0x3df */ 22767c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 22777c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 22787c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 22797c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 22807c478bd9Sstevel@tonic-gate nreg++, nasgn++; 22818fc7923fSDana Myers (void) memlist_remove(io_res, 0x3c0, 0x20); 22828fc7923fSDana Myers memlist_insert(io_res_used, 0x3c0, 0x20); 22837c478bd9Sstevel@tonic-gate 22847c478bd9Sstevel@tonic-gate /* Video memory */ 22857c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 22863e98767bSMax zhen (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc); 22877c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = 22887c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = 0xa0000; 22897c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 22907c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = 0x20000; 22917c478bd9Sstevel@tonic-gate nreg++, nasgn++; 22928fc7923fSDana Myers /* remove from MEM and PMEM space */ 22938fc7923fSDana Myers (void) memlist_remove(mem_res, 0xa0000, 0x20000); 22948fc7923fSDana Myers (void) memlist_remove(pmem_res, 0xa0000, 0x20000); 22958fc7923fSDana Myers memlist_insert(mem_res_used, 0xa0000, 0x20000); 22967c478bd9Sstevel@tonic-gate } 22977c478bd9Sstevel@tonic-gate 22987c478bd9Sstevel@tonic-gate /* add the hard-decode, aliased address spaces for 8514 */ 22997c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY) && 23009896aa55Sjveta (subclass == PCI_DISPLAY_VGA) && 23019896aa55Sjveta (progclass & PCI_DISPLAY_IF_8514)) { 23027c478bd9Sstevel@tonic-gate 23037c478bd9Sstevel@tonic-gate /* hard decode 0x2e8 */ 23047c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 23057c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 23067c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 23077c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 23087c478bd9Sstevel@tonic-gate nreg++, nasgn++; 23098fc7923fSDana Myers (void) memlist_remove(io_res, 0x2e8, 0x1); 23108fc7923fSDana Myers memlist_insert(io_res_used, 0x2e8, 0x1); 23117c478bd9Sstevel@tonic-gate 23127c478bd9Sstevel@tonic-gate /* hard decode 0x2ea-0x2ef */ 23137c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 23147c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 23157c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 23167c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 23177c478bd9Sstevel@tonic-gate nreg++, nasgn++; 23188fc7923fSDana Myers (void) memlist_remove(io_res, 0x2ea, 0x6); 23198fc7923fSDana Myers memlist_insert(io_res_used, 0x2ea, 0x6); 23207c478bd9Sstevel@tonic-gate } 23217c478bd9Sstevel@tonic-gate 23227c478bd9Sstevel@tonic-gate done: 23237c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 23247c478bd9Sstevel@tonic-gate (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 23257c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 23267c478bd9Sstevel@tonic-gate "assigned-addresses", 23277c478bd9Sstevel@tonic-gate (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2328c8711d4dSgs 23297c478bd9Sstevel@tonic-gate return (reprogram); 23307c478bd9Sstevel@tonic-gate } 23317c478bd9Sstevel@tonic-gate 23327c478bd9Sstevel@tonic-gate static void 233370025d76Sjohnny add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 233449fbdd30SErwin T Tsaur int pciex, ushort_t is_pci_bridge) 23357c478bd9Sstevel@tonic-gate { 233670025d76Sjohnny char *dev_type; 23377c478bd9Sstevel@tonic-gate int i; 23387c478bd9Sstevel@tonic-gate uint_t val, io_range[2], mem_range[2], pmem_range[2]; 23397c478bd9Sstevel@tonic-gate uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 23407c478bd9Sstevel@tonic-gate uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 234105f867c3Sgs uchar_t progclass; 234205f867c3Sgs 2343f55ce205Sszhou ASSERT(secbus <= subbus); 23447c478bd9Sstevel@tonic-gate 234505f867c3Sgs /* 234605f867c3Sgs * Check if it's a subtractive PPB. 234705f867c3Sgs */ 234805f867c3Sgs progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 234905f867c3Sgs if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 235005f867c3Sgs pci_bus_res[secbus].subtractive = B_TRUE; 235105f867c3Sgs 2352f55ce205Sszhou /* 2353f55ce205Sszhou * Some BIOSes lie about max pci busses, we allow for 2354f55ce205Sszhou * such mistakes here 2355f55ce205Sszhou */ 2356f55ce205Sszhou if (subbus > pci_bios_nbus) { 2357f55ce205Sszhou pci_bios_nbus = subbus; 2358f55ce205Sszhou alloc_res_array(); 2359f55ce205Sszhou } 2360f55ce205Sszhou 2361f55ce205Sszhou ASSERT(pci_bus_res[secbus].dip == NULL); 23627c478bd9Sstevel@tonic-gate pci_bus_res[secbus].dip = dip; 23637c478bd9Sstevel@tonic-gate pci_bus_res[secbus].par_bus = bus; 23647c478bd9Sstevel@tonic-gate 236549fbdd30SErwin T Tsaur dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 236670025d76Sjohnny 23677c478bd9Sstevel@tonic-gate /* setup bus number hierarchy */ 23687c478bd9Sstevel@tonic-gate pci_bus_res[secbus].sub_bus = subbus; 236953273e82Ssethg /* 237053273e82Ssethg * Keep track of the largest subordinate bus number (this is essential 237153273e82Ssethg * for peer busses because there is no other way of determining its 237253273e82Ssethg * subordinate bus number). 237353273e82Ssethg */ 23747c478bd9Sstevel@tonic-gate if (subbus > pci_bus_res[bus].sub_bus) 23757c478bd9Sstevel@tonic-gate pci_bus_res[bus].sub_bus = subbus; 237653273e82Ssethg /* 237753273e82Ssethg * Loop through subordinate busses, initializing their parent bus 237853273e82Ssethg * field to this bridge's parent. The subordinate busses' parent 237953273e82Ssethg * fields may very well be further refined later, as child bridges 238053273e82Ssethg * are enumerated. (The value is to note that the subordinate busses 238153273e82Ssethg * are not peer busses by changing their par_bus fields to anything 238253273e82Ssethg * other than -1.) 238353273e82Ssethg */ 23847c478bd9Sstevel@tonic-gate for (i = secbus + 1; i <= subbus; i++) 23857c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = bus; 23867c478bd9Sstevel@tonic-gate 23877c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 238870025d76Sjohnny "device_type", dev_type); 23897c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 23907c478bd9Sstevel@tonic-gate "#address-cells", 3); 23917c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 23927c478bd9Sstevel@tonic-gate "#size-cells", 2); 23937c478bd9Sstevel@tonic-gate 23947c478bd9Sstevel@tonic-gate /* 23957c478bd9Sstevel@tonic-gate * According to PPB spec, the base register should be programmed 23967c478bd9Sstevel@tonic-gate * with a value bigger than the limit register when there are 23977c478bd9Sstevel@tonic-gate * no resources available. This applies to io, memory, and 23987c478bd9Sstevel@tonic-gate * prefetchable memory. 23997c478bd9Sstevel@tonic-gate */ 24009896aa55Sjveta 24019896aa55Sjveta /* 24029896aa55Sjveta * io range 240305f867c3Sgs * We determine i/o windows that are left unconfigured by BIOS 24049896aa55Sjveta * through its i/o enable bit as Microsoft recommends OEMs to do. 24059896aa55Sjveta * If it is unset, we disable i/o and mark it for reconfiguration in 24069896aa55Sjveta * later passes by setting the base > limit 24079896aa55Sjveta */ 24089896aa55Sjveta val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 24099896aa55Sjveta if (val & PCI_COMM_IO) { 24109896aa55Sjveta val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 24119896aa55Sjveta io_range[0] = ((val & 0xf0) << 8); 24129896aa55Sjveta val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 24139896aa55Sjveta io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 24149896aa55Sjveta } else { 24159896aa55Sjveta io_range[0] = 0x9fff; 24169896aa55Sjveta io_range[1] = 0x1000; 24179896aa55Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 24189896aa55Sjveta (uint8_t)((io_range[0] >> 8) & 0xf0)); 24199896aa55Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 24209896aa55Sjveta (uint8_t)((io_range[1] >> 8) & 0xf0)); 24219896aa55Sjveta pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 24229896aa55Sjveta pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 24239896aa55Sjveta } 24249896aa55Sjveta 24257c478bd9Sstevel@tonic-gate if (io_range[0] != 0 && io_range[0] < io_range[1]) { 24267c478bd9Sstevel@tonic-gate memlist_insert(&pci_bus_res[secbus].io_ports, 24277c478bd9Sstevel@tonic-gate (uint64_t)io_range[0], 24287c478bd9Sstevel@tonic-gate (uint64_t)(io_range[1] - io_range[0] + 1)); 242905f867c3Sgs memlist_insert(&pci_bus_res[bus].io_ports_used, 243005f867c3Sgs (uint64_t)io_range[0], 243105f867c3Sgs (uint64_t)(io_range[1] - io_range[0] + 1)); 24327c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].io_ports != NULL) { 24337c478bd9Sstevel@tonic-gate (void) memlist_remove(&pci_bus_res[bus].io_ports, 24347c478bd9Sstevel@tonic-gate (uint64_t)io_range[0], 24357c478bd9Sstevel@tonic-gate (uint64_t)(io_range[1] - io_range[0] + 1)); 24367c478bd9Sstevel@tonic-gate } 24377c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 24387c478bd9Sstevel@tonic-gate secbus, io_range[0], io_range[1]); 24392269adc8Sszhou /* if 32-bit supported, make sure upper bits are not set */ 24402269adc8Sszhou if ((val & 0xf) == 1 && 24412269adc8Sszhou pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 24422269adc8Sszhou cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 24432269adc8Sszhou " pci-pci bridge [%d/%d/%d]", bus, dev, func); 24442269adc8Sszhou } 24457c478bd9Sstevel@tonic-gate } 24467c478bd9Sstevel@tonic-gate 24477c478bd9Sstevel@tonic-gate /* mem range */ 24487c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 24497c478bd9Sstevel@tonic-gate mem_range[0] = ((val & 0xFFF0) << 16); 24507c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 24517c478bd9Sstevel@tonic-gate mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 24527c478bd9Sstevel@tonic-gate if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 24537c478bd9Sstevel@tonic-gate memlist_insert(&pci_bus_res[secbus].mem_space, 24547c478bd9Sstevel@tonic-gate (uint64_t)mem_range[0], 24557c478bd9Sstevel@tonic-gate (uint64_t)(mem_range[1] - mem_range[0] + 1)); 245605f867c3Sgs memlist_insert(&pci_bus_res[bus].mem_space_used, 245705f867c3Sgs (uint64_t)mem_range[0], 245805f867c3Sgs (uint64_t)(mem_range[1] - mem_range[0] + 1)); 245986ce93f0SGuoli Shu /* remove from parent resource list */ 24608fc7923fSDana Myers (void) memlist_remove(&pci_bus_res[bus].mem_space, 24618fc7923fSDana Myers (uint64_t)mem_range[0], 24628fc7923fSDana Myers (uint64_t)(mem_range[1] - mem_range[0] + 1)); 24638fc7923fSDana Myers (void) memlist_remove(&pci_bus_res[bus].pmem_space, 24648fc7923fSDana Myers (uint64_t)mem_range[0], 24658fc7923fSDana Myers (uint64_t)(mem_range[1] - mem_range[0] + 1)); 24667c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 24677c478bd9Sstevel@tonic-gate secbus, mem_range[0], mem_range[1]); 24687c478bd9Sstevel@tonic-gate } 24697c478bd9Sstevel@tonic-gate 24707c478bd9Sstevel@tonic-gate /* prefetchable memory range */ 24717c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 24727c478bd9Sstevel@tonic-gate pmem_range[0] = ((val & 0xFFF0) << 16); 24737c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 24747c478bd9Sstevel@tonic-gate pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 24757c478bd9Sstevel@tonic-gate if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 24767c478bd9Sstevel@tonic-gate memlist_insert(&pci_bus_res[secbus].pmem_space, 24777c478bd9Sstevel@tonic-gate (uint64_t)pmem_range[0], 24787c478bd9Sstevel@tonic-gate (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 247905f867c3Sgs memlist_insert(&pci_bus_res[bus].pmem_space_used, 248005f867c3Sgs (uint64_t)pmem_range[0], 248105f867c3Sgs (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 248286ce93f0SGuoli Shu /* remove from parent resource list */ 24838fc7923fSDana Myers (void) memlist_remove(&pci_bus_res[bus].pmem_space, 24848fc7923fSDana Myers (uint64_t)pmem_range[0], 24858fc7923fSDana Myers (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 24868fc7923fSDana Myers (void) memlist_remove(&pci_bus_res[bus].mem_space, 24878fc7923fSDana Myers (uint64_t)pmem_range[0], 24888fc7923fSDana Myers (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 24897c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 24907c478bd9Sstevel@tonic-gate secbus, pmem_range[0], pmem_range[1]); 24912269adc8Sszhou /* if 64-bit supported, make sure upper bits are not set */ 24922269adc8Sszhou if ((val & 0xf) == 1 && 24932269adc8Sszhou pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 24942269adc8Sszhou cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 24952269adc8Sszhou " pci-pci bridge [%d/%d/%d]", bus, dev, func); 24962269adc8Sszhou } 24977c478bd9Sstevel@tonic-gate } 24987c478bd9Sstevel@tonic-gate 24997c478bd9Sstevel@tonic-gate add_bus_range_prop(secbus); 25008fc7923fSDana Myers add_ranges_prop(secbus, 1); 25017c478bd9Sstevel@tonic-gate } 25027c478bd9Sstevel@tonic-gate 250309f67678Sanish extern const struct pci_class_strings_s class_pci[]; 250409f67678Sanish extern int class_pci_items; 25057c478bd9Sstevel@tonic-gate 25067c478bd9Sstevel@tonic-gate static void 25077c478bd9Sstevel@tonic-gate add_model_prop(dev_info_t *dip, uint_t classcode) 25087c478bd9Sstevel@tonic-gate { 25097c478bd9Sstevel@tonic-gate const char *desc; 25107c478bd9Sstevel@tonic-gate int i; 25117c478bd9Sstevel@tonic-gate uchar_t baseclass = classcode >> 16; 25127c478bd9Sstevel@tonic-gate uchar_t subclass = (classcode >> 8) & 0xff; 25137c478bd9Sstevel@tonic-gate uchar_t progclass = classcode & 0xff; 25147c478bd9Sstevel@tonic-gate 25157c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 25167c478bd9Sstevel@tonic-gate desc = "IDE controller"; 25177c478bd9Sstevel@tonic-gate } else { 25187c478bd9Sstevel@tonic-gate for (desc = 0, i = 0; i < class_pci_items; i++) { 25197c478bd9Sstevel@tonic-gate if ((baseclass == class_pci[i].base_class) && 25207c478bd9Sstevel@tonic-gate (subclass == class_pci[i].sub_class) && 25217c478bd9Sstevel@tonic-gate (progclass == class_pci[i].prog_class)) { 252209f67678Sanish desc = class_pci[i].actual_desc; 25237c478bd9Sstevel@tonic-gate break; 25247c478bd9Sstevel@tonic-gate } 25257c478bd9Sstevel@tonic-gate } 252609f67678Sanish if (i == class_pci_items) 25277c478bd9Sstevel@tonic-gate desc = "Unknown class of pci/pnpbios device"; 25287c478bd9Sstevel@tonic-gate } 25297c478bd9Sstevel@tonic-gate 25307c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 25317c478bd9Sstevel@tonic-gate (char *)desc); 25327c478bd9Sstevel@tonic-gate } 25337c478bd9Sstevel@tonic-gate 25347c478bd9Sstevel@tonic-gate static void 25357c478bd9Sstevel@tonic-gate add_bus_range_prop(int bus) 25367c478bd9Sstevel@tonic-gate { 25377c478bd9Sstevel@tonic-gate int bus_range[2]; 25387c478bd9Sstevel@tonic-gate 25397c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].dip == NULL) 25407c478bd9Sstevel@tonic-gate return; 25417c478bd9Sstevel@tonic-gate bus_range[0] = bus; 25427c478bd9Sstevel@tonic-gate bus_range[1] = pci_bus_res[bus].sub_bus; 25437c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 25447c478bd9Sstevel@tonic-gate "bus-range", (int *)bus_range, 2); 25457c478bd9Sstevel@tonic-gate } 25467c478bd9Sstevel@tonic-gate 2547b1f176e8Sjg /* 2548b1f176e8Sjg * Add slot-names property for any named pci hot-plug slots 2549b1f176e8Sjg */ 2550b1f176e8Sjg static void 2551b1f176e8Sjg add_bus_slot_names_prop(int bus) 2552b1f176e8Sjg { 2553b1f176e8Sjg char slotprop[256]; 2554b1f176e8Sjg int len; 2555b1f176e8Sjg 2556d57b3b3dSprasad if (pci_bus_res[bus].dip != NULL) { 2557d57b3b3dSprasad /* simply return if the property is already defined */ 2558d57b3b3dSprasad if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 2559d57b3b3dSprasad DDI_PROP_DONTPASS, "slot-names")) 2560d57b3b3dSprasad return; 2561d57b3b3dSprasad } 2562d57b3b3dSprasad 2563b1f176e8Sjg len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 2564b1f176e8Sjg if (len > 0) { 256553273e82Ssethg /* 256653273e82Ssethg * Only create a peer bus node if this bus may be a peer bus. 256753273e82Ssethg * It may be a peer bus if the dip is NULL and if par_bus is 256853273e82Ssethg * -1 (par_bus is -1 if this bus was not found to be 256953273e82Ssethg * subordinate to any PCI-PCI bridge). 257053273e82Ssethg * If it's not a peer bus, then the ACPI BBN-handling code 257153273e82Ssethg * will remove it later. 257253273e82Ssethg */ 257353273e82Ssethg if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 257453273e82Ssethg pci_bus_res[bus].dip == NULL) { 257553273e82Ssethg 2576b1f176e8Sjg create_root_bus_dip(bus); 257753273e82Ssethg } 257853273e82Ssethg if (pci_bus_res[bus].dip != NULL) { 257953273e82Ssethg ASSERT((len % sizeof (int)) == 0); 258053273e82Ssethg (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 258153273e82Ssethg pci_bus_res[bus].dip, "slot-names", 258253273e82Ssethg (int *)slotprop, len / sizeof (int)); 258353273e82Ssethg } else { 258453273e82Ssethg cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 258553273e82Ssethg "IRQ routing table; Not adding slot-names " 258653273e82Ssethg "property for incorrect bus %d", bus); 258753273e82Ssethg } 2588b1f176e8Sjg } 2589b1f176e8Sjg } 2590b1f176e8Sjg 25918fc7923fSDana Myers /* 25928fc7923fSDana Myers * Handle both PCI root and PCI-PCI bridge range properties; 25938fc7923fSDana Myers * non-zero 'ppb' argument select PCI-PCI bridges versus root. 25948fc7923fSDana Myers */ 25958fc7923fSDana Myers static void 25968fc7923fSDana Myers memlist_to_ranges(void **rp, struct memlist *entry, int type, int ppb) 25977c478bd9Sstevel@tonic-gate { 25988fc7923fSDana Myers ppb_ranges_t *ppb_rp = *rp; 25998fc7923fSDana Myers pci_ranges_t *pci_rp = *rp; 26008fc7923fSDana Myers 26018fc7923fSDana Myers while (entry != NULL) { 26028fc7923fSDana Myers if (ppb) { 26038fc7923fSDana Myers ppb_rp->child_high = ppb_rp->parent_high = type; 26048fc7923fSDana Myers ppb_rp->child_mid = ppb_rp->parent_mid = 26058fc7923fSDana Myers (uint32_t)(entry->address >> 32); /* XXX */ 26068fc7923fSDana Myers ppb_rp->child_low = ppb_rp->parent_low = 26078fc7923fSDana Myers (uint32_t)entry->address; 26088fc7923fSDana Myers ppb_rp->size_high = 26098fc7923fSDana Myers (uint32_t)(entry->size >> 32); /* XXX */ 26108fc7923fSDana Myers ppb_rp->size_low = (uint32_t)entry->size; 26118fc7923fSDana Myers *rp = ++ppb_rp; 26128fc7923fSDana Myers } else { 26138fc7923fSDana Myers pci_rp->child_high = type; 26148fc7923fSDana Myers pci_rp->child_mid = pci_rp->parent_high = 26158fc7923fSDana Myers (uint32_t)(entry->address >> 32); /* XXX */ 26168fc7923fSDana Myers pci_rp->child_low = pci_rp->parent_low = 26178fc7923fSDana Myers (uint32_t)entry->address; 26188fc7923fSDana Myers pci_rp->size_high = 26198fc7923fSDana Myers (uint32_t)(entry->size >> 32); /* XXX */ 26208fc7923fSDana Myers pci_rp->size_low = (uint32_t)entry->size; 26218fc7923fSDana Myers *rp = ++pci_rp; 26228fc7923fSDana Myers } 26238fc7923fSDana Myers entry = entry->next; 26248fc7923fSDana Myers } 26258fc7923fSDana Myers } 26267c478bd9Sstevel@tonic-gate 26278fc7923fSDana Myers static void 26288fc7923fSDana Myers add_ranges_prop(int bus, int ppb) 26298fc7923fSDana Myers { 26308fc7923fSDana Myers int total, alloc_size; 26318fc7923fSDana Myers void *rp, *next_rp; 26328fc7923fSDana Myers 2633ec0c94e7SDana Myers /* no devinfo node - unused bus, return */ 2634ec0c94e7SDana Myers if (pci_bus_res[bus].dip == NULL) 2635ec0c94e7SDana Myers return; 2636ec0c94e7SDana Myers 26378fc7923fSDana Myers total = memlist_count(pci_bus_res[bus].io_ports); 26388fc7923fSDana Myers total += memlist_count(pci_bus_res[bus].mem_space); 26398fc7923fSDana Myers total += memlist_count(pci_bus_res[bus].pmem_space); 26408fc7923fSDana Myers 26418fc7923fSDana Myers /* no property is created if no ranges are present */ 26428fc7923fSDana Myers if (total == 0) 26438fc7923fSDana Myers return; 26448fc7923fSDana Myers 26458fc7923fSDana Myers alloc_size = total * 26468fc7923fSDana Myers (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); 26478fc7923fSDana Myers 26488fc7923fSDana Myers next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); 26498fc7923fSDana Myers 26508fc7923fSDana Myers memlist_to_ranges(&next_rp, pci_bus_res[bus].io_ports, 26518fc7923fSDana Myers PCI_ADDR_IO | PCI_REG_REL_M, ppb); 26528fc7923fSDana Myers memlist_to_ranges(&next_rp, pci_bus_res[bus].mem_space, 26538fc7923fSDana Myers PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb); 26548fc7923fSDana Myers memlist_to_ranges(&next_rp, pci_bus_res[bus].pmem_space, 26558fc7923fSDana Myers PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb); 26568fc7923fSDana Myers 26578fc7923fSDana Myers (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 26588fc7923fSDana Myers "ranges", (int *)rp, alloc_size / sizeof (int)); 26598fc7923fSDana Myers 26608fc7923fSDana Myers kmem_free(rp, alloc_size); 26617c478bd9Sstevel@tonic-gate } 26627c478bd9Sstevel@tonic-gate 26637c478bd9Sstevel@tonic-gate static void 26648fc7923fSDana Myers memlist_remove_list(struct memlist **list, struct memlist *remove_list) 26657c478bd9Sstevel@tonic-gate { 26668fc7923fSDana Myers while (list && *list && remove_list) { 26678fc7923fSDana Myers (void) memlist_remove(list, remove_list->address, 26688fc7923fSDana Myers remove_list->size); 26698fc7923fSDana Myers remove_list = remove_list->next; 26708fc7923fSDana Myers } 26717c478bd9Sstevel@tonic-gate } 26727c478bd9Sstevel@tonic-gate 26737c478bd9Sstevel@tonic-gate static int 26747c478bd9Sstevel@tonic-gate memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 26757c478bd9Sstevel@tonic-gate { 26767c478bd9Sstevel@tonic-gate int i = 0; 26777c478bd9Sstevel@tonic-gate 26787c478bd9Sstevel@tonic-gate while (list) { 26797c478bd9Sstevel@tonic-gate /* assume 32-bit addresses */ 26807c478bd9Sstevel@tonic-gate sp->pci_phys_hi = type; 26817c478bd9Sstevel@tonic-gate sp->pci_phys_mid = 0; 26827c478bd9Sstevel@tonic-gate sp->pci_phys_low = (uint32_t)list->address; 26837c478bd9Sstevel@tonic-gate sp->pci_size_hi = 0; 26847c478bd9Sstevel@tonic-gate sp->pci_size_low = (uint32_t)list->size; 26857c478bd9Sstevel@tonic-gate 26867c478bd9Sstevel@tonic-gate list = list->next; 26877c478bd9Sstevel@tonic-gate sp++, i++; 26887c478bd9Sstevel@tonic-gate } 26897c478bd9Sstevel@tonic-gate return (i); 26907c478bd9Sstevel@tonic-gate } 26917c478bd9Sstevel@tonic-gate 26927c478bd9Sstevel@tonic-gate static void 26937c478bd9Sstevel@tonic-gate add_bus_available_prop(int bus) 26947c478bd9Sstevel@tonic-gate { 26957c478bd9Sstevel@tonic-gate int i, count; 26967c478bd9Sstevel@tonic-gate struct pci_phys_spec *sp; 26977c478bd9Sstevel@tonic-gate 2698ec0c94e7SDana Myers /* no devinfo node - unused bus, return */ 2699ec0c94e7SDana Myers if (pci_bus_res[bus].dip == NULL) 2700ec0c94e7SDana Myers return; 2701ec0c94e7SDana Myers 27027c478bd9Sstevel@tonic-gate count = memlist_count(pci_bus_res[bus].io_ports) + 27037c478bd9Sstevel@tonic-gate memlist_count(pci_bus_res[bus].mem_space) + 27047c478bd9Sstevel@tonic-gate memlist_count(pci_bus_res[bus].pmem_space); 27057c478bd9Sstevel@tonic-gate 27067c478bd9Sstevel@tonic-gate if (count == 0) /* nothing available */ 27077c478bd9Sstevel@tonic-gate return; 27087c478bd9Sstevel@tonic-gate 27097c478bd9Sstevel@tonic-gate sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 27107c478bd9Sstevel@tonic-gate i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 27117c478bd9Sstevel@tonic-gate PCI_ADDR_IO | PCI_REG_REL_M); 27127c478bd9Sstevel@tonic-gate i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 27137c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M); 27147c478bd9Sstevel@tonic-gate i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 27157c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 27167c478bd9Sstevel@tonic-gate ASSERT(i == count); 27177c478bd9Sstevel@tonic-gate 27187c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 27197c478bd9Sstevel@tonic-gate "available", (int *)sp, 27207c478bd9Sstevel@tonic-gate i * sizeof (struct pci_phys_spec) / sizeof (int)); 27217c478bd9Sstevel@tonic-gate kmem_free(sp, count * sizeof (*sp)); 27227c478bd9Sstevel@tonic-gate } 2723f55ce205Sszhou 2724f55ce205Sszhou static void 2725f55ce205Sszhou alloc_res_array(void) 2726f55ce205Sszhou { 2727f55ce205Sszhou static int array_max = 0; 2728f55ce205Sszhou int old_max; 2729f55ce205Sszhou void *old_res; 2730f55ce205Sszhou 2731f55ce205Sszhou if (array_max > pci_bios_nbus + 1) 2732f55ce205Sszhou return; /* array is big enough */ 2733f55ce205Sszhou 2734f55ce205Sszhou old_max = array_max; 2735f55ce205Sszhou old_res = pci_bus_res; 2736f55ce205Sszhou 2737f55ce205Sszhou if (array_max == 0) 2738f55ce205Sszhou array_max = 16; /* start with a reasonable number */ 2739f55ce205Sszhou 2740f55ce205Sszhou while (array_max < pci_bios_nbus + 1) 2741f55ce205Sszhou array_max <<= 1; 2742f55ce205Sszhou pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 2743f55ce205Sszhou array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 2744f55ce205Sszhou 2745f55ce205Sszhou if (old_res) { /* copy content and free old array */ 2746f55ce205Sszhou bcopy(old_res, pci_bus_res, 2747f55ce205Sszhou old_max * sizeof (struct pci_bus_resource)); 2748f55ce205Sszhou kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 2749f55ce205Sszhou } 2750f55ce205Sszhou } 2751c8589f13Ssethg 2752c8589f13Ssethg static void 2753c8589f13Ssethg create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 2754c8589f13Ssethg ushort_t deviceid) 2755c8589f13Ssethg { 2756c8589f13Ssethg static dev_info_t *ioapicsnode = NULL; 2757c8589f13Ssethg static int numioapics = 0; 2758c8589f13Ssethg dev_info_t *ioapic_node; 2759c8589f13Ssethg uint64_t physaddr; 2760c8589f13Ssethg uint32_t lobase, hibase = 0; 2761c8589f13Ssethg 2762c8589f13Ssethg /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 2763c8589f13Ssethg lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 2764c8589f13Ssethg 2765c8589f13Ssethg /* We (and the rest of the world) only support memory-mapped IOAPICs */ 2766c8589f13Ssethg if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 2767c8589f13Ssethg return; 2768c8589f13Ssethg 2769c8589f13Ssethg if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 2770c8589f13Ssethg hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 2771c8589f13Ssethg 2772c8589f13Ssethg lobase &= PCI_BASE_M_ADDR_M; 2773c8589f13Ssethg 2774c8589f13Ssethg physaddr = (((uint64_t)hibase) << 32) | lobase; 2775c8589f13Ssethg 2776c8589f13Ssethg /* 2777c8589f13Ssethg * Create a nexus node for all IOAPICs under the root node. 2778c8589f13Ssethg */ 2779c8589f13Ssethg if (ioapicsnode == NULL) { 2780c8589f13Ssethg if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 2781c8589f13Ssethg (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 2782c8589f13Ssethg return; 2783c8589f13Ssethg } 2784c8589f13Ssethg (void) ndi_devi_online(ioapicsnode, 0); 2785c8589f13Ssethg } 2786c8589f13Ssethg 2787c8589f13Ssethg /* 2788c8589f13Ssethg * Create a child node for this IOAPIC 2789c8589f13Ssethg */ 2790c8589f13Ssethg ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 2791c8589f13Ssethg DEVI_SID_NODEID, numioapics++); 2792c8589f13Ssethg if (ioapic_node == NULL) { 2793c8589f13Ssethg return; 2794c8589f13Ssethg } 2795c8589f13Ssethg 2796c8589f13Ssethg /* Vendor and Device ID */ 2797c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2798c8589f13Ssethg IOAPICS_PROP_VENID, vendorid); 2799c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2800c8589f13Ssethg IOAPICS_PROP_DEVID, deviceid); 2801c8589f13Ssethg 2802c8589f13Ssethg /* device_type */ 2803c8589f13Ssethg (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 2804c8589f13Ssethg "device_type", IOAPICS_DEV_TYPE); 2805c8589f13Ssethg 2806c8589f13Ssethg /* reg */ 2807c8589f13Ssethg (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 2808c8589f13Ssethg "reg", physaddr); 2809c8589f13Ssethg } 2810d57b3b3dSprasad 2811d57b3b3dSprasad /* 2812d57b3b3dSprasad * NOTE: For PCIe slots, the name is generated from the slot number 2813d57b3b3dSprasad * information obtained from Slot Capabilities register. 2814d57b3b3dSprasad * For non-PCIe slots, it is generated based on the slot number 2815d57b3b3dSprasad * information in the PCI IRQ table. 2816d57b3b3dSprasad */ 2817d57b3b3dSprasad static void 2818d57b3b3dSprasad pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 2819d57b3b3dSprasad { 2820d57b3b3dSprasad char slotprop[256]; 2821d57b3b3dSprasad int len; 2822d57b3b3dSprasad 2823d57b3b3dSprasad bzero(slotprop, sizeof (slotprop)); 2824d57b3b3dSprasad 2825d57b3b3dSprasad /* set mask to 1 as there is only one slot (i.e dev 0) */ 2826d57b3b3dSprasad *(uint32_t *)slotprop = 1; 2827d57b3b3dSprasad len = 4; 2828d57b3b3dSprasad (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 2829d57b3b3dSprasad slot_num); 2830d57b3b3dSprasad len += strlen(slotprop + len) + 1; 2831d57b3b3dSprasad len += len % 4; 2832d57b3b3dSprasad (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 2833d57b3b3dSprasad (int *)slotprop, len / sizeof (int)); 2834d57b3b3dSprasad } 2835