1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/stat.h> 30 #include <sys/sunndi.h> 31 #include <sys/pci.h> 32 #include <sys/pci_impl.h> 33 #include <sys/pci_cfgspace.h> 34 #include <sys/memlist.h> 35 #include <sys/bootconf.h> 36 #include <io/pci/mps_table.h> 37 #include <sys/pci_cfgspace.h> 38 #include <sys/pci_cfgspace_impl.h> 39 #include <sys/psw.h> 40 #include "../../../../common/pci/pci_strings.h" 41 #include <io/pciex/pcie_ck804_boot.h> 42 #include <sys/acpi/acpi.h> 43 #include <sys/acpica.h> 44 45 #define pci_getb (*pci_getb_func) 46 #define pci_getw (*pci_getw_func) 47 #define pci_getl (*pci_getl_func) 48 #define pci_putb (*pci_putb_func) 49 #define pci_putw (*pci_putw_func) 50 #define pci_putl (*pci_putl_func) 51 #define dcmn_err if (pci_boot_debug) cmn_err 52 53 #define CONFIG_INFO 0 54 #define CONFIG_UPDATE 1 55 #define CONFIG_NEW 2 56 #define COMPAT_BUFSIZE 512 57 58 extern int pci_bios_nbus; 59 static uchar_t max_dev_pci = 32; /* PCI standard */ 60 int pci_boot_debug = 0; 61 extern struct memlist *find_bus_res(int, int); 62 63 /* 64 * Module prototypes 65 */ 66 static void enumerate_bus_devs(uchar_t bus, int config_op); 67 static void create_root_bus_dip(uchar_t bus); 68 static dev_info_t *new_func_pci(uchar_t, uchar_t, uchar_t, uchar_t, 69 ushort_t, int); 70 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 71 ushort_t, ushort_t, uchar_t, uint_t, int); 72 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 73 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int); 74 static void add_model_prop(dev_info_t *, uint_t); 75 static void add_bus_range_prop(int); 76 static void add_bus_slot_names_prop(int); 77 static void add_ppb_ranges_prop(int); 78 static void add_bus_available_prop(int); 79 static void alloc_res_array(); 80 81 extern int pci_slot_names_prop(int, char *, int); 82 83 /* set non-zero to force PCI peer-bus renumbering */ 84 int pci_bus_always_renumber = 0; 85 86 /* get the subordinate bus # for a root/peer bus */ 87 static int 88 pci_root_subbus(int bus, uchar_t *subbus) 89 { 90 ACPI_HANDLE hdl; 91 ACPI_BUFFER rb; 92 ACPI_RESOURCE *rp; 93 int rv; 94 95 if (pci_bus_res[bus].dip == NULL) { 96 /* non-used bus # */ 97 return (AE_ERROR); 98 } 99 if (acpica_find_pciobj(pci_bus_res[bus].dip, &hdl) != AE_OK) { 100 cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus); 101 return (AE_ERROR); 102 } 103 104 rb.Length = ACPI_ALLOCATE_BUFFER; 105 if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) { 106 cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus); 107 return (AE_ERROR); 108 } 109 110 rv = AE_ERROR; 111 112 for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG; 113 rp = ACPI_NEXT_RESOURCE(rp)) { 114 115 switch (rp->Type) { 116 case ACPI_RESOURCE_TYPE_ADDRESS16: 117 if (rp->Data.Address.ResourceType 118 != ACPI_BUS_NUMBER_RANGE) 119 continue; 120 *subbus = (uchar_t)rp->Data.Address16.Maximum; 121 dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus); 122 break; 123 case ACPI_RESOURCE_TYPE_ADDRESS32: 124 if (rp->Data.Address.ResourceType 125 != ACPI_BUS_NUMBER_RANGE) 126 continue; 127 *subbus = (uchar_t)rp->Data.Address32.Maximum; 128 dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus); 129 break; 130 case ACPI_RESOURCE_TYPE_ADDRESS64: 131 if (rp->Data.Address.ResourceType 132 != ACPI_BUS_NUMBER_RANGE) 133 continue; 134 *subbus = (uchar_t)rp->Data.Address64.Maximum; 135 dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus); 136 break; 137 case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: 138 if (rp->Data.Address.ResourceType 139 != ACPI_BUS_NUMBER_RANGE) 140 continue; 141 *subbus = (uchar_t)rp->Data.ExtAddress64.Maximum; 142 dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus); 143 break; 144 default: 145 dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type); 146 continue; 147 } 148 149 /* found the bus-range resource */ 150 dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus); 151 rv = AE_OK; 152 153 /* This breaks out of the resource scanning loop */ 154 break; 155 } 156 157 AcpiOsFree(rb.Pointer); 158 if (rv != AE_OK) 159 cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus); 160 161 return (rv); 162 163 } 164 165 /* 166 * Enumerate all PCI devices 167 */ 168 void 169 pci_setup_tree() 170 { 171 uchar_t i, root_bus_addr = 0; 172 173 alloc_res_array(); 174 for (i = 0; i <= pci_bios_nbus; i++) { 175 pci_bus_res[i].par_bus = (uchar_t)-1; 176 pci_bus_res[i].root_addr = (uchar_t)-1; 177 pci_bus_res[i].sub_bus = i; 178 } 179 180 pci_bus_res[0].root_addr = root_bus_addr++; 181 create_root_bus_dip(0); 182 enumerate_bus_devs(0, CONFIG_INFO); 183 184 /* 185 * Now enumerate peer busses 186 * 187 * We loop till pci_bios_nbus. On most systems, there is 188 * one more bus at the high end, which implements the ISA 189 * compatibility bus. We don't care about that. 190 * 191 * Note: In the old (bootconf) enumeration, the peer bus 192 * address did not use the bus number, and there were 193 * too many peer busses created. The root_bus_addr is 194 * used to maintain the old peer bus address assignment. 195 * However, we stop enumerating phantom peers with no 196 * device below. 197 */ 198 for (i = 1; i <= pci_bios_nbus; i++) { 199 if (pci_bus_res[i].dip == NULL) { 200 pci_bus_res[i].root_addr = root_bus_addr++; 201 } 202 enumerate_bus_devs(i, CONFIG_INFO); 203 204 /* add slot-names property for named pci hot-plug slots */ 205 add_bus_slot_names_prop(i); 206 } 207 208 } 209 210 /* 211 * >0 = present, 0 = not present, <0 = error 212 */ 213 static int 214 pci_bbn_present(int bus) 215 { 216 ACPI_HANDLE hdl; 217 ACPI_BUFFER rb; 218 int rv; 219 220 /* no dip means no _BBN */ 221 if (pci_bus_res[bus].dip == NULL) 222 return (0); 223 224 rv = acpica_find_pciobj(pci_bus_res[bus].dip, &hdl); 225 if (rv != AE_OK) 226 return (-1); 227 228 rb.Length = ACPI_ALLOCATE_BUFFER; 229 230 rv = AcpiEvaluateObject(hdl, "_BBN", NULL, &rb); 231 232 if (rb.Length > 0) 233 AcpiOsFree(rb.Pointer); 234 235 if (rv == AE_OK) 236 return (1); 237 else if (rv == AE_NOT_FOUND) 238 return (0); 239 else 240 return (-1); 241 } 242 243 /* 244 * Return non-zero if any PCI bus in the system has an associated 245 * _BBN object, 0 otherwise. 246 */ 247 static int 248 pci_roots_have_bbn(void) 249 { 250 int i; 251 252 /* 253 * Scan the PCI busses and look for at least 1 _BBN 254 */ 255 for (i = 0; i <= pci_bios_nbus; i++) { 256 /* skip non-root (peer) PCI busses */ 257 if (pci_bus_res[i].par_bus != (uchar_t)-1) 258 continue; 259 260 if (pci_bbn_present(i) > 0) 261 return (1); 262 } 263 return (0); 264 265 } 266 267 /* 268 * return non-zero if the machine is one on which we renumber 269 * the internal pci unit-addresses 270 */ 271 static int 272 pci_bus_renumber() 273 { 274 ACPI_TABLE_HEADER *fadt; 275 276 if (pci_bus_always_renumber) 277 return (1); 278 279 /* get the FADT */ 280 if (AcpiGetFirmwareTable(FADT_SIG, 1, ACPI_LOGICAL_ADDRESSING, 281 (ACPI_TABLE_HEADER **)&fadt) != AE_OK) 282 return (0); 283 284 /* compare OEM Table ID to "SUNm31" */ 285 if (strncmp("SUNm31", fadt->OemId, 6)) 286 return (0); 287 else 288 return (1); 289 } 290 291 /* 292 * Initial enumeration of the physical PCI bus hierarchy can 293 * leave 'gaps' in the order of peer PCI bus unit-addresses. 294 * Systems with more than one peer PCI bus *must* have an ACPI 295 * _BBN object associated with each peer bus; use the presence 296 * of this object to remove gaps in the numbering of the peer 297 * PCI bus unit-addresses - only peer busses with an associated 298 * _BBN are counted. 299 */ 300 static void 301 pci_renumber_root_busses(void) 302 { 303 int pci_regs[] = {0, 0, 0}; 304 int i, root_addr = 0; 305 306 /* 307 * Currently, we only enable the re-numbering on specific 308 * Sun machines; this is a work-around for the more complicated 309 * issue of upgrade changing physical device paths 310 */ 311 if (!pci_bus_renumber()) 312 return; 313 314 /* 315 * If we find no _BBN objects at all, we either don't need 316 * to do anything or can't do anything anyway 317 */ 318 if (!pci_roots_have_bbn()) 319 return; 320 321 for (i = 0; i <= pci_bios_nbus; i++) { 322 /* skip non-root (peer) PCI busses */ 323 if (pci_bus_res[i].par_bus != (uchar_t)-1) 324 continue; 325 326 if (pci_bbn_present(i) < 1) { 327 pci_bus_res[i].root_addr = (uchar_t)-1; 328 continue; 329 } 330 331 ASSERT(pci_bus_res[i].dip != NULL); 332 if (pci_bus_res[i].root_addr != root_addr) { 333 /* update reg property for node */ 334 pci_bus_res[i].root_addr = root_addr; 335 pci_regs[0] = pci_bus_res[i].root_addr; 336 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 337 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 338 } 339 root_addr++; 340 } 341 } 342 343 void 344 pci_reprogram(void) 345 { 346 int i, pci_reconfig = 1; 347 char *onoff; 348 349 /* 350 * Excise phantom roots if possible 351 */ 352 pci_renumber_root_busses(); 353 354 /* add bus-range property for root/peer bus nodes */ 355 for (i = 0; i <= pci_bios_nbus; i++) { 356 if (pci_bus_res[i].par_bus == (uchar_t)-1) { 357 uchar_t subbus; 358 if (pci_root_subbus(i, &subbus) == AE_OK) 359 pci_bus_res[i].sub_bus = subbus; 360 add_bus_range_prop(i); 361 } 362 } 363 364 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 365 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 366 if (strcmp(onoff, "off") == 0) { 367 pci_reconfig = 0; 368 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 369 } 370 ddi_prop_free(onoff); 371 } 372 373 for (i = 0; i <= pci_bios_nbus; i++) { 374 /* configure devices not configured by bios */ 375 if (pci_reconfig) 376 enumerate_bus_devs(i, CONFIG_NEW); 377 /* All dev programmed, so we can create available prop */ 378 add_bus_available_prop(i); 379 } 380 } 381 382 /* 383 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 384 */ 385 static void 386 create_root_bus_dip(uchar_t bus) 387 { 388 int pci_regs[] = {0, 0, 0}; 389 dev_info_t *dip; 390 391 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 392 393 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 394 (pnode_t)DEVI_SID_NODEID, &dip); 395 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 396 "#address-cells", 3); 397 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 398 "#size-cells", 2); 399 pci_regs[0] = pci_bus_res[bus].root_addr; 400 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 401 "reg", (int *)pci_regs, 3); 402 403 /* 404 * If system has PCIe bus, then create different properties 405 */ 406 if (create_pcie_root_bus(bus, dip) == B_FALSE) 407 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 408 "device_type", "pci"); 409 410 (void) ndi_devi_bind_driver(dip, 0); 411 pci_bus_res[bus].dip = dip; 412 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 413 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 414 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 415 416 if (bus != 0) 417 return; 418 419 /* 420 * Special treatment of bus 0: 421 * If no resource from MPSPEC/HRT, copy pcimem from boot 422 * and make io space the entire range. There is no difference 423 * between prefetchable memory or not. 424 */ 425 if (pci_bus_res[0].mem_space == NULL) 426 pci_bus_res[0].mem_space = 427 memlist_dup(bootops->boot_mem->pcimem); 428 if (pci_bus_res[0].io_ports == NULL) 429 memlist_insert(&pci_bus_res[0].io_ports, 0, 0x10000); 430 } 431 432 /* 433 * For any fixed configuration (often compatability) pci devices 434 * and those with their own expansion rom, create device nodes 435 * to hold the already configured device details. 436 */ 437 void 438 enumerate_bus_devs(uchar_t bus, int config_op) 439 { 440 uchar_t dev, func, nfunc, header; 441 ushort_t venid; 442 dev_info_t *dip; 443 struct pci_devfunc { 444 struct pci_devfunc *next; 445 dev_info_t *dip; 446 uchar_t bus; 447 uchar_t dev; 448 uchar_t func; 449 } *devlist = NULL, *entry; 450 451 if (config_op == CONFIG_NEW) { 452 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 453 } else 454 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 455 456 for (dev = 0; dev < max_dev_pci; dev++) { 457 nfunc = 1; 458 for (func = 0; func < nfunc; func++) { 459 460 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 461 dev, func); 462 463 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 464 if ((venid == 0xffff) || (venid == 0)) { 465 /* no function at this address */ 466 continue; 467 } 468 469 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 470 if (header == 0xff) { 471 continue; /* illegal value */ 472 } 473 474 /* 475 * according to some mail from Microsoft posted 476 * to the pci-drivers alias, their only requirement 477 * for a multifunction device is for the 1st 478 * function to have to PCI_HEADER_MULTI bit set. 479 */ 480 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 481 nfunc = 8; 482 } 483 484 if (config_op == CONFIG_INFO) { 485 /* 486 * Create the node, unconditionally, on the 487 * first pass only. It may still need 488 * resource assignment, which will be 489 * done on the second, CONFIG_NEW, pass. 490 */ 491 dip = new_func_pci(bus, dev, func, header, 492 venid, config_op); 493 /* 494 * If dip isn't null, put on a list to 495 * save for reprogramming when config_op 496 * is CONFIG_NEW. 497 */ 498 499 if (dip) { 500 entry = kmem_alloc(sizeof (*entry), 501 KM_SLEEP); 502 entry->dip = dip; 503 entry->dev = dev; 504 entry->func = func; 505 entry->next = devlist; 506 devlist = entry; 507 } 508 } 509 } 510 } 511 512 if (config_op == CONFIG_NEW) { 513 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 514 while (devlist) { 515 entry = devlist; 516 devlist = entry->next; 517 cmn_err(CE_NOTE, 518 "!reprogram pci device [%d/%d/%d] (%s)", 519 bus, entry->dev, entry->func, 520 ddi_driver_name(entry->dip)); 521 (void) add_reg_props(entry->dip, bus, entry->dev, 522 entry->func, CONFIG_UPDATE, 0); 523 kmem_free(entry, sizeof (*entry)); 524 } 525 pci_bus_res[bus].privdata = NULL; 526 } else { 527 pci_bus_res[bus].privdata = devlist; 528 } 529 } 530 531 static int 532 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 533 ushort_t subvenid, ushort_t subdevid) 534 { 535 static int prop_exist = -1; 536 static char *pciide_str; 537 char compat[32]; 538 539 if (prop_exist == -1) { 540 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 541 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 542 &pciide_str) == DDI_SUCCESS); 543 } 544 545 if (!prop_exist) 546 return (0); 547 548 /* compare property value against various forms of compatible */ 549 if (subvenid) { 550 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 551 venid, devid, subvenid, subdevid, revid); 552 if (strcmp(pciide_str, compat) == 0) 553 return (1); 554 555 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 556 venid, devid, subvenid, subdevid); 557 if (strcmp(pciide_str, compat) == 0) 558 return (1); 559 560 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 561 subvenid, subdevid); 562 if (strcmp(pciide_str, compat) == 0) 563 return (1); 564 } 565 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 566 venid, devid, revid); 567 if (strcmp(pciide_str, compat) == 0) 568 return (1); 569 570 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 571 if (strcmp(pciide_str, compat) == 0) 572 return (1); 573 574 return (0); 575 } 576 577 static int 578 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 579 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 580 { 581 struct ide_table { /* table for PCI_MASS_OTHER */ 582 ushort_t venid; 583 ushort_t devid; 584 } *entry; 585 586 /* XXX SATA devices: need a way to add dynamically */ 587 static struct ide_table ide_other[] = { 588 {0x1095, 0x3112}, 589 {0x1095, 0x3114}, 590 {0x1095, 0x3512}, 591 {0, 0} 592 }; 593 594 if (basecl != PCI_CLASS_MASS) 595 return (0); 596 597 if (subcl == PCI_MASS_IDE) { 598 return (1); 599 } 600 601 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 602 return (0); 603 } 604 605 entry = &ide_other[0]; 606 while (entry->venid) { 607 if (entry->venid == venid && entry->devid == devid) 608 return (1); 609 entry++; 610 } 611 return (check_pciide_prop(revid, venid, devid, subvenid, subdevid)); 612 } 613 614 static int 615 is_display(uint_t classcode) 616 { 617 static uint_t disp_classes[] = { 618 0x000100, 619 0x030000, 620 0x030001 621 }; 622 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 623 624 for (i = 0; i < nclasses; i++) { 625 if (classcode == disp_classes[i]) 626 return (1); 627 } 628 return (0); 629 } 630 631 static dev_info_t * 632 new_func_pci(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 633 ushort_t vendorid, int config_op) 634 { 635 char nodename[32], unitaddr[5]; 636 dev_info_t *dip; 637 uchar_t basecl, subcl, intr, revid; 638 ushort_t subvenid, subdevid, status; 639 ushort_t slot_num; 640 uint_t classcode, revclass; 641 int reprogram = 0, pciide; 642 int power[2] = {1, 1}; 643 int pciex = 0; 644 ushort_t is_pci_bridge = 0; 645 646 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 647 648 switch (header & PCI_HEADER_TYPE_M) { 649 case PCI_HEADER_ZERO: 650 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 651 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 652 break; 653 case PCI_HEADER_CARDBUS: 654 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 655 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 656 break; 657 default: 658 subvenid = 0; 659 subdevid = 0; 660 break; 661 } 662 663 /* XXX should be use generic names? derive from class? */ 664 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 665 classcode = revclass >> 8; 666 revid = revclass & 0xff; 667 668 /* figure out if this is pci-ide */ 669 basecl = classcode >> 16; 670 subcl = (classcode >> 8) & 0xff; 671 pciide = is_pciide(basecl, subcl, revid, vendorid, deviceid, 672 subvenid, subdevid); 673 674 if (pciide) 675 (void) snprintf(nodename, sizeof (nodename), "pci-ide"); 676 else if (is_display(classcode)) 677 (void) snprintf(nodename, sizeof (nodename), "display"); 678 else if (subvenid != 0) 679 (void) snprintf(nodename, sizeof (nodename), 680 "pci%x,%x", subvenid, subdevid); 681 else 682 (void) snprintf(nodename, sizeof (nodename), 683 "pci%x,%x", vendorid, deviceid); 684 685 /* make sure parent bus dip has been created */ 686 if (pci_bus_res[bus].dip == NULL) { 687 create_root_bus_dip(bus); 688 } 689 690 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 691 DEVI_SID_NODEID, &dip); 692 693 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 694 &is_pci_bridge) == B_TRUE) 695 pciex = 1; 696 697 /* add properties */ 698 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 699 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 700 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 701 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 702 "class-code", classcode); 703 if (func == 0) 704 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 705 else 706 (void) snprintf(unitaddr, sizeof (unitaddr), 707 "%x,%x", dev, func); 708 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 709 "unit-address", unitaddr); 710 711 /* add device_type for display nodes */ 712 if (is_display(classcode)) { 713 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 714 "device_type", "display"); 715 } 716 /* add special stuff for header type */ 717 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 718 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 719 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 720 721 if (subvenid != 0) { 722 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 723 "subsystem-id", subdevid); 724 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 725 "subsystem-vendor-id", subvenid); 726 } 727 if (!pciex) 728 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 729 "min-grant", mingrant); 730 if (!pciex) 731 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 732 "max-latency", maxlatency); 733 } 734 735 /* interrupt, record if not 0 */ 736 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 737 if (intr != 0) 738 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 739 "interrupts", intr); 740 741 /* 742 * Add support for 133 mhz pci eventually 743 */ 744 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 745 746 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 747 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 748 if (!pciex && (status & PCI_STAT_FBBC)) 749 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 750 "fast-back-to-back"); 751 if (!pciex && (status & PCI_STAT_66MHZ)) 752 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 753 "66mhz-capable"); 754 if (status & PCI_STAT_UDF) 755 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 756 "udf-supported"); 757 if (pciex && slot_num) 758 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 759 "physical-slot#", slot_num); 760 761 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 762 "power-consumption", power, 2); 763 764 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 765 add_ppb_props(dip, bus, dev, func, pciex); 766 767 /* check for ck8-04 based PCI ISA bridge only */ 768 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 769 (func == 0)) 770 add_ck804_isa_bridge_props(dip, bus, dev, func); 771 772 if (pciex && is_pci_bridge) 773 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 774 (char *)"PCIe-PCI bridge"); 775 else 776 add_model_prop(dip, classcode); 777 778 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 779 revid, classcode, pciex); 780 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 781 (void) ndi_devi_bind_driver(dip, 0); 782 783 /* special handling for pci-ide */ 784 if (pciide) { 785 dev_info_t *cdip; 786 787 /* 788 * Create properties specified by P1275 Working Group 789 * Proposal #414 Version 1 790 */ 791 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 792 "device_type", "pci-ide"); 793 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 794 "#address-cells", 1); 795 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 796 "#size-cells", 0); 797 798 /* allocate two child nodes */ 799 ndi_devi_alloc_sleep(dip, "ide", 800 (pnode_t)DEVI_SID_NODEID, &cdip); 801 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 802 "reg", 0); 803 (void) ndi_devi_bind_driver(cdip, 0); 804 ndi_devi_alloc_sleep(dip, "ide", 805 (pnode_t)DEVI_SID_NODEID, &cdip); 806 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 807 "reg", 1); 808 (void) ndi_devi_bind_driver(cdip, 0); 809 810 reprogram = 0; /* don't reprogram pci-ide bridge */ 811 } 812 813 814 if (reprogram) 815 return (dip); 816 return (NULL); 817 } 818 819 /* 820 * Set the compatible property to a value compliant with 821 * rev 2.1 of the IEEE1275 PCI binding. 822 * (Also used for PCI-Express devices). 823 * 824 * pciVVVV,DDDD.SSSS.ssss.RR (0) 825 * pciVVVV,DDDD.SSSS.ssss (1) 826 * pciSSSS,ssss (2) 827 * pciVVVV,DDDD.RR (3) 828 * pciVVVV,DDDD (4) 829 * pciclass,CCSSPP (5) 830 * pciclass,CCSS (6) 831 * 832 * The Subsystem (SSSS) forms are not inserted if 833 * subsystem-vendor-id is 0. 834 * 835 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 836 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 837 * 838 * Set with setprop and \x00 between each 839 * to generate the encoded string array form. 840 */ 841 void 842 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 843 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 844 int pciex) 845 { 846 int i = 0; 847 int size = COMPAT_BUFSIZE; 848 char *compat[13]; 849 char *buf, *curr; 850 851 curr = buf = kmem_alloc(size, KM_SLEEP); 852 853 if (pciex) { 854 if (subvenid) { 855 compat[i++] = curr; /* form 0 */ 856 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 857 vendorid, deviceid, subvenid, subdevid, revid); 858 size -= strlen(curr) + 1; 859 curr += strlen(curr) + 1; 860 861 compat[i++] = curr; /* form 1 */ 862 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 863 vendorid, deviceid, subvenid, subdevid); 864 size -= strlen(curr) + 1; 865 curr += strlen(curr) + 1; 866 867 } 868 compat[i++] = curr; /* form 3 */ 869 (void) snprintf(curr, size, "pciex%x,%x.%x", 870 vendorid, deviceid, revid); 871 size -= strlen(curr) + 1; 872 curr += strlen(curr) + 1; 873 874 compat[i++] = curr; /* form 4 */ 875 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 876 size -= strlen(curr) + 1; 877 curr += strlen(curr) + 1; 878 879 compat[i++] = curr; /* form 5 */ 880 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 881 size -= strlen(curr) + 1; 882 curr += strlen(curr) + 1; 883 884 compat[i++] = curr; /* form 6 */ 885 (void) snprintf(curr, size, "pciexclass,%04x", 886 (classcode >> 8)); 887 size -= strlen(curr) + 1; 888 curr += strlen(curr) + 1; 889 } 890 891 if (subvenid) { 892 compat[i++] = curr; /* form 0 */ 893 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 894 vendorid, deviceid, subvenid, subdevid, revid); 895 size -= strlen(curr) + 1; 896 curr += strlen(curr) + 1; 897 898 compat[i++] = curr; /* form 1 */ 899 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 900 vendorid, deviceid, subvenid, subdevid); 901 size -= strlen(curr) + 1; 902 curr += strlen(curr) + 1; 903 904 compat[i++] = curr; /* form 2 */ 905 (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 906 size -= strlen(curr) + 1; 907 curr += strlen(curr) + 1; 908 } 909 compat[i++] = curr; /* form 3 */ 910 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 911 size -= strlen(curr) + 1; 912 curr += strlen(curr) + 1; 913 914 compat[i++] = curr; /* form 4 */ 915 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 916 size -= strlen(curr) + 1; 917 curr += strlen(curr) + 1; 918 919 compat[i++] = curr; /* form 5 */ 920 (void) snprintf(curr, size, "pciclass,%06x", classcode); 921 size -= strlen(curr) + 1; 922 curr += strlen(curr) + 1; 923 924 compat[i++] = curr; /* form 6 */ 925 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 926 size -= strlen(curr) + 1; 927 curr += strlen(curr) + 1; 928 929 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 930 "compatible", compat, i); 931 kmem_free(buf, COMPAT_BUFSIZE); 932 } 933 934 /* 935 * Adjust the reg properties for a dual channel PCI-IDE device. 936 * 937 * NOTE: don't do anything that changes the order of the hard-decodes 938 * and programmed BARs. The kernel driver depends on these values 939 * being in this order regardless of whether they're for a 'native' 940 * mode BAR or not. 941 */ 942 /* 943 * config info for pci-ide devices 944 */ 945 static struct { 946 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 947 uchar_t bar_offset; /* offset for alt status register */ 948 ushort_t addr; /* compatibility mode base address */ 949 ushort_t length; /* number of ports for this BAR */ 950 } pciide_bar[] = { 951 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 952 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 953 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 954 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 955 }; 956 957 static int 958 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 959 { 960 int hard_decode = 0; 961 962 /* 963 * Adjust the base and len for the BARs of the PCI-IDE 964 * device's primary and secondary controllers. The first 965 * two BARs are for the primary controller and the next 966 * two BARs are for the secondary controller. The fifth 967 * and sixth bars are never adjusted. 968 */ 969 if (index >= 0 && index <= 3) { 970 *lenp = pciide_bar[index].length; 971 972 if (progcl & pciide_bar[index].native_mask) { 973 *basep += pciide_bar[index].bar_offset; 974 } else { 975 *basep = pciide_bar[index].addr; 976 hard_decode = 1; 977 } 978 } 979 980 /* 981 * if either base or len is zero make certain both are zero 982 */ 983 if (*basep == 0 || *lenp == 0) { 984 *basep = 0; 985 *lenp = 0; 986 hard_decode = 0; 987 } 988 989 return (hard_decode); 990 } 991 992 993 /* 994 * Add the "reg" and "assigned-addresses" property 995 */ 996 static int 997 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 998 int config_op, int pciide) 999 { 1000 uchar_t baseclass, subclass, progclass, header; 1001 ushort_t bar_sz; 1002 uint_t value = 0, len, devloc; 1003 uint_t base, base_hi, type; 1004 ushort_t offset, end; 1005 int max_basereg, j, reprogram = 0; 1006 uint_t phys_hi; 1007 struct memlist **io_res, **mres, **mem_res, **pmem_res; 1008 uint16_t cmd_reg; 1009 1010 pci_regspec_t regs[16] = {{0}}; 1011 pci_regspec_t assigned[15] = {{0}}; 1012 int nreg, nasgn, enable = 0; 1013 1014 io_res = &pci_bus_res[bus].io_ports; 1015 mem_res = &pci_bus_res[bus].mem_space; 1016 if (bus == 0) /* for bus 0, there is only mem_space */ 1017 pmem_res = mem_res; 1018 else 1019 pmem_res = &pci_bus_res[bus].pmem_space; 1020 1021 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1022 regs[0].pci_phys_hi = devloc; 1023 nreg = 1; /* rest of regs[0] is all zero */ 1024 nasgn = 0; 1025 1026 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 1027 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 1028 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 1029 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1030 /* Fetch PCI command, disable I/O and memory */ 1031 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 1032 pci_putw(bus, dev, func, PCI_CONF_COMM, 1033 cmd_reg & ~(PCI_COMM_IO | PCI_COMM_MAE)); 1034 1035 switch (header) { 1036 case PCI_HEADER_ZERO: 1037 max_basereg = PCI_BASE_NUM; 1038 break; 1039 case PCI_HEADER_PPB: 1040 max_basereg = PCI_BCNF_BASE_NUM; 1041 break; 1042 case PCI_HEADER_CARDBUS: 1043 max_basereg = PCI_CBUS_BASE_NUM; 1044 break; 1045 default: 1046 max_basereg = 0; 1047 break; 1048 } 1049 1050 /* 1051 * Create the register property by saving the current 1052 * value of the base register. Disable memory/io, then 1053 * write 0xffffffff to the base register. Read the 1054 * value back to determine the required size of the 1055 * address space. Restore the base register 1056 * contents. 1057 */ 1058 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 1059 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 1060 j++, offset += bar_sz) { 1061 int hard_decode = 0; 1062 1063 /* determine the size of the address space */ 1064 base = pci_getl(bus, dev, func, offset); 1065 pci_putl(bus, dev, func, offset, 0xffffffff); 1066 value = pci_getl(bus, dev, func, offset); 1067 pci_putl(bus, dev, func, offset, base); 1068 1069 /* construct phys hi,med.lo, size hi, lo */ 1070 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 1071 /* i/o space */ 1072 bar_sz = PCI_BAR_SZ_32; 1073 value &= PCI_BASE_IO_ADDR_M; 1074 len = ((value ^ (value-1)) + 1) >> 1; 1075 1076 /* XXX Adjust first 4 IDE registers */ 1077 if (pciide) { 1078 if (subclass != PCI_MASS_IDE) 1079 progclass = (PCI_IDE_IF_NATIVE_PRI | 1080 PCI_IDE_IF_NATIVE_SEC); 1081 hard_decode = pciIdeAdjustBAR(progclass, j, 1082 &base, &len); 1083 } else if (value == 0) { 1084 /* skip base regs with size of 0 */ 1085 continue; 1086 } 1087 1088 regs[nreg].pci_size_low = 1089 assigned[nasgn].pci_size_low = len; 1090 if (!hard_decode) { 1091 regs[nreg].pci_phys_hi = 1092 (PCI_ADDR_IO | devloc) + offset; 1093 } else { 1094 regs[nreg].pci_phys_hi = 1095 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 1096 offset; 1097 regs[nreg].pci_phys_low = 1098 base & PCI_BASE_IO_ADDR_M; 1099 } 1100 assigned[nasgn].pci_phys_hi = 1101 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 1102 type = base & (~PCI_BASE_IO_ADDR_M); 1103 base &= PCI_BASE_IO_ADDR_M; 1104 1105 /* 1106 * first pass - gather what's there 1107 * update/second pass - adjust/allocate regions 1108 * config - allocate regions 1109 */ 1110 if (config_op == CONFIG_INFO) { /* first pass */ 1111 /* take out of the resource map of the bus */ 1112 if (*io_res && base != 0) 1113 (void) memlist_remove(io_res, 1114 (uint64_t)base, (uint64_t)len); 1115 else if (*io_res) 1116 reprogram = 1; 1117 } else if (*io_res && base == 0) { 1118 base = (uint_t)memlist_find(io_res, 1119 (uint64_t)len, (uint64_t)0x4); 1120 if (base != 0) { 1121 /* XXX need to worry about 64-bit? */ 1122 pci_putl(bus, dev, func, offset, 1123 base | type); 1124 base = pci_getl(bus, dev, func, offset); 1125 base &= PCI_BASE_IO_ADDR_M; 1126 } 1127 if (base == 0) { 1128 cmn_err(CE_WARN, "failed to program" 1129 " IO space [%d/%d/%d] BAR@0x%x" 1130 " length 0x%x", 1131 bus, dev, func, offset, len); 1132 } else 1133 enable |= PCI_COMM_IO; 1134 } 1135 assigned[nasgn].pci_phys_low = base; 1136 nreg++, nasgn++; 1137 1138 } else { 1139 /* memory space */ 1140 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 1141 bar_sz = PCI_BAR_SZ_64; 1142 base_hi = pci_getl(bus, dev, func, offset + 4); 1143 phys_hi = PCI_ADDR_MEM64; 1144 } else { 1145 bar_sz = PCI_BAR_SZ_32; 1146 base_hi = 0; 1147 phys_hi = PCI_ADDR_MEM32; 1148 } 1149 1150 /* skip base regs with size of 0 */ 1151 value &= PCI_BASE_M_ADDR_M; 1152 1153 if (value == 0) { 1154 continue; 1155 } 1156 len = ((value ^ (value-1)) + 1) >> 1; 1157 regs[nreg].pci_size_low = 1158 assigned[nasgn].pci_size_low = len; 1159 1160 phys_hi |= (devloc | offset); 1161 if (base & PCI_BASE_PREF_M) { 1162 mres = pmem_res; 1163 phys_hi |= PCI_PREFETCH_B; 1164 } else { 1165 mres = mem_res; 1166 } 1167 regs[nreg].pci_phys_hi = 1168 assigned[nasgn].pci_phys_hi = phys_hi; 1169 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 1170 assigned[nasgn].pci_phys_mid = base_hi; 1171 type = base & ~PCI_BASE_M_ADDR_M; 1172 base &= PCI_BASE_M_ADDR_M; 1173 1174 if (config_op == CONFIG_INFO) { 1175 /* take out of the resource map of the bus */ 1176 if (*mres && base != 0) { 1177 (void) memlist_remove(mres, 1178 (uint64_t)base, (uint64_t)len); 1179 } else if (*mres) 1180 reprogram = 1; 1181 } else if (*mres && base == 0) { 1182 base = (uint_t)memlist_find(mres, 1183 (uint64_t)len, (uint64_t)0x1000); 1184 if (base != NULL) { 1185 pci_putl(bus, dev, func, offset, 1186 base | type); 1187 base = pci_getl(bus, dev, func, offset); 1188 base &= PCI_BASE_M_ADDR_M; 1189 } 1190 1191 if (base == 0) { 1192 cmn_err(CE_WARN, "failed to program " 1193 "mem space [%d/%d/%d] BAR@0x%x" 1194 " length 0x%x", 1195 bus, dev, func, offset, len); 1196 } else 1197 enable |= PCI_COMM_MAE; 1198 } 1199 assigned[nasgn].pci_phys_low = base; 1200 nreg++, nasgn++; 1201 } 1202 } 1203 switch (header) { 1204 case PCI_HEADER_ZERO: 1205 offset = PCI_CONF_ROM; 1206 break; 1207 case PCI_HEADER_PPB: 1208 offset = PCI_BCNF_ROM; 1209 break; 1210 default: /* including PCI_HEADER_CARDBUS */ 1211 goto done; 1212 } 1213 1214 /* 1215 * Add the expansion rom memory space 1216 * Determine the size of the ROM base reg; don't write reserved bits 1217 * ROM isn't in the PCI memory space. 1218 */ 1219 base = pci_getl(bus, dev, func, offset); 1220 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 1221 value = pci_getl(bus, dev, func, offset); 1222 pci_putl(bus, dev, func, offset, base); 1223 if (value & PCI_BASE_ROM_ENABLE) 1224 value &= PCI_BASE_ROM_ADDR_M; 1225 else 1226 value = 0; 1227 1228 if (value != 0) { 1229 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 1230 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 1231 PCI_ADDR_MEM32 | devloc) + offset; 1232 base &= PCI_BASE_ROM_ADDR_M; 1233 assigned[nasgn].pci_phys_low = base; 1234 len = ((value ^ (value-1)) + 1) >> 1; 1235 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 1236 nreg++, nasgn++; 1237 /* take it out of the memory resource */ 1238 if (*mem_res && base != 0) 1239 (void) memlist_remove(mem_res, 1240 (uint64_t)base, (uint64_t)len); 1241 } 1242 1243 /* 1244 * The following are ISA resources. There are not part 1245 * of the PCI local bus resources. So don't attempt to 1246 * do resource accounting against PCI. 1247 */ 1248 1249 /* add the three hard-decode, aliased address spaces for VGA */ 1250 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 1251 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 1252 1253 /* VGA hard decode 0x3b0-0x3bb */ 1254 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1255 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1256 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 1257 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 1258 nreg++, nasgn++; 1259 1260 /* VGA hard decode 0x3c0-0x3df */ 1261 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1262 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1263 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 1264 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 1265 nreg++, nasgn++; 1266 1267 /* Video memory */ 1268 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1269 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 1270 regs[nreg].pci_phys_low = 1271 assigned[nasgn].pci_phys_low = 0xa0000; 1272 regs[nreg].pci_size_low = 1273 assigned[nasgn].pci_size_low = 0x20000; 1274 nreg++, nasgn++; 1275 } 1276 1277 /* add the hard-decode, aliased address spaces for 8514 */ 1278 if ((baseclass == PCI_CLASS_DISPLAY) && 1279 (subclass == PCI_DISPLAY_VGA) && 1280 (progclass & PCI_DISPLAY_IF_8514)) { 1281 1282 /* hard decode 0x2e8 */ 1283 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1284 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1285 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 1286 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 1287 nreg++, nasgn++; 1288 1289 /* hard decode 0x2ea-0x2ef */ 1290 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1291 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1292 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 1293 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 1294 nreg++, nasgn++; 1295 } 1296 1297 done: 1298 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 1299 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 1300 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1301 "assigned-addresses", 1302 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 1303 if (config_op == CONFIG_NEW && enable) { 1304 cmn_err(CE_NOTE, 1305 "!enable PCI device [%d/%d/%d]", bus, dev, func); 1306 cmd_reg |= (enable | PCI_COMM_ME); 1307 } 1308 /* restore device enables */ 1309 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1310 return (reprogram); 1311 } 1312 1313 static void 1314 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1315 int pciex) 1316 { 1317 char *dev_type; 1318 int i; 1319 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 1320 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1321 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1322 ASSERT(secbus <= subbus); 1323 1324 /* 1325 * Some BIOSes lie about max pci busses, we allow for 1326 * such mistakes here 1327 */ 1328 if (subbus > pci_bios_nbus) { 1329 pci_bios_nbus = subbus; 1330 alloc_res_array(); 1331 } 1332 1333 ASSERT(pci_bus_res[secbus].dip == NULL); 1334 pci_bus_res[secbus].dip = dip; 1335 pci_bus_res[secbus].par_bus = bus; 1336 1337 dev_type = pciex ? "pciex" : "pci"; 1338 1339 /* setup bus number hierarchy */ 1340 pci_bus_res[secbus].sub_bus = subbus; 1341 if (subbus > pci_bus_res[bus].sub_bus) 1342 pci_bus_res[bus].sub_bus = subbus; 1343 for (i = secbus + 1; i <= subbus; i++) 1344 pci_bus_res[i].par_bus = bus; 1345 1346 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1347 "device_type", dev_type); 1348 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1349 "#address-cells", 3); 1350 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1351 "#size-cells", 2); 1352 1353 /* 1354 * According to PPB spec, the base register should be programmed 1355 * with a value bigger than the limit register when there are 1356 * no resources available. This applies to io, memory, and 1357 * prefetchable memory. 1358 */ 1359 /* io range */ 1360 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1361 io_range[0] = ((val & 0xf0) << 8); 1362 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1363 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 1364 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 1365 memlist_insert(&pci_bus_res[secbus].io_ports, 1366 (uint64_t)io_range[0], 1367 (uint64_t)(io_range[1] - io_range[0] + 1)); 1368 if (pci_bus_res[bus].io_ports != NULL) { 1369 (void) memlist_remove(&pci_bus_res[bus].io_ports, 1370 (uint64_t)io_range[0], 1371 (uint64_t)(io_range[1] - io_range[0] + 1)); 1372 } 1373 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 1374 secbus, io_range[0], io_range[1]); 1375 /* if 32-bit supported, make sure upper bits are not set */ 1376 if ((val & 0xf) == 1 && 1377 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 1378 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 1379 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1380 } 1381 } 1382 1383 /* mem range */ 1384 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1385 mem_range[0] = ((val & 0xFFF0) << 16); 1386 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1387 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1388 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 1389 memlist_insert(&pci_bus_res[secbus].mem_space, 1390 (uint64_t)mem_range[0], 1391 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1392 /* remove from parent resouce list */ 1393 if (pci_bus_res[bus].mem_space != NULL) { 1394 (void) memlist_remove(&pci_bus_res[bus].mem_space, 1395 (uint64_t)mem_range[0], 1396 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1397 } 1398 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 1399 secbus, mem_range[0], mem_range[1]); 1400 } 1401 1402 /* prefetchable memory range */ 1403 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1404 pmem_range[0] = ((val & 0xFFF0) << 16); 1405 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 1406 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1407 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 1408 memlist_insert(&pci_bus_res[secbus].pmem_space, 1409 (uint64_t)pmem_range[0], 1410 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1411 if (pci_bus_res[bus].pmem_space != NULL) { 1412 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 1413 (uint64_t)pmem_range[0], 1414 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1415 } 1416 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 1417 secbus, pmem_range[0], pmem_range[1]); 1418 /* if 64-bit supported, make sure upper bits are not set */ 1419 if ((val & 0xf) == 1 && 1420 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 1421 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 1422 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1423 } 1424 } 1425 1426 add_bus_range_prop(secbus); 1427 add_ppb_ranges_prop(secbus); 1428 } 1429 1430 extern const struct pci_class_strings_s class_pci[]; 1431 extern int class_pci_items; 1432 1433 static void 1434 add_model_prop(dev_info_t *dip, uint_t classcode) 1435 { 1436 const char *desc; 1437 int i; 1438 uchar_t baseclass = classcode >> 16; 1439 uchar_t subclass = (classcode >> 8) & 0xff; 1440 uchar_t progclass = classcode & 0xff; 1441 1442 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 1443 desc = "IDE controller"; 1444 } else { 1445 for (desc = 0, i = 0; i < class_pci_items; i++) { 1446 if ((baseclass == class_pci[i].base_class) && 1447 (subclass == class_pci[i].sub_class) && 1448 (progclass == class_pci[i].prog_class)) { 1449 desc = class_pci[i].actual_desc; 1450 break; 1451 } 1452 } 1453 if (i == class_pci_items) 1454 desc = "Unknown class of pci/pnpbios device"; 1455 } 1456 1457 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1458 (char *)desc); 1459 } 1460 1461 static void 1462 add_bus_range_prop(int bus) 1463 { 1464 int bus_range[2]; 1465 1466 if (pci_bus_res[bus].dip == NULL) 1467 return; 1468 bus_range[0] = bus; 1469 bus_range[1] = pci_bus_res[bus].sub_bus; 1470 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1471 "bus-range", (int *)bus_range, 2); 1472 } 1473 1474 /* 1475 * Add slot-names property for any named pci hot-plug slots 1476 */ 1477 static void 1478 add_bus_slot_names_prop(int bus) 1479 { 1480 char slotprop[256]; 1481 int len; 1482 1483 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 1484 if (len > 0) { 1485 if (pci_bus_res[bus].dip == NULL) 1486 create_root_bus_dip(bus); 1487 ASSERT(pci_bus_res[bus].dip); 1488 ASSERT((len % sizeof (int)) == 0); 1489 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1490 pci_bus_res[bus].dip, "slot-names", 1491 (int *)slotprop, len / sizeof (int)); 1492 } 1493 } 1494 1495 static int 1496 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type) 1497 { 1498 if (entry == NULL) 1499 return (0); 1500 1501 /* assume 32-bit addresses */ 1502 rp->child_high = rp->parent_high = type; 1503 rp->child_mid = rp->parent_mid = 0; 1504 rp->child_low = rp->parent_low = (uint32_t)entry->address; 1505 rp->size_high = 0; 1506 rp->size_low = (uint32_t)entry->size; 1507 return (1); 1508 } 1509 1510 static void 1511 add_ppb_ranges_prop(int bus) 1512 { 1513 int i = 0; 1514 ppb_ranges_t *rp; 1515 1516 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 1517 1518 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 1519 PCI_ADDR_IO | PCI_REG_REL_M); 1520 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 1521 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1522 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 1523 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1524 1525 if (i != 0) 1526 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1527 pci_bus_res[bus].dip, "ranges", (int *)rp, 1528 i * sizeof (ppb_ranges_t) / sizeof (int)); 1529 kmem_free(rp, 3 * sizeof (*rp)); 1530 } 1531 1532 static int 1533 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 1534 { 1535 int i = 0; 1536 1537 while (list) { 1538 /* assume 32-bit addresses */ 1539 sp->pci_phys_hi = type; 1540 sp->pci_phys_mid = 0; 1541 sp->pci_phys_low = (uint32_t)list->address; 1542 sp->pci_size_hi = 0; 1543 sp->pci_size_low = (uint32_t)list->size; 1544 1545 list = list->next; 1546 sp++, i++; 1547 } 1548 return (i); 1549 } 1550 1551 static void 1552 add_bus_available_prop(int bus) 1553 { 1554 int i, count; 1555 struct pci_phys_spec *sp; 1556 1557 count = memlist_count(pci_bus_res[bus].io_ports) + 1558 memlist_count(pci_bus_res[bus].mem_space) + 1559 memlist_count(pci_bus_res[bus].pmem_space); 1560 1561 if (count == 0) /* nothing available */ 1562 return; 1563 1564 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 1565 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 1566 PCI_ADDR_IO | PCI_REG_REL_M); 1567 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 1568 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1569 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 1570 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1571 ASSERT(i == count); 1572 1573 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1574 "available", (int *)sp, 1575 i * sizeof (struct pci_phys_spec) / sizeof (int)); 1576 kmem_free(sp, count * sizeof (*sp)); 1577 } 1578 1579 static void 1580 alloc_res_array(void) 1581 { 1582 static int array_max = 0; 1583 int old_max; 1584 void *old_res; 1585 1586 if (array_max > pci_bios_nbus + 1) 1587 return; /* array is big enough */ 1588 1589 old_max = array_max; 1590 old_res = pci_bus_res; 1591 1592 if (array_max == 0) 1593 array_max = 16; /* start with a reasonable number */ 1594 1595 while (array_max < pci_bios_nbus + 1) 1596 array_max <<= 1; 1597 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 1598 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 1599 1600 if (old_res) { /* copy content and free old array */ 1601 bcopy(old_res, pci_bus_res, 1602 old_max * sizeof (struct pci_bus_resource)); 1603 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 1604 } 1605 } 1606